1 /* $NetBSD: pci.c,v 1.151 2016/01/23 17:09:51 macallan Exp $ */
2
3 /*
4 * Copyright (c) 1995, 1996, 1997, 1998
5 * Christopher G. Demetriou. All rights reserved.
6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Charles M. Hannum.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * PCI bus autoconfiguration.
36 */
37
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.151 2016/01/23 17:09:51 macallan Exp $");
40
41 #ifdef _KERNEL_OPT
42 #include "opt_pci.h"
43 #endif
44
45 #include <sys/param.h>
46 #include <sys/malloc.h>
47 #include <sys/systm.h>
48 #include <sys/device.h>
49 #include <sys/module.h>
50
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pcivar.h>
53 #include <dev/pci/pcidevs.h>
54
55 #include <net/if.h>
56
57 #include "locators.h"
58
59 static bool pci_child_register(device_t);
60
61 #ifdef PCI_CONFIG_DUMP
62 int pci_config_dump = 1;
63 #else
64 int pci_config_dump = 0;
65 #endif
66
67 int pciprint(void *, const char *);
68
69 #ifdef PCI_MACHDEP_ENUMERATE_BUS
70 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS
71 #endif
72
73 /*
74 * Important note about PCI-ISA bridges:
75 *
76 * Callbacks are used to configure these devices so that ISA/EISA bridges
77 * can attach their child busses after PCI configuration is done.
78 *
79 * This works because:
80 * (1) there can be at most one ISA/EISA bridge per PCI bus, and
81 * (2) any ISA/EISA bridges must be attached to primary PCI
82 * busses (i.e. bus zero).
83 *
84 * That boils down to: there can only be one of these outstanding
85 * at a time, it is cleared when configuring PCI bus 0 before any
86 * subdevices have been found, and it is run after all subdevices
87 * of PCI bus 0 have been found.
88 *
89 * This is needed because there are some (legacy) PCI devices which
90 * can show up as ISA/EISA devices as well (the prime example of which
91 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge,
92 * and the bridge is seen before the video board is, the board can show
93 * up as an ISA device, and that can (bogusly) complicate the PCI device's
94 * attach code, or make the PCI device not be properly attached at all.
95 *
96 * We use the generic config_defer() facility to achieve this.
97 */
98
99 int
pcirescan(device_t self,const char * ifattr,const int * locators)100 pcirescan(device_t self, const char *ifattr, const int *locators)
101 {
102 struct pci_softc *sc = device_private(self);
103
104 KASSERT(ifattr && !strcmp(ifattr, "pci"));
105 KASSERT(locators);
106
107 pci_enumerate_bus(sc, locators, NULL, NULL);
108
109 return 0;
110 }
111
112 int
pcimatch(device_t parent,cfdata_t cf,void * aux)113 pcimatch(device_t parent, cfdata_t cf, void *aux)
114 {
115 struct pcibus_attach_args *pba = aux;
116
117 /* Check the locators */
118 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT &&
119 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus)
120 return 0;
121
122 /* sanity */
123 if (pba->pba_bus < 0 || pba->pba_bus > 255)
124 return 0;
125
126 /*
127 * XXX check other (hardware?) indicators
128 */
129
130 return 1;
131 }
132
133 void
pciattach(device_t parent,device_t self,void * aux)134 pciattach(device_t parent, device_t self, void *aux)
135 {
136 struct pcibus_attach_args *pba = aux;
137 struct pci_softc *sc = device_private(self);
138 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled;
139 const char *sep = "";
140 static const int wildcard[PCICF_NLOCS] = {
141 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT
142 };
143
144 sc->sc_dev = self;
145
146 pci_attach_hook(parent, self, pba);
147
148 aprint_naive("\n");
149 aprint_normal("\n");
150
151 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY);
152 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY);
153 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY);
154 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY);
155 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY);
156
157 if (io_enabled == 0 && mem_enabled == 0) {
158 aprint_error_dev(self, "no spaces enabled!\n");
159 goto fail;
160 }
161
162 #define PRINT(str) \
163 do { \
164 aprint_verbose("%s%s", sep, str); \
165 sep = ", "; \
166 } while (/*CONSTCOND*/0)
167
168 aprint_verbose_dev(self, "");
169
170 if (io_enabled)
171 PRINT("i/o space");
172 if (mem_enabled)
173 PRINT("memory space");
174 aprint_verbose(" enabled");
175
176 if (mrl_enabled || mrm_enabled || mwi_enabled) {
177 if (mrl_enabled)
178 PRINT("rd/line");
179 if (mrm_enabled)
180 PRINT("rd/mult");
181 if (mwi_enabled)
182 PRINT("wr/inv");
183 aprint_verbose(" ok");
184 }
185
186 aprint_verbose("\n");
187
188 #undef PRINT
189
190 sc->sc_iot = pba->pba_iot;
191 sc->sc_memt = pba->pba_memt;
192 sc->sc_dmat = pba->pba_dmat;
193 sc->sc_dmat64 = pba->pba_dmat64;
194 sc->sc_pc = pba->pba_pc;
195 sc->sc_bus = pba->pba_bus;
196 sc->sc_bridgetag = pba->pba_bridgetag;
197 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus);
198 sc->sc_intrswiz = pba->pba_intrswiz;
199 sc->sc_intrtag = pba->pba_intrtag;
200 sc->sc_flags = pba->pba_flags;
201
202 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register);
203
204 pcirescan(sc->sc_dev, "pci", wildcard);
205
206 fail:
207 if (!pmf_device_register(self, NULL, NULL))
208 aprint_error_dev(self, "couldn't establish power handler\n");
209 }
210
211 int
pcidetach(device_t self,int flags)212 pcidetach(device_t self, int flags)
213 {
214 int rc;
215
216 if ((rc = config_detach_children(self, flags)) != 0)
217 return rc;
218 pmf_device_deregister(self);
219 return 0;
220 }
221
222 int
pciprint(void * aux,const char * pnp)223 pciprint(void *aux, const char *pnp)
224 {
225 struct pci_attach_args *pa = aux;
226 char devinfo[256];
227 const struct pci_quirkdata *qd;
228
229 if (pnp) {
230 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo));
231 aprint_normal("%s at %s", devinfo, pnp);
232 }
233 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function);
234 if (pci_config_dump) {
235 printf(": ");
236 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
237 if (!pnp)
238 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo));
239 printf("%s at %s", devinfo, pnp ? pnp : "?");
240 printf(" dev %d function %d (", pa->pa_device, pa->pa_function);
241 #ifdef __i386__
242 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx",
243 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag,
244 (long)pa->pa_intrswiz, (long)pa->pa_intrpin);
245 #else
246 printf("intrswiz %#lx, intrpin %#lx",
247 (long)pa->pa_intrswiz, (long)pa->pa_intrpin);
248 #endif
249 printf(", i/o %s, mem %s,",
250 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off",
251 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off");
252 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id),
253 PCI_PRODUCT(pa->pa_id));
254 if (qd == NULL) {
255 printf(" no quirks");
256 } else {
257 snprintb(devinfo, sizeof (devinfo),
258 "\002\001multifn\002singlefn\003skipfunc0"
259 "\004skipfunc1\005skipfunc2\006skipfunc3"
260 "\007skipfunc4\010skipfunc5\011skipfunc6"
261 "\012skipfunc7", qd->quirks);
262 printf(" quirks %s", devinfo);
263 }
264 printf(")");
265 }
266 return UNCONF;
267 }
268
269 int
pci_probe_device(struct pci_softc * sc,pcitag_t tag,int (* match)(const struct pci_attach_args *),struct pci_attach_args * pap)270 pci_probe_device(struct pci_softc *sc, pcitag_t tag,
271 int (*match)(const struct pci_attach_args *),
272 struct pci_attach_args *pap)
273 {
274 pci_chipset_tag_t pc = sc->sc_pc;
275 struct pci_attach_args pa;
276 pcireg_t id, /* csr, */ pciclass, intr, bhlcr, bar, endbar;
277 #ifdef __HAVE_PCI_MSI_MSIX
278 pcireg_t cap;
279 int off;
280 #endif
281 int ret, pin, bus, device, function, i, width;
282 int locs[PCICF_NLOCS];
283
284 pci_decompose_tag(pc, tag, &bus, &device, &function);
285
286 /* a driver already attached? */
287 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match)
288 return 0;
289
290 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG);
291 if (PCI_HDRTYPE_TYPE(bhlcr) > 2)
292 return 0;
293
294 id = pci_conf_read(pc, tag, PCI_ID_REG);
295 /* csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); */
296 pciclass = pci_conf_read(pc, tag, PCI_CLASS_REG);
297
298 /* Invalid vendor ID value? */
299 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
300 return 0;
301 /* XXX Not invalid, but we've done this ~forever. */
302 if (PCI_VENDOR(id) == 0)
303 return 0;
304
305 /* Collect memory range info */
306 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0,
307 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range));
308 i = 0;
309 switch (PCI_HDRTYPE_TYPE(bhlcr)) {
310 case PCI_HDRTYPE_PPB:
311 endbar = PCI_MAPREG_PPB_END;
312 break;
313 case PCI_HDRTYPE_PCB:
314 endbar = PCI_MAPREG_PCB_END;
315 break;
316 default:
317 endbar = PCI_MAPREG_END;
318 break;
319 }
320 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) {
321 struct pci_range *r;
322 pcireg_t type;
323
324 width = 4;
325 if (pci_mapreg_probe(pc, tag, bar, &type) == 0)
326 continue;
327
328 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) {
329 if (PCI_MAPREG_MEM_TYPE(type) ==
330 PCI_MAPREG_MEM_TYPE_64BIT)
331 width = 8;
332
333 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++];
334 if (pci_mapreg_info(pc, tag, bar, type,
335 &r->r_offset, &r->r_size, &r->r_flags) != 0)
336 break;
337 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10)
338 && (r->r_size == 0x1000000)) {
339 struct pci_range *nr;
340 /*
341 * this has to be a mach64
342 * split things up so each half-aperture can
343 * be mapped PREFETCHABLE except the last page
344 * which may contain registers
345 */
346 r->r_size = 0x7ff000;
347 r->r_flags = BUS_SPACE_MAP_LINEAR |
348 BUS_SPACE_MAP_PREFETCHABLE;
349 nr = &sc->PCI_SC_DEVICESC(device,
350 function).c_range[i++];
351 nr->r_offset = r->r_offset + 0x800000;
352 nr->r_size = 0x7ff000;
353 nr->r_flags = BUS_SPACE_MAP_LINEAR |
354 BUS_SPACE_MAP_PREFETCHABLE;
355 } else if ((PCI_VENDOR(id) == PCI_VENDOR_SILMOTION) &&
356 (PCI_PRODUCT(id) == PCI_PRODUCT_SILMOTION_SM502) &&
357 (bar == 0x10)) {
358 r->r_flags = BUS_SPACE_MAP_LINEAR |
359 BUS_SPACE_MAP_PREFETCHABLE;
360 }
361 }
362 }
363
364 pa.pa_iot = sc->sc_iot;
365 pa.pa_memt = sc->sc_memt;
366 pa.pa_dmat = sc->sc_dmat;
367 pa.pa_dmat64 = sc->sc_dmat64;
368 pa.pa_pc = pc;
369 pa.pa_bus = bus;
370 pa.pa_device = device;
371 pa.pa_function = function;
372 pa.pa_tag = tag;
373 pa.pa_id = id;
374 pa.pa_class = pciclass;
375
376 /*
377 * Set up memory, I/O enable, and PCI command flags
378 * as appropriate.
379 */
380 pa.pa_flags = sc->sc_flags;
381
382 /*
383 * If the cache line size is not configured, then
384 * clear the MRL/MRM/MWI command-ok flags.
385 */
386 if (PCI_CACHELINE(bhlcr) == 0) {
387 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY|
388 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY);
389 }
390
391 if (sc->sc_bridgetag == NULL) {
392 pa.pa_intrswiz = 0;
393 pa.pa_intrtag = tag;
394 } else {
395 pa.pa_intrswiz = sc->sc_intrswiz + device;
396 pa.pa_intrtag = sc->sc_intrtag;
397 }
398
399 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
400
401 pin = PCI_INTERRUPT_PIN(intr);
402 pa.pa_rawintrpin = pin;
403 if (pin == PCI_INTERRUPT_PIN_NONE) {
404 /* no interrupt */
405 pa.pa_intrpin = 0;
406 } else {
407 /*
408 * swizzle it based on the number of busses we're
409 * behind and our device number.
410 */
411 pa.pa_intrpin = /* XXX */
412 ((pin + pa.pa_intrswiz - 1) % 4) + 1;
413 }
414 pa.pa_intrline = PCI_INTERRUPT_LINE(intr);
415
416 #ifdef __HAVE_PCI_MSI_MSIX
417 if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSIMAP, &off, &cap)) {
418 /*
419 * XXX Should we enable MSI mapping ourselves on
420 * systems that have it disabled?
421 */
422 if (cap & PCI_HT_MSI_ENABLED) {
423 uint64_t addr;
424 if ((cap & PCI_HT_MSI_FIXED) == 0) {
425 addr = pci_conf_read(pc, tag,
426 off + PCI_HT_MSI_ADDR_LO);
427 addr |= (uint64_t)pci_conf_read(pc, tag,
428 off + PCI_HT_MSI_ADDR_HI) << 32;
429 } else
430 addr = PCI_HT_MSI_FIXED_ADDR;
431
432 /*
433 * XXX This will fail to enable MSI on systems
434 * that don't use the canonical address.
435 */
436 if (addr == PCI_HT_MSI_FIXED_ADDR) {
437 pa.pa_flags |= PCI_FLAGS_MSI_OKAY;
438 pa.pa_flags |= PCI_FLAGS_MSIX_OKAY;
439 } else
440 aprint_verbose_dev(sc->sc_dev,
441 "HyperTransport MSI mapping is not supported yet. Disable MSI/MSI-X.\n");
442 }
443 }
444 #endif
445
446 if (match != NULL) {
447 ret = (*match)(&pa);
448 if (ret != 0 && pap != NULL)
449 *pap = pa;
450 } else {
451 struct pci_child *c;
452 locs[PCICF_DEV] = device;
453 locs[PCICF_FUNCTION] = function;
454
455 c = &sc->PCI_SC_DEVICESC(device, function);
456 pci_conf_capture(pc, tag, &c->c_conf);
457 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0)
458 c->c_psok = true;
459 else
460 c->c_psok = false;
461
462 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa,
463 pciprint, config_stdsubmatch);
464
465 ret = (c->c_dev != NULL);
466 }
467
468 return ret;
469 }
470
471 void
pcidevdetached(device_t self,device_t child)472 pcidevdetached(device_t self, device_t child)
473 {
474 struct pci_softc *sc = device_private(self);
475 int d, f;
476 pcitag_t tag;
477 struct pci_child *c;
478
479 d = device_locator(child, PCICF_DEV);
480 f = device_locator(child, PCICF_FUNCTION);
481
482 c = &sc->PCI_SC_DEVICESC(d, f);
483
484 KASSERT(c->c_dev == child);
485
486 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f);
487 if (c->c_psok)
488 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate);
489 pci_conf_restore(sc->sc_pc, tag, &c->c_conf);
490 c->c_dev = NULL;
491 }
492
493 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc),
494 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached,
495 DVF_DETACH_SHUTDOWN);
496
497 int
pci_get_capability(pci_chipset_tag_t pc,pcitag_t tag,int capid,int * offset,pcireg_t * value)498 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid,
499 int *offset, pcireg_t *value)
500 {
501 pcireg_t reg;
502 unsigned int ofs;
503
504 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
505 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT))
506 return 0;
507
508 /* Determine the Capability List Pointer register to start with. */
509 reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
510 switch (PCI_HDRTYPE_TYPE(reg)) {
511 case 0: /* standard device header */
512 case 1: /* PCI-PCI bridge header */
513 ofs = PCI_CAPLISTPTR_REG;
514 break;
515 case 2: /* PCI-CardBus Bridge header */
516 ofs = PCI_CARDBUS_CAPLISTPTR_REG;
517 break;
518 default:
519 return 0;
520 }
521
522 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs));
523 while (ofs != 0) {
524 if ((ofs & 3) || (ofs < 0x40)) {
525 int bus, device, function;
526
527 pci_decompose_tag(pc, tag, &bus, &device, &function);
528
529 printf("Skipping broken PCI header on %d:%d:%d\n",
530 bus, device, function);
531 break;
532 }
533 reg = pci_conf_read(pc, tag, ofs);
534 if (PCI_CAPLIST_CAP(reg) == capid) {
535 if (offset)
536 *offset = ofs;
537 if (value)
538 *value = reg;
539 return 1;
540 }
541 ofs = PCI_CAPLIST_NEXT(reg);
542 }
543
544 return 0;
545 }
546
547 int
pci_get_ht_capability(pci_chipset_tag_t pc,pcitag_t tag,int capid,int * offset,pcireg_t * value)548 pci_get_ht_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid,
549 int *offset, pcireg_t *value)
550 {
551 pcireg_t reg;
552 unsigned int ofs;
553
554 if (pci_get_capability(pc, tag, PCI_CAP_LDT, &ofs, NULL) == 0)
555 return 0;
556
557 while (ofs != 0) {
558 #ifdef DIAGNOSTIC
559 if ((ofs & 3) || (ofs < 0x40))
560 panic("pci_get_ht_capability");
561 #endif
562 reg = pci_conf_read(pc, tag, ofs);
563 if (PCI_HT_CAP(reg) == capid) {
564 if (offset)
565 *offset = ofs;
566 if (value)
567 *value = reg;
568 return 1;
569 }
570 ofs = PCI_CAPLIST_NEXT(reg);
571 }
572
573 return 0;
574 }
575
576 /*
577 * return number of the devices's MSI vectors
578 * return 0 if the device does not support MSI
579 */
580 int
pci_msi_count(pci_chipset_tag_t pc,pcitag_t tag)581 pci_msi_count(pci_chipset_tag_t pc, pcitag_t tag)
582 {
583 pcireg_t reg;
584 uint32_t mmc;
585 int count, offset;
586
587 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &offset, NULL) == 0)
588 return 0;
589
590 reg = pci_conf_read(pc, tag, offset + PCI_MSI_CTL);
591 mmc = PCI_MSI_CTL_MMC(reg);
592 count = 1 << mmc;
593 if (count > PCI_MSI_MAX_VECTORS) {
594 aprint_error("detect an illegal device! The device use reserved MMC values.\n");
595 return 0;
596 }
597
598 return count;
599 }
600
601 /*
602 * return number of the devices's MSI-X vectors
603 * return 0 if the device does not support MSI-X
604 */
605 int
pci_msix_count(pci_chipset_tag_t pc,pcitag_t tag)606 pci_msix_count(pci_chipset_tag_t pc, pcitag_t tag)
607 {
608 pcireg_t reg;
609 int offset;
610
611 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &offset, NULL) == 0)
612 return 0;
613
614 reg = pci_conf_read(pc, tag, offset + PCI_MSIX_CTL);
615
616 return PCI_MSIX_CTL_TBLSIZE(reg);
617 }
618
619 int
pci_get_ext_capability(pci_chipset_tag_t pc,pcitag_t tag,int capid,int * offset,pcireg_t * value)620 pci_get_ext_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid,
621 int *offset, pcireg_t *value)
622 {
623 pcireg_t reg;
624 unsigned int ofs;
625
626 /* Only supported for PCI-express devices */
627 if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, NULL, NULL))
628 return 0;
629
630 ofs = PCI_EXTCAPLIST_BASE;
631 reg = pci_conf_read(pc, tag, ofs);
632 if (reg == 0xffffffff || reg == 0)
633 return 0;
634
635 for (;;) {
636 #ifdef DIAGNOSTIC
637 if ((ofs & 3) || ofs < PCI_EXTCAPLIST_BASE)
638 panic("%s: invalid offset %u", __func__, ofs);
639 #endif
640 if (PCI_EXTCAPLIST_CAP(reg) == capid) {
641 if (offset != NULL)
642 *offset = ofs;
643 if (value != NULL)
644 *value = reg;
645 return 1;
646 }
647 ofs = PCI_EXTCAPLIST_NEXT(reg);
648 if (ofs == 0)
649 break;
650 reg = pci_conf_read(pc, tag, ofs);
651 }
652
653 return 0;
654 }
655
656 int
pci_find_device(struct pci_attach_args * pa,int (* match)(const struct pci_attach_args *))657 pci_find_device(struct pci_attach_args *pa,
658 int (*match)(const struct pci_attach_args *))
659 {
660 extern struct cfdriver pci_cd;
661 device_t pcidev;
662 int i;
663 static const int wildcard[2] = {
664 PCICF_DEV_DEFAULT,
665 PCICF_FUNCTION_DEFAULT
666 };
667
668 for (i = 0; i < pci_cd.cd_ndevs; i++) {
669 pcidev = device_lookup(&pci_cd, i);
670 if (pcidev != NULL &&
671 pci_enumerate_bus(device_private(pcidev), wildcard,
672 match, pa) != 0)
673 return 1;
674 }
675 return 0;
676 }
677
678 #ifndef PCI_MACHDEP_ENUMERATE_BUS
679 /*
680 * Generic PCI bus enumeration routine. Used unless machine-dependent
681 * code needs to provide something else.
682 */
683 int
pci_enumerate_bus(struct pci_softc * sc,const int * locators,int (* match)(const struct pci_attach_args *),struct pci_attach_args * pap)684 pci_enumerate_bus(struct pci_softc *sc, const int *locators,
685 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap)
686 {
687 pci_chipset_tag_t pc = sc->sc_pc;
688 int device, function, nfunctions, ret;
689 const struct pci_quirkdata *qd;
690 pcireg_t id, bhlcr;
691 pcitag_t tag;
692 uint8_t devs[32];
693 int i, n;
694
695 n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs));
696 for (i = 0; i < n; i++) {
697 device = devs[i];
698
699 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) &&
700 (locators[PCICF_DEV] != device))
701 continue;
702
703 tag = pci_make_tag(pc, sc->sc_bus, device, 0);
704
705 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG);
706 if (PCI_HDRTYPE_TYPE(bhlcr) > 2)
707 continue;
708
709 id = pci_conf_read(pc, tag, PCI_ID_REG);
710
711 /* Invalid vendor ID value? */
712 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
713 continue;
714 /* XXX Not invalid, but we've done this ~forever. */
715 if (PCI_VENDOR(id) == 0)
716 continue;
717
718 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id));
719
720 if (qd != NULL &&
721 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)
722 nfunctions = 8;
723 else if (qd != NULL &&
724 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0)
725 nfunctions = 1;
726 else
727 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1;
728
729 #ifdef __PCI_DEV_FUNCORDER
730 char funcs[8];
731 int j;
732 for (j = 0; j < nfunctions; j++) {
733 funcs[j] = j;
734 }
735 if (j < __arraycount(funcs))
736 funcs[j] = -1;
737 if (nfunctions > 1) {
738 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device,
739 nfunctions, funcs);
740 }
741 for (j = 0;
742 j < 8 && (function = funcs[j]) < 8 && function >= 0;
743 j++) {
744 #else
745 for (function = 0; function < nfunctions; function++) {
746 #endif
747 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT)
748 && (locators[PCICF_FUNCTION] != function))
749 continue;
750
751 if (qd != NULL &&
752 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0)
753 continue;
754 tag = pci_make_tag(pc, sc->sc_bus, device, function);
755 ret = pci_probe_device(sc, tag, match, pap);
756 if (match != NULL && ret != 0)
757 return ret;
758 }
759 }
760 return 0;
761 }
762 #endif /* PCI_MACHDEP_ENUMERATE_BUS */
763
764
765 /*
766 * Vital Product Data (PCI 2.2)
767 */
768
769 int
770 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count,
771 pcireg_t *data)
772 {
773 uint32_t reg;
774 int ofs, i, j;
775
776 KASSERT(data != NULL);
777 KASSERT((offset + count) < 0x7fff);
778
779 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0)
780 return 1;
781
782 for (i = 0; i < count; offset += sizeof(*data), i++) {
783 reg &= 0x0000ffff;
784 reg &= ~PCI_VPD_OPFLAG;
785 reg |= PCI_VPD_ADDRESS(offset);
786 pci_conf_write(pc, tag, ofs, reg);
787
788 /*
789 * PCI 2.2 does not specify how long we should poll
790 * for completion nor whether the operation can fail.
791 */
792 j = 0;
793 do {
794 if (j++ == 20)
795 return 1;
796 delay(4);
797 reg = pci_conf_read(pc, tag, ofs);
798 } while ((reg & PCI_VPD_OPFLAG) == 0);
799 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs));
800 }
801
802 return 0;
803 }
804
805 int
806 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count,
807 pcireg_t *data)
808 {
809 pcireg_t reg;
810 int ofs, i, j;
811
812 KASSERT(data != NULL);
813 KASSERT((offset + count) < 0x7fff);
814
815 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0)
816 return 1;
817
818 for (i = 0; i < count; offset += sizeof(*data), i++) {
819 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]);
820
821 reg &= 0x0000ffff;
822 reg |= PCI_VPD_OPFLAG;
823 reg |= PCI_VPD_ADDRESS(offset);
824 pci_conf_write(pc, tag, ofs, reg);
825
826 /*
827 * PCI 2.2 does not specify how long we should poll
828 * for completion nor whether the operation can fail.
829 */
830 j = 0;
831 do {
832 if (j++ == 20)
833 return 1;
834 delay(1);
835 reg = pci_conf_read(pc, tag, ofs);
836 } while (reg & PCI_VPD_OPFLAG);
837 }
838
839 return 0;
840 }
841
842 int
843 pci_dma64_available(const struct pci_attach_args *pa)
844 {
845 #ifdef _PCI_HAVE_DMA64
846 if (BUS_DMA_TAG_VALID(pa->pa_dmat64))
847 return 1;
848 #endif
849 return 0;
850 }
851
852 void
853 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag,
854 struct pci_conf_state *pcs)
855 {
856 int off;
857
858 for (off = 0; off < 16; off++)
859 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4));
860
861 return;
862 }
863
864 void
865 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag,
866 struct pci_conf_state *pcs)
867 {
868 int off;
869 pcireg_t val;
870
871 for (off = 15; off >= 0; off--) {
872 val = pci_conf_read(pc, tag, (off * 4));
873 if (val != pcs->reg[off])
874 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]);
875 }
876
877 return;
878 }
879
880 /*
881 * Power Management Capability (Rev 2.2)
882 */
883 static int
884 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state,
885 int offset)
886 {
887 pcireg_t value, now;
888
889 value = pci_conf_read(pc, tag, offset + PCI_PMCSR);
890 now = value & PCI_PMCSR_STATE_MASK;
891 switch (now) {
892 case PCI_PMCSR_STATE_D0:
893 case PCI_PMCSR_STATE_D1:
894 case PCI_PMCSR_STATE_D2:
895 case PCI_PMCSR_STATE_D3:
896 *state = now;
897 return 0;
898 default:
899 return EINVAL;
900 }
901 }
902
903 int
904 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state)
905 {
906 int offset;
907 pcireg_t value;
908
909 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value))
910 return EOPNOTSUPP;
911
912 return pci_get_powerstate_int(pc, tag, state, offset);
913 }
914
915 static int
916 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state,
917 int offset, pcireg_t cap_reg)
918 {
919 pcireg_t value, cap, now;
920
921 cap = cap_reg >> PCI_PMCR_SHIFT;
922 value = pci_conf_read(pc, tag, offset + PCI_PMCSR);
923 now = value & PCI_PMCSR_STATE_MASK;
924 value &= ~PCI_PMCSR_STATE_MASK;
925
926 if (now == state)
927 return 0;
928 switch (state) {
929 case PCI_PMCSR_STATE_D0:
930 break;
931 case PCI_PMCSR_STATE_D1:
932 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) {
933 printf("invalid transition from %d to D1\n", (int)now);
934 return EINVAL;
935 }
936 if (!(cap & PCI_PMCR_D1SUPP)) {
937 printf("D1 not supported\n");
938 return EOPNOTSUPP;
939 }
940 break;
941 case PCI_PMCSR_STATE_D2:
942 if (now == PCI_PMCSR_STATE_D3) {
943 printf("invalid transition from %d to D2\n", (int)now);
944 return EINVAL;
945 }
946 if (!(cap & PCI_PMCR_D2SUPP)) {
947 printf("D2 not supported\n");
948 return EOPNOTSUPP;
949 }
950 break;
951 case PCI_PMCSR_STATE_D3:
952 break;
953 default:
954 return EINVAL;
955 }
956 value |= state;
957 pci_conf_write(pc, tag, offset + PCI_PMCSR, value);
958 /* delay according to pcipm1.2, ch. 5.6.1 */
959 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3)
960 DELAY(10000);
961 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2)
962 DELAY(200);
963
964 return 0;
965 }
966
967 int
968 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state)
969 {
970 int offset;
971 pcireg_t value;
972
973 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) {
974 printf("pci_set_powerstate not supported\n");
975 return EOPNOTSUPP;
976 }
977
978 return pci_set_powerstate_int(pc, tag, state, offset, value);
979 }
980
981 int
982 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev,
983 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t))
984 {
985 pcireg_t pmode;
986 int error;
987
988 if ((error = pci_get_powerstate(pc, tag, &pmode)))
989 return error;
990
991 switch (pmode) {
992 case PCI_PMCSR_STATE_D0:
993 break;
994 case PCI_PMCSR_STATE_D3:
995 if (wakefun == NULL) {
996 /*
997 * The card has lost all configuration data in
998 * this state, so punt.
999 */
1000 aprint_error_dev(dev,
1001 "unable to wake up from power state D3\n");
1002 return EOPNOTSUPP;
1003 }
1004 /*FALLTHROUGH*/
1005 default:
1006 if (wakefun) {
1007 error = (*wakefun)(pc, tag, dev, pmode);
1008 if (error)
1009 return error;
1010 }
1011 aprint_normal_dev(dev, "waking up from power state D%d\n",
1012 pmode);
1013 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0)))
1014 return error;
1015 }
1016 return 0;
1017 }
1018
1019 int
1020 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag,
1021 device_t dev, pcireg_t state)
1022 {
1023 return 0;
1024 }
1025
1026 struct pci_child_power {
1027 struct pci_conf_state p_pciconf;
1028 pci_chipset_tag_t p_pc;
1029 pcitag_t p_tag;
1030 bool p_has_pm;
1031 int p_pm_offset;
1032 pcireg_t p_pm_cap;
1033 pcireg_t p_class;
1034 pcireg_t p_csr;
1035 };
1036
1037 static bool
1038 pci_child_suspend(device_t dv, const pmf_qual_t *qual)
1039 {
1040 struct pci_child_power *priv = device_pmf_bus_private(dv);
1041 pcireg_t ocsr, csr;
1042
1043 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf);
1044
1045 if (!priv->p_has_pm)
1046 return true; /* ??? hopefully handled by ACPI */
1047 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY)
1048 return true; /* XXX */
1049
1050 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */
1051 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG);
1052 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE
1053 | PCI_COMMAND_MASTER_ENABLE);
1054 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr);
1055 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag,
1056 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) {
1057 pci_conf_write(priv->p_pc, priv->p_tag,
1058 PCI_COMMAND_STATUS_REG, ocsr);
1059 aprint_error_dev(dv, "unsupported state, continuing.\n");
1060 return false;
1061 }
1062 return true;
1063 }
1064
1065 static bool
1066 pci_child_resume(device_t dv, const pmf_qual_t *qual)
1067 {
1068 struct pci_child_power *priv = device_pmf_bus_private(dv);
1069
1070 if (priv->p_has_pm &&
1071 pci_set_powerstate_int(priv->p_pc, priv->p_tag,
1072 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) {
1073 aprint_error_dev(dv, "unsupported state, continuing.\n");
1074 return false;
1075 }
1076
1077 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf);
1078
1079 return true;
1080 }
1081
1082 static bool
1083 pci_child_shutdown(device_t dv, int how)
1084 {
1085 struct pci_child_power *priv = device_pmf_bus_private(dv);
1086 pcireg_t csr;
1087
1088 /* restore original bus-mastering state */
1089 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG);
1090 csr &= ~PCI_COMMAND_MASTER_ENABLE;
1091 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE;
1092 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr);
1093 return true;
1094 }
1095
1096 static void
1097 pci_child_deregister(device_t dv)
1098 {
1099 struct pci_child_power *priv = device_pmf_bus_private(dv);
1100
1101 free(priv, M_DEVBUF);
1102 }
1103
1104 static bool
1105 pci_child_register(device_t child)
1106 {
1107 device_t self = device_parent(child);
1108 struct pci_softc *sc = device_private(self);
1109 struct pci_child_power *priv;
1110 int device, function, off;
1111 pcireg_t reg;
1112
1113 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK);
1114
1115 device = device_locator(child, PCICF_DEV);
1116 function = device_locator(child, PCICF_FUNCTION);
1117
1118 priv->p_pc = sc->sc_pc;
1119 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device,
1120 function);
1121 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG);
1122 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag,
1123 PCI_COMMAND_STATUS_REG);
1124
1125 if (pci_get_capability(priv->p_pc, priv->p_tag,
1126 PCI_CAP_PWRMGMT, &off, ®)) {
1127 priv->p_has_pm = true;
1128 priv->p_pm_offset = off;
1129 priv->p_pm_cap = reg;
1130 } else {
1131 priv->p_has_pm = false;
1132 priv->p_pm_offset = -1;
1133 }
1134
1135 device_pmf_bus_register(child, priv, pci_child_suspend,
1136 pci_child_resume, pci_child_shutdown, pci_child_deregister);
1137
1138 return true;
1139 }
1140
1141 MODULE(MODULE_CLASS_DRIVER, pci, NULL);
1142
1143 static int
1144 pci_modcmd(modcmd_t cmd, void *priv)
1145 {
1146 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI)
1147 return 0;
1148 return ENOTTY;
1149 }
1150