1 /* $NetBSD: radeonfb.c,v 1.88 2014/11/05 19:39:17 macallan Exp $ */
2
3 /*-
4 * Copyright (c) 2006 Itronix Inc.
5 * All rights reserved.
6 *
7 * Written by Garrett D'Amore for Itronix Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of Itronix Inc. may not be used to endorse
18 * or promote products derived from this software without specific
19 * prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS
22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and
36 * does not endorse, this software. ATI will not be responsible or liable
37 * for any actual or alleged damage or loss caused by or in connection with
38 * the use of or reliance on this software.
39 */
40
41 /*
42 * Portions of this code were taken from XFree86's Radeon driver, which bears
43 * this notice:
44 *
45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
46 * VA Linux Systems Inc., Fremont, California.
47 *
48 * All Rights Reserved.
49 *
50 * Permission is hereby granted, free of charge, to any person obtaining
51 * a copy of this software and associated documentation files (the
52 * "Software"), to deal in the Software without restriction, including
53 * without limitation on the rights to use, copy, modify, merge,
54 * publish, distribute, sublicense, and/or sell copies of the Software,
55 * and to permit persons to whom the Software is furnished to do so,
56 * subject to the following conditions:
57 *
58 * The above copyright notice and this permission notice (including the
59 * next paragraph) shall be included in all copies or substantial
60 * portions of the Software.
61 *
62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
69 * DEALINGS IN THE SOFTWARE.
70 */
71
72 #include <sys/cdefs.h>
73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.88 2014/11/05 19:39:17 macallan Exp $");
74
75 #include <sys/param.h>
76 #include <sys/systm.h>
77 #include <sys/device.h>
78 #include <sys/malloc.h>
79 #include <sys/bus.h>
80 #include <sys/kernel.h>
81 #include <sys/lwp.h>
82 #include <sys/kauth.h>
83
84 #include <dev/wscons/wsdisplayvar.h>
85 #include <dev/wscons/wsconsio.h>
86 #include <dev/wsfont/wsfont.h>
87 #include <dev/rasops/rasops.h>
88 #include <dev/videomode/videomode.h>
89 #include <dev/videomode/edidvar.h>
90 #include <dev/wscons/wsdisplay_vconsvar.h>
91 #include <dev/pci/wsdisplay_pci.h>
92 #include <dev/wscons/wsdisplay_glyphcachevar.h>
93
94 #include <dev/pci/pcidevs.h>
95 #include <dev/pci/pcireg.h>
96 #include <dev/pci/pcivar.h>
97 #include <dev/pci/pciio.h>
98 #include <dev/pci/radeonfbreg.h>
99 #include <dev/pci/radeonfbvar.h>
100 #include "opt_radeonfb.h"
101 #include "opt_vcons.h"
102
103 #ifdef RADEONFB_DEPTH_32
104 #define RADEONFB_DEFAULT_DEPTH 32
105 #else
106 #define RADEONFB_DEFAULT_DEPTH 8
107 #endif
108
109 static int radeonfb_match(device_t, cfdata_t, void *);
110 static void radeonfb_attach(device_t, device_t, void *);
111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int,
112 struct lwp *);
113 static paddr_t radeonfb_mmap(void *, void *, off_t, int);
114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t);
115 static void radeonfb_loadbios(struct radeonfb_softc *,
116 const struct pci_attach_args *);
117
118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *,
119 uintmax_t);
120 static int radeonfb_getclocks(struct radeonfb_softc *);
121 static int radeonfb_gettmds(struct radeonfb_softc *);
122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t,
123 uint32_t *, uint32_t *);
124 static int radeonfb_getconnectors(struct radeonfb_softc *);
125 static const struct videomode *radeonfb_modelookup(const char *);
126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *);
127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int);
128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int);
129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int);
130 static void radeonfb_modeswitch(struct radeonfb_display *);
131 static void radeonfb_setcrtc(struct radeonfb_display *, int);
132 static void radeonfb_init_misc(struct radeonfb_softc *);
133 static void radeonfb_set_fbloc(struct radeonfb_softc *);
134 static void radeonfb_init_palette(struct radeonfb_display *);
135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *);
136
137 static int radeonfb_isblank(struct radeonfb_display *);
138 static void radeonfb_blank(struct radeonfb_display *, int);
139 static int radeonfb_set_cursor(struct radeonfb_display *,
140 struct wsdisplay_cursor *);
141 static int radeonfb_set_curpos(struct radeonfb_display *,
142 struct wsdisplay_curpos *);
143 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int);
144 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *);
145 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *);
146
147 /* acceleration support */
148 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty,
149 int width, int height, uint32_t color);
150 static void radeonfb_rectfill_a(void *, int, int, int, int, long);
151 static void radeonfb_bitblt(void *, int srcx, int srcy,
152 int dstx, int dsty, int width, int height, int rop);
153
154 /* hw cursor support */
155 static void radeonfb_cursor_cmap(struct radeonfb_display *);
156 static void radeonfb_cursor_shape(struct radeonfb_display *);
157 static void radeonfb_cursor_position(struct radeonfb_display *);
158 static void radeonfb_cursor_visible(struct radeonfb_display *);
159 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned);
160
161 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int);
162 static void radeonfb_engine_idle(struct radeonfb_softc *);
163 static void radeonfb_engine_flush(struct radeonfb_softc *);
164 static void radeonfb_engine_reset(struct radeonfb_softc *);
165 static void radeonfb_engine_init(struct radeonfb_display *);
166 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused;
167
168 static void radeonfb_eraserows(void *, int, int, long);
169 static void radeonfb_erasecols(void *, int, int, int, long);
170 static void radeonfb_copyrows(void *, int, int, int);
171 static void radeonfb_copycols(void *, int, int, int, int);
172 static void radeonfb_cursor(void *, int, int, int);
173 static void radeonfb_putchar(void *, int, int, unsigned, long);
174 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long);
175 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long);
176 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR
177 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long);
178 #endif
179
180 static int radeonfb_set_backlight(struct radeonfb_display *, int);
181 static int radeonfb_get_backlight(struct radeonfb_display *);
182 static void radeonfb_switch_backlight(struct radeonfb_display *, int);
183 static void radeonfb_lvds_callout(void *);
184
185 static void radeonfb_brightness_up(device_t);
186 static void radeonfb_brightness_down(device_t);
187
188 static struct videomode *radeonfb_best_refresh(struct videomode *,
189 struct videomode *);
190 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *,
191 uint16_t *, int);
192 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *,
193 struct radeonfb_port *, int, int);
194
195 static int radeonfb_drm_print(void *, const char *);
196
197 #ifdef RADEONFB_DEBUG
198 int radeon_debug = 1;
199 #define DPRINTF(x) \
200 if (radeon_debug) printf x
201 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r)))
202 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r)))
203 #else
204 #define DPRINTF(x)
205 #define PRINTREG(r)
206 #define PRINTPLL(r)
207 #endif
208
209 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1))
210
211 #ifndef RADEON_DEFAULT_MODE
212 /* any reasonably modern display should handle this */
213 #define RADEON_DEFAULT_MODE "1024x768x60"
214 #endif
215
216 extern const u_char rasops_cmap[768];
217
218 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE;
219
220 static struct {
221 int size; /* minimum memory size (MB) */
222 int maxx; /* maximum x dimension */
223 int maxy; /* maximum y dimension */
224 int maxbpp; /* maximum bpp */
225 int maxdisp; /* maximum logical display count */
226 } radeonfb_limits[] = {
227 { 32, 2048, 1536, 32, 2 },
228 { 16, 1600, 1200, 32, 2 },
229 { 8, 1600, 1200, 32, 1 },
230 { 0, 0, 0, 0, 0 },
231 };
232
233 static struct wsscreen_descr radeonfb_stdscreen = {
234 "fb", /* name */
235 0, 0, /* ncols, nrows */
236 NULL, /* textops */
237 8, 16, /* fontwidth, fontheight */
238 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */
239 0, /* modecookie */
240 };
241
242 struct wsdisplay_accessops radeonfb_accessops = {
243 radeonfb_ioctl,
244 radeonfb_mmap,
245 NULL, /* vcons_alloc_screen */
246 NULL, /* vcons_free_screen */
247 NULL, /* vcons_show_screen */
248 NULL, /* load_font */
249 NULL, /* pollc */
250 NULL, /* scroll */
251 };
252
253 static struct {
254 uint16_t devid;
255 uint16_t family;
256 uint16_t flags;
257 } radeonfb_devices[] =
258 {
259 /* R100 family */
260 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 },
261 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 },
262 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 },
263 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 },
264
265 /* RV100 family */
266 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB },
267 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB },
268 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 },
269 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 },
270
271 /* RS100 family */
272 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 },
273 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB },
274
275 /* RS200/RS250 family */
276 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB },
277 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 },
278 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB },
279 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 },
280
281 /* R200 family */
282 /* add more R200 products? , 5148 */
283 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 },
284 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 },
285 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 },
286 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 },
287 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 },
288
289 /* RV200 family */
290 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB },
291 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB },
292 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 },
293 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 },
294
295 /* RV250 family */
296 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 },
297 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 },
298 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB },
299 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB },
300 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB },
301
302 /* RS300 family */
303 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 },
304 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 },
305 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 },
306 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB },
307
308 /* RV280 family */
309 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 },
310 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 },
311 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 },
312 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 },
313 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 },
314 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB },
315 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB },
316
317 /* R300 family */
318 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 },
319 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 },
320 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 },
321 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 },
322 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 },
323 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 },
324 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 },
325 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 },
326
327 /* RV350/RV360 family */
328 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 },
329 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 },
330 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 },
331 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 },
332 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 },
333 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 },
334 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB },
335 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB },
336 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB },
337 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB },
338 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB },
339 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB },
340
341 /* R350/R360 family */
342 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 },
343 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 },
344 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 },
345 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 },
346 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 },
347 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 },
348 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 },
349 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 },
350
351 /* RV380/RV370 family */
352 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB },
353 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB },
354 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 },
355 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 },
356 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB },
357 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB },
358 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 },
359 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 },
360 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 },
361 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 },
362
363 #if notyet
364 /* R420/R423 family */
365 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 },
366 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 },
367 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 },
368 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 },
369 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 },
370 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 },
371 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB },
372 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 },
373 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 },
374 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 },
375 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 },
376 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 },
377 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 },
378 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 },
379 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 },
380 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 },
381 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 },
382 #endif
383 { 0, 0, 0 }
384 };
385
386 static struct {
387 int divider;
388 int mask;
389 } radeonfb_dividers[] = {
390 { 16, 5 },
391 { 12, 7 },
392 { 8, 3 },
393 { 6, 6 },
394 { 4, 2 },
395 { 3, 4 },
396 { 2, 1 },
397 { 1, 0 },
398 { 0, 0 }
399 };
400
401 /*
402 * This table taken from X11.
403 */
404 static const struct {
405 int family;
406 struct radeon_tmds_pll plls[4];
407 } radeonfb_tmds_pll[] = {
408 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}},
409 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}},
410 { RADEON_RS100, {{0, 0}}},
411 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}},
412 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}},
413 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}},
414 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}},
415 { RADEON_RS300, {{0, 0}}},
416 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}},
417 { RADEON_R300, {{-1, 0xb01cb}}},
418 { RADEON_R350, {{-1, 0xb01cb}}},
419 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}},
420 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}},
421 { RADEON_R420, {{-1, 0xb01cb}}},
422 };
423
424 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */
425
426
427 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc),
428 radeonfb_match, radeonfb_attach, NULL, NULL);
429
430 static int
radeonfb_match(device_t parent,cfdata_t match,void * aux)431 radeonfb_match(device_t parent, cfdata_t match, void *aux)
432 {
433 const struct pci_attach_args *pa = aux;
434 int i;
435
436 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI)
437 return 0;
438
439 for (i = 0; radeonfb_devices[i].devid; i++) {
440 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid)
441 return 100; /* high to defeat VGA/VESA */
442 }
443
444 return 0;
445 }
446
447 static void
radeonfb_attach(device_t parent,device_t dev,void * aux)448 radeonfb_attach(device_t parent, device_t dev, void *aux)
449 {
450 struct radeonfb_softc *sc = device_private(dev);
451 const struct pci_attach_args *pa = aux;
452 const char *mptr;
453 bus_size_t bsz;
454 pcireg_t screg;
455 int i, j, fg, bg, ul, flags;
456 uint32_t v;
457
458 sc->sc_dev = dev;
459 sc->sc_id = pa->pa_id;
460 for (i = 0; radeonfb_devices[i].devid; i++) {
461 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid)
462 break;
463 }
464
465 pci_aprint_devinfo(pa, NULL);
466
467 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev))));
468
469 KASSERT(radeonfb_devices[i].devid != 0);
470 sc->sc_pt = pa->pa_tag;
471 sc->sc_iot = pa->pa_iot;
472 sc->sc_pc = pa->pa_pc;
473 sc->sc_family = radeonfb_devices[i].family;
474 sc->sc_flags = radeonfb_devices[i].flags;
475
476 /* enable memory and IO access */
477 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG);
478 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
479 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg);
480
481 /*
482 * Some flags are general to entire chip families, and rather
483 * than clutter up the table with them, we go ahead and set
484 * them here.
485 */
486 switch (sc->sc_family) {
487 case RADEON_RS100:
488 case RADEON_RS200:
489 sc->sc_flags |= RFB_IGP | RFB_RV100;
490 break;
491
492 case RADEON_RV100:
493 case RADEON_RV200:
494 case RADEON_RV250:
495 case RADEON_RV280:
496 sc->sc_flags |= RFB_RV100;
497 break;
498
499 case RADEON_RS300:
500 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100;
501 break;
502
503 case RADEON_R300:
504 case RADEON_RV350:
505 case RADEON_R350:
506 case RADEON_RV380:
507 case RADEON_R420:
508 /* newer chips */
509 sc->sc_flags |= RFB_R300;
510 break;
511
512 case RADEON_R100:
513 sc->sc_flags |= RFB_NCRTC2;
514 break;
515 }
516
517 if ((sc->sc_family == RADEON_RV200) ||
518 (sc->sc_family == RADEON_RV250) ||
519 (sc->sc_family == RADEON_RV280) ||
520 (sc->sc_family == RADEON_RV350)) {
521 bool inverted = 0;
522 /* backlight level is linear */
523 DPRINTF(("found RV* chip, backlight is supposedly linear\n"));
524 prop_dictionary_get_bool(device_properties(sc->sc_dev),
525 "backlight_level_reverted", &inverted);
526 if (inverted) {
527 DPRINTF(("nope, it's inverted\n"));
528 sc->sc_flags |= RFB_INV_BLIGHT;
529 }
530 } else
531 sc->sc_flags |= RFB_INV_BLIGHT;
532
533 /*
534 * XXX: to support true multihead, this must change.
535 */
536 sc->sc_ndisplays = 1;
537
538 /* XXX: */
539 if (!HAS_CRTC2(sc)) {
540 sc->sc_ndisplays = 1;
541 }
542
543 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0,
544 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr,
545 &sc->sc_regsz) != 0) {
546 aprint_error("%s: unable to map registers!\n", XNAME(sc));
547 goto error;
548 }
549
550 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM,
551 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0)
552 {
553 aprint_error("%s: unable to find ROM!\n", XNAME(sc));
554 goto error;
555 }
556 sc->sc_romt = sc->sc_memt;
557
558 sc->sc_mapped = TRUE;
559
560 /* scratch register test... */
561 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) ||
562 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) {
563 aprint_error("%s: scratch register test failed!\n", XNAME(sc));
564 goto error;
565 }
566
567 PRINTREG(RADEON_CRTC_EXT_CNTL);
568 PRINTREG(RADEON_CRTC_GEN_CNTL);
569 PRINTREG(RADEON_CRTC2_GEN_CNTL);
570 PRINTREG(RADEON_DISP_OUTPUT_CNTL);
571 PRINTREG(RADEON_DAC_CNTL2);
572 PRINTREG(RADEON_FP_GEN_CNTL);
573 PRINTREG(RADEON_FP2_GEN_CNTL);
574
575 PRINTREG(RADEON_BIOS_4_SCRATCH);
576 PRINTREG(RADEON_FP_GEN_CNTL);
577 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL);
578 PRINTREG(RADEON_FP2_GEN_CNTL);
579 PRINTREG(RADEON_TMDS_CNTL);
580 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL);
581 PRINTREG(RADEON_TMDS_PLL_CNTL);
582 PRINTREG(RADEON_LVDS_GEN_CNTL);
583 PRINTREG(RADEON_FP_HORZ_STRETCH);
584 PRINTREG(RADEON_FP_VERT_STRETCH);
585
586 if (IS_RV100(sc))
587 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27);
588
589 /* XXX
590 * according to xf86-video-radeon R3xx has this bit backwards
591 */
592 if (IS_R300(sc)) {
593 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL,
594 0,
595 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST));
596 } else {
597 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL,
598 RADEON_TMDS_TRANSMITTER_PLLEN,
599 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST));
600 }
601
602 radeonfb_i2c_init(sc);
603
604 radeonfb_loadbios(sc, pa);
605
606 #ifdef RADEONFB_BIOS_INIT
607 if (radeonfb_bios_init(sc)) {
608 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc));
609 }
610 #endif
611
612 if (radeonfb_getclocks(sc)) {
613 aprint_error("%s: Unable to get reference clocks from BIOS\n",
614 XNAME(sc));
615 goto error;
616 }
617
618 if (radeonfb_gettmds(sc)) {
619 aprint_error("%s: Unable to identify TMDS PLL settings\n",
620 XNAME(sc));
621 goto error;
622 }
623
624 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d "
625 "minpll = %d, maxpll = %d\n", XNAME(sc),
626 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000,
627 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll);
628
629 radeonfb_getconnectors(sc);
630
631 radeonfb_set_fbloc(sc);
632
633 /* 64 MB should be enough -- more just wastes map entries */
634 if (sc->sc_memsz > (64 << 20))
635 sc->sc_memsz = (64 << 20);
636
637 for (i = 0; radeonfb_limits[i].size; i++) {
638 if (sc->sc_memsz >= radeonfb_limits[i].size) {
639 sc->sc_maxx = radeonfb_limits[i].maxx;
640 sc->sc_maxy = radeonfb_limits[i].maxy;
641 sc->sc_maxbpp = radeonfb_limits[i].maxbpp;
642 /* framebuffer offset, start at a 4K page */
643 sc->sc_fboffset = sc->sc_memsz /
644 radeonfb_limits[i].maxdisp;
645 /*
646 * we use the fbsize to figure out where we can store
647 * things like cursor data.
648 */
649 sc->sc_fbsize =
650 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 ,
651 RADEON_STRIDEALIGN) * sc->sc_maxy,
652 4096);
653 break;
654 }
655 }
656
657
658 radeonfb_init_misc(sc);
659
660 /* program the DAC wirings */
661 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) {
662 switch (sc->sc_ports[i].rp_dac_type) {
663 case RADEON_DAC_PRIMARY:
664 PATCH32(sc, RADEON_DAC_CNTL2,
665 i ? RADEON_DAC2_DAC_CLK_SEL : 0,
666 ~RADEON_DAC2_DAC_CLK_SEL);
667 break;
668 case RADEON_DAC_TVDAC:
669 /* we always use the TVDAC to drive a secondary analog
670 * CRT for now. if we ever support TV-out this will
671 * have to change.
672 */
673 SET32(sc, RADEON_DAC_CNTL2,
674 RADEON_DAC2_DAC2_CLK_SEL);
675 PATCH32(sc, RADEON_DISP_HW_DEBUG,
676 i ? 0 : RADEON_CRT2_DISP1_SEL,
677 ~RADEON_CRT2_DISP1_SEL);
678 /* we're using CRTC2 for the 2nd port */
679 if (sc->sc_ports[i].rp_number == 1) {
680 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL,
681 RADEON_DISP_DAC2_SOURCE_CRTC2,
682 ~RADEON_DISP_DAC2_SOURCE_MASK);
683 }
684
685 break;
686 }
687 DPRINTF(("%s: port %d tmds type %d\n", __func__, i,
688 sc->sc_ports[i].rp_tmds_type));
689 switch (sc->sc_ports[i].rp_tmds_type) {
690 case RADEON_TMDS_INT:
691 /* point FP0 at the CRTC this port uses */
692 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n",
693 __func__, sc->sc_ports[i].rp_number));
694 if (IS_R300(sc)) {
695 PATCH32(sc, RADEON_FP_GEN_CNTL,
696 sc->sc_ports[i].rp_number ?
697 R200_FP_SOURCE_SEL_CRTC2 :
698 R200_FP_SOURCE_SEL_CRTC1,
699 ~R200_FP_SOURCE_SEL_MASK);
700 } else {
701 PATCH32(sc, RADEON_FP_GEN_CNTL,
702 sc->sc_ports[i].rp_number ?
703 RADEON_FP_SEL_CRTC2 :
704 RADEON_FP_SEL_CRTC1,
705 ~RADEON_FP_SEL_MASK);
706 }
707 }
708 }
709 PRINTREG(RADEON_DAC_CNTL2);
710 PRINTREG(RADEON_DISP_HW_DEBUG);
711
712 /* other DAC programming */
713 v = GET32(sc, RADEON_DAC_CNTL);
714 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING);
715 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN;
716 PUT32(sc, RADEON_DAC_CNTL, v);
717 PRINTREG(RADEON_DAC_CNTL);
718
719 /* XXX: this may need more investigation */
720 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203);
721 PRINTREG(RADEON_TV_DAC_CNTL);
722
723 /* enable TMDS */
724 SET32(sc, RADEON_FP_GEN_CNTL,
725 RADEON_FP_TMDS_EN |
726 RADEON_FP_CRTC_DONT_SHADOW_VPAR |
727 RADEON_FP_CRTC_DONT_SHADOW_HEND);
728 /*
729 * XXX
730 * no idea why this is necessary - if I do not clear this bit on my
731 * iBook G4 the screen remains black, even though it's already clear.
732 * It needs to be set on my Sun XVR-100 for the DVI port to work
733 * TODO:
734 * see if this is still necessary now that CRTCs, DACs and outputs are
735 * getting wired up in a halfway sane way
736 */
737 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) {
738 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2);
739 } else {
740 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2);
741 }
742
743 /*
744 * we use bus_space_map instead of pci_mapreg, because we don't
745 * need the full aperature space. no point in wasting virtual
746 * address space we don't intend to use, right?
747 */
748 if ((sc->sc_memsz < (4096 * 1024)) ||
749 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM,
750 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) ||
751 (bsz < sc->sc_memsz)) {
752 sc->sc_memsz = 0;
753 aprint_error("%s: Bad frame buffer configuration\n",
754 XNAME(sc));
755 goto error;
756 }
757
758 sc->sc_memt = pa->pa_memt;
759 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz,
760 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) {
761 sc->sc_memsz = 0;
762 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc));
763 goto error;
764 }
765
766 aprint_normal("%s: %d MB aperture at 0x%08x, "
767 "%d KB registers at 0x%08x\n", XNAME(sc),
768 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr,
769 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr);
770
771 /* setup default video mode from devprop (allows PROM override) */
772 sc->sc_defaultmode = radeonfb_default_mode;
773 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev),
774 "videomode", &mptr)) {
775
776 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf));
777 sc->sc_defaultmode = sc->sc_modebuf;
778 }
779
780 /* initialize some basic display parameters */
781 for (i = 0; i < sc->sc_ndisplays; i++) {
782 struct radeonfb_display *dp = &sc->sc_displays[i];
783 struct rasops_info *ri;
784 long defattr;
785 struct wsemuldisplaydev_attach_args aa;
786
787 /*
788 * Figure out how many "displays" (desktops) we are going to
789 * support. If more than one, then each CRTC gets its own
790 * programming.
791 *
792 * XXX: this code needs to change to support mergedfb.
793 * XXX: would be nice to allow this to be overridden
794 */
795 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) {
796 DPRINTF(("dual crtcs!\n"));
797 dp->rd_ncrtcs = 2;
798 dp->rd_crtcs[0].rc_port =
799 &sc->sc_ports[0];
800 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number;
801 dp->rd_crtcs[1].rc_port =
802 &sc->sc_ports[1];
803 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number;
804 } else {
805 dp->rd_ncrtcs = 1;
806 dp->rd_crtcs[0].rc_port =
807 &sc->sc_ports[i];
808 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number;
809 }
810
811 dp->rd_softc = sc;
812 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL;
813 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */
814
815 /* for text mode, we pick a resolution that won't
816 * require panning */
817 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0);
818
819 aprint_normal("%s: display %d: "
820 "initial virtual resolution %dx%d at %d bpp\n",
821 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp);
822 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n",
823 sc->sc_fboffset >> 20);
824 /* now select the *video mode* that we will use */
825 for (j = 0; j < dp->rd_ncrtcs; j++) {
826 const struct videomode *vmp;
827 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port,
828 dp->rd_virtx, dp->rd_virty);
829
830 /*
831 * virtual resolution should be at least as high as
832 * physical
833 */
834 if (dp->rd_virtx < vmp->hdisplay ||
835 dp->rd_virty < vmp->vdisplay) {
836 dp->rd_virtx = vmp->hdisplay;
837 dp->rd_virty = vmp->vdisplay;
838 }
839
840 dp->rd_crtcs[j].rc_videomode = *vmp;
841 printf("%s: port %d: physical %dx%d %dHz\n",
842 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay,
843 DIVIDE(DIVIDE(vmp->dot_clock * 1000,
844 vmp->htotal), vmp->vtotal));
845 }
846
847 /* N.B.: radeon wants 64-byte aligned stride */
848 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8;
849 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN);
850 DPRINTF(("stride: %d\n", dp->rd_stride));
851
852 dp->rd_offset = sc->sc_fboffset * i;
853 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt,
854 sc->sc_memh) + dp->rd_offset;
855 dp->rd_curoff = sc->sc_fboffset - 4096; /* 4KB cursor space */
856 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff;
857
858 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr));
859
860 switch (dp->rd_bpp) {
861 case 8:
862 dp->rd_format = 2;
863 break;
864 case 32:
865 dp->rd_format = 6;
866 break;
867 default:
868 aprint_error("%s: bad depth %d\n", XNAME(sc),
869 dp->rd_bpp);
870 goto error;
871 }
872
873 DPRINTF(("init engine\n"));
874 /* XXX: this seems suspicious - per display engine
875 initialization? */
876 radeonfb_engine_init(dp);
877
878 /* copy the template into place */
879 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen;
880 dp->rd_wsscreens = dp->rd_wsscreens_storage;
881
882 /* and make up the list */
883 dp->rd_wsscreenlist.nscreens = 1;
884 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens;
885
886 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens,
887 &radeonfb_accessops);
888
889 dp->rd_vd.init_screen = radeonfb_init_screen;
890
891 #ifdef RADEONFB_DEBUG
892 dp->rd_virty -= 200;
893 #endif
894
895 dp->rd_console = 0;
896 prop_dictionary_get_bool(device_properties(sc->sc_dev),
897 "is_console", &dp->rd_console);
898
899 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC;
900
901
902 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen,
903 dp->rd_console, &defattr);
904
905 ri = &dp->rd_vscreen.scr_ri;
906
907 /* clear the screen */
908 rasops_unpack_attr(defattr, &fg, &bg, &ul);
909 dp->rd_bg = ri->ri_devcmap[bg & 0xf];
910 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height,
911 dp->rd_bg);
912
913 dp->rd_wsscreens->textops = &ri->ri_ops;
914 dp->rd_wsscreens->capabilities = ri->ri_caps;
915 dp->rd_wsscreens->nrows = ri->ri_rows;
916 dp->rd_wsscreens->ncols = ri->ri_cols;
917
918 #ifdef SPLASHSCREEN
919 dp->rd_splash.si_depth = ri->ri_depth;
920 dp->rd_splash.si_bits = ri->ri_bits;
921 dp->rd_splash.si_hwbits = ri->ri_hwbits;
922 dp->rd_splash.si_width = ri->ri_width;
923 dp->rd_splash.si_height = ri->ri_height;
924 dp->rd_splash.si_stride = ri->ri_stride;
925 dp->rd_splash.si_fillrect = NULL;
926 #endif
927 dp->rd_gc.gc_bitblt = radeonfb_bitblt;
928 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a;
929 dp->rd_gc.gc_rop = RADEON_ROP3_S;
930 dp->rd_gc.gc_blitcookie = dp;
931 /*
932 * use memory between framebuffer and cursor area as glyph
933 * cache, cap at 4096 lines
934 */
935 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4,
936 min(4096,
937 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)),
938 dp->rd_virtx,
939 ri->ri_font->fontwidth,
940 ri->ri_font->fontheight,
941 defattr);
942 if (dp->rd_console) {
943
944 radeonfb_modeswitch(dp);
945 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0,
946 defattr);
947 #ifdef SPLASHSCREEN
948 if (splash_render(&dp->rd_splash,
949 SPLASH_F_CENTER|SPLASH_F_FILL) == 0)
950 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen);
951 else
952 #endif
953 vcons_replay_msgbuf(&dp->rd_vscreen);
954 } else {
955
956 /*
957 * since we're not the console we can postpone
958 * the rest until someone actually allocates a
959 * screen for us. but we do clear the screen
960 * at least.
961 */
962 memset(ri->ri_bits, 0, 1024);
963
964 radeonfb_modeswitch(dp);
965 #ifdef SPLASHSCREEN
966 if (splash_render(&dp->rd_splash,
967 SPLASH_F_CENTER|SPLASH_F_FILL) == 0)
968 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen);
969 #endif
970 }
971
972 aa.console = dp->rd_console;
973 aa.scrdata = &dp->rd_wsscreenlist;
974 aa.accessops = &radeonfb_accessops;
975 aa.accesscookie = &dp->rd_vd;
976
977 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint);
978
979 radeonfb_blank(dp, 0);
980
981 /* Initialise delayed lvds operations for backlight. */
982 callout_init(&dp->rd_bl_lvds_co, 0);
983 callout_setfunc(&dp->rd_bl_lvds_co,
984 radeonfb_lvds_callout, dp);
985 dp->rd_bl_on = 1;
986 dp->rd_bl_level = radeonfb_get_backlight(dp);
987 radeonfb_set_backlight(dp, dp->rd_bl_level);
988 }
989
990 for (i = 0; i < RADEON_NDISPLAYS; i++)
991 radeonfb_init_palette(&sc->sc_displays[i]);
992
993 if (HAS_CRTC2(sc)) {
994 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS);
995 }
996
997 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS);
998 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON);
999 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP,
1000 radeonfb_brightness_up, TRUE);
1001 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN,
1002 radeonfb_brightness_down, TRUE);
1003
1004 /*
1005 * if we attach a DRM we need to unmap registers in
1006 * WSDISPLAYIO_MODE_MAPPED, since this keeps us from doing things like
1007 * screen blanking we only do it if needed
1008 */
1009 sc->sc_needs_unmap =
1010 (config_found_ia(dev, "drm", aux, radeonfb_drm_print) != 0);
1011 DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap));
1012
1013 PRINTREG(RADEON_CRTC_EXT_CNTL);
1014 PRINTREG(RADEON_CRTC_GEN_CNTL);
1015 PRINTREG(RADEON_CRTC2_GEN_CNTL);
1016 PRINTREG(RADEON_DISP_OUTPUT_CNTL);
1017 PRINTREG(RADEON_DAC_CNTL2);
1018 PRINTREG(RADEON_FP_GEN_CNTL);
1019 PRINTREG(RADEON_FP2_GEN_CNTL);
1020
1021 return;
1022
1023 error:
1024 if (sc->sc_biossz)
1025 free(sc->sc_bios, M_DEVBUF);
1026
1027 if (sc->sc_regsz)
1028 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz);
1029
1030 if (sc->sc_memsz)
1031 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz);
1032 }
1033
1034 static void
radeonfb_map(struct radeonfb_softc * sc)1035 radeonfb_map(struct radeonfb_softc *sc)
1036 {
1037 if (!sc->sc_mapped) {
1038 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0,
1039 &sc->sc_regh) != 0) {
1040 aprint_error_dev(sc->sc_dev,
1041 "unable to map registers!\n");
1042 return;
1043 }
1044 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz,
1045 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) {
1046 sc->sc_memsz = 0;
1047 aprint_error_dev(sc->sc_dev,
1048 "Unable to map frame buffer\n");
1049 return;
1050 }
1051 sc->sc_mapped = TRUE;
1052 }
1053 }
1054
1055 static void
radeonfb_unmap(struct radeonfb_softc * sc)1056 radeonfb_unmap(struct radeonfb_softc *sc)
1057 {
1058 if (!sc->sc_needs_unmap)
1059 return;
1060
1061 if (sc->sc_mapped) {
1062 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz);
1063 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz);
1064 sc->sc_mapped = FALSE;
1065 }
1066 }
1067
1068 static int
radeonfb_drm_print(void * aux,const char * pnp)1069 radeonfb_drm_print(void *aux, const char *pnp)
1070 {
1071 if (pnp)
1072 aprint_normal("drm at %s", pnp);
1073 return (UNCONF);
1074 }
1075
1076 int
radeonfb_ioctl(void * v,void * vs,unsigned long cmd,void * d,int flag,struct lwp * l)1077 radeonfb_ioctl(void *v, void *vs,
1078 unsigned long cmd, void *d, int flag, struct lwp *l)
1079 {
1080 struct vcons_data *vd;
1081 struct radeonfb_display *dp;
1082 struct radeonfb_softc *sc;
1083 struct wsdisplay_param *param;
1084 struct vcons_screen *ms;
1085
1086 vd = (struct vcons_data *)v;
1087 ms = vd->active;
1088 dp = (struct radeonfb_display *)vd->cookie;
1089 sc = dp->rd_softc;
1090
1091 /* can't do these without registers being mapped */
1092 if (!sc->sc_mapped) {
1093 switch (cmd) {
1094 case WSDISPLAYIO_GVIDEO:
1095 case WSDISPLAYIO_SVIDEO:
1096 case WSDISPLAYIO_GETCMAP:
1097 case WSDISPLAYIO_PUTCMAP:
1098 case WSDISPLAYIO_SCURSOR:
1099 case WSDISPLAYIO_GCURPOS:
1100 case WSDISPLAYIO_SCURPOS:
1101 case WSDISPLAYIO_SETPARAM:
1102 return EINVAL;
1103 }
1104 }
1105
1106 switch (cmd) {
1107 case WSDISPLAYIO_GTYPE:
1108 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC;
1109 return 0;
1110
1111 case WSDISPLAYIO_GINFO:
1112 if (vd->active != NULL) {
1113 struct wsdisplay_fbinfo *fb;
1114 fb = (struct wsdisplay_fbinfo *)d;
1115 fb->width = dp->rd_virtx;
1116 fb->height = dp->rd_virty;
1117 fb->depth = dp->rd_bpp;
1118 fb->cmsize = 256;
1119 return 0;
1120 } else
1121 return ENODEV;
1122 case WSDISPLAYIO_GVIDEO:
1123 if (radeonfb_isblank(dp))
1124 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF;
1125 else
1126 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON;
1127 return 0;
1128
1129 case WSDISPLAYIO_SVIDEO:
1130 radeonfb_blank(dp,
1131 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF));
1132 radeonfb_switch_backlight(dp,
1133 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON));
1134 return 0;
1135
1136 case WSDISPLAYIO_GETCMAP:
1137 if (dp->rd_bpp == 8)
1138 return radeonfb_getcmap(dp,
1139 (struct wsdisplay_cmap *)d);
1140 return EINVAL;
1141
1142 case WSDISPLAYIO_PUTCMAP:
1143 if (dp->rd_bpp == 8)
1144 return radeonfb_putcmap(dp,
1145 (struct wsdisplay_cmap *)d);
1146 return EINVAL;
1147
1148 case WSDISPLAYIO_LINEBYTES:
1149 *(unsigned *)d = dp->rd_stride;
1150 return 0;
1151
1152 case WSDISPLAYIO_SMODE:
1153 if (*(int *)d != dp->rd_wsmode) {
1154 dp->rd_wsmode = *(int *)d;
1155 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) ||
1156 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB))
1157 radeonfb_map(sc);
1158
1159 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) &&
1160 (dp->rd_vd.active)) {
1161 radeonfb_engine_init(dp);
1162 glyphcache_wipe(&dp->rd_gc);
1163 radeonfb_init_palette(dp);
1164 radeonfb_modeswitch(dp);
1165 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx,
1166 dp->rd_virty, dp->rd_bg);
1167 vcons_redraw_screen(dp->rd_vd.active);
1168 }
1169 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED)
1170 radeonfb_unmap(sc);
1171 }
1172 return 0;
1173
1174 case WSDISPLAYIO_GCURMAX:
1175 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX;
1176 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY;
1177 return 0;
1178
1179 case WSDISPLAYIO_SCURSOR:
1180 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d);
1181
1182 case WSDISPLAYIO_GCURSOR:
1183 return EPASSTHROUGH;
1184
1185 case WSDISPLAYIO_GCURPOS:
1186 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x;
1187 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y;
1188 return 0;
1189
1190 case WSDISPLAYIO_SCURPOS:
1191 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d);
1192
1193 case WSDISPLAYIO_SSPLASH:
1194 #if defined(SPLASHSCREEN)
1195 if (*(int *)d == 1) {
1196 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen);
1197 splash_render(&dp->rd_splash,
1198 SPLASH_F_CENTER|SPLASH_F_FILL);
1199 } else
1200 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen);
1201 return 0;
1202 #else
1203 return ENODEV;
1204 #endif
1205 case WSDISPLAYIO_GETPARAM:
1206 param = (struct wsdisplay_param *)d;
1207 switch (param->param) {
1208 case WSDISPLAYIO_PARAM_BRIGHTNESS:
1209 param->min = 0;
1210 param->max = 255;
1211 param->curval = dp->rd_bl_level;
1212 return 0;
1213 case WSDISPLAYIO_PARAM_BACKLIGHT:
1214 param->min = 0;
1215 param->max = RADEONFB_BACKLIGHT_MAX;
1216 param->curval = dp->rd_bl_on;
1217 return 0;
1218 }
1219 return EPASSTHROUGH;
1220
1221 case WSDISPLAYIO_SETPARAM:
1222 param = (struct wsdisplay_param *)d;
1223 switch (param->param) {
1224 case WSDISPLAYIO_PARAM_BRIGHTNESS:
1225 radeonfb_set_backlight(dp, param->curval);
1226 return 0;
1227 case WSDISPLAYIO_PARAM_BACKLIGHT:
1228 radeonfb_switch_backlight(dp, param->curval);
1229 return 0;
1230 }
1231 return EPASSTHROUGH;
1232
1233 /* PCI config read/write passthrough. */
1234 case PCI_IOC_CFGREAD:
1235 case PCI_IOC_CFGWRITE:
1236 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l);
1237
1238 case WSDISPLAYIO_GET_BUSID:
1239 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc,
1240 sc->sc_pt, d);
1241
1242 case WSDISPLAYIO_GET_EDID: {
1243 struct wsdisplayio_edid_info *ei = d;
1244 return wsdisplayio_get_edid(sc->sc_dev, ei);
1245 }
1246
1247 case WSDISPLAYIO_GET_FBINFO: {
1248 struct wsdisplayio_fbinfo *fbi = d;
1249 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi);
1250 }
1251
1252 default:
1253 return EPASSTHROUGH;
1254 }
1255 }
1256
1257 paddr_t
radeonfb_mmap(void * v,void * vs,off_t offset,int prot)1258 radeonfb_mmap(void *v, void *vs, off_t offset, int prot)
1259 {
1260 struct vcons_data *vd;
1261 struct radeonfb_display *dp;
1262 struct radeonfb_softc *sc;
1263 paddr_t pa;
1264
1265 vd = (struct vcons_data *)v;
1266 dp = (struct radeonfb_display *)vd->cookie;
1267 sc = dp->rd_softc;
1268
1269 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) {
1270 pa = bus_space_mmap(sc->sc_memt,
1271 sc->sc_memaddr + dp->rd_offset + offset, 0,
1272 prot, BUS_SPACE_MAP_LINEAR);
1273 return pa;
1274 }
1275
1276 /*
1277 * restrict all other mappings to processes with superuser privileges
1278 * or the kernel itself
1279 */
1280 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM,
1281 NULL, NULL, NULL, NULL) != 0) {
1282 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n");
1283 return -1;
1284 }
1285
1286 if ((offset >= sc->sc_regaddr) &&
1287 (offset < sc->sc_regaddr + sc->sc_regsz)) {
1288 return bus_space_mmap(sc->sc_regt, offset, 0, prot,
1289 BUS_SPACE_MAP_LINEAR);
1290 }
1291
1292 if ((offset >= sc->sc_memaddr) &&
1293 (offset < sc->sc_memaddr + sc->sc_memsz)) {
1294 return bus_space_mmap(sc->sc_memt, offset, 0, prot,
1295 BUS_SPACE_MAP_LINEAR);
1296 }
1297
1298 if ((offset >= sc->sc_romaddr) &&
1299 (offset < sc->sc_romaddr + sc->sc_romsz)) {
1300 return bus_space_mmap(sc->sc_memt, offset, 0, prot,
1301 BUS_SPACE_MAP_LINEAR);
1302 }
1303
1304 #ifdef PCI_MAGIC_IO_RANGE
1305 /* allow mapping of IO space */
1306 if ((offset >= PCI_MAGIC_IO_RANGE) &&
1307 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) {
1308 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE,
1309 0, prot, 0);
1310 return pa;
1311 }
1312 #endif /* PCI_MAGIC_IO_RANGE */
1313
1314 return -1;
1315 }
1316
1317 static void
radeonfb_loadbios(struct radeonfb_softc * sc,const struct pci_attach_args * pa)1318 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa)
1319 {
1320 bus_space_tag_t romt;
1321 bus_space_handle_t romh, biosh;
1322 bus_size_t romsz;
1323 bus_addr_t ptr;
1324
1325 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM,
1326 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) {
1327 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc));
1328 return;
1329 }
1330
1331 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh,
1332 &sc->sc_biossz);
1333 if (sc->sc_biossz == 0) {
1334 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc));
1335 return;
1336 }
1337
1338 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK);
1339 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz);
1340
1341 /* unmap the PCI expansion rom */
1342 bus_space_unmap(romt, romh, romsz);
1343
1344 /* turn off rom decoder now */
1345 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM,
1346 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) &
1347 ~PCI_MAPREG_ROM_ENABLE);
1348
1349 ptr = GETBIOS16(sc, 0x48);
1350 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) ||
1351 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) {
1352 sc->sc_flags |= RFB_ATOM;
1353 }
1354
1355 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc),
1356 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy");
1357 }
1358
1359
1360 uint32_t
radeonfb_get32(struct radeonfb_softc * sc,uint32_t reg)1361 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg)
1362 {
1363
1364 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg);
1365 }
1366
1367 void
radeonfb_put32(struct radeonfb_softc * sc,uint32_t reg,uint32_t val)1368 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val)
1369 {
1370
1371 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val);
1372 }
1373
1374 void
radeonfb_put32s(struct radeonfb_softc * sc,uint32_t reg,uint32_t val)1375 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val)
1376 {
1377
1378 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val);
1379 }
1380
1381 void
radeonfb_mask32(struct radeonfb_softc * sc,uint32_t reg,uint32_t andmask,uint32_t ormask)1382 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg,
1383 uint32_t andmask, uint32_t ormask)
1384 {
1385 int s;
1386 uint32_t val;
1387
1388 s = splhigh();
1389 val = radeonfb_get32(sc, reg);
1390 val = (val & andmask) | ormask;
1391 radeonfb_put32(sc, reg, val);
1392 splx(s);
1393 }
1394
1395 uint32_t
radeonfb_getindex(struct radeonfb_softc * sc,uint32_t idx)1396 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx)
1397 {
1398 int s;
1399 uint32_t val;
1400
1401 s = splhigh();
1402 radeonfb_put32(sc, RADEON_MM_INDEX, idx);
1403 val = radeonfb_get32(sc, RADEON_MM_DATA);
1404 splx(s);
1405
1406 return (val);
1407 }
1408
1409 void
radeonfb_putindex(struct radeonfb_softc * sc,uint32_t idx,uint32_t val)1410 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val)
1411 {
1412 int s;
1413
1414 s = splhigh();
1415 radeonfb_put32(sc, RADEON_MM_INDEX, idx);
1416 radeonfb_put32(sc, RADEON_MM_DATA, val);
1417 splx(s);
1418 }
1419
1420 void
radeonfb_maskindex(struct radeonfb_softc * sc,uint32_t idx,uint32_t andmask,uint32_t ormask)1421 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx,
1422 uint32_t andmask, uint32_t ormask)
1423 {
1424 int s;
1425 uint32_t val;
1426
1427 s = splhigh();
1428 radeonfb_put32(sc, RADEON_MM_INDEX, idx);
1429 val = radeonfb_get32(sc, RADEON_MM_DATA);
1430 val = (val & andmask) | ormask;
1431 radeonfb_put32(sc, RADEON_MM_DATA, val);
1432 splx(s);
1433 }
1434
1435 uint32_t
radeonfb_getpll(struct radeonfb_softc * sc,uint32_t idx)1436 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx)
1437 {
1438 int s;
1439 uint32_t val;
1440
1441 s = splhigh();
1442 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f));
1443 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA);
1444 if (HAS_R300CG(sc))
1445 radeonfb_r300cg_workaround(sc);
1446 splx(s);
1447
1448 return (val);
1449 }
1450
1451 void
radeonfb_putpll(struct radeonfb_softc * sc,uint32_t idx,uint32_t val)1452 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val)
1453 {
1454 int s;
1455
1456 s = splhigh();
1457 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) |
1458 RADEON_PLL_WR_EN);
1459 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val);
1460 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0);
1461 splx(s);
1462 }
1463
1464 void
radeonfb_maskpll(struct radeonfb_softc * sc,uint32_t idx,uint32_t andmask,uint32_t ormask)1465 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx,
1466 uint32_t andmask, uint32_t ormask)
1467 {
1468 int s;
1469 uint32_t val;
1470
1471 s = splhigh();
1472 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) |
1473 RADEON_PLL_WR_EN);
1474 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA);
1475 val = (val & andmask) | ormask;
1476 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val);
1477 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0);
1478 splx(s);
1479 }
1480
1481 int
radeonfb_scratch_test(struct radeonfb_softc * sc,int reg,uint32_t v)1482 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v)
1483 {
1484 uint32_t saved;
1485
1486 saved = GET32(sc, reg);
1487 PUT32(sc, reg, v);
1488 if (GET32(sc, reg) != v) {
1489 return -1;
1490 }
1491 PUT32(sc, reg, saved);
1492 return 0;
1493 }
1494
1495 uintmax_t
radeonfb_getprop_num(struct radeonfb_softc * sc,const char * name,uintmax_t defval)1496 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name,
1497 uintmax_t defval)
1498 {
1499 prop_number_t pn;
1500 pn = prop_dictionary_get(device_properties(sc->sc_dev), name);
1501 if (pn == NULL) {
1502 return defval;
1503 }
1504 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
1505 return (prop_number_integer_value(pn));
1506 }
1507
1508 int
radeonfb_getclocks(struct radeonfb_softc * sc)1509 radeonfb_getclocks(struct radeonfb_softc *sc)
1510 {
1511 bus_addr_t ptr;
1512 int refclk = 0;
1513 int refdiv = 0;
1514 int minpll = 0;
1515 int maxpll = 0;
1516
1517 /* load initial property values if port/board provides them */
1518 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff;
1519 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff;
1520 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU;
1521 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU;
1522
1523 PRINTPLL(RADEON_PPLL_REF_DIV);
1524 PRINTPLL(RADEON_PPLL_DIV_0);
1525 PRINTPLL(RADEON_PPLL_DIV_1);
1526 PRINTPLL(RADEON_PPLL_DIV_2);
1527 PRINTPLL(RADEON_PPLL_DIV_3);
1528 PRINTREG(RADEON_CLOCK_CNTL_INDEX);
1529 PRINTPLL(RADEON_P2PLL_REF_DIV);
1530 PRINTPLL(RADEON_P2PLL_DIV_0);
1531
1532 if (refclk && refdiv && minpll && maxpll)
1533 goto dontprobe;
1534
1535 if (!sc->sc_biossz) {
1536 /* no BIOS */
1537 aprint_verbose("%s: No video BIOS, using default clocks\n",
1538 XNAME(sc));
1539 if (IS_IGP(sc))
1540 refclk = refclk ? refclk : 1432;
1541 else
1542 refclk = refclk ? refclk : 2700;
1543 refdiv = refdiv ? refdiv : 12;
1544 minpll = minpll ? minpll : 12500;
1545 /* XXX
1546 * Need to check if the firmware or something programmed a
1547 * higher value than this, and if so, bump it.
1548 * The RV280 in my iBook is unhappy if the PLL input is less
1549 * than 360MHz
1550 */
1551 maxpll = maxpll ? maxpll : 40000/*35000*/;
1552 } else if (IS_ATOM(sc)) {
1553 /* ATOM BIOS */
1554 ptr = GETBIOS16(sc, 0x48);
1555 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */
1556 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */
1557 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82);
1558 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78);
1559 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32);
1560 /*
1561 * ATOM BIOS doesn't supply a reference divider, so we
1562 * have to probe for it.
1563 */
1564 if (refdiv < 2)
1565 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) &
1566 RADEON_PPLL_REF_DIV_MASK;
1567 /*
1568 * if probe is zero, just assume one that should work
1569 * for most parts
1570 */
1571 if (refdiv < 2)
1572 refdiv = 12;
1573
1574 } else {
1575 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV);
1576 /* Legacy BIOS */
1577 ptr = GETBIOS16(sc, 0x48);
1578 ptr = GETBIOS16(sc, ptr + 0x30);
1579 if (IS_R300(sc)) {
1580 refdiv = refdiv ? refdiv :
1581 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >>
1582 R300_PPLL_REF_DIV_ACC_SHIFT;
1583 } else {
1584 refdiv = refdiv ? refdiv :
1585 tmp & RADEON_PPLL_REF_DIV_MASK;
1586 }
1587 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E);
1588 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10);
1589 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12);
1590 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16);
1591 }
1592
1593
1594 dontprobe:
1595 sc->sc_refclk = refclk * 10;
1596 sc->sc_refdiv = refdiv;
1597 sc->sc_minpll = minpll * 10;
1598 sc->sc_maxpll = maxpll * 10;
1599 return 0;
1600 }
1601
1602 int
radeonfb_calc_dividers(struct radeonfb_softc * sc,uint32_t dotclock,uint32_t * postdivbit,uint32_t * feedbackdiv)1603 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock,
1604 uint32_t *postdivbit, uint32_t *feedbackdiv)
1605 {
1606 int i;
1607 uint32_t outfreq;
1608 int div;
1609
1610 DPRINTF(("dot clock: %u\n", dotclock));
1611 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) {
1612 outfreq = div * dotclock;
1613 if ((outfreq >= sc->sc_minpll) &&
1614 (outfreq <= sc->sc_maxpll)) {
1615 DPRINTF(("outfreq: %u\n", outfreq));
1616 *postdivbit =
1617 ((uint32_t)radeonfb_dividers[i].mask << 16);
1618 DPRINTF(("post divider: %d (mask %x)\n", div,
1619 *postdivbit));
1620 break;
1621 }
1622 }
1623
1624 if (div == 0)
1625 return 1;
1626
1627 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk);
1628 DPRINTF(("feedback divider: %d\n", *feedbackdiv));
1629 return 0;
1630 }
1631
1632 #if 0
1633 #ifdef RADEONFB_DEBUG
1634 static void
1635 dump_buffer(const char *pfx, void *buffer, unsigned int size)
1636 {
1637 char asc[17];
1638 unsigned ptr = (unsigned)buffer;
1639 char *start = (char *)(ptr & ~0xf);
1640 char *end = (char *)(ptr + size);
1641
1642 end = (char *)(((unsigned)end + 0xf) & ~0xf);
1643
1644 if (pfx == NULL) {
1645 pfx = "";
1646 }
1647
1648 while (start < end) {
1649 unsigned offset = (unsigned)start & 0xf;
1650 if (offset == 0) {
1651 printf("%s%x: ", pfx, (unsigned)start);
1652 }
1653 if (((unsigned)start < ptr) ||
1654 ((unsigned)start >= (ptr + size))) {
1655 printf(" ");
1656 asc[offset] = ' ';
1657 } else {
1658 printf("%02x", *(unsigned char *)start);
1659 if ((*start >= ' ') && (*start <= '~')) {
1660 asc[offset] = *start;
1661 } else {
1662 asc[offset] = '.';
1663 }
1664 }
1665 asc[offset + 1] = 0;
1666 if (offset % 2) {
1667 printf(" ");
1668 }
1669 if (offset == 15) {
1670 printf(" %s\n", asc);
1671 }
1672 start++;
1673 }
1674 }
1675 #endif
1676 #endif
1677
1678 int
radeonfb_getconnectors(struct radeonfb_softc * sc)1679 radeonfb_getconnectors(struct radeonfb_softc *sc)
1680 {
1681 int i;
1682 int found = 0;
1683
1684 for (i = 0; i < 2; i++) {
1685 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN;
1686 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE;
1687 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN;
1688 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE;
1689 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN;
1690 }
1691
1692 /*
1693 * This logic is borrowed from Xorg's radeon driver.
1694 */
1695 if (!sc->sc_biossz)
1696 goto nobios;
1697
1698 if (IS_ATOM(sc)) {
1699 /* not done yet */
1700 } else {
1701 uint16_t ptr;
1702 int port = 0;
1703
1704 ptr = GETBIOS16(sc, 0x48);
1705 ptr = GETBIOS16(sc, ptr + 0x50);
1706 for (i = 1; i < 4; i++) {
1707 uint16_t entry;
1708 uint8_t conn, ddc, dac, tmds;
1709
1710 /*
1711 * Parse the connector table. From reading the code,
1712 * it appears to made up of 16-bit entries for each
1713 * connector. The 16-bits are defined as:
1714 *
1715 * bits 12-15 - connector type (0 == end of table)
1716 * bits 8-11 - DDC type
1717 * bits 5-7 - ???
1718 * bit 4 - TMDS type (1 = EXT, 0 = INT)
1719 * bits 1-3 - ???
1720 * bit 0 - DAC, 1 = TVDAC, 0 = primary
1721 */
1722 if (!GETBIOS8(sc, ptr + i * 2) && i > 1)
1723 break;
1724 entry = GETBIOS16(sc, ptr + i * 2);
1725
1726 conn = (entry >> 12) & 0xf;
1727 ddc = (entry >> 8) & 0xf;
1728 dac = (entry & 0x1) ? RADEON_DAC_TVDAC :
1729 RADEON_DAC_PRIMARY;
1730 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT :
1731 RADEON_TMDS_INT;
1732
1733 if (conn == RADEON_CONN_NONE)
1734 continue; /* no connector */
1735
1736 if ((found > 0) &&
1737 (sc->sc_ports[port].rp_ddc_type == ddc)) {
1738 /* duplicate entry for same connector */
1739 continue;
1740 }
1741
1742 /* internal DDC_DVI port gets priority */
1743 if ((ddc == RADEON_DDC_DVI) || (port == 1))
1744 port = 0;
1745 else
1746 port = 1;
1747
1748 sc->sc_ports[port].rp_ddc_type =
1749 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc;
1750 sc->sc_ports[port].rp_dac_type = dac;
1751 sc->sc_ports[port].rp_conn_type =
1752 min(conn, RADEON_CONN_UNSUPPORTED) ;
1753
1754 sc->sc_ports[port].rp_tmds_type = tmds;
1755
1756 if ((conn != RADEON_CONN_DVI_I) &&
1757 (conn != RADEON_CONN_DVI_D) &&
1758 (tmds == RADEON_TMDS_INT))
1759 sc->sc_ports[port].rp_tmds_type =
1760 RADEON_TMDS_UNKNOWN;
1761 sc->sc_ports[port].rp_number = i - 1;
1762
1763 found += (port + 1);
1764 }
1765 }
1766
1767 nobios:
1768 if (!found) {
1769 DPRINTF(("No connector info in BIOS!\n"));
1770 if IS_MOBILITY(sc) {
1771 /* default, port 0 = internal TMDS, port 1 = CRT */
1772 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN;
1773 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI;
1774 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC;
1775 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D;
1776 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT;
1777 sc->sc_ports[0].rp_number = 0;
1778
1779 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN;
1780 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA;
1781 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY;
1782 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT;
1783 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT;
1784 sc->sc_ports[1].rp_number = 1;
1785 } else {
1786 /* default, port 0 = DVI, port 1 = CRT */
1787 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN;
1788 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI;
1789 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC;
1790 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D;
1791 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT;
1792 sc->sc_ports[0].rp_number = 1;
1793
1794 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN;
1795 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA;
1796 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY;
1797 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT;
1798 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN;
1799 sc->sc_ports[1].rp_number = 0;
1800 }
1801 }
1802
1803 /*
1804 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC.
1805 * these chips should use TVDAC for the VGA port.
1806 */
1807 if (HAS_SDAC(sc)) {
1808 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) {
1809 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC;
1810 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY;
1811 } else {
1812 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC;
1813 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY;
1814 }
1815 } else if (!HAS_CRTC2(sc)) {
1816 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY;
1817 }
1818
1819 for (i = 0; i < 2; i++) {
1820 char edid[128];
1821 uint8_t ddc;
1822 struct edid_info *eip = &sc->sc_ports[i].rp_edid;
1823 prop_data_t edid_data;
1824
1825 DPRINTF(("Port #%d:\n", i));
1826 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type));
1827 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type));
1828 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type));
1829 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type));
1830 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number));
1831
1832 sc->sc_ports[i].rp_edid_valid = 0;
1833 /* first look for static EDID data */
1834 if ((edid_data = prop_dictionary_get(device_properties(
1835 sc->sc_dev), "EDID")) != NULL) {
1836
1837 aprint_debug_dev(sc->sc_dev, "using static EDID\n");
1838 memcpy(edid, prop_data_data_nocopy(edid_data), 128);
1839 if (edid_parse(edid, eip) == 0) {
1840
1841 sc->sc_ports[i].rp_edid_valid = 1;
1842 }
1843 }
1844 /* if we didn't find any we'll try to talk to the monitor */
1845 if (sc->sc_ports[i].rp_edid_valid != 1) {
1846
1847 ddc = sc->sc_ports[i].rp_ddc_type;
1848 if (ddc != RADEON_DDC_NONE) {
1849 if ((radeonfb_i2c_read_edid(sc, ddc, edid)
1850 == 0) && (edid_parse(edid, eip) == 0)) {
1851
1852 sc->sc_ports[i].rp_edid_valid = 1;
1853 #ifdef RADEONFB_DEBUG
1854 edid_print(eip);
1855 #endif
1856 }
1857 }
1858 }
1859 }
1860
1861 return found;
1862 }
1863
1864 int
radeonfb_gettmds(struct radeonfb_softc * sc)1865 radeonfb_gettmds(struct radeonfb_softc *sc)
1866 {
1867 int i;
1868
1869 if (!sc->sc_biossz) {
1870 goto nobios;
1871 }
1872
1873 if (IS_ATOM(sc)) {
1874 /* XXX: not done yet */
1875 } else {
1876 uint16_t ptr;
1877 int n;
1878
1879 ptr = GETBIOS16(sc, 0x48);
1880 ptr = GETBIOS16(sc, ptr + 0x34);
1881 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr)));
1882 if (GETBIOS8(sc, ptr) == 3) {
1883 /* revision three table */
1884 n = GETBIOS8(sc, ptr + 5) + 1;
1885 n = min(n, 4);
1886
1887 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll));
1888 for (i = 0; i < n; i++) {
1889 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc,
1890 ptr + i * 10 + 8);
1891 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc,
1892 ptr + i * 10 + 0x10);
1893 DPRINTF(("TMDS_PLL dot clock %d pll %x\n",
1894 sc->sc_tmds_pll[i].rtp_freq,
1895 sc->sc_tmds_pll[i].rtp_pll));
1896 }
1897 return 0;
1898 }
1899 }
1900
1901 nobios:
1902 DPRINTF(("no suitable DFP table present\n"));
1903 for (i = 0;
1904 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]);
1905 i++) {
1906 int j;
1907
1908 if (radeonfb_tmds_pll[i].family != sc->sc_family)
1909 continue;
1910
1911 for (j = 0; j < 4; j++) {
1912 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j];
1913 DPRINTF(("TMDS_PLL dot clock %d pll %x\n",
1914 sc->sc_tmds_pll[j].rtp_freq,
1915 sc->sc_tmds_pll[j].rtp_pll));
1916 }
1917 return 0;
1918 }
1919
1920 return -1;
1921 }
1922
1923 const struct videomode *
radeonfb_modelookup(const char * name)1924 radeonfb_modelookup(const char *name)
1925 {
1926 int i;
1927
1928 for (i = 0; i < videomode_count; i++)
1929 if (!strcmp(name, videomode_list[i].name))
1930 return &videomode_list[i];
1931
1932 return NULL;
1933 }
1934
1935 void
radeonfb_pllwriteupdate(struct radeonfb_softc * sc,int crtc)1936 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc)
1937 {
1938 if (crtc) {
1939 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) &
1940 RADEON_P2PLL_ATOMIC_UPDATE_R);
1941 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W);
1942 } else {
1943 while (GETPLL(sc, RADEON_PPLL_REF_DIV) &
1944 RADEON_PPLL_ATOMIC_UPDATE_R);
1945 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W);
1946 }
1947 }
1948
1949 void
radeonfb_pllwaitatomicread(struct radeonfb_softc * sc,int crtc)1950 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc)
1951 {
1952 int i;
1953
1954 for (i = 10000; i; i--) {
1955 if (crtc) {
1956 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) &
1957 RADEON_P2PLL_ATOMIC_UPDATE_R)
1958 break;
1959 } else {
1960 if (GETPLL(sc, RADEON_PPLL_REF_DIV) &
1961 RADEON_PPLL_ATOMIC_UPDATE_R)
1962 break;
1963 }
1964 }
1965 }
1966
1967 void
radeonfb_program_vclk(struct radeonfb_softc * sc,int dotclock,int crtc)1968 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc)
1969 {
1970 uint32_t pbit = 0;
1971 uint32_t feed = 0;
1972 uint32_t data, refdiv, div0;
1973
1974 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed);
1975
1976 if (crtc == 0) {
1977
1978 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV);
1979 if (IS_R300(sc)) {
1980 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) |
1981 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT);
1982 } else {
1983 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) |
1984 sc->sc_refdiv;
1985 }
1986 div0 = GETPLL(sc, RADEON_PPLL_DIV_0);
1987 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK |
1988 RADEON_PPLL_POST3_DIV_MASK);
1989 div0 |= pbit;
1990 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK);
1991
1992 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) &&
1993 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) {
1994 /*
1995 * nothing to do here, the PLL is already where we
1996 * want it
1997 */
1998 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0,
1999 ~RADEON_PLL_DIV_SEL);
2000 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n");
2001 return;
2002 }
2003
2004 /* alright, we do need to reprogram stuff */
2005 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL,
2006 RADEON_VCLK_SRC_SEL_CPUCLK,
2007 ~RADEON_VCLK_SRC_SEL_MASK);
2008
2009 /* put vclk into reset, use atomic updates */
2010 SETPLL(sc, RADEON_PPLL_CNTL,
2011 RADEON_PPLL_REFCLK_SEL |
2012 RADEON_PPLL_FBCLK_SEL |
2013 RADEON_PPLL_RESET |
2014 RADEON_PPLL_ATOMIC_UPDATE_EN |
2015 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN);
2016
2017 /* select clock 0 */
2018 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0,
2019 ~RADEON_PLL_DIV_SEL);
2020
2021 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv);
2022
2023 /* xf86-video-radeon does this, not sure why */
2024 PUTPLL(sc, RADEON_PPLL_DIV_0, div0);
2025 PUTPLL(sc, RADEON_PPLL_DIV_0, div0);
2026
2027 /* use the atomic update */
2028 radeonfb_pllwriteupdate(sc, crtc);
2029
2030 /* and wait for it to complete */
2031 radeonfb_pllwaitatomicread(sc, crtc);
2032
2033 /* program HTOTAL (why?) */
2034 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0);
2035
2036 /* drop reset */
2037 CLRPLL(sc, RADEON_PPLL_CNTL,
2038 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP |
2039 RADEON_PPLL_ATOMIC_UPDATE_EN |
2040 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN);
2041
2042 PRINTPLL(RADEON_PPLL_CNTL);
2043 PRINTPLL(RADEON_PPLL_REF_DIV);
2044 PRINTPLL(RADEON_PPLL_DIV_3);
2045
2046 /* give clock time to lock */
2047 delay(50000);
2048
2049 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL,
2050 RADEON_VCLK_SRC_SEL_PPLLCLK,
2051 ~RADEON_VCLK_SRC_SEL_MASK);
2052
2053 } else {
2054
2055 PATCHPLL(sc, RADEON_PIXCLKS_CNTL,
2056 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
2057 ~RADEON_PIX2CLK_SRC_SEL_MASK);
2058
2059 /* put vclk into reset, use atomic updates */
2060 SETPLL(sc, RADEON_P2PLL_CNTL,
2061 RADEON_P2PLL_RESET |
2062 RADEON_P2PLL_ATOMIC_UPDATE_EN |
2063 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN);
2064
2065 /* program reference divider */
2066 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv,
2067 ~RADEON_P2PLL_REF_DIV_MASK);
2068
2069 /* program feedback and post dividers */
2070 data = GETPLL(sc, RADEON_P2PLL_DIV_0);
2071 data &= ~(RADEON_P2PLL_FB0_DIV_MASK |
2072 RADEON_P2PLL_POST0_DIV_MASK);
2073 data |= pbit;
2074 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK);
2075 PUTPLL(sc, RADEON_P2PLL_DIV_0, data);
2076 PUTPLL(sc, RADEON_P2PLL_DIV_0, data);
2077
2078 PRINTPLL(RADEON_P2PLL_REF_DIV);
2079 PRINTPLL(RADEON_P2PLL_DIV_0);
2080
2081 /* use the atomic update */
2082 radeonfb_pllwriteupdate(sc, crtc);
2083
2084 /* and wait for it to complete */
2085 radeonfb_pllwaitatomicread(sc, crtc);
2086
2087 /* program HTOTAL (why?) */
2088 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0);
2089
2090 /* drop reset */
2091 CLRPLL(sc, RADEON_P2PLL_CNTL,
2092 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP |
2093 RADEON_P2PLL_ATOMIC_UPDATE_EN |
2094 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN);
2095
2096 /* allow time for clock to lock */
2097 delay(50000);
2098
2099 PATCHPLL(sc, RADEON_PIXCLKS_CNTL,
2100 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
2101 ~RADEON_PIX2CLK_SRC_SEL_MASK);
2102 }
2103 PRINTREG(RADEON_CRTC_MORE_CNTL);
2104 }
2105
2106 void
radeonfb_modeswitch(struct radeonfb_display * dp)2107 radeonfb_modeswitch(struct radeonfb_display *dp)
2108 {
2109 struct radeonfb_softc *sc = dp->rd_softc;
2110 int i;
2111
2112 /* blank the display while we switch modes */
2113 radeonfb_blank(dp, 1);
2114
2115 #if 0
2116 SET32(sc, RADEON_CRTC_EXT_CNTL,
2117 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS |
2118 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */);
2119 #endif
2120
2121 /* these registers might get in the way... */
2122 PUT32(sc, RADEON_OVR_CLR, 0);
2123 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0);
2124 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0);
2125 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0);
2126 PUT32(sc, RADEON_SUBPIC_CNTL, 0);
2127 PUT32(sc, RADEON_VIPH_CONTROL, 0);
2128 PUT32(sc, RADEON_I2C_CNTL_1, 0);
2129 PUT32(sc, RADEON_GEN_INT_CNTL, 0);
2130 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0);
2131 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0);
2132 PUT32(sc, RADEON_SURFACE_CNTL, 0);
2133
2134 for (i = 0; i < dp->rd_ncrtcs; i++)
2135 radeonfb_setcrtc(dp, i);
2136
2137 /* activate the display */
2138 radeonfb_blank(dp, 0);
2139 }
2140
2141 void
radeonfb_setcrtc(struct radeonfb_display * dp,int index)2142 radeonfb_setcrtc(struct radeonfb_display *dp, int index)
2143 {
2144 int crtc;
2145 struct videomode *mode;
2146 struct radeonfb_softc *sc;
2147 struct radeonfb_crtc *cp;
2148 uint32_t v;
2149 uint32_t gencntl;
2150 uint32_t htotaldisp;
2151 uint32_t hsyncstrt;
2152 uint32_t vtotaldisp;
2153 uint32_t vsyncstrt;
2154 uint32_t fphsyncstrt;
2155 uint32_t fpvsyncstrt;
2156 uint32_t fphtotaldisp;
2157 uint32_t fpvtotaldisp;
2158 uint32_t pitch;
2159
2160 sc = dp->rd_softc;
2161 cp = &dp->rd_crtcs[index];
2162 crtc = cp->rc_number;
2163 mode = &cp->rc_videomode;
2164
2165 #if 1
2166 pitch = dp->rd_stride / dp->rd_bpp;
2167 #else
2168 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) /
2169 (sc->sc_maxbpp * 8));
2170 #endif
2171 switch (crtc) {
2172 case 0:
2173 gencntl = RADEON_CRTC_GEN_CNTL;
2174 htotaldisp = RADEON_CRTC_H_TOTAL_DISP;
2175 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID;
2176 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP;
2177 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID;
2178 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID;
2179 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID;
2180 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP;
2181 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP;
2182 break;
2183 case 1:
2184 gencntl = RADEON_CRTC2_GEN_CNTL;
2185 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP;
2186 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID;
2187 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP;
2188 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID;
2189 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID;
2190 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID;
2191 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP;
2192 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP;
2193 break;
2194 default:
2195 panic("Bad CRTC!");
2196 break;
2197 }
2198
2199 /*
2200 * CRTC_GEN_CNTL - depth, accelerator mode, etc.
2201 */
2202 /* only bother with 32bpp and 8bpp */
2203 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT;
2204
2205 if (crtc == 1) {
2206 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN;
2207 } else {
2208 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN;
2209 }
2210
2211 if (mode->flags & VID_DBLSCAN)
2212 v |= RADEON_CRTC2_DBL_SCAN_EN;
2213
2214 if (mode->flags & VID_INTERLACE)
2215 v |= RADEON_CRTC2_INTERLACE_EN;
2216
2217 if (mode->flags & VID_CSYNC) {
2218 v |= RADEON_CRTC2_CSYNC_EN;
2219 if (crtc == 1)
2220 v |= RADEON_CRTC2_VSYNC_TRISTAT;
2221 }
2222
2223 PUT32(sc, gencntl, v);
2224 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v));
2225
2226 /*
2227 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT
2228 */
2229 v = GET32(sc, RADEON_CRTC_EXT_CNTL);
2230 if (crtc == 0) {
2231 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS |
2232 RADEON_CRTC_DISPLAY_DIS);
2233 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR;
2234 if (mode->flags & VID_CSYNC)
2235 v |= RADEON_CRTC_VSYNC_TRISTAT;
2236 }
2237 /* unconditional turn on CRT, in case first CRTC is DFP */
2238 v |= RADEON_CRTC_CRT_ON;
2239 PUT32(sc, RADEON_CRTC_EXT_CNTL, v);
2240 PRINTREG(RADEON_CRTC_EXT_CNTL);
2241
2242 /*
2243 * H_TOTAL_DISP
2244 */
2245 v = ((mode->hdisplay / 8) - 1) << 16;
2246 v |= (mode->htotal / 8) - 1;
2247 PUT32(sc, htotaldisp, v);
2248 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
2249 PUT32(sc, fphtotaldisp, v);
2250 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
2251
2252 /*
2253 * H_SYNC_STRT_WID
2254 */
2255 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16);
2256 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */
2257 if (mode->flags & VID_NHSYNC)
2258 v |= RADEON_CRTC_H_SYNC_POL;
2259 PUT32(sc, hsyncstrt, v);
2260 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
2261 PUT32(sc, fphsyncstrt, v);
2262 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
2263
2264 /*
2265 * V_TOTAL_DISP
2266 */
2267 v = ((mode->vdisplay - 1) << 16);
2268 v |= (mode->vtotal - 1);
2269 PUT32(sc, vtotaldisp, v);
2270 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
2271 PUT32(sc, fpvtotaldisp, v);
2272 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
2273
2274 /*
2275 * V_SYNC_STRT_WID
2276 */
2277 v = ((mode->vsync_end - mode->vsync_start) << 16);
2278 v |= (mode->vsync_start - 1);
2279 if (mode->flags & VID_NVSYNC)
2280 v |= RADEON_CRTC_V_SYNC_POL;
2281 PUT32(sc, vsyncstrt, v);
2282 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
2283 PUT32(sc, fpvsyncstrt, v);
2284 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
2285
2286 radeonfb_program_vclk(sc, mode->dot_clock, crtc);
2287
2288 switch (crtc) {
2289 case 0:
2290 PUT32(sc, RADEON_CRTC_OFFSET, 0);
2291 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0);
2292 PUT32(sc, RADEON_CRTC_PITCH, pitch);
2293 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN);
2294
2295 CLR32(sc, RADEON_CRTC_EXT_CNTL,
2296 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS |
2297 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */);
2298 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B);
2299 PRINTREG(RADEON_CRTC_EXT_CNTL);
2300 PRINTREG(RADEON_CRTC_GEN_CNTL);
2301 PRINTREG(RADEON_CLOCK_CNTL_INDEX);
2302 break;
2303
2304 case 1:
2305 PUT32(sc, RADEON_CRTC2_OFFSET, 0);
2306 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0);
2307 PUT32(sc, RADEON_CRTC2_PITCH, pitch);
2308 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN);
2309 CLR32(sc, RADEON_CRTC2_GEN_CNTL,
2310 RADEON_CRTC2_VSYNC_DIS |
2311 RADEON_CRTC2_HSYNC_DIS |
2312 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B);
2313 PRINTREG(RADEON_CRTC2_GEN_CNTL);
2314 break;
2315 }
2316 }
2317
2318 int
radeonfb_isblank(struct radeonfb_display * dp)2319 radeonfb_isblank(struct radeonfb_display *dp)
2320 {
2321 uint32_t reg, mask;
2322
2323 if(!dp->rd_softc->sc_mapped)
2324 return 1;
2325
2326 if (dp->rd_crtcs[0].rc_number) {
2327 reg = RADEON_CRTC2_GEN_CNTL;
2328 mask = RADEON_CRTC2_DISP_DIS;
2329 } else {
2330 reg = RADEON_CRTC_EXT_CNTL;
2331 mask = RADEON_CRTC_DISPLAY_DIS;
2332 }
2333 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0);
2334 }
2335
2336 void
radeonfb_blank(struct radeonfb_display * dp,int blank)2337 radeonfb_blank(struct radeonfb_display *dp, int blank)
2338 {
2339 struct radeonfb_softc *sc = dp->rd_softc;
2340 uint32_t reg, mask;
2341 uint32_t fpreg, fpval;
2342 int i;
2343
2344 if (!sc->sc_mapped)
2345 return;
2346
2347 for (i = 0; i < dp->rd_ncrtcs; i++) {
2348
2349 if (dp->rd_crtcs[i].rc_number) {
2350 reg = RADEON_CRTC2_GEN_CNTL;
2351 mask = RADEON_CRTC2_DISP_DIS;
2352 fpreg = RADEON_FP2_GEN_CNTL;
2353 fpval = RADEON_FP2_ON;
2354 } else {
2355 reg = RADEON_CRTC_EXT_CNTL;
2356 mask = RADEON_CRTC_DISPLAY_DIS;
2357 fpreg = RADEON_FP_GEN_CNTL;
2358 fpval = RADEON_FP_FPON;
2359 }
2360
2361 if (blank) {
2362 SET32(sc, reg, mask);
2363 CLR32(sc, fpreg, fpval);
2364 } else {
2365 CLR32(sc, reg, mask);
2366 SET32(sc, fpreg, fpval);
2367 }
2368 }
2369 PRINTREG(RADEON_FP_GEN_CNTL);
2370 PRINTREG(RADEON_FP2_GEN_CNTL);
2371 }
2372
2373 void
radeonfb_init_screen(void * cookie,struct vcons_screen * scr,int existing,long * defattr)2374 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing,
2375 long *defattr)
2376 {
2377 struct radeonfb_display *dp = cookie;
2378 struct rasops_info *ri = &scr->scr_ri;
2379
2380 /* initialize font subsystem */
2381 wsfont_init();
2382
2383 DPRINTF(("init screen called, existing %d\n", existing));
2384
2385 ri->ri_depth = dp->rd_bpp;
2386 ri->ri_width = dp->rd_virtx;
2387 ri->ri_height = dp->rd_virty;
2388 ri->ri_stride = dp->rd_stride;
2389 ri->ri_flg = RI_CENTER;
2390 switch (ri->ri_depth) {
2391 case 8:
2392 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB;
2393 break;
2394 case 32:
2395 ri->ri_flg |= RI_ENABLE_ALPHA;
2396 /* we run radeons in RGB even on SPARC hardware */
2397 ri->ri_rnum = 8;
2398 ri->ri_gnum = 8;
2399 ri->ri_bnum = 8;
2400 ri->ri_rpos = 16;
2401 ri->ri_gpos = 8;
2402 ri->ri_bpos = 0;
2403 break;
2404 }
2405
2406 ri->ri_bits = (void *)dp->rd_fbptr;
2407
2408 #ifdef VCONS_DRAW_INTR
2409 scr->scr_flags |= VCONS_DONT_READ;
2410 #endif
2411
2412 if (existing) {
2413 ri->ri_flg |= RI_CLEAR;
2414
2415 /* start a modeswitch now */
2416 radeonfb_modeswitch(dp);
2417 }
2418
2419 /*
2420 * XXX: font selection should be based on properties, with some
2421 * normal/reasonable default.
2422 */
2423
2424 /* initialize and look for an initial font */
2425 rasops_init(ri, 0, 0);
2426 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT |
2427 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE;
2428
2429 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight,
2430 dp->rd_virtx / ri->ri_font->fontwidth);
2431
2432 /* enable acceleration */
2433 dp->rd_putchar = ri->ri_ops.putchar;
2434 ri->ri_ops.copyrows = radeonfb_copyrows;
2435 ri->ri_ops.copycols = radeonfb_copycols;
2436 ri->ri_ops.eraserows = radeonfb_eraserows;
2437 ri->ri_ops.erasecols = radeonfb_erasecols;
2438 /* pick a putchar method based on font and Radeon model */
2439 if (ri->ri_font->stride < ri->ri_font->fontwidth) {
2440 /* got a bitmap font */
2441 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR
2442 if (IS_R300(dp->rd_softc)) {
2443 /*
2444 * radeonfb_putchar() doesn't work right on some R3xx
2445 * so we use software drawing here, the wrapper just
2446 * makes sure the engine is idle before scribbling
2447 * into vram
2448 */
2449 ri->ri_ops.putchar = radeonfb_putchar_wrapper;
2450 } else
2451 #endif
2452 ri->ri_ops.putchar = radeonfb_putchar;
2453 } else {
2454 /* got an alpha font */
2455 switch(ri->ri_depth) {
2456 case 32:
2457 ri->ri_ops.putchar = radeonfb_putchar_aa32;
2458 break;
2459 case 8:
2460 ri->ri_ops.putchar = radeonfb_putchar_aa8;
2461 break;
2462 default:
2463 /* XXX this should never happen */
2464 panic("%s: depth is not 8 or 32 but we got an" \
2465 " alpha font?!", __func__);
2466 }
2467 }
2468 ri->ri_ops.cursor = radeonfb_cursor;
2469 }
2470
2471 void
radeonfb_set_fbloc(struct radeonfb_softc * sc)2472 radeonfb_set_fbloc(struct radeonfb_softc *sc)
2473 {
2474 uint32_t gen, ext, gen2 = 0;
2475 uint32_t agploc, aperbase, apersize, mcfbloc;
2476
2477 gen = GET32(sc, RADEON_CRTC_GEN_CNTL);
2478 /* XXX */
2479 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS;
2480 agploc = GET32(sc, RADEON_MC_AGP_LOCATION);
2481 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE);
2482 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE);
2483
2484 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B);
2485 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS);
2486 #if 0
2487 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS);
2488 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B);
2489 #endif
2490
2491 if (HAS_CRTC2(sc)) {
2492 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL);
2493 PUT32(sc, RADEON_CRTC2_GEN_CNTL,
2494 gen2 | RADEON_CRTC2_DISP_REQ_EN_B);
2495 }
2496
2497 delay(100000);
2498
2499 mcfbloc = (aperbase >> 16) |
2500 ((aperbase + (apersize - 1)) & 0xffff0000);
2501
2502 sc->sc_aperbase = (mcfbloc & 0xffff) << 16;
2503 sc->sc_memsz = apersize;
2504
2505 if (((agploc & 0xffff) << 16) !=
2506 ((mcfbloc & 0xffff0000U) + 0x10000)) {
2507 agploc = mcfbloc & 0xffff0000U;
2508 agploc |= ((agploc + 0x10000) >> 16);
2509 }
2510
2511 PUT32(sc, RADEON_HOST_PATH_CNTL, 0);
2512
2513 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc);
2514 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc);
2515
2516 DPRINTF(("aperbase = %u\n", aperbase));
2517 PRINTREG(RADEON_MC_FB_LOCATION);
2518 PRINTREG(RADEON_MC_AGP_LOCATION);
2519
2520 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase);
2521
2522 if (HAS_CRTC2(sc))
2523 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase);
2524
2525 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase);
2526
2527 #if 0
2528 /* XXX: what is this AGP garbage? :-) */
2529 PUT32(sc, RADEON_AGP_CNTL, 0x00100000);
2530 #endif
2531
2532 delay(100000);
2533
2534 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen);
2535 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext);
2536
2537 if (HAS_CRTC2(sc))
2538 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2);
2539 }
2540
2541 void
radeonfb_init_misc(struct radeonfb_softc * sc)2542 radeonfb_init_misc(struct radeonfb_softc *sc)
2543 {
2544 PUT32(sc, RADEON_BUS_CNTL,
2545 RADEON_BUS_MASTER_DIS |
2546 RADEON_BUS_PREFETCH_MODE_ACT |
2547 RADEON_BUS_PCI_READ_RETRY_EN |
2548 RADEON_BUS_PCI_WRT_RETRY_EN |
2549 (3 << RADEON_BUS_RETRY_WS_SHIFT) |
2550 RADEON_BUS_MSTR_RD_MULT |
2551 RADEON_BUS_MSTR_RD_LINE |
2552 RADEON_BUS_RD_DISCARD_EN |
2553 RADEON_BUS_MSTR_DISCONNECT_EN |
2554 RADEON_BUS_READ_BURST);
2555
2556 PUT32(sc, RADEON_BUS_CNTL1, 0xf0);
2557 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */
2558 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND);
2559 PUT32(sc, RADEON_RBBM_CNTL,
2560 (3 << RADEON_RB_SETTLE_SHIFT) |
2561 (4 << RADEON_ABORTCLKS_HI_SHIFT) |
2562 (4 << RADEON_ABORTCLKS_CP_SHIFT) |
2563 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT));
2564
2565 /* XXX: figure out what these mean! */
2566 PUT32(sc, RADEON_AGP_CNTL, 0x00100000);
2567 PUT32(sc, RADEON_HOST_PATH_CNTL, 0);
2568 #if 0
2569 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400);
2570 #endif
2571
2572 PUT32(sc, RADEON_GEN_INT_CNTL, 0);
2573 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS));
2574 }
2575
2576 static void
radeonfb_putpal(struct radeonfb_display * dp,int idx,int r,int g,int b)2577 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b)
2578 {
2579 struct radeonfb_softc *sc = dp->rd_softc;
2580 int crtc, cc;
2581 uint32_t vclk;
2582
2583 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL);
2584 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb);
2585
2586 /* initialize the palette for every CRTC used by this display */
2587 for (cc = 0; cc < dp->rd_ncrtcs; cc++) {
2588 crtc = dp->rd_crtcs[cc].rc_number;
2589 DPRINTF(("%s: doing crtc %d %d\n", __func__, cc, crtc));
2590
2591 if (crtc)
2592 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL);
2593 else
2594 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL);
2595
2596 PUT32(sc, RADEON_PALETTE_INDEX, idx);
2597 PUT32(sc, RADEON_PALETTE_30_DATA,
2598 (r << 22) | (g << 12) | (b << 2));
2599 }
2600
2601 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk);
2602 }
2603
2604 /*
2605 * This loads a linear color map for true color.
2606 */
2607 void
radeonfb_init_palette(struct radeonfb_display * dp)2608 radeonfb_init_palette(struct radeonfb_display *dp)
2609 {
2610 int i;
2611
2612 #define DAC_WIDTH ((1 << 10) - 1)
2613 #define CLUT_WIDTH ((1 << 8) - 1)
2614 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2)
2615
2616 if (dp->rd_bpp == 8) {
2617
2618 /* R3G3B2 palette */
2619 uint32_t tmp, r, g, b;
2620
2621 for (i = 0; i <= CLUT_WIDTH; ++i) {
2622 tmp = i & 0xe0;
2623
2624 /*
2625 * replicate bits so 0xe0 maps to a red value of 0xff
2626 * in order to make white look actually white
2627 */
2628 tmp |= (tmp >> 3) | (tmp >> 6);
2629 r = tmp;
2630
2631 tmp = (i & 0x1c) << 3;
2632 tmp |= (tmp >> 3) | (tmp >> 6);
2633 g = tmp;
2634
2635 tmp = (i & 0x03) << 6;
2636 tmp |= tmp >> 2;
2637 tmp |= tmp >> 4;
2638 b = tmp;
2639
2640 radeonfb_putpal(dp, i, r, g, b);
2641 }
2642 } else {
2643 /* linear ramp */
2644 for (i = 0; i <= CLUT_WIDTH; ++i) {
2645 radeonfb_putpal(dp, i, i, i, i);
2646 }
2647 }
2648 }
2649
2650 static int
radeonfb_putcmap(struct radeonfb_display * dp,struct wsdisplay_cmap * cm)2651 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm)
2652 {
2653 u_char *r, *g, *b;
2654 u_int index = cm->index;
2655 u_int count = cm->count;
2656 int i, error;
2657 u_char rbuf[256], gbuf[256], bbuf[256];
2658
2659 #ifdef GENFB_DEBUG
2660 aprint_debug("putcmap: %d %d\n",index, count);
2661 #endif
2662 if (cm->index >= 256 || cm->count > 256 ||
2663 (cm->index + cm->count) > 256)
2664 return EINVAL;
2665 error = copyin(cm->red, &rbuf[index], count);
2666 if (error)
2667 return error;
2668 error = copyin(cm->green, &gbuf[index], count);
2669 if (error)
2670 return error;
2671 error = copyin(cm->blue, &bbuf[index], count);
2672 if (error)
2673 return error;
2674
2675 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count);
2676 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count);
2677 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count);
2678
2679 r = &dp->rd_cmap_red[index];
2680 g = &dp->rd_cmap_green[index];
2681 b = &dp->rd_cmap_blue[index];
2682
2683 for (i = 0; i < count; i++) {
2684 radeonfb_putpal(dp, index, *r, *g, *b);
2685 index++;
2686 r++, g++, b++;
2687 }
2688 return 0;
2689 }
2690
2691 static int
radeonfb_getcmap(struct radeonfb_display * dp,struct wsdisplay_cmap * cm)2692 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm)
2693 {
2694 u_int index = cm->index;
2695 u_int count = cm->count;
2696 int error;
2697
2698 if (index >= 255 || count > 256 || index + count > 256)
2699 return EINVAL;
2700
2701 error = copyout(&dp->rd_cmap_red[index], cm->red, count);
2702 if (error)
2703 return error;
2704 error = copyout(&dp->rd_cmap_green[index], cm->green, count);
2705 if (error)
2706 return error;
2707 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count);
2708 if (error)
2709 return error;
2710
2711 return 0;
2712 }
2713
2714 /*
2715 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX.
2716 */
2717 void
radeonfb_r300cg_workaround(struct radeonfb_softc * sc)2718 radeonfb_r300cg_workaround(struct radeonfb_softc *sc)
2719 {
2720 uint32_t tmp, save;
2721
2722 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX);
2723 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2724 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp);
2725 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA);
2726 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save);
2727 }
2728
2729 /*
2730 * Acceleration entry points.
2731 */
2732
2733 /* this one draws characters using bitmap fonts */
2734 static void
radeonfb_putchar(void * cookie,int row,int col,u_int c,long attr)2735 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr)
2736 {
2737 struct rasops_info *ri = cookie;
2738 struct vcons_screen *scr = ri->ri_hw;
2739 struct radeonfb_display *dp = scr->scr_cookie;
2740 struct radeonfb_softc *sc = dp->rd_softc;
2741 struct wsdisplay_font *font = PICK_FONT(ri, c);
2742 uint32_t w, h;
2743 int xd, yd, offset, i;
2744 uint32_t bg, fg, gmc;
2745 uint32_t reg;
2746 uint8_t *data8;
2747 uint16_t *data16;
2748 void *data;
2749
2750 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL)
2751 return;
2752
2753 if (!CHAR_IN_FONT(c, font))
2754 return;
2755
2756 w = font->fontwidth;
2757 h = font->fontheight;
2758
2759 bg = ri->ri_devcmap[(attr >> 16) & 0xf];
2760 fg = ri->ri_devcmap[(attr >> 24) & 0xf];
2761
2762 xd = ri->ri_xorigin + col * w;
2763 yd = ri->ri_yorigin + row * h;
2764
2765 if (c == 0x20) {
2766 radeonfb_rectfill(dp, xd, yd, w, h, bg);
2767 return;
2768 }
2769 data = WSFONT_GLYPH(c, font);
2770
2771 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
2772
2773 radeonfb_wait_fifo(sc, 9);
2774
2775 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
2776 RADEON_GMC_BRUSH_NONE |
2777 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG |
2778 RADEON_GMC_DST_CLIPPING |
2779 RADEON_ROP3_S |
2780 RADEON_DP_SRC_SOURCE_HOST_DATA |
2781 RADEON_GMC_CLR_CMP_CNTL_DIS |
2782 RADEON_GMC_WR_MSK_DIS |
2783 gmc);
2784
2785 PUT32(sc, RADEON_SC_LEFT, xd);
2786 PUT32(sc, RADEON_SC_RIGHT, xd + w);
2787 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg);
2788 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg);
2789 PUT32(sc, RADEON_DP_CNTL,
2790 RADEON_DST_X_LEFT_TO_RIGHT |
2791 RADEON_DST_Y_TOP_TO_BOTTOM);
2792
2793 PUT32(sc, RADEON_SRC_X_Y, 0);
2794 offset = 32 - (font->stride << 3);
2795 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd);
2796 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h);
2797
2798 radeonfb_wait_fifo(sc, h);
2799 switch (font->stride) {
2800 case 1: {
2801 data8 = data;
2802 for (i = 0; i < h; i++) {
2803 reg = *data8;
2804 #if BYTE_ORDER == LITTLE_ENDIAN
2805 reg = reg << 24;
2806 #endif
2807 bus_space_write_stream_4(sc->sc_regt,
2808 sc->sc_regh, RADEON_HOST_DATA0, reg);
2809 data8++;
2810 }
2811 break;
2812 }
2813 case 2: {
2814 data16 = data;
2815 for (i = 0; i < h; i++) {
2816 reg = *data16;
2817 #if BYTE_ORDER == LITTLE_ENDIAN
2818 reg = reg << 16;
2819 #endif
2820 bus_space_write_stream_4(sc->sc_regt,
2821 sc->sc_regh, RADEON_HOST_DATA0, reg);
2822 data16++;
2823 }
2824 break;
2825 }
2826 }
2827 if (attr & 1)
2828 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg);
2829 }
2830
2831 /* ... while this one is for anti-aliased ones */
2832 static void
radeonfb_putchar_aa32(void * cookie,int row,int col,u_int c,long attr)2833 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr)
2834 {
2835 struct rasops_info *ri = cookie;
2836 struct vcons_screen *scr = ri->ri_hw;
2837 struct radeonfb_display *dp = scr->scr_cookie;
2838 struct radeonfb_softc *sc = dp->rd_softc;
2839 struct wsdisplay_font *font = PICK_FONT(ri, c);
2840 uint32_t bg, fg, gmc;
2841 uint8_t *data;
2842 int w, h, xd, yd;
2843 int i, r, g, b, aval;
2844 int rf, gf, bf, rb, gb, bb;
2845 uint32_t pixel;
2846 int rv;
2847
2848 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL)
2849 return;
2850
2851 if (!CHAR_IN_FONT(c, font))
2852 return;
2853
2854 w = font->fontwidth;
2855 h = font->fontheight;
2856
2857 bg = ri->ri_devcmap[(attr >> 16) & 0xf];
2858 fg = ri->ri_devcmap[(attr >> 24) & 0xf];
2859
2860 xd = ri->ri_xorigin + col * w;
2861 yd = ri->ri_yorigin + row * h;
2862
2863 if (c == 0x20) {
2864 radeonfb_rectfill(dp, xd, yd, w, h, bg);
2865 if (attr & 1)
2866 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg);
2867 return;
2868 }
2869 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr);
2870 if (rv == GC_OK)
2871 return;
2872
2873 data = WSFONT_GLYPH(c, font);
2874
2875 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
2876
2877 radeonfb_wait_fifo(sc, 5);
2878
2879 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
2880 RADEON_GMC_BRUSH_NONE |
2881 RADEON_GMC_SRC_DATATYPE_COLOR |
2882 RADEON_ROP3_S |
2883 RADEON_DP_SRC_SOURCE_HOST_DATA |
2884 RADEON_GMC_CLR_CMP_CNTL_DIS |
2885 RADEON_GMC_WR_MSK_DIS |
2886 gmc);
2887
2888 PUT32(sc, RADEON_DP_CNTL,
2889 RADEON_DST_X_LEFT_TO_RIGHT |
2890 RADEON_DST_Y_TOP_TO_BOTTOM);
2891
2892 PUT32(sc, RADEON_SRC_X_Y, 0);
2893 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd);
2894 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h);
2895
2896 rf = (fg >> 16) & 0xff;
2897 rb = (bg >> 16) & 0xff;
2898 gf = (fg >> 8) & 0xff;
2899 gb = (bg >> 8) & 0xff;
2900 bf = fg & 0xff;
2901 bb = bg & 0xff;
2902
2903 /*
2904 * I doubt we can upload data faster than even the slowest Radeon
2905 * could process them, especially when doing the alpha blending stuff
2906 * along the way, so just make sure there's some room in the FIFO and
2907 * then hammer away
2908 * As it turns out we can, so make periodic stops to let the FIFO
2909 * drain.
2910 */
2911 radeonfb_wait_fifo(sc, 20);
2912 for (i = 0; i < ri->ri_fontscale; i++) {
2913 aval = *data;
2914 data++;
2915 if (aval == 0) {
2916 pixel = bg;
2917 } else if (aval == 255) {
2918 pixel = fg;
2919 } else {
2920 r = aval * rf + (255 - aval) * rb;
2921 g = aval * gf + (255 - aval) * gb;
2922 b = aval * bf + (255 - aval) * bb;
2923 pixel = (r & 0xff00) << 8 |
2924 (g & 0xff00) |
2925 (b & 0xff00) >> 8;
2926 }
2927 if (i & 16)
2928 radeonfb_wait_fifo(sc, 20);
2929 PUT32(sc, RADEON_HOST_DATA0, pixel);
2930 }
2931 if (rv == GC_ADD) {
2932 glyphcache_add(&dp->rd_gc, c, xd, yd);
2933 } else
2934 if (attr & 1)
2935 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg);
2936
2937 }
2938
2939 static void
radeonfb_putchar_aa8(void * cookie,int row,int col,u_int c,long attr)2940 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr)
2941 {
2942 struct rasops_info *ri = cookie;
2943 struct vcons_screen *scr = ri->ri_hw;
2944 struct radeonfb_display *dp = scr->scr_cookie;
2945 struct radeonfb_softc *sc = dp->rd_softc;
2946 struct wsdisplay_font *font = PICK_FONT(ri, c);
2947 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc;
2948 int i, x, y, wi, he, r, g, b, aval;
2949 int r1, g1, b1, r0, g0, b0, fgo, bgo;
2950 uint8_t *data8;
2951 int rv, cnt;
2952
2953 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL)
2954 return;
2955
2956 if (!CHAR_IN_FONT(c, font))
2957 return;
2958
2959 wi = font->fontwidth;
2960 he = font->fontheight;
2961
2962 bg = ri->ri_devcmap[(attr >> 16) & 0xf];
2963 fg = ri->ri_devcmap[(attr >> 24) & 0xf];
2964
2965 x = ri->ri_xorigin + col * wi;
2966 y = ri->ri_yorigin + row * he;
2967
2968 if (c == 0x20) {
2969 radeonfb_rectfill(dp, x, y, wi, he, bg);
2970 if (attr & 1)
2971 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg);
2972 return;
2973 }
2974 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr);
2975 if (rv == GC_OK)
2976 return;
2977
2978 data8 = WSFONT_GLYPH(c, font);
2979
2980 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
2981
2982 radeonfb_wait_fifo(sc, 5);
2983
2984 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
2985 RADEON_GMC_BRUSH_NONE |
2986 RADEON_GMC_SRC_DATATYPE_COLOR |
2987 RADEON_ROP3_S |
2988 RADEON_DP_SRC_SOURCE_HOST_DATA |
2989 RADEON_GMC_CLR_CMP_CNTL_DIS |
2990 RADEON_GMC_WR_MSK_DIS |
2991 gmc);
2992
2993 PUT32(sc, RADEON_DP_CNTL,
2994 RADEON_DST_X_LEFT_TO_RIGHT |
2995 RADEON_DST_Y_TOP_TO_BOTTOM);
2996
2997 PUT32(sc, RADEON_SRC_X_Y, 0);
2998 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y);
2999 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he);
3000
3001 /*
3002 * we need the RGB colours here, so get offsets into rasops_cmap
3003 */
3004 fgo = ((attr >> 24) & 0xf) * 3;
3005 bgo = ((attr >> 16) & 0xf) * 3;
3006
3007 r0 = rasops_cmap[bgo];
3008 r1 = rasops_cmap[fgo];
3009 g0 = rasops_cmap[bgo + 1];
3010 g1 = rasops_cmap[fgo + 1];
3011 b0 = rasops_cmap[bgo + 2];
3012 b1 = rasops_cmap[fgo + 2];
3013 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6))
3014 bg8 = R3G3B2(r0, g0, b0);
3015 fg8 = R3G3B2(r1, g1, b1);
3016
3017 radeonfb_wait_fifo(sc, 20);
3018 cnt = 0;
3019 for (i = 0; i < ri->ri_fontscale; i++) {
3020 aval = *data8;
3021 if (aval == 0) {
3022 pixel = bg8;
3023 } else if (aval == 255) {
3024 pixel = fg8;
3025 } else {
3026 r = aval * r1 + (255 - aval) * r0;
3027 g = aval * g1 + (255 - aval) * g0;
3028 b = aval * b1 + (255 - aval) * b0;
3029 pixel = ((r & 0xe000) >> 8) |
3030 ((g & 0xe000) >> 11) |
3031 ((b & 0xc000) >> 14);
3032 }
3033 latch |= pixel << (8 * (i & 3));
3034 /* write in 32bit chunks */
3035 if ((i & 3) == 3) {
3036 PUT32(sc, RADEON_HOST_DATA0, latch);
3037 /*
3038 * not strictly necessary, old data should be shifted
3039 * out
3040 */
3041 latch = 0;
3042 cnt++;
3043 if (cnt > 16) {
3044 cnt = 0;
3045 radeonfb_wait_fifo(sc, 20);
3046 }
3047 }
3048 data8++;
3049 }
3050 /* if we have pixels left in latch write them out */
3051 if ((i & 3) != 0) {
3052 /*
3053 * radeon is weird - apparently leftover pixels are written
3054 * from the middle, not from the left as everything else
3055 */
3056 PUT32(sc, RADEON_HOST_DATA0, latch);
3057 }
3058
3059 if (rv == GC_ADD) {
3060 glyphcache_add(&dp->rd_gc, c, x, y);
3061 } else
3062 if (attr & 1)
3063 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg);
3064
3065 }
3066
3067 /*
3068 * wrapper for software character drawing
3069 * just sync the engine and call rasops*_putchar()
3070 */
3071
3072 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR
3073 static void
radeonfb_putchar_wrapper(void * cookie,int row,int col,u_int c,long attr)3074 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr)
3075 {
3076 struct rasops_info *ri = cookie;
3077 struct vcons_screen *scr = ri->ri_hw;
3078 struct radeonfb_display *dp = scr->scr_cookie;
3079
3080 radeonfb_engine_idle(dp->rd_softc);
3081 dp->rd_putchar(ri, row, col, c, attr);
3082 }
3083 #endif
3084
3085 static void
radeonfb_eraserows(void * cookie,int row,int nrows,long fillattr)3086 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr)
3087 {
3088 struct rasops_info *ri = cookie;
3089 struct vcons_screen *scr = ri->ri_hw;
3090 struct radeonfb_display *dp = scr->scr_cookie;
3091 uint32_t x, y, w, h, fg, bg, ul;
3092
3093 /* XXX: check for full emulation mode? */
3094 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
3095 x = ri->ri_xorigin;
3096 y = ri->ri_yorigin + ri->ri_font->fontheight * row;
3097 w = ri->ri_emuwidth;
3098 h = ri->ri_font->fontheight * nrows;
3099
3100 rasops_unpack_attr(fillattr, &fg, &bg, &ul);
3101 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]);
3102 }
3103 }
3104
3105 static void
radeonfb_copyrows(void * cookie,int srcrow,int dstrow,int nrows)3106 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows)
3107 {
3108 struct rasops_info *ri = cookie;
3109 struct vcons_screen *scr = ri->ri_hw;
3110 struct radeonfb_display *dp = scr->scr_cookie;
3111 uint32_t x, ys, yd, w, h;
3112
3113 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
3114 x = ri->ri_xorigin;
3115 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow;
3116 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow;
3117 w = ri->ri_emuwidth;
3118 h = ri->ri_font->fontheight * nrows;
3119 radeonfb_bitblt(dp, x, ys, x, yd, w, h,
3120 RADEON_ROP3_S);
3121 }
3122 }
3123
3124 static void
radeonfb_copycols(void * cookie,int row,int srccol,int dstcol,int ncols)3125 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols)
3126 {
3127 struct rasops_info *ri = cookie;
3128 struct vcons_screen *scr = ri->ri_hw;
3129 struct radeonfb_display *dp = scr->scr_cookie;
3130 uint32_t xs, xd, y, w, h;
3131
3132 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
3133 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol;
3134 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol;
3135 y = ri->ri_yorigin + ri->ri_font->fontheight * row;
3136 w = ri->ri_font->fontwidth * ncols;
3137 h = ri->ri_font->fontheight;
3138 radeonfb_bitblt(dp, xs, y, xd, y, w, h,
3139 RADEON_ROP3_S);
3140 }
3141 }
3142
3143 static void
radeonfb_erasecols(void * cookie,int row,int startcol,int ncols,long fillattr)3144 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols,
3145 long fillattr)
3146 {
3147 struct rasops_info *ri = cookie;
3148 struct vcons_screen *scr = ri->ri_hw;
3149 struct radeonfb_display *dp = scr->scr_cookie;
3150 uint32_t x, y, w, h, fg, bg, ul;
3151
3152 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
3153 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol;
3154 y = ri->ri_yorigin + ri->ri_font->fontheight * row;
3155 w = ri->ri_font->fontwidth * ncols;
3156 h = ri->ri_font->fontheight;
3157
3158 rasops_unpack_attr(fillattr, &fg, &bg, &ul);
3159 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]);
3160 }
3161 }
3162
3163 static void
radeonfb_cursor(void * cookie,int on,int row,int col)3164 radeonfb_cursor(void *cookie, int on, int row, int col)
3165 {
3166 struct rasops_info *ri = cookie;
3167 struct vcons_screen *scr = ri->ri_hw;
3168 struct radeonfb_display *dp = scr->scr_cookie;
3169 int x, y, wi, he;
3170
3171 wi = ri->ri_font->fontwidth;
3172 he = ri->ri_font->fontheight;
3173
3174 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
3175 x = ri->ri_ccol * wi + ri->ri_xorigin;
3176 y = ri->ri_crow * he + ri->ri_yorigin;
3177 /* first turn off the old cursor */
3178 if (ri->ri_flg & RI_CURSOR) {
3179 radeonfb_bitblt(dp, x, y, x, y, wi, he,
3180 RADEON_ROP3_Dn);
3181 ri->ri_flg &= ~RI_CURSOR;
3182 }
3183 ri->ri_crow = row;
3184 ri->ri_ccol = col;
3185 /* then (possibly) turn on the new one */
3186 if (on) {
3187 x = ri->ri_ccol * wi + ri->ri_xorigin;
3188 y = ri->ri_crow * he + ri->ri_yorigin;
3189 radeonfb_bitblt(dp, x, y, x, y, wi, he,
3190 RADEON_ROP3_Dn);
3191 ri->ri_flg |= RI_CURSOR;
3192 }
3193 } else {
3194 scr->scr_ri.ri_crow = row;
3195 scr->scr_ri.ri_ccol = col;
3196 scr->scr_ri.ri_flg &= ~RI_CURSOR;
3197 }
3198 }
3199
3200 /*
3201 * Underlying acceleration support.
3202 */
3203
3204 static void
radeonfb_rectfill(struct radeonfb_display * dp,int dstx,int dsty,int width,int height,uint32_t color)3205 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty,
3206 int width, int height, uint32_t color)
3207 {
3208 struct radeonfb_softc *sc = dp->rd_softc;
3209 uint32_t gmc;
3210
3211 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
3212
3213 radeonfb_wait_fifo(sc, 6);
3214
3215 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3216 RADEON_GMC_BRUSH_SOLID_COLOR |
3217 RADEON_GMC_SRC_DATATYPE_COLOR |
3218 RADEON_GMC_CLR_CMP_CNTL_DIS |
3219 RADEON_ROP3_P | gmc);
3220
3221 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color);
3222 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);
3223 PUT32(sc, RADEON_DP_CNTL,
3224 RADEON_DST_X_LEFT_TO_RIGHT |
3225 RADEON_DST_Y_TOP_TO_BOTTOM);
3226 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx);
3227 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height));
3228
3229 }
3230
3231 static void
radeonfb_rectfill_a(void * cookie,int dstx,int dsty,int width,int height,long attr)3232 radeonfb_rectfill_a(void *cookie, int dstx, int dsty,
3233 int width, int height, long attr)
3234 {
3235 struct radeonfb_display *dp = cookie;
3236
3237 radeonfb_rectfill(dp, dstx, dsty, width, height,
3238 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]);
3239 }
3240
3241 static void
radeonfb_bitblt(void * cookie,int srcx,int srcy,int dstx,int dsty,int width,int height,int rop)3242 radeonfb_bitblt(void *cookie, int srcx, int srcy,
3243 int dstx, int dsty, int width, int height, int rop)
3244 {
3245 struct radeonfb_display *dp = cookie;
3246 struct radeonfb_softc *sc = dp->rd_softc;
3247 uint32_t gmc;
3248 uint32_t dir;
3249
3250 if (dsty < srcy) {
3251 dir = RADEON_DST_Y_TOP_TO_BOTTOM;
3252 } else {
3253 srcy += height - 1;
3254 dsty += height - 1;
3255 dir = 0;
3256 }
3257 if (dstx < srcx) {
3258 dir |= RADEON_DST_X_LEFT_TO_RIGHT;
3259 } else {
3260 srcx += width - 1;
3261 dstx += width - 1;
3262 }
3263
3264 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
3265
3266 radeonfb_wait_fifo(sc, 6);
3267
3268 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3269 RADEON_GMC_BRUSH_SOLID_COLOR |
3270 RADEON_GMC_SRC_DATATYPE_COLOR |
3271 RADEON_GMC_CLR_CMP_CNTL_DIS |
3272 RADEON_DP_SRC_SOURCE_MEMORY |
3273 rop | gmc);
3274
3275 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);
3276 PUT32(sc, RADEON_DP_CNTL, dir);
3277 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx);
3278 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx);
3279 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height));
3280 }
3281
3282 static void
radeonfb_engine_idle(struct radeonfb_softc * sc)3283 radeonfb_engine_idle(struct radeonfb_softc *sc)
3284 {
3285
3286 radeonfb_wait_fifo(sc, 64);
3287 while ((GET32(sc, RADEON_RBBM_STATUS) &
3288 RADEON_RBBM_ACTIVE) != 0);
3289 radeonfb_engine_flush(sc);
3290 }
3291
3292 static inline void
radeonfb_wait_fifo(struct radeonfb_softc * sc,int n)3293 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n)
3294 {
3295 int i;
3296
3297 for (i = RADEON_TIMEOUT; i; i--) {
3298 if ((GET32(sc, RADEON_RBBM_STATUS) &
3299 RADEON_RBBM_FIFOCNT_MASK) >= n)
3300 return;
3301 }
3302 #ifdef DIAGNOSTIC
3303 if (!i)
3304 printf("%s: timed out waiting for fifo (%x)\n",
3305 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS));
3306 #endif
3307 }
3308
3309 static void
radeonfb_engine_flush(struct radeonfb_softc * sc)3310 radeonfb_engine_flush(struct radeonfb_softc *sc)
3311 {
3312 int i = 0;
3313
3314 if (IS_R300(sc)) {
3315 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL);
3316 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) {
3317 i++;
3318 }
3319 } else {
3320 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT,
3321 RADEON_RB2D_DC_FLUSH_ALL);
3322 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) &
3323 RADEON_RB2D_DC_BUSY) {
3324 i++;
3325 }
3326 }
3327 #ifdef DIAGNOSTIC
3328 if (i > RADEON_TIMEOUT)
3329 printf("%s: engine flush timed out!\n", XNAME(sc));
3330 #endif
3331 }
3332
3333 static inline void
radeonfb_unclip(struct radeonfb_softc * sc)3334 radeonfb_unclip(struct radeonfb_softc *sc)
3335 {
3336
3337 radeonfb_wait_fifo(sc, 2);
3338 PUT32(sc, RADEON_SC_TOP_LEFT, 0);
3339 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff);
3340 }
3341
3342 static void
radeonfb_engine_init(struct radeonfb_display * dp)3343 radeonfb_engine_init(struct radeonfb_display *dp)
3344 {
3345 struct radeonfb_softc *sc = dp->rd_softc;
3346 uint32_t pitch;
3347
3348 /* no 3D */
3349 PUT32(sc, RADEON_RB3D_CNTL, 0);
3350
3351 radeonfb_engine_reset(sc);
3352 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6;
3353
3354 radeonfb_wait_fifo(sc, 1);
3355 if (!IS_R300(sc))
3356 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0);
3357
3358 radeonfb_wait_fifo(sc, 3);
3359 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET,
3360 (pitch << 22) | (sc->sc_aperbase >> 10));
3361
3362
3363 PUT32(sc, RADEON_DST_PITCH_OFFSET,
3364 (pitch << 22) | (sc->sc_aperbase >> 10));
3365 PUT32(sc, RADEON_SRC_PITCH_OFFSET,
3366 (pitch << 22) | (sc->sc_aperbase >> 10));
3367
3368 (void)GET32(sc, RADEON_DP_DATATYPE);
3369
3370 /* default scissors -- no clipping */
3371 radeonfb_wait_fifo(sc, 1);
3372 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT,
3373 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);
3374
3375 radeonfb_wait_fifo(sc, 1);
3376 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3377 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) |
3378 RADEON_GMC_CLR_CMP_CNTL_DIS |
3379 RADEON_GMC_BRUSH_SOLID_COLOR |
3380 RADEON_GMC_SRC_DATATYPE_COLOR);
3381
3382 radeonfb_wait_fifo(sc, 10);
3383 PUT32(sc, RADEON_DST_LINE_START, 0);
3384 PUT32(sc, RADEON_DST_LINE_END, 0);
3385 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);
3386 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0);
3387 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff);
3388 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0);
3389 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);
3390 PUT32(sc, RADEON_SC_TOP_LEFT, 0);
3391 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff);
3392 PUT32(sc, RADEON_AUX_SC_CNTL, 0);
3393 radeonfb_engine_idle(sc);
3394 }
3395
3396 static void
radeonfb_engine_reset(struct radeonfb_softc * sc)3397 radeonfb_engine_reset(struct radeonfb_softc *sc)
3398 {
3399 uint32_t hpc, rbbm, mclkcntl, clkindex;
3400
3401 radeonfb_engine_flush(sc);
3402
3403 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX);
3404 if (HAS_R300CG(sc))
3405 radeonfb_r300cg_workaround(sc);
3406 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL);
3407
3408 /*
3409 * According to comments in XFree code, resetting the HDP via
3410 * the RBBM_SOFT_RESET can cause bad behavior on some systems.
3411 * So we use HOST_PATH_CNTL instead.
3412 */
3413
3414 hpc = GET32(sc, RADEON_HOST_PATH_CNTL);
3415 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET);
3416 if (IS_R300(sc)) {
3417 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm |
3418 RADEON_SOFT_RESET_CP |
3419 RADEON_SOFT_RESET_HI |
3420 RADEON_SOFT_RESET_E2);
3421 GET32(sc, RADEON_RBBM_SOFT_RESET);
3422 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0);
3423 /*
3424 * XXX: this bit is not defined in any ATI docs I have,
3425 * nor in the XFree code, but XFree does it. Why?
3426 */
3427 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17));
3428 } else {
3429 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm |
3430 RADEON_SOFT_RESET_CP |
3431 RADEON_SOFT_RESET_SE |
3432 RADEON_SOFT_RESET_RE |
3433 RADEON_SOFT_RESET_PP |
3434 RADEON_SOFT_RESET_E2 |
3435 RADEON_SOFT_RESET_RB);
3436 GET32(sc, RADEON_RBBM_SOFT_RESET);
3437 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm &
3438 ~(RADEON_SOFT_RESET_CP |
3439 RADEON_SOFT_RESET_SE |
3440 RADEON_SOFT_RESET_RE |
3441 RADEON_SOFT_RESET_PP |
3442 RADEON_SOFT_RESET_E2 |
3443 RADEON_SOFT_RESET_RB));
3444 GET32(sc, RADEON_RBBM_SOFT_RESET);
3445 }
3446
3447 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET);
3448 GET32(sc, RADEON_HOST_PATH_CNTL);
3449 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc);
3450
3451 if (IS_R300(sc))
3452 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm);
3453
3454 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex);
3455 PRINTREG(RADEON_CLOCK_CNTL_INDEX);
3456 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl);
3457
3458 if (HAS_R300CG(sc))
3459 radeonfb_r300cg_workaround(sc);
3460 }
3461
3462 static int
radeonfb_set_curpos(struct radeonfb_display * dp,struct wsdisplay_curpos * pos)3463 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos)
3464 {
3465 int x, y;
3466
3467 x = pos->x;
3468 y = pos->y;
3469
3470 /*
3471 * This doesn't let a cursor move off the screen. I'm not
3472 * sure if this will have negative effects for e.g. Xinerama.
3473 * I'd guess Xinerama handles it by changing the cursor shape,
3474 * but that needs verification.
3475 */
3476 if (x >= dp->rd_virtx)
3477 x = dp->rd_virtx - 1;
3478 if (x < 0)
3479 x = 0;
3480 if (y >= dp->rd_virty)
3481 y = dp->rd_virty - 1;
3482 if (y < 0)
3483 y = 0;
3484
3485 dp->rd_cursor.rc_pos.x = x;
3486 dp->rd_cursor.rc_pos.y = y;
3487
3488 radeonfb_cursor_position(dp);
3489 return 0;
3490 }
3491
3492 static int
radeonfb_set_cursor(struct radeonfb_display * dp,struct wsdisplay_cursor * wc)3493 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc)
3494 {
3495 unsigned flags;
3496
3497 uint8_t r[2], g[2], b[2];
3498 unsigned index, count;
3499 int i, err;
3500 int pitch, size;
3501 struct radeonfb_cursor nc;
3502
3503 flags = wc->which;
3504
3505 /* copy old values */
3506 nc = dp->rd_cursor;
3507
3508 if (flags & WSDISPLAY_CURSOR_DOCMAP) {
3509 index = wc->cmap.index;
3510 count = wc->cmap.count;
3511
3512 if (index >= 2 || (index + count) > 2)
3513 return EINVAL;
3514
3515 err = copyin(wc->cmap.red, &r[index], count);
3516 if (err)
3517 return err;
3518 err = copyin(wc->cmap.green, &g[index], count);
3519 if (err)
3520 return err;
3521 err = copyin(wc->cmap.blue, &b[index], count);
3522 if (err)
3523 return err;
3524
3525 for (i = index; i < index + count; i++) {
3526 nc.rc_cmap[i] =
3527 (r[i] << 16) + (g[i] << 8) + (b[i] << 0);
3528 }
3529 }
3530
3531 if (flags & WSDISPLAY_CURSOR_DOSHAPE) {
3532 if ((wc->size.x > RADEON_CURSORMAXX) ||
3533 (wc->size.y > RADEON_CURSORMAXY))
3534 return EINVAL;
3535
3536 /* figure bytes per line */
3537 pitch = (wc->size.x + 7) / 8;
3538 size = pitch * wc->size.y;
3539
3540 /* clear the old cursor and mask */
3541 memset(nc.rc_image, 0, 512);
3542 memset(nc.rc_mask, 0, 512);
3543
3544 nc.rc_size = wc->size;
3545
3546 if ((err = copyin(wc->image, nc.rc_image, size)) != 0)
3547 return err;
3548
3549 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0)
3550 return err;
3551 }
3552
3553 if (flags & WSDISPLAY_CURSOR_DOHOT) {
3554 nc.rc_hot = wc->hot;
3555 if (nc.rc_hot.x >= nc.rc_size.x)
3556 nc.rc_hot.x = nc.rc_size.x - 1;
3557 if (nc.rc_hot.y >= nc.rc_size.y)
3558 nc.rc_hot.y = nc.rc_size.y - 1;
3559 }
3560
3561 if (flags & WSDISPLAY_CURSOR_DOPOS) {
3562 nc.rc_pos = wc->pos;
3563 if (nc.rc_pos.x >= dp->rd_virtx)
3564 nc.rc_pos.x = dp->rd_virtx - 1;
3565 #if 0
3566 if (nc.rc_pos.x < 0)
3567 nc.rc_pos.x = 0;
3568 #endif
3569 if (nc.rc_pos.y >= dp->rd_virty)
3570 nc.rc_pos.y = dp->rd_virty - 1;
3571 #if 0
3572 if (nc.rc_pos.y < 0)
3573 nc.rc_pos.y = 0;
3574 #endif
3575 }
3576 if (flags & WSDISPLAY_CURSOR_DOCUR) {
3577 nc.rc_visible = wc->enable;
3578 }
3579
3580 dp->rd_cursor = nc;
3581 radeonfb_cursor_update(dp, wc->which);
3582
3583 return 0;
3584 }
3585
3586 static uint8_t
radeonfb_backwards(uint8_t d)3587 radeonfb_backwards(uint8_t d)
3588 {
3589 uint8_t l;
3590
3591 l = d << 7;
3592 l |= ((d & 0x02) << 5);
3593 l |= ((d & 0x04) << 3);
3594 l |= ((d & 0x08) << 1);
3595 l |= ((d & 0x10) >> 1);
3596 l |= ((d & 0x20) >> 3);
3597 l |= ((d & 0x40) >> 5);
3598 l |= ((d & 0x80) >> 7);
3599 return l;
3600 }
3601
3602 /*
3603 * Change the cursor shape. Call this with the cursor locked to avoid
3604 * flickering/tearing.
3605 */
3606 static void
radeonfb_cursor_shape(struct radeonfb_display * dp)3607 radeonfb_cursor_shape(struct radeonfb_display *dp)
3608 {
3609 uint8_t and[512], xor[512];
3610 int i, j, src, dst /* , pitch */;
3611 const uint8_t *msk = dp->rd_cursor.rc_mask;
3612 const uint8_t *img = dp->rd_cursor.rc_image;
3613
3614 /*
3615 * Radeon cursor data interleaves one line of AND data followed
3616 * by a line of XOR data. (Each line corresponds to a whole hardware
3617 * pitch - i.e. 64 pixels or 8 bytes.)
3618 *
3619 * The cursor is displayed using the following table:
3620 *
3621 * AND XOR Result
3622 * ----------------------
3623 * 0 0 Cursor color 0
3624 * 0 1 Cursor color 1
3625 * 1 0 Transparent
3626 * 1 1 Complement of background
3627 *
3628 * Our masks are therefore different from what we were passed.
3629 * Passed in, I'm assuming the data represents either color 0 or 1,
3630 * and a mask, so the passed in table looks like:
3631 *
3632 * IMG Mask Result
3633 * -----------------------
3634 * 0 0 Transparent
3635 * 0 1 Cursor color 0
3636 * 1 0 Transparent
3637 * 1 1 Cursor color 1
3638 *
3639 * IF mask bit == 1, AND = 0, XOR = color.
3640 * IF mask bit == 0, AND = 1, XOR = 0.
3641 *
3642 * hence: AND = ~(mask); XOR = color & ~(mask);
3643 */
3644
3645 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */
3646
3647 /* start by assuming all bits are transparent */
3648 memset(and, 0xff, 512);
3649 memset(xor, 0x00, 512);
3650
3651 src = 0;
3652 dst = 0;
3653 for (i = 0; i < 64; i++) {
3654 for (j = 0; j < 64; j += 8) {
3655 if ((i < dp->rd_cursor.rc_size.y) &&
3656 (j < dp->rd_cursor.rc_size.x)) {
3657
3658 /* take care to leave odd bits alone */
3659 and[dst] &= ~(msk[src]);
3660 xor[dst] = img[src] & msk[src];
3661 src++;
3662 }
3663 dst++;
3664 }
3665 }
3666
3667 for (i = 0; i < 512; i++) {
3668 and[i] = radeonfb_backwards(and[i]);
3669 xor[i] = radeonfb_backwards(xor[i]);
3670 }
3671
3672 /* copy the image into place */
3673 for (i = 0; i < 64; i++) {
3674 memcpy((uint8_t *)dp->rd_curptr + (i * 16),
3675 &and[i * 8], 8);
3676 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8,
3677 &xor[i * 8], 8);
3678 }
3679 }
3680
3681 static void
radeonfb_cursor_position(struct radeonfb_display * dp)3682 radeonfb_cursor_position(struct radeonfb_display *dp)
3683 {
3684 struct radeonfb_softc *sc = dp->rd_softc;
3685 uint32_t offset, hvoff, hvpos; /* registers */
3686 uint32_t coff; /* cursor offset */
3687 int i, x, y, xoff, yoff, crtcoff;
3688
3689 /*
3690 * XXX: this also needs to handle pan/scan
3691 */
3692 for (i = 0; i < dp->rd_ncrtcs; i++) {
3693
3694 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i];
3695
3696 if (rcp->rc_number) {
3697 offset = RADEON_CUR2_OFFSET;
3698 hvoff = RADEON_CUR2_HORZ_VERT_OFF;
3699 hvpos = RADEON_CUR2_HORZ_VERT_POSN;
3700 crtcoff = RADEON_CRTC2_OFFSET;
3701 } else {
3702 offset = RADEON_CUR_OFFSET;
3703 hvoff = RADEON_CUR_HORZ_VERT_OFF;
3704 hvpos = RADEON_CUR_HORZ_VERT_POSN;
3705 crtcoff = RADEON_CRTC_OFFSET;
3706 }
3707
3708 x = dp->rd_cursor.rc_pos.x;
3709 y = dp->rd_cursor.rc_pos.y;
3710
3711 while (y < rcp->rc_yoffset) {
3712 rcp->rc_yoffset -= RADEON_PANINCREMENT;
3713 }
3714 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) {
3715 rcp->rc_yoffset += RADEON_PANINCREMENT;
3716 }
3717 while (x < rcp->rc_xoffset) {
3718 rcp->rc_xoffset -= RADEON_PANINCREMENT;
3719 }
3720 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) {
3721 rcp->rc_xoffset += RADEON_PANINCREMENT;
3722 }
3723
3724 /* adjust for the cursor's hotspot */
3725 x -= dp->rd_cursor.rc_hot.x;
3726 y -= dp->rd_cursor.rc_hot.y;
3727 xoff = yoff = 0;
3728
3729 if (x >= dp->rd_virtx)
3730 x = dp->rd_virtx - 1;
3731 if (y >= dp->rd_virty)
3732 y = dp->rd_virty - 1;
3733
3734 /* now adjust cursor so it is relative to viewport */
3735 x -= rcp->rc_xoffset;
3736 y -= rcp->rc_yoffset;
3737
3738 /*
3739 * no need to check for fall off, because we should
3740 * never move off the screen entirely!
3741 */
3742 coff = 0;
3743 if (x < 0) {
3744 xoff = -x;
3745 x = 0;
3746 }
3747 if (y < 0) {
3748 yoff = -y;
3749 y = 0;
3750 coff = (yoff * 2) * 8;
3751 }
3752
3753 /* pan the display */
3754 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) +
3755 rcp->rc_xoffset);
3756
3757 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK);
3758 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK);
3759 /* NB: this unlocks the cursor */
3760 PUT32(sc, hvpos, (x << 16) | y);
3761 }
3762 }
3763
3764 static void
radeonfb_cursor_visible(struct radeonfb_display * dp)3765 radeonfb_cursor_visible(struct radeonfb_display *dp)
3766 {
3767 int i;
3768 uint32_t gencntl, bit;
3769
3770 for (i = 0; i < dp->rd_ncrtcs; i++) {
3771 if (dp->rd_crtcs[i].rc_number) {
3772 gencntl = RADEON_CRTC2_GEN_CNTL;
3773 bit = RADEON_CRTC2_CUR_EN;
3774 } else {
3775 gencntl = RADEON_CRTC_GEN_CNTL;
3776 bit = RADEON_CRTC_CUR_EN;
3777 }
3778
3779 if (dp->rd_cursor.rc_visible)
3780 SET32(dp->rd_softc, gencntl, bit);
3781 else
3782 CLR32(dp->rd_softc, gencntl, bit);
3783 }
3784 }
3785
3786 static void
radeonfb_cursor_cmap(struct radeonfb_display * dp)3787 radeonfb_cursor_cmap(struct radeonfb_display *dp)
3788 {
3789 int i;
3790 uint32_t c0reg, c1reg;
3791 struct radeonfb_softc *sc = dp->rd_softc;
3792
3793 for (i = 0; i < dp->rd_ncrtcs; i++) {
3794 if (dp->rd_crtcs[i].rc_number) {
3795 c0reg = RADEON_CUR2_CLR0;
3796 c1reg = RADEON_CUR2_CLR1;
3797 } else {
3798 c0reg = RADEON_CUR_CLR0;
3799 c1reg = RADEON_CUR_CLR1;
3800 }
3801
3802 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]);
3803 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]);
3804 }
3805 }
3806
3807 static void
radeonfb_cursor_update(struct radeonfb_display * dp,unsigned which)3808 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which)
3809 {
3810 struct radeonfb_softc *sc;
3811 int i;
3812
3813 sc = dp->rd_softc;
3814 for (i = 0; i < dp->rd_ncrtcs; i++) {
3815 if (dp->rd_crtcs[i].rc_number) {
3816 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK);
3817 } else {
3818 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK);
3819 }
3820 }
3821
3822 if (which & WSDISPLAY_CURSOR_DOCMAP)
3823 radeonfb_cursor_cmap(dp);
3824
3825 if (which & WSDISPLAY_CURSOR_DOSHAPE)
3826 radeonfb_cursor_shape(dp);
3827
3828 if (which & WSDISPLAY_CURSOR_DOCUR)
3829 radeonfb_cursor_visible(dp);
3830
3831 /* this one is unconditional, because it updates other stuff */
3832 radeonfb_cursor_position(dp);
3833 }
3834
3835 static struct videomode *
radeonfb_best_refresh(struct videomode * m1,struct videomode * m2)3836 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2)
3837 {
3838 int r1, r2;
3839
3840 /* otherwise pick the higher refresh rate */
3841 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal);
3842 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal);
3843
3844 return (r1 < r2 ? m2 : m1);
3845 }
3846
3847 static const struct videomode *
radeonfb_port_mode(struct radeonfb_softc * sc,struct radeonfb_port * rp,int x,int y)3848 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp,
3849 int x, int y)
3850 {
3851 struct edid_info *ep = &rp->rp_edid;
3852 struct videomode *vmp = NULL;
3853 int i;
3854
3855 if (!rp->rp_edid_valid) {
3856 /* fallback to safe mode */
3857 return radeonfb_modelookup(sc->sc_defaultmode);
3858 }
3859
3860 /* always choose the preferred mode first! */
3861 if (ep->edid_preferred_mode) {
3862
3863 /* XXX: add auto-stretching support for native mode */
3864
3865 /* this may want panning to occur, btw */
3866 if ((ep->edid_preferred_mode->hdisplay <= x) &&
3867 (ep->edid_preferred_mode->vdisplay <= y))
3868 return ep->edid_preferred_mode;
3869 }
3870
3871 for (i = 0; i < ep->edid_nmodes; i++) {
3872 /*
3873 * We elect to pick a resolution that is too large for
3874 * the monitor than one that is too small. This means
3875 * that we will prefer to pan rather than to try to
3876 * center a smaller display on a larger screen. In
3877 * practice, this shouldn't matter because if a
3878 * monitor can support a larger resolution, it can
3879 * probably also support the smaller. A specific
3880 * exception is fixed format panels, but hopefully
3881 * they are properly dealt with by the "autostretch"
3882 * logic above.
3883 */
3884 if ((ep->edid_modes[i].hdisplay > x) ||
3885 (ep->edid_modes[i].vdisplay > y)) {
3886 continue;
3887 }
3888
3889 /*
3890 * at this point, the display mode is no larger than
3891 * what we've requested.
3892 */
3893 if (vmp == NULL)
3894 vmp = &ep->edid_modes[i];
3895
3896 /* eliminate smaller modes */
3897 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) ||
3898 (vmp->vdisplay >= ep->edid_modes[i].vdisplay))
3899 continue;
3900
3901 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) ||
3902 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) {
3903 vmp = &ep->edid_modes[i];
3904 continue;
3905 }
3906
3907 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay);
3908 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay);
3909
3910 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]);
3911 }
3912
3913 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode));
3914 }
3915
3916 static int
radeonfb_hasres(struct videomode * list,int nlist,int x,int y)3917 radeonfb_hasres(struct videomode *list, int nlist, int x, int y)
3918 {
3919 int i;
3920
3921 for (i = 0; i < nlist; i++) {
3922 if ((x == list[i].hdisplay) &&
3923 (y == list[i].vdisplay)) {
3924 return 1;
3925 }
3926 }
3927 return 0;
3928 }
3929
3930 static void
radeonfb_pickres(struct radeonfb_display * dp,uint16_t * x,uint16_t * y,int pan)3931 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y,
3932 int pan)
3933 {
3934 struct radeonfb_port *rp;
3935 struct edid_info *ep;
3936 int i, j;
3937
3938 *x = 0;
3939 *y = 0;
3940
3941 if (pan) {
3942 for (i = 0; i < dp->rd_ncrtcs; i++) {
3943 rp = dp->rd_crtcs[i].rc_port;
3944 ep = &rp->rp_edid;
3945 if (!rp->rp_edid_valid) {
3946 /* monitor not present */
3947 continue;
3948 }
3949
3950 /*
3951 * For now we are ignoring "conflict" that
3952 * could occur when mixing some modes like
3953 * 1280x1024 and 1400x800. It isn't clear
3954 * which is better, so the first one wins.
3955 */
3956 for (j = 0; j < ep->edid_nmodes; j++) {
3957 /*
3958 * ignore resolutions that are too big for
3959 * the radeon
3960 */
3961 if (ep->edid_modes[j].hdisplay >
3962 dp->rd_softc->sc_maxx)
3963 continue;
3964 if (ep->edid_modes[j].vdisplay >
3965 dp->rd_softc->sc_maxy)
3966 continue;
3967
3968 /*
3969 * pick largest resolution, the
3970 * smaller monitor will pan
3971 */
3972 if ((ep->edid_modes[j].hdisplay >= *x) &&
3973 (ep->edid_modes[j].vdisplay >= *y)) {
3974 *x = ep->edid_modes[j].hdisplay;
3975 *y = ep->edid_modes[j].vdisplay;
3976 }
3977 }
3978 }
3979
3980 } else {
3981 struct videomode modes[64];
3982 int nmodes = 0;
3983 int valid = 0;
3984
3985 for (i = 0; i < dp->rd_ncrtcs; i++) {
3986 /*
3987 * pick the largest resolution in common.
3988 */
3989 rp = dp->rd_crtcs[i].rc_port;
3990 ep = &rp->rp_edid;
3991
3992 if (!rp->rp_edid_valid)
3993 continue;
3994
3995 if (!valid) {
3996 /*
3997 * Pick the preferred mode for this port
3998 * if available.
3999 */
4000 if (ep->edid_preferred_mode) {
4001 struct videomode *vmp =
4002 ep->edid_preferred_mode;
4003
4004 if ((vmp->hdisplay <=
4005 dp->rd_softc->sc_maxx) &&
4006 (vmp->vdisplay <=
4007 dp->rd_softc->sc_maxy))
4008 modes[nmodes++] = *vmp;
4009 } else {
4010
4011 /* initialize starting list */
4012 for (j = 0; j < ep->edid_nmodes; j++) {
4013 /*
4014 * ignore resolutions that are
4015 * too big for the radeon
4016 */
4017 if (ep->edid_modes[j].hdisplay >
4018 dp->rd_softc->sc_maxx)
4019 continue;
4020 if (ep->edid_modes[j].vdisplay >
4021 dp->rd_softc->sc_maxy)
4022 continue;
4023
4024 modes[nmodes] =
4025 ep->edid_modes[j];
4026 nmodes++;
4027 }
4028 }
4029 valid = 1;
4030 } else {
4031 /* merge into preexisting list */
4032 for (j = 0; j < nmodes; j++) {
4033 if (!radeonfb_hasres(ep->edid_modes,
4034 ep->edid_nmodes,
4035 modes[j].hdisplay,
4036 modes[j].vdisplay)) {
4037 modes[j] = modes[nmodes];
4038 j--;
4039 nmodes--;
4040 }
4041 }
4042 }
4043 }
4044
4045 /* now we have to pick from the merged list */
4046 for (i = 0; i < nmodes; i++) {
4047 if ((modes[i].hdisplay >= *x) &&
4048 (modes[i].vdisplay >= *y)) {
4049 *x = modes[i].hdisplay;
4050 *y = modes[i].vdisplay;
4051 }
4052 }
4053 }
4054
4055 if ((*x == 0) || (*y == 0)) {
4056 /* fallback to safe mode */
4057 *x = 640;
4058 *y = 480;
4059 }
4060 }
4061
4062 /*
4063 * backlight levels are linear on:
4064 * - RV200, RV250, RV280, RV350
4065 * - but NOT on PowerBook4,3 6,3 6,5
4066 * according to Linux' radeonfb
4067 */
4068
4069 /* Get the current backlight level for the display. */
4070
4071 static int
radeonfb_get_backlight(struct radeonfb_display * dp)4072 radeonfb_get_backlight(struct radeonfb_display *dp)
4073 {
4074 int s;
4075 uint32_t level;
4076
4077 s = spltty();
4078
4079 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL);
4080 level &= RADEON_LVDS_BL_MOD_LEV_MASK;
4081 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT;
4082
4083 /*
4084 * On some chips, we should negate the backlight level.
4085 * XXX Find out on which chips.
4086 */
4087 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT)
4088 level = RADEONFB_BACKLIGHT_MAX - level;
4089
4090 splx(s);
4091
4092 return level;
4093 }
4094
4095 /* Set the backlight to the given level for the display. */
4096 static void
radeonfb_switch_backlight(struct radeonfb_display * dp,int on)4097 radeonfb_switch_backlight(struct radeonfb_display *dp, int on)
4098 {
4099 if (dp->rd_bl_on == on)
4100 return;
4101 dp->rd_bl_on = on;
4102 radeonfb_set_backlight(dp, dp->rd_bl_level);
4103 }
4104
4105 static int
radeonfb_set_backlight(struct radeonfb_display * dp,int level)4106 radeonfb_set_backlight(struct radeonfb_display *dp, int level)
4107 {
4108 struct radeonfb_softc *sc = dp->rd_softc;;
4109 int rlevel, s;
4110 uint32_t lvds;
4111
4112 if(!sc->sc_mapped)
4113 return 0;
4114
4115 s = spltty();
4116
4117 dp->rd_bl_level = level;
4118 if (dp->rd_bl_on == 0)
4119 level = 0;
4120
4121 if (level < 0)
4122 level = 0;
4123 else if (level >= RADEONFB_BACKLIGHT_MAX)
4124 level = RADEONFB_BACKLIGHT_MAX;
4125
4126 /* On some chips, we should negate the backlight level. */
4127 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) {
4128 rlevel = RADEONFB_BACKLIGHT_MAX - level;
4129 } else
4130 rlevel = level;
4131
4132 callout_stop(&dp->rd_bl_lvds_co);
4133 radeonfb_engine_idle(sc);
4134
4135 /*
4136 * Turn off the display if the backlight is set to 0, since the
4137 * display is useless without backlight anyway.
4138 */
4139 if (level == 0)
4140 radeonfb_blank(dp, 1);
4141 else if (radeonfb_get_backlight(dp) == 0)
4142 radeonfb_blank(dp, 0);
4143
4144 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL);
4145 lvds &= ~RADEON_LVDS_DISPLAY_DIS;
4146 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) {
4147 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON;
4148 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN;
4149 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds);
4150 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK;
4151 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT;
4152 lvds |= RADEON_LVDS_ON;
4153 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN;
4154 } else {
4155 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK;
4156 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT;
4157 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds);
4158 }
4159
4160 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK;
4161 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK;
4162 /* XXX What is the correct delay? */
4163 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz);
4164
4165 splx(s);
4166
4167 return 0;
4168 }
4169
4170 /*
4171 * Callout function for delayed operations on the LVDS_GEN_CNTL register.
4172 * Set the delayed bits in the register, and clear the stored delayed
4173 * value.
4174 */
4175
radeonfb_lvds_callout(void * arg)4176 static void radeonfb_lvds_callout(void *arg)
4177 {
4178 struct radeonfb_display *dp = arg;
4179 int s;
4180
4181 s = splhigh();
4182
4183 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0,
4184 dp->rd_bl_lvds_val);
4185 dp->rd_bl_lvds_val = 0;
4186
4187 splx(s);
4188 }
4189
4190 static void
radeonfb_brightness_up(device_t dev)4191 radeonfb_brightness_up(device_t dev)
4192 {
4193 struct radeonfb_softc *sc = device_private(dev);
4194 struct radeonfb_display *dp = &sc->sc_displays[0];
4195 int level;
4196
4197 /* we assume the main display is the first one - need a better way */
4198 if (sc->sc_ndisplays < 1) return;
4199 /* make sure pushing the hotkeys always has an effect */
4200 dp->rd_bl_on = 1;
4201 level = dp->rd_bl_level;
4202 level = min(RADEONFB_BACKLIGHT_MAX, level + 5);
4203 radeonfb_set_backlight(dp, level);
4204 }
4205
4206 static void
radeonfb_brightness_down(device_t dev)4207 radeonfb_brightness_down(device_t dev)
4208 {
4209 struct radeonfb_softc *sc = device_private(dev);
4210 struct radeonfb_display *dp = &sc->sc_displays[0];
4211 int level;
4212
4213 /* we assume the main display is the first one - need a better way */
4214 if (sc->sc_ndisplays < 1) return;
4215 /* make sure pushing the hotkeys always has an effect */
4216 dp->rd_bl_on = 1;
4217 level = dp->rd_bl_level;
4218 level = max(0, level - 5);
4219 radeonfb_set_backlight(dp, level);
4220 }
4221