1 /*
2 * Copyright (C) 2007 Ben Skeggs.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27 #include "drmP.h"
28 #include "nouveau_drv.h"
29 #include "nouveau_drm.h"
30
31
32 #define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \
33 NV40_RAMFC_##offset/4, (val))
34 #define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \
35 NV40_RAMFC_##offset/4)
36 #define NV40_RAMFC(c) (dev_priv->ramfc_offset + ((c)*NV40_RAMFC__SIZE))
37 #define NV40_RAMFC__SIZE 128
38
39 int
nv40_fifo_create_context(struct nouveau_channel * chan)40 nv40_fifo_create_context(struct nouveau_channel *chan)
41 {
42 struct drm_device *dev = chan->dev;
43 struct drm_nouveau_private *dev_priv = dev->dev_private;
44 int ret;
45
46 if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0,
47 NV40_RAMFC__SIZE,
48 NVOBJ_FLAG_ZERO_ALLOC |
49 NVOBJ_FLAG_ZERO_FREE,
50 NULL, &chan->ramfc)))
51 return ret;
52
53 /* Fill entries that are seen filled in dumps of nvidia driver just
54 * after channel's is put into DMA mode
55 */
56 RAMFC_WR(DMA_PUT , chan->pushbuf_base);
57 RAMFC_WR(DMA_GET , chan->pushbuf_base);
58 RAMFC_WR(DMA_INSTANCE , chan->pushbuf->instance >> 4);
59 RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
60 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
61 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
62 #ifdef __BIG_ENDIAN
63 NV_PFIFO_CACHE1_BIG_ENDIAN |
64 #endif
65 0x30000000 /* no idea.. */);
66 RAMFC_WR(DMA_SUBROUTINE, 0);
67 RAMFC_WR(GRCTX_INSTANCE, chan->ramin_grctx->instance >> 4);
68 RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF);
69
70 /* enable the fifo dma operation */
71 NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<chan->id));
72 return 0;
73 }
74
75 void
nv40_fifo_destroy_context(struct nouveau_channel * chan)76 nv40_fifo_destroy_context(struct nouveau_channel *chan)
77 {
78 struct drm_device *dev = chan->dev;
79 struct drm_nouveau_private *dev_priv = dev->dev_private;
80
81 NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
82
83 if (chan->ramfc)
84 nouveau_gpuobj_ref_del(dev, &chan->ramfc);
85 }
86
87 int
nv40_fifo_load_context(struct nouveau_channel * chan)88 nv40_fifo_load_context(struct nouveau_channel *chan)
89 {
90 struct drm_device *dev = chan->dev;
91 struct drm_nouveau_private *dev_priv = dev->dev_private;
92 uint32_t tmp, tmp2;
93
94 NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET));
95 NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT));
96 NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT , RAMFC_RD(REF_CNT));
97 NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE , RAMFC_RD(DMA_INSTANCE));
98 NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT , RAMFC_RD(DMA_DCOUNT));
99 NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE , RAMFC_RD(DMA_STATE));
100
101 /* No idea what 0x2058 is.. */
102 tmp = RAMFC_RD(DMA_FETCH);
103 tmp2 = NV_READ(0x2058) & 0xFFF;
104 tmp2 |= (tmp & 0x30000000);
105 NV_WRITE(0x2058, tmp2);
106 tmp &= ~0x30000000;
107 NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH , tmp);
108
109 NV_WRITE(NV04_PFIFO_CACHE1_ENGINE , RAMFC_RD(ENGINE));
110 NV_WRITE(NV04_PFIFO_CACHE1_PULL1 , RAMFC_RD(PULL1_ENGINE));
111 NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE , RAMFC_RD(ACQUIRE_VALUE));
112 NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, RAMFC_RD(ACQUIRE_TIMESTAMP));
113 NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT , RAMFC_RD(ACQUIRE_TIMEOUT));
114 NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE , RAMFC_RD(SEMAPHORE));
115 NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE , RAMFC_RD(DMA_SUBROUTINE));
116 NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE , RAMFC_RD(GRCTX_INSTANCE));
117 NV_WRITE(0x32e4, RAMFC_RD(UNK_40));
118 /* NVIDIA does this next line twice... */
119 NV_WRITE(0x32e8, RAMFC_RD(UNK_44));
120 NV_WRITE(0x2088, RAMFC_RD(UNK_4C));
121 NV_WRITE(0x3300, RAMFC_RD(UNK_50));
122
123 /* not sure what part is PUT, and which is GET.. never seen a non-zero
124 * value appear in a mmio-trace yet..
125 */
126 #if 0
127 tmp = NV_READ(UNK_84);
128 NV_WRITE(NV_PFIFO_CACHE1_GET, tmp ???);
129 NV_WRITE(NV_PFIFO_CACHE1_PUT, tmp ???);
130 #endif
131
132 /* Don't clobber the TIMEOUT_ENABLED flag when restoring from RAMFC */
133 tmp = NV_READ(NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF;
134 tmp |= RAMFC_RD(DMA_TIMESLICE) & 0x1FFFF;
135 NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, tmp);
136
137 /* Set channel active, and in DMA mode */
138 NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,
139 NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
140
141 /* Reset DMA_CTL_AT_INFO to INVALID */
142 tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
143 NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
144
145 return 0;
146 }
147
148 int
nv40_fifo_save_context(struct nouveau_channel * chan)149 nv40_fifo_save_context(struct nouveau_channel *chan)
150 {
151 struct drm_device *dev = chan->dev;
152 struct drm_nouveau_private *dev_priv = dev->dev_private;
153 uint32_t tmp;
154
155 RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
156 RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
157 RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
158 RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE));
159 RAMFC_WR(DMA_DCOUNT , NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT));
160 RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
161
162 tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH);
163 tmp |= NV_READ(0x2058) & 0x30000000;
164 RAMFC_WR(DMA_FETCH , tmp);
165
166 RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
167 RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1));
168 RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
169 tmp = NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
170 RAMFC_WR(ACQUIRE_TIMESTAMP, tmp);
171 RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
172 RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
173
174 /* NVIDIA read 0x3228 first, then write DMA_GET here.. maybe something
175 * more involved depending on the value of 0x3228?
176 */
177 RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
178
179 RAMFC_WR(GRCTX_INSTANCE , NV_READ(NV40_PFIFO_GRCTX_INSTANCE));
180
181 /* No idea what the below is for exactly, ripped from a mmio-trace */
182 RAMFC_WR(UNK_40 , NV_READ(NV40_PFIFO_UNK32E4));
183
184 /* NVIDIA do this next line twice.. bug? */
185 RAMFC_WR(UNK_44 , NV_READ(0x32e8));
186 RAMFC_WR(UNK_4C , NV_READ(0x2088));
187 RAMFC_WR(UNK_50 , NV_READ(0x3300));
188
189 #if 0 /* no real idea which is PUT/GET in UNK_48.. */
190 tmp = NV_READ(NV04_PFIFO_CACHE1_GET);
191 tmp |= (NV_READ(NV04_PFIFO_CACHE1_PUT) << 16);
192 RAMFC_WR(UNK_48 , tmp);
193 #endif
194
195 return 0;
196 }
197
198 int
nv40_fifo_init(struct drm_device * dev)199 nv40_fifo_init(struct drm_device *dev)
200 {
201 struct drm_nouveau_private *dev_priv = dev->dev_private;
202 int ret;
203
204 if ((ret = nouveau_fifo_init(dev)))
205 return ret;
206
207 NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff);
208 return 0;
209 }
210