1 /* savage_drv.h -- Private header for the savage driver */ 2 /* 3 * Copyright 2004 Felix Kuehling 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sub license, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef __SAVAGE_DRV_H__ 27 #define __SAVAGE_DRV_H__ 28 29 #define DRIVER_AUTHOR "Felix Kuehling" 30 31 #define DRIVER_NAME "savage" 32 #define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]" 33 #define DRIVER_DATE "20050313" 34 35 #define DRIVER_MAJOR 2 36 #define DRIVER_MINOR 4 37 #define DRIVER_PATCHLEVEL 1 38 /* Interface history: 39 * 40 * 1.x The DRM driver from the VIA/S3 code drop, basically a dummy 41 * 2.0 The first real DRM 42 * 2.1 Scissors registers managed by the DRM, 3D operations clipped by 43 * cliprects of the cmdbuf ioctl 44 * 2.2 Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX 45 * 2.3 Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits 46 * wide and thus very long lived (unlikely to ever wrap). The size 47 * in the struct was 32 bits before, but only 16 bits were used 48 * 2.4 Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is 49 * actually used 50 */ 51 52 typedef struct drm_savage_age { 53 uint16_t event; 54 unsigned int wrap; 55 } drm_savage_age_t; 56 57 typedef struct drm_savage_buf_priv { 58 struct drm_savage_buf_priv *next; 59 struct drm_savage_buf_priv *prev; 60 drm_savage_age_t age; 61 struct drm_buf *buf; 62 } drm_savage_buf_priv_t; 63 64 typedef struct drm_savage_dma_page { 65 drm_savage_age_t age; 66 unsigned int used, flushed; 67 } drm_savage_dma_page_t; 68 #define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */ 69 /* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command 70 * size of 16kbytes or 4k entries. Minimum requirement would be 71 * 10kbytes for 255 40-byte vertices in one drawing command. */ 72 #define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4) 73 74 /* interesting bits of hardware state that are saved in dev_priv */ 75 typedef union { 76 struct drm_savage_common_state { 77 uint32_t vbaddr; 78 } common; 79 struct { 80 unsigned char pad[sizeof(struct drm_savage_common_state)]; 81 uint32_t texctrl, texaddr; 82 uint32_t scstart, new_scstart; 83 uint32_t scend, new_scend; 84 } s3d; 85 struct { 86 unsigned char pad[sizeof(struct drm_savage_common_state)]; 87 uint32_t texdescr, texaddr0, texaddr1; 88 uint32_t drawctrl0, new_drawctrl0; 89 uint32_t drawctrl1, new_drawctrl1; 90 } s4; 91 } drm_savage_state_t; 92 93 /* these chip tags should match the ones in the 2D driver in savage_regs.h. */ 94 enum savage_family { 95 S3_UNKNOWN = 0, 96 S3_SAVAGE3D, 97 S3_SAVAGE_MX, 98 S3_SAVAGE4, 99 S3_PROSAVAGE, 100 S3_TWISTER, 101 S3_PROSAVAGEDDR, 102 S3_SUPERSAVAGE, 103 S3_SAVAGE2000, 104 S3_LAST 105 }; 106 107 extern const struct drm_ioctl_desc savage_ioctls[]; 108 extern int savage_max_ioctl; 109 110 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) 111 112 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \ 113 || (chip==S3_PROSAVAGE) \ 114 || (chip==S3_TWISTER) \ 115 || (chip==S3_PROSAVAGEDDR)) 116 117 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) 118 119 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) 120 121 #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \ 122 ||(chip==S3_PROSAVAGEDDR)) 123 124 /* flags */ 125 #define SAVAGE_IS_AGP 1 126 127 typedef struct drm_savage_private { 128 drm_savage_sarea_t *sarea_priv; 129 130 drm_savage_buf_priv_t head, tail; 131 132 /* who am I? */ 133 enum savage_family chipset; 134 135 unsigned int cob_size; 136 unsigned int bci_threshold_lo, bci_threshold_hi; 137 unsigned int dma_type; 138 139 /* frame buffer layout */ 140 unsigned int fb_bpp; 141 unsigned int front_offset, front_pitch; 142 unsigned int back_offset, back_pitch; 143 unsigned int depth_bpp; 144 unsigned int depth_offset, depth_pitch; 145 146 /* bitmap descriptors for swap and clear */ 147 unsigned int front_bd, back_bd, depth_bd; 148 149 /* local textures */ 150 unsigned int texture_offset; 151 unsigned int texture_size; 152 153 /* memory regions in physical memory */ 154 drm_local_map_t *sarea; 155 drm_local_map_t *mmio; 156 drm_local_map_t *fb; 157 drm_local_map_t *aperture; 158 drm_local_map_t *status; 159 drm_local_map_t *agp_textures; 160 drm_local_map_t *cmd_dma; 161 drm_local_map_t fake_dma; 162 163 int mtrr_handles[3]; 164 165 /* BCI and status-related stuff */ 166 volatile uint32_t *status_ptr, *bci_ptr; 167 uint32_t status_used_mask; 168 uint16_t event_counter; 169 unsigned int event_wrap; 170 171 /* Savage4 command DMA */ 172 drm_savage_dma_page_t *dma_pages; 173 unsigned int nr_dma_pages, first_dma_page, current_dma_page; 174 drm_savage_age_t last_dma_age; 175 176 /* saved hw state for global/local check on S3D */ 177 uint32_t hw_draw_ctrl, hw_zbuf_ctrl; 178 /* and for scissors (global, so don't emit if not changed) */ 179 uint32_t hw_scissors_start, hw_scissors_end; 180 181 drm_savage_state_t state; 182 183 /* after emitting a wait cmd Savage3D needs 63 nops before next DMA */ 184 unsigned int waiting; 185 186 /* config/hardware-dependent function pointers */ 187 int (*wait_fifo) (struct drm_savage_private * dev_priv, unsigned int n); 188 int (*wait_evnt) (struct drm_savage_private * dev_priv, uint16_t e); 189 /* Err, there is a macro wait_event in include/linux/wait.h. 190 * Avoid unwanted macro expansion. */ 191 void (*emit_clip_rect) (struct drm_savage_private * dev_priv, 192 const struct drm_clip_rect * pbox); 193 void (*dma_flush) (struct drm_savage_private * dev_priv); 194 } drm_savage_private_t; 195 196 /* ioctls */ 197 extern int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv); 198 extern int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 199 200 /* BCI functions */ 201 extern uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv, 202 unsigned int flags); 203 extern void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf); 204 extern void savage_dma_reset(drm_savage_private_t * dev_priv); 205 extern void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page); 206 extern uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, 207 unsigned int n); 208 extern int savage_driver_load(struct drm_device *dev, unsigned long chipset); 209 extern int savage_driver_firstopen(struct drm_device *dev); 210 extern void savage_driver_lastclose(struct drm_device *dev); 211 extern int savage_driver_unload(struct drm_device *dev); 212 extern void savage_reclaim_buffers(struct drm_device *dev, 213 struct drm_file *file_priv); 214 215 /* state functions */ 216 extern void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv, 217 const struct drm_clip_rect * pbox); 218 extern void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv, 219 const struct drm_clip_rect * pbox); 220 221 #define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ 222 #define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ 223 #define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */ 224 #define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */ 225 #define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */ 226 227 #define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region 228 * inside the MMIO region */ 229 #define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip 230 * BCI FIFO */ 231 232 /* 233 * MMIO registers 234 */ 235 #define SAVAGE_STATUS_WORD0 0x48C00 236 #define SAVAGE_STATUS_WORD1 0x48C04 237 #define SAVAGE_ALT_STATUS_WORD0 0x48C60 238 239 #define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff 240 #define SAVAGE_FIFO_USED_MASK_S4 0x001fffff 241 242 /* Copied from savage_bci.h in the 2D driver with some renaming. */ 243 244 /* Bitmap descriptors */ 245 #define SAVAGE_BD_STRIDE_SHIFT 0 246 #define SAVAGE_BD_BPP_SHIFT 16 247 #define SAVAGE_BD_TILE_SHIFT 24 248 #define SAVAGE_BD_BW_DISABLE (1<<28) 249 /* common: */ 250 #define SAVAGE_BD_TILE_LINEAR 0 251 /* savage4, MX, IX, 3D */ 252 #define SAVAGE_BD_TILE_16BPP 2 253 #define SAVAGE_BD_TILE_32BPP 3 254 /* twister, prosavage, DDR, supersavage, 2000 */ 255 #define SAVAGE_BD_TILE_DEST 1 256 #define SAVAGE_BD_TILE_TEXTURE 2 257 /* GBD - BCI enable */ 258 /* savage4, MX, IX, 3D */ 259 #define SAVAGE_GBD_BCI_ENABLE 8 260 /* twister, prosavage, DDR, supersavage, 2000 */ 261 #define SAVAGE_GBD_BCI_ENABLE_TWISTER 0 262 263 #define SAVAGE_GBD_BIG_ENDIAN 4 264 #define SAVAGE_GBD_LITTLE_ENDIAN 0 265 #define SAVAGE_GBD_64 1 266 267 /* Global Bitmap Descriptor */ 268 #define SAVAGE_BCI_GLB_BD_LOW 0x8168 269 #define SAVAGE_BCI_GLB_BD_HIGH 0x816C 270 271 /* 272 * BCI registers 273 */ 274 /* Savage4/Twister/ProSavage 3D registers */ 275 #define SAVAGE_DRAWLOCALCTRL_S4 0x1e 276 #define SAVAGE_TEXPALADDR_S4 0x1f 277 #define SAVAGE_TEXCTRL0_S4 0x20 278 #define SAVAGE_TEXCTRL1_S4 0x21 279 #define SAVAGE_TEXADDR0_S4 0x22 280 #define SAVAGE_TEXADDR1_S4 0x23 281 #define SAVAGE_TEXBLEND0_S4 0x24 282 #define SAVAGE_TEXBLEND1_S4 0x25 283 #define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */ 284 #define SAVAGE_TEXDESCR_S4 0x27 285 #define SAVAGE_FOGTABLE_S4 0x28 286 #define SAVAGE_FOGCTRL_S4 0x30 287 #define SAVAGE_STENCILCTRL_S4 0x31 288 #define SAVAGE_ZBUFCTRL_S4 0x32 289 #define SAVAGE_ZBUFOFF_S4 0x33 290 #define SAVAGE_DESTCTRL_S4 0x34 291 #define SAVAGE_DRAWCTRL0_S4 0x35 292 #define SAVAGE_DRAWCTRL1_S4 0x36 293 #define SAVAGE_ZWATERMARK_S4 0x37 294 #define SAVAGE_DESTTEXRWWATERMARK_S4 0x38 295 #define SAVAGE_TEXBLENDCOLOR_S4 0x39 296 /* Savage3D/MX/IX 3D registers */ 297 #define SAVAGE_TEXPALADDR_S3D 0x18 298 #define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */ 299 #define SAVAGE_TEXADDR_S3D 0x1A 300 #define SAVAGE_TEXDESCR_S3D 0x1B 301 #define SAVAGE_TEXCTRL_S3D 0x1C 302 #define SAVAGE_FOGTABLE_S3D 0x20 303 #define SAVAGE_FOGCTRL_S3D 0x30 304 #define SAVAGE_DRAWCTRL_S3D 0x31 305 #define SAVAGE_ZBUFCTRL_S3D 0x32 306 #define SAVAGE_ZBUFOFF_S3D 0x33 307 #define SAVAGE_DESTCTRL_S3D 0x34 308 #define SAVAGE_SCSTART_S3D 0x35 309 #define SAVAGE_SCEND_S3D 0x36 310 #define SAVAGE_ZWATERMARK_S3D 0x37 311 #define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38 312 /* common stuff */ 313 #define SAVAGE_VERTBUFADDR 0x3e 314 #define SAVAGE_BITPLANEWTMASK 0xd7 315 #define SAVAGE_DMABUFADDR 0x51 316 317 /* texture enable bits (needed for tex addr checking) */ 318 #define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */ 319 #define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */ 320 #define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */ 321 322 /* Global fields in Savage4/Twister/ProSavage 3D registers: 323 * 324 * All texture registers and DrawLocalCtrl are local. All other 325 * registers are global. */ 326 327 /* Global fields in Savage3D/MX/IX 3D registers: 328 * 329 * All texture registers are local. DrawCtrl and ZBufCtrl are 330 * partially local. All other registers are global. 331 * 332 * DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal 333 * ZBufCtrl global fields: zCmpFunc, zBufEn 334 */ 335 #define SAVAGE_DRAWCTRL_S3D_GLOBAL 0x03f3c00c 336 #define SAVAGE_ZBUFCTRL_S3D_GLOBAL 0x00000027 337 338 /* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d) 339 */ 340 #define SAVAGE_SCISSOR_MASK_S4 0x00fff7ff 341 #define SAVAGE_SCISSOR_MASK_S3D 0x07ff07ff 342 343 /* 344 * BCI commands 345 */ 346 #define BCI_CMD_NOP 0x40000000 347 #define BCI_CMD_RECT 0x48000000 348 #define BCI_CMD_RECT_XP 0x01000000 349 #define BCI_CMD_RECT_YP 0x02000000 350 #define BCI_CMD_SCANLINE 0x50000000 351 #define BCI_CMD_LINE 0x5C000000 352 #define BCI_CMD_LINE_LAST_PIXEL 0x58000000 353 #define BCI_CMD_BYTE_TEXT 0x63000000 354 #define BCI_CMD_NT_BYTE_TEXT 0x67000000 355 #define BCI_CMD_BIT_TEXT 0x6C000000 356 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) 357 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16)) 358 #define BCI_CMD_SEND_COLOR 0x00008000 359 360 #define BCI_CMD_CLIP_NONE 0x00000000 361 #define BCI_CMD_CLIP_CURRENT 0x00002000 362 #define BCI_CMD_CLIP_LR 0x00004000 363 #define BCI_CMD_CLIP_NEW 0x00006000 364 365 #define BCI_CMD_DEST_GBD 0x00000000 366 #define BCI_CMD_DEST_PBD 0x00000800 367 #define BCI_CMD_DEST_PBD_NEW 0x00000C00 368 #define BCI_CMD_DEST_SBD 0x00001000 369 #define BCI_CMD_DEST_SBD_NEW 0x00001400 370 371 #define BCI_CMD_SRC_TRANSPARENT 0x00000200 372 #define BCI_CMD_SRC_SOLID 0x00000000 373 #define BCI_CMD_SRC_GBD 0x00000020 374 #define BCI_CMD_SRC_COLOR 0x00000040 375 #define BCI_CMD_SRC_MONO 0x00000060 376 #define BCI_CMD_SRC_PBD_COLOR 0x00000080 377 #define BCI_CMD_SRC_PBD_MONO 0x000000A0 378 #define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0 379 #define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0 380 #define BCI_CMD_SRC_SBD_COLOR 0x00000100 381 #define BCI_CMD_SRC_SBD_MONO 0x00000120 382 #define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140 383 #define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160 384 385 #define BCI_CMD_PAT_TRANSPARENT 0x00000010 386 #define BCI_CMD_PAT_NONE 0x00000000 387 #define BCI_CMD_PAT_COLOR 0x00000002 388 #define BCI_CMD_PAT_MONO 0x00000003 389 #define BCI_CMD_PAT_PBD_COLOR 0x00000004 390 #define BCI_CMD_PAT_PBD_MONO 0x00000005 391 #define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006 392 #define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007 393 #define BCI_CMD_PAT_SBD_COLOR 0x00000008 394 #define BCI_CMD_PAT_SBD_MONO 0x00000009 395 #define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A 396 #define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B 397 398 #define BCI_BD_BW_DISABLE 0x10000000 399 #define BCI_BD_TILE_MASK 0x03000000 400 #define BCI_BD_TILE_NONE 0x00000000 401 #define BCI_BD_TILE_16 0x02000000 402 #define BCI_BD_TILE_32 0x03000000 403 #define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF) 404 #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16)) 405 #define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF) 406 #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF)) 407 408 #define BCI_CMD_SET_REGISTER 0x96000000 409 410 #define BCI_CMD_WAIT 0xC0000000 411 #define BCI_CMD_WAIT_3D 0x00010000 412 #define BCI_CMD_WAIT_2D 0x00020000 413 414 #define BCI_CMD_UPDATE_EVENT_TAG 0x98000000 415 416 #define BCI_CMD_DRAW_PRIM 0x80000000 417 #define BCI_CMD_DRAW_INDEXED_PRIM 0x88000000 418 #define BCI_CMD_DRAW_CONT 0x01000000 419 #define BCI_CMD_DRAW_TRILIST 0x00000000 420 #define BCI_CMD_DRAW_TRISTRIP 0x02000000 421 #define BCI_CMD_DRAW_TRIFAN 0x04000000 422 #define BCI_CMD_DRAW_SKIPFLAGS 0x000000ff 423 #define BCI_CMD_DRAW_NO_Z 0x00000001 424 #define BCI_CMD_DRAW_NO_W 0x00000002 425 #define BCI_CMD_DRAW_NO_CD 0x00000004 426 #define BCI_CMD_DRAW_NO_CS 0x00000008 427 #define BCI_CMD_DRAW_NO_U0 0x00000010 428 #define BCI_CMD_DRAW_NO_V0 0x00000020 429 #define BCI_CMD_DRAW_NO_UV0 0x00000030 430 #define BCI_CMD_DRAW_NO_U1 0x00000040 431 #define BCI_CMD_DRAW_NO_V1 0x00000080 432 #define BCI_CMD_DRAW_NO_UV1 0x000000c0 433 434 #define BCI_CMD_DMA 0xa8000000 435 436 #define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF) 437 #define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF) 438 #define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF) 439 #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF) 440 #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF) 441 #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF) 442 443 #define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF)) 444 #define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF)) 445 #define BCI_LINE_MISC(maj, ym, xp, yp, err) \ 446 (((maj) & 0x1FFF) | \ 447 ((ym) ? 1<<13 : 0) | \ 448 ((xp) ? 1<<14 : 0) | \ 449 ((yp) ? 1<<15 : 0) | \ 450 ((err) << 16)) 451 452 /* 453 * common commands 454 */ 455 #define BCI_SET_REGISTERS( first, n ) \ 456 BCI_WRITE(BCI_CMD_SET_REGISTER | \ 457 ((uint32_t)(n) & 0xff) << 16 | \ 458 ((uint32_t)(first) & 0xffff)) 459 #define DMA_SET_REGISTERS( first, n ) \ 460 DMA_WRITE(BCI_CMD_SET_REGISTER | \ 461 ((uint32_t)(n) & 0xff) << 16 | \ 462 ((uint32_t)(first) & 0xffff)) 463 464 #define BCI_DRAW_PRIMITIVE(n, type, skip) \ 465 BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ 466 ((n) << 16)) 467 #define DMA_DRAW_PRIMITIVE(n, type, skip) \ 468 DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ 469 ((n) << 16)) 470 471 #define BCI_DRAW_INDICES_S3D(n, type, i0) \ 472 BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ 473 ((n) << 16) | (i0)) 474 475 #define BCI_DRAW_INDICES_S4(n, type, skip) \ 476 BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ 477 (skip) | ((n) << 16)) 478 479 #define BCI_DMA(n) \ 480 BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1)) 481 482 /* 483 * access to MMIO 484 */ 485 #define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 486 #define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) ) 487 488 /* 489 * access to the burst command interface (BCI) 490 */ 491 #define SAVAGE_BCI_DEBUG 1 492 493 #define BCI_LOCALS volatile uint32_t *bci_ptr; 494 495 #define BEGIN_BCI( n ) do { \ 496 dev_priv->wait_fifo(dev_priv, (n)); \ 497 bci_ptr = dev_priv->bci_ptr; \ 498 } while(0) 499 500 #define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val) 501 502 /* 503 * command DMA support 504 */ 505 #define SAVAGE_DMA_DEBUG 1 506 507 #define DMA_LOCALS uint32_t *dma_ptr; 508 509 #define BEGIN_DMA( n ) do { \ 510 unsigned int cur = dev_priv->current_dma_page; \ 511 unsigned int rest = SAVAGE_DMA_PAGE_SIZE - \ 512 dev_priv->dma_pages[cur].used; \ 513 if ((n) > rest) { \ 514 dma_ptr = savage_dma_alloc(dev_priv, (n)); \ 515 } else { /* fast path for small allocations */ \ 516 dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \ 517 cur * SAVAGE_DMA_PAGE_SIZE + \ 518 dev_priv->dma_pages[cur].used; \ 519 if (dev_priv->dma_pages[cur].used == 0) \ 520 savage_dma_wait(dev_priv, cur); \ 521 dev_priv->dma_pages[cur].used += (n); \ 522 } \ 523 } while(0) 524 525 #define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val) 526 527 #define DMA_COPY(src, n) do { \ 528 memcpy(dma_ptr, (src), (n)*4); \ 529 dma_ptr += n; \ 530 } while(0) 531 532 #if SAVAGE_DMA_DEBUG 533 #define DMA_COMMIT() do { \ 534 unsigned int cur = dev_priv->current_dma_page; \ 535 uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \ 536 cur * SAVAGE_DMA_PAGE_SIZE + \ 537 dev_priv->dma_pages[cur].used; \ 538 if (dma_ptr != expected) { \ 539 DRM_ERROR("DMA allocation and use don't match: " \ 540 "%p != %p\n", expected, dma_ptr); \ 541 savage_dma_reset(dev_priv); \ 542 } \ 543 } while(0) 544 #else 545 #define DMA_COMMIT() do {/* nothing */} while(0) 546 #endif 547 548 #define DMA_FLUSH() dev_priv->dma_flush(dev_priv) 549 550 /* Buffer aging via event tag 551 */ 552 553 #define UPDATE_EVENT_COUNTER( ) do { \ 554 if (dev_priv->status_ptr) { \ 555 uint16_t count; \ 556 /* coordinate with Xserver */ \ 557 count = dev_priv->status_ptr[1023]; \ 558 if (count < dev_priv->event_counter) \ 559 dev_priv->event_wrap++; \ 560 dev_priv->event_counter = count; \ 561 } \ 562 } while(0) 563 564 #define SET_AGE( age, e, w ) do { \ 565 (age)->event = e; \ 566 (age)->wrap = w; \ 567 } while(0) 568 569 #define TEST_AGE( age, e, w ) \ 570 ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) ) 571 572 #endif /* __SAVAGE_DRV_H__ */ 573