1 /*
2  * Copyright � 2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the
13  * next paragraph) shall be included in all copies or substantial portions
14  * of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *     Wei Lin<wei.w.lin@intel.com>
26  *     Yuting Yang<yuting.yang@intel.com>
27  */
28 #ifndef __GENHW_CM_G8__
29 #define __GENHW_CM_G8__
30 
31 #include "gen_hw.h"
32 #include "os_interface.h"
33 #include "hw_interface.h"
34 
35 #define CM_PREMP_DBG_ADDRESS_OFFSET             (0x2248)
36 #define CM_PREMP_DEFAULT_VALUE                  (0x00000000)
37 #define CM_PREMP_ON_MI_ARB_CHECK_ONLY           (0x00000100)
38 
39 #define GENHW_CM_THREADS_PER_EU_BDW_GT1             CM_GEN8_HW_THREADS_PER_EU
40 #define GENHW_CM_THREADS_PER_EU_BDW_GT2             CM_GEN8_HW_THREADS_PER_EU
41 #define GENHW_CM_THREADS_PER_EU_BDW_GT3             CM_GEN8_HW_THREADS_PER_EU
42 #define GENHW_CM_THREADS_PER_EU_CHV                 CM_GEN8LP_HW_THREADS_PER_EU
43 
44 #define GENHW_CM_EU_PER_SUBSLICE_BDW_GT1               CM_GEN8_GT1_EUS_PER_SUBSLICE
45 #define GENHW_CM_EU_PER_SUBSLICE_BDW_GT2               CM_GEN8_GT2_EUS_PER_SUBSLICE
46 #define GENHW_CM_EU_PER_SUBSLICE_BDW_GT3               CM_GEN8_GT3_EUS_PER_SUBSLICE
47 #define GENHW_CM_EU_PER_SUBSLICE_CHV                   CM_GEN8LP_EUS_PER_SUBSLICE
48 
49 #define CM_CONFIG_CNTLREG_VALUE_G8_BDW_SLM	0x00808021
50 #define CM_CONFIG_CNTLREG_VALUE_G8_BDW_NONSLM	0x80000040
51 
52 #define CM_CONFIG_CNTLREG_VALUE_G8_CHV_SLM	0x00410011
53 #define CM_CONFIG_CNTLREG_VALUE_G8_CHV_NONSLM	0x00418020
54 
55 GENOS_STATUS HalCm_SubmitCommands_g8(PCM_HAL_STATE pState,
56 				     PGENHW_BATCH_BUFFER pBatchBuffer,
57 				     INT iTaskId,
58 				     PCM_HAL_KERNEL_PARAM * pKernels,
59 				     PVOID * PPCmdBuffer);
60 
61 GENOS_STATUS HalCm_HwSetSurfaceMemoryObjectControl_g8(PCM_HAL_STATE pState,
62 						      WORD wMemObjCtl,
63 						      PGENHW_SURFACE_STATE_PARAMS
64 						      pParams);
65 
66 VOID HalCm_HwSendL3CacheConfig_g8(PCM_HAL_STATE pState,
67 				  PGENOS_COMMAND_BUFFER pCmdBuffer,
68 				  PGENHW_L3_CACHE_CONFIG  pL3CacheConfig);
69 
70 INT HalCm_GetCurbeBlockAlignSize_g8();
71 
72 GENOS_STATUS HalCm_AddMediaStateFlushBb_g8(PGENHW_HW_INTERFACE pHwInterface,
73 					   PGENHW_BATCH_BUFFER pBatchBuffer,
74 					   PMEDIA_STATE_FLUSH_CMD_G75
75 					   pMediaStateFlush);
76 
77 GENOS_STATUS HalCm_SkipMediaStateFlushBb_g8(PGENHW_HW_INTERFACE pHwInterface,
78 					    PGENHW_BATCH_BUFFER pBatchBuffer);
79 
80 GENOS_STATUS HalCm_GetUserDefinedThreadCountPerThreadGroup_g8(PCM_HAL_STATE
81 							      pState,
82 							      UINT *
83 							      pThreadsPerThreadGroup);
84 
85 #endif
86