1 /* 2 * Copyright (c) 2014-2020, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox.h 24 //! \brief This modules implements HW interface layer to be used on all platforms on all operating systems/DDIs, across MHW components. 25 //! 26 #ifndef _MHW_VDBOX_H_ 27 #define _MHW_VDBOX_H_ 28 29 #include "codec_def_encode_avc.h" 30 #include "codec_def_encode_jpeg.h" 31 #include "codec_def_encode_mpeg2.h" 32 #include "codec_def_encode_vp9.h" 33 #include "codec_def_decode_vp9.h" 34 #include "codec_def_decode_vc1.h" 35 #include "codec_def_decode_avc.h" 36 #include "codec_def_decode_hevc.h" 37 #include "mos_os.h" 38 #include "mhw_utilities.h" 39 #include "mhw_cp_interface.h" 40 41 #define MHW_VDBOX_VC1_BITPLANE_BUFFER_PITCH_SMALL 64 42 #define MHW_VDBOX_VC1_BITPLANE_BUFFER_PITCH_LARGE 128 43 44 #define MHW_VDBOX_MFX_RAW_UV_PLANE_ALIGNMENT_GEN9 4 // starting Gen9 the alignment is relaxed to 4x instead of 16x 45 #define MHW_VDBOX_MFX_UV_PLANE_ALIGNMENT_LEGACY 16 46 #define MHW_VDBOX_MFX_RECON_UV_PLANE_ALIGNMENT 16 47 #define MHW_VDBOX_HCP_RAW_UV_PLANE_ALIGNMENT 4 // starting Gen9 the alignment is relaxed to 4x instead of 16x 48 #define MHW_VDBOX_HCP_RECON_UV_PLANE_ALIGNMENT 8 49 50 #define MHW_VDBOX_PAK_BITSTREAM_OVERFLOW_SIZE 400 51 #define MHW_VDBOX_PAK_SLICE_HEADER_OVERFLOW_SIZE 50 52 #define MHW_VDBOX_VDENC_DYNAMIC_SLICE_WA_COUNT 1500 53 54 // Rowstore Cache values 55 #define MHW_VDBOX_PICWIDTH_1K 1024 56 #define MHW_VDBOX_PICWIDTH_2K 2048 57 #define MHW_VDBOX_PICWIDTH_3K 3072 58 #define MHW_VDBOX_PICWIDTH_4K 4096 59 #define MHW_VDBOX_PICWIDTH_8K 8192 60 #define INTRAROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_LESS_THAN_2K 256 61 #define INTRAROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_3K 384 62 #define INTRAROWSTORE_MBAFF_BASEADDRESS_PICWIDTH_LESS_THAN_2K 512 63 #define INTRAROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_BETWEEN_3K_AND_4K 384 64 #define DEBLOCKINGROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_LESS_THAN_2K 384 65 #define BSDMPCROWSTORE_BASEADDRESS 0 66 #define MPRROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_LESS_THAN_2K 128 67 #define MPRROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_3K 192 68 #define MPRROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_GREATER_THAN_3K 256 69 #define MPRROWSTORE_MBAFF_BASEADDRESS_PICWIDTH_LESS_THAN_2K 256 70 #define VDENCROWSTORE_FRAME_BASEADDRESS_PICWIDTH_LESS_THAN_2K 128 71 #define VDENCROWSTORE_FRAME_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_3K 192 72 #define VDENCROWSTORE_FRAME_BASEADDRESS_PICWIDTH_BETWEEN_3K_AND_4K 256 73 #define HEVCDATROWSTORE_BASEADDRESS 0 74 #define HEVCDFROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_2K 64 75 #define HEVCDFROWSTORE_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_4K 128 76 #define HEVCSAOROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_2K 320 77 #define VP9HVDROWSTORE_BASEADDRESS 0 78 #define VP9DFROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_2K 32 79 #define MHW_CACHELINE_SIZE 64 80 #define BYTES_PER_DWORD 4 81 #define NUM_PAK_DWS_PER_LCU 5 82 #define NUM_DWS_PER_CU 8 83 84 #define VP9DFROWSTORE_BASEADDRESS_8BIT_PICWIDTH_LESS_THAN_OR_EQU_TO_4K 384 85 #define VP9DATROWSTORE_BASEADDRESS_8BIT_PICWIDTH_LESS_THAN_OR_EQU_TO_4K 64 86 87 typedef enum _MHW_VDBOX_ADDRESS_SHIFT 88 { 89 MHW_VDBOX_SURFACE_STATE_SHIFT = 0, 90 MHW_VDBOX_MFX_GENERAL_STATE_SHIFT = 6, 91 MHW_VDBOX_HCP_GENERAL_STATE_SHIFT = 6, 92 MHW_VDBOX_HUC_GENERAL_STATE_SHIFT = 6, 93 MHW_VDBOX_MFX_UPPER_BOUND_STATE_SHIFT = 12, 94 MHW_VDBOX_STATE_BASE_ADDRESS_SHIFT = 12, 95 MHW_VDBOX_HCP_UPPER_BOUND_STATE_SHIFT = 12, 96 MHW_VDBOX_HUC_UPPER_BOUND_STATE_SHIFT = 12, 97 MHW_VDBOX_HUC_IMEM_STATE_SHIFT = 15, 98 MHW_VDBOX_HCP_DECODED_BUFFER_SHIFT = 12 99 } MHW_VDBOX_ADDRESS_SHIFT; 100 101 typedef enum _MHW_VDBOX_NODE_IND 102 { 103 MHW_VDBOX_NODE_1 = 0x0, 104 MHW_VDBOX_NODE_2 = 0x1, 105 MHW_VDBOX_NODE_MAX 106 } MHW_VDBOX_NODE_IND; 107 108 typedef struct _MHW_VDBOX_AVC_QM_PARAMS 109 { 110 uint8_t List4x4[6][16]; 111 uint8_t List8x8[2][64]; 112 } MHW_VDBOX_AVC_QM_PARAMS, *PMHW_VDBOX_AVC_QM_PARAMS; 113 114 typedef struct _MHW_VDBOX_HEVC_QM_PARAMS 115 { 116 uint8_t List4x4[6][16]; 117 uint8_t List8x8[6][64]; 118 uint8_t List16x16[6][64]; 119 uint8_t List32x32[2][64]; 120 uint8_t ListDC16x16[6]; 121 uint8_t ListDC32x32[2]; 122 } MHW_VDBOX_HEVC_QM_PARAMS, *PMHW_VDBOX_HEVC_QM_PARAMS; 123 124 typedef enum _HCP_SURFACE_FORMAT 125 { 126 HCP_SURFACE_FORMAT_YUY2 = 0x0, 127 HCP_SURFACE_FORMAT_RGBX8888 = 0x1, 128 HCP_SURFACE_FORMAT_AYUV4444 = 0x2, 129 HCP_SURFACE_FORMAT_P010_VARIANT = 0x3, 130 HCP_SURFACE_FORMAT_PLANAR_420_8 = 0x4, 131 HCP_SURFACE_FORMAT_UYVY = 0x5, 132 HCP_SURFACE_FORMAT_YVYU = 0x6, 133 HCP_SURFACE_FORMAT_VYUY = 0x7, 134 HCP_SURFACE_FORMAT_Y210 = 0x8, 135 HCP_SURFACE_FORMAT_Y216 = 0x8, 136 HCP_SURFACE_FORMAT_RGBA1010102 = 0x9, 137 HCP_SURFACE_FORMAT_Y410 = 0xA, 138 HCP_SURFACE_FORMAT_NV21 = 0xB, 139 HCP_SURFACE_FORMAT_Y416 = 0xC, 140 HCP_SURFACE_FORMAT_P010 = 0xD, 141 HCP_SURFACE_FORMAT_P016 = 0xE, 142 HCP_SURFACE_FORMAT_Y8 = 0xF, 143 HCP_SURFACE_FORMAT_Y16 = 0x10, 144 HCP_SURFACE_FORMAT_Y216_VARIANT = 0x11, 145 HCP_SURFACE_FORMAT_Y416_VARIANT = 0x12, 146 HCP_SURFACE_FORMAT_YUYV_VARIANT = 0x13, 147 HCP_SURFACE_FORMAT_AYUV4444_VARIANT = 0x14, 148 HCP_SURFACE_FORMAT_RESERVED = 0x15, 149 } HCP_SURFACE_FORMAT; 150 151 typedef enum _PIPE_WORK_MODE 152 { 153 MHW_VDBOX_HCP_PIPE_WORK_MODE_LEGACY = 0, 154 MHW_VDBOX_HCP_PIPE_WORK_MODE_CABAC_FE = 1, 155 MHW_VDBOX_HCP_PIPE_WORK_MODE_CODEC_BE = 2, 156 MHW_VDBOX_HCP_PIPE_WORK_MODE_CABAC_REAL_TILE = 3, 157 }MHW_VDBOX_HCP_PIPE_WORK_MODE; 158 159 typedef enum _MULTI_ENGINE_MODE 160 { 161 MHW_VDBOX_HCP_MULTI_ENGINE_MODE_FE_LEGACY = 0, 162 MHW_VDBOX_HCP_MULTI_ENGINE_MODE_LEFT = 1, 163 MHW_VDBOX_HCP_MULTI_ENGINE_MODE_RIGHT = 2, 164 MHW_VDBOX_HCP_MULTI_ENGINE_MODE_MIDDLE = 3, 165 }MHW_VDBOX_HCP_MULTI_ENGINE_MODE; 166 167 typedef enum _VDENC_PIPE_NUM_OF_PIPE 168 { 169 VDENC_PIPE_SINGLE_PIPE = 0, 170 VDENC_PIPE_TWO_PIPE = 1, 171 VDENC_PIPE_INVALID = 2, 172 VDENC_PIPE_FOUR_PIPE = 3, 173 }VDENC_PIPE_NUM_OF_PIPE; 174 175 typedef enum 176 { 177 HCP_CHROMA_FORMAT_MONOCHROME = 0, 178 HCP_CHROMA_FORMAT_YUV420 = 1, 179 HCP_CHROMA_FORMAT_YUV422 = 2, 180 HCP_CHROMA_FORMAT_YUV444 = 3 181 } HCP_CHROMA_FORMAT_IDC; 182 183 // Media memory compression trigger 184 typedef enum _MHW_MEDIA_MEMORY_COMPRESSION_EN 185 { 186 MHW_MEDIA_MEMCOMP_DISABLED = 0x0, 187 MHW_MEDIA_MEMCOMP_ENABLED = 0x1 188 } MHW_MEDIA_MEMORY_COMPRESSION_EN; 189 190 // Media memory compression mode 191 typedef enum _MHW_MEDIA_MEMORY_COMPRESSION_MODE 192 { 193 MHW_MEDIA_MEMCOMP_MODE_HORIZONTAL = 0x0, 194 MHW_MEDIA_MEMCOMP_MODE_VERTICAL = 0x1, 195 } MHW_MEDIA_MEMORY_COMPRESSION_MODE; 196 197 //! 198 //! \enum ROWSTORE_SCRATCH_BUFFER_CACHE 199 //! \brief Rowstore scratch buffer cache select 200 //! 201 enum ROWSTORE_SCRATCH_BUFFER_CACHE 202 { 203 BUFFER_TO_LLC = 0x0, 204 BUFFER_TO_INTERNALMEDIASTORAGE = 0x1 205 }; 206 207 //! 208 //! \enum SLICE_THRESHOLD_TABLE_MODE 209 //! \brief Slice thershold table mode, dynamic slice tuning params 210 //! 211 enum SLICE_THRESHOLD_TABLE_MODE 212 { 213 NO_SLICE_THRESHOLD_TABLE = 0, 214 USE_SLICE_THRESHOLD_TABLE_100_PERCENT = 1, 215 USE_SLICE_THRESHOLD_TABLE_90_PERCENT = 2 216 }; 217 218 struct MHW_VDBOX_PIPE_MODE_SELECT_PARAMS 219 { 220 uint32_t Mode = 0; 221 bool bStreamOutEnabled = false; 222 bool bStreamOutEnabledExtEnabled = false; 223 bool bShortFormatInUse = false; 224 bool bVC1OddFrameHeight = false; 225 bool pakFrmLvlStrmoutEnable = false; 226 bool pakPiplnStrmoutEnabled = false; 227 228 bool bDeblockerStreamOutEnable = false; 229 bool bPostDeblockOutEnable = false; 230 bool bPreDeblockOutEnable = false; 231 bool bDynamicSliceEnable = false; 232 bool bSaoFirstPass = false; 233 bool bRdoqEnable = false; 234 bool bDynamicScalingEnabled = false; 235 236 // VDEnc specific 237 bool bVdencEnabled = false; 238 bool bVdencStreamInEnable = false; 239 uint8_t ucVdencBitDepthMinus8 = 0; 240 bool bPakThresholdCheckEnable = false; 241 bool bVdencPakObjCmdStreamOutEnable = false; 242 bool bBatchBufferInUse = false; 243 bool bTlbPrefetchEnable = 0; 244 PMHW_BATCH_BUFFER pBatchBuffer = nullptr; 245 uint32_t ChromaType = 0; 246 MOS_FORMAT Format = {}; 247 248 // HuC specific 249 uint32_t dwMediaSoftResetCounterValue = 0; 250 bool bAdvancedRateControlEnable = false; 251 bool bStreamObjectUsed = false; 252 // No need to set protection settings 253 bool disableProtectionSetting = false; ~MHW_VDBOX_PIPE_MODE_SELECT_PARAMSMHW_VDBOX_PIPE_MODE_SELECT_PARAMS254 virtual ~MHW_VDBOX_PIPE_MODE_SELECT_PARAMS() {} 255 }; 256 using PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS = MHW_VDBOX_PIPE_MODE_SELECT_PARAMS * ; 257 258 typedef struct _MHW_VDBOX_SURFACE_PARAMS 259 { 260 uint32_t Mode; 261 PMOS_SURFACE psSurface; // 2D surface parameters 262 uint8_t ucVDirection; 263 uint8_t ChromaType; 264 uint8_t ucSurfaceStateId; 265 uint8_t ucBitDepthLumaMinus8; 266 uint8_t ucBitDepthChromaMinus8; 267 uint32_t dwUVPlaneAlignment; 268 bool bDisplayFormatSwizzle; 269 bool bSrc8Pak10Mode; 270 bool bColorSpaceSelection; 271 bool bVdencDynamicScaling; 272 uint32_t dwActualWidth; 273 uint32_t dwActualHeight; 274 uint32_t dwReconSurfHeight; 275 MOS_MEMCOMP_STATE mmcState; 276 uint8_t mmcSkipMask; 277 uint32_t dwCompressionFormat; 278 } MHW_VDBOX_SURFACE_PARAMS, *PMHW_VDBOX_SURFACE_PARAMS; 279 280 struct MHW_VDBOX_PIPE_BUF_ADDR_PARAMS 281 { 282 uint32_t Mode = 0; 283 PMOS_SURFACE psPreDeblockSurface = nullptr; // Pointer to MOS_SURFACE of render surface 284 MOS_MEMCOMP_STATE PreDeblockSurfMmcState = MOS_MEMCOMP_DISABLED; 285 PMOS_SURFACE psPostDeblockSurface = nullptr; // Pointer to MOS_SURFACE of render surface 286 MOS_MEMCOMP_STATE PostDeblockSurfMmcState = MOS_MEMCOMP_DISABLED; 287 PMOS_SURFACE psRawSurface = nullptr; // Pointer to MOS_SURFACE of raw surface 288 MOS_MEMCOMP_STATE RawSurfMmcState = MOS_MEMCOMP_DISABLED; 289 PMOS_SURFACE ps4xDsSurface = nullptr; 290 MOS_MEMCOMP_STATE Ps4xDsSurfMmcState = MOS_MEMCOMP_DISABLED; 291 PMOS_SURFACE ps8xDsSurface = nullptr; 292 MOS_MEMCOMP_STATE Ps8xDsSurfMmcState = MOS_MEMCOMP_DISABLED; 293 PMOS_RESOURCE presDataBuffer = nullptr; // Handle of residual difference surface 294 PMOS_RESOURCE presReferences[CODEC_MAX_NUM_REF_FRAME] = {}; 295 PMOS_RESOURCE presMfdIntraRowStoreScratchBuffer = nullptr; // Handle of MFD Intra Row Store Scratch data surface 296 PMOS_RESOURCE presMfdDeblockingFilterRowStoreScratchBuffer = nullptr; // Handle of MFD Deblocking Filter Row Store Scratch data surface 297 PMOS_RESOURCE presStreamOutBuffer = nullptr; 298 MOS_MEMCOMP_STATE StreamOutBufMmcState = MOS_MEMCOMP_DISABLED; 299 PMOS_RESOURCE presMacroblockIldbStreamOutBuffer1 = nullptr; 300 PMOS_RESOURCE presMacroblockIldbStreamOutBuffer2 = nullptr; 301 PMOS_RESOURCE presSliceSizeStreamOutBuffer = nullptr; 302 PMOS_SURFACE psFwdRefSurface0 = nullptr; 303 PMOS_SURFACE psFwdRefSurface1 = nullptr; 304 PMOS_SURFACE psFwdRefSurface2 = nullptr; 305 bool bDynamicScalingEnable = false; 306 307 PMOS_RESOURCE presVdencIntraRowStoreScratchBuffer = nullptr; // For VDEnc, Handle of VDEnc Intra Row Store Scratch data surface 308 PMOS_RESOURCE presVdencTileRowStoreBuffer = nullptr; 309 PMOS_RESOURCE presVdencStreamOutBuffer = nullptr; 310 PMOS_RESOURCE presVdencCuObjStreamOutBuffer = nullptr; 311 PMOS_RESOURCE presVdencPakObjCmdStreamOutBuffer = nullptr; 312 PMOS_RESOURCE presVdencStreamInBuffer = nullptr; 313 PMOS_RESOURCE presVdencReferences[CODEC_MAX_NUM_REF_FRAME] = {}; 314 PMOS_RESOURCE presVdenc4xDsSurface[CODEC_MAX_NUM_REF_FRAME] = {}; 315 PMOS_RESOURCE presVdenc8xDsSurface[CODEC_MAX_NUM_REF_FRAME] = {}; 316 317 PMOS_RESOURCE presVdencColocatedMVWriteBuffer = nullptr; // For AVC only 318 PMOS_RESOURCE presVdencColocatedMVReadBuffer = nullptr; // For AVC only 319 PMOS_RESOURCE presDeblockingFilterTileRowStoreScratchBuffer = nullptr; // For HEVC, VP9 320 PMOS_RESOURCE presDeblockingFilterColumnRowStoreScratchBuffer = nullptr; // For HEVC, VP9 321 PMOS_RESOURCE presMetadataLineBuffer = nullptr; // For HEVC, VP9 322 PMOS_RESOURCE presMetadataTileLineBuffer = nullptr; // For HEVC, VP9 323 PMOS_RESOURCE presMetadataTileColumnBuffer = nullptr; // For HEVC, VP9 324 PMOS_RESOURCE presSaoLineBuffer = nullptr; // For HEVC only 325 PMOS_RESOURCE presSaoTileLineBuffer = nullptr; // For HEVC only 326 PMOS_RESOURCE presSaoTileColumnBuffer = nullptr; // For HEVC only 327 PMOS_RESOURCE presCurMvTempBuffer = nullptr; // For HEVC, VP9 328 PMOS_RESOURCE presColMvTempBuffer[CODEC_MAX_NUM_REF_FRAME] = {}; // For HEVC, VP9 329 PMOS_RESOURCE presLcuBaseAddressBuffer = nullptr; // For HEVC only 330 PMOS_RESOURCE presLcuILDBStreamOutBuffer = nullptr; // For HEVC only 331 PMOS_RESOURCE presVp9ProbBuffer = nullptr; // For VP9 only 332 PMOS_RESOURCE presVp9SegmentIdBuffer = nullptr; // For VP9 only 333 PMOS_RESOURCE presHvdLineRowStoreBuffer = nullptr; // For VP9 only 334 PMOS_RESOURCE presHvdTileRowStoreBuffer = nullptr; // For VP9 only 335 PMOS_RESOURCE presSaoStreamOutBuffer = nullptr; // For HEVC only 336 PMOS_RESOURCE presSaoRowStoreBuffer = nullptr; // For HEVC only 337 PMOS_SURFACE presP010RTSurface = nullptr; // For HEVC only 338 PMOS_RESOURCE presFrameStatStreamOutBuffer = nullptr; 339 PMOS_RESOURCE presSseSrcPixelRowStoreBuffer = nullptr; 340 PMOS_RESOURCE presSegmentMapStreamIn = nullptr; 341 PMOS_RESOURCE presSegmentMapStreamOut = nullptr; 342 PMOS_RESOURCE presPakCuLevelStreamoutBuffer = nullptr; 343 PMHW_VDBOX_SURFACE_PARAMS pRawSurfParam = nullptr; 344 PMHW_VDBOX_SURFACE_PARAMS pDecodedReconParam = nullptr; 345 bool bVdencEnabled = false; 346 bool bRawIs10Bit = false; 347 bool bDecodecReconIs10Bit = false; 348 uint32_t dwNumRefIdxL0ActiveMinus1 = 0; 349 uint32_t dwNumRefIdxL1ActiveMinus1 = 0; 350 uint32_t dwLcuStreamOutOffset = 0; 351 uint32_t dwFrameStatStreamOutOffset = 0; 352 uint32_t dwVdencStatsStreamOutOffset = 0; 353 bool oneOnOneMapping = false; // Flag for indicating using 1:1 ref index mapping for vdenc 354 bool isLowDelayB = true; // Flag to indicate if it is LDB 355 uint8_t IBCRefIdxMask = 0; 356 PMOS_RESOURCE presVdencCumulativeCuCountStreamoutSurface = nullptr; ~MHW_VDBOX_PIPE_BUF_ADDR_PARAMSMHW_VDBOX_PIPE_BUF_ADDR_PARAMS357 virtual ~MHW_VDBOX_PIPE_BUF_ADDR_PARAMS() {} 358 }; 359 using PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS = MHW_VDBOX_PIPE_BUF_ADDR_PARAMS * ; 360 361 typedef struct _MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS 362 { 363 uint32_t Mode; 364 PMOS_RESOURCE presDataBuffer; 365 uint32_t dwDataSize; 366 uint32_t dwDataOffset; 367 PMOS_RESOURCE presMvObjectBuffer; 368 uint32_t dwMvObjectSize; 369 uint32_t dwMvObjectOffset; 370 PMOS_RESOURCE presPakBaseObjectBuffer; 371 uint32_t dwPakBaseObjectSize; 372 uint32_t dwPakBaseObjectOffset; 373 PMOS_RESOURCE presPakTileSizeStasBuffer; 374 uint32_t dwPakTileSizeStasBufferSize; 375 uint32_t dwPakTileSizeRecordOffset; 376 // used by VP9 377 PMOS_RESOURCE presCompressedHeaderBuffer; 378 uint32_t dwCompressedHeaderSize; 379 PMOS_RESOURCE presProbabilityDeltaBuffer; 380 uint32_t dwProbabilityDeltaSize; 381 PMOS_RESOURCE presProbabilityCounterBuffer; 382 uint32_t dwProbabilityCounterOffset; 383 uint32_t dwProbabilityCounterSize; 384 PMOS_RESOURCE presTileRecordBuffer; 385 uint32_t dwTileRecordSize; 386 PMOS_RESOURCE presCuStatsBuffer; 387 uint32_t dwCuStatsSize; 388 389 PMOS_RESOURCE presStreamOutObjectBuffer; 390 uint32_t dwStreamOutObjectSize; 391 uint32_t dwStreamOutObjectOffset; 392 } MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS, *PMHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS; 393 394 struct MHW_VDBOX_AVC_IMG_PARAMS 395 { 396 // Decoding Params 397 PCODEC_AVC_PIC_PARAMS pAvcPicParams = nullptr; 398 PCODEC_MVC_EXT_PIC_PARAMS pMvcExtPicParams = nullptr; 399 uint8_t ucActiveFrameCnt = 0; 400 // Encoding Params 401 PCODEC_AVC_ENCODE_SEQUENCE_PARAMS pEncodeAvcSeqParams = nullptr; 402 PCODEC_AVC_ENCODE_PIC_PARAMS pEncodeAvcPicParams = nullptr; 403 PCODEC_AVC_ENCODE_SLICE_PARAMS pEncodeAvcSliceParams = nullptr; 404 PCODEC_REF_LIST *ppRefList = nullptr; 405 CODEC_PIC_ID *pPicIdx = nullptr; 406 uint32_t dwTqEnabled = 0; 407 uint32_t dwTqRounding = 0; 408 uint32_t dwMaxVmvR = 0; 409 uint16_t wPicWidthInMb = 0; 410 uint16_t wPicHeightInMb = 0; 411 uint16_t wSlcHeightInMb = 0; 412 uint8_t ucKernelMode = 0; // normal, performance, quality. 413 414 //FEI multiple passes PAK ---max frame size 415 uint8_t ucCurrPass = 0; 416 uint8_t *pDeltaQp = nullptr; 417 uint32_t dwMaxFrameSize = 0; 418 419 bool bIPCMPass = false; 420 // VDEnc specific 421 bool bVdencEnabled = false; 422 bool bVDEncPerfModeEnabled = false; 423 bool bVdencStreamInEnabled = false; 424 bool bVdencBRCEnabled = false; 425 bool bSliceSizeStreamOutEnabled = false; 426 bool bCrePrefetchEnable = false; 427 bool bPerMBStreamOut = false; 428 429 uint32_t dwMbSlcThresholdValue = 0; // For VDENC dynamic slice size control 430 uint32_t dwSliceThresholdTable = 0; 431 uint32_t dwVdencSliceMinusBytes = 0; 432 uint8_t *pVDEncModeCost = nullptr; 433 uint8_t *pVDEncMvCost = nullptr; 434 uint8_t *pVDEncHmeMvCost = nullptr; 435 uint32_t biWeight = 0; ~MHW_VDBOX_AVC_IMG_PARAMSMHW_VDBOX_AVC_IMG_PARAMS436 virtual ~MHW_VDBOX_AVC_IMG_PARAMS(){} 437 }; 438 using PMHW_VDBOX_AVC_IMG_PARAMS = MHW_VDBOX_AVC_IMG_PARAMS * ; 439 440 typedef struct _MHW_VDBOX_QM_PARAMS 441 { 442 uint32_t Standard; 443 uint32_t Mode; 444 PMHW_VDBOX_AVC_QM_PARAMS pAvcIqMatrix; 445 CodecMpeg2IqMatrix *pMpeg2IqMatrix; 446 CodecJpegQuantMatrix *pJpegQuantMatrix; 447 uint32_t JpegQMTableSelector; 448 bool bJpegQMRotation; 449 PMHW_VDBOX_HEVC_QM_PARAMS pHevcIqMatrix; 450 } MHW_VDBOX_QM_PARAMS, *PMHW_VDBOX_QM_PARAMS; 451 452 typedef struct _MHW_VDBOX_AVC_WEIGHTOFFSET_PARAMS 453 { 454 uint32_t uiList; 455 uint32_t uiLumaLogWeightDenom; 456 uint32_t uiChromaLogWeightDenom; 457 uint32_t uiLumaWeightFlag; 458 uint32_t uiChromaWeightFlag; 459 uint32_t uiNumRefForList; 460 int16_t Weights[2][32][3][2]; 461 PCODEC_AVC_ENCODE_PIC_PARAMS pAvcPicParams; 462 } MHW_VDBOX_AVC_WEIGHTOFFSET_PARAMS, *PMHW_VDBOX_AVC_WEIGHTOFFSET_PARAMS; 463 464 typedef struct _MHW_VDBOX_PAK_INSERT_PARAMS 465 { 466 PBSBuffer pBsBuffer; 467 // also reuse dwBitSize for passing SrcDataEndingBitInclusion when (pEncoder->bLastPicInStream || pEncoder->bLastPicInSeq) 468 uint32_t dwBitSize; 469 uint32_t dwOffset; 470 uint32_t uiSkipEmulationCheckCount; 471 bool bLastPicInSeq; 472 bool bLastPicInStream; 473 bool bLastHeader; 474 bool bEmulationByteBitsInsert; 475 bool bSetLastPicInStreamData; 476 bool bSliceHeaderIndicator; 477 bool bHeaderLengthExcludeFrmSize; 478 uint32_t *pdwMpeg2PicHeaderTotalBufferSize; 479 uint32_t *pdwMpeg2PicHeaderDataStartOffset; 480 bool bResetBitstreamStartingPos; 481 bool bEndOfSlice; 482 uint32_t dwLastPicInSeqData; 483 uint32_t dwLastPicInStreamData; 484 PMHW_BATCH_BUFFER pBatchBufferForPakSlices; 485 bool bVdencInUse; 486 } MHW_VDBOX_PAK_INSERT_PARAMS, *PMHW_VDBOX_PAK_INSERT_PARAMS; 487 488 typedef struct _MHW_VDBOX_VP9_SEGMENT_STATE 489 { 490 uint32_t Mode; 491 PCODEC_VP9_SEGMENT_PARAMS pVp9SegmentParams; 492 PCODEC_VP9_ENCODE_SEGMENT_PARAMS pVp9EncodeSegmentParams; 493 uint8_t ucCurrentSegmentId; 494 uint8_t ucQPIndexLumaAC; 495 const uint8_t *pcucLfQpLookup; 496 uint8_t *pbSegStateBufferPtr; 497 } MHW_VDBOX_VP9_SEGMENT_STATE, *PMHW_VDBOX_VP9_SEGMENT_STATE; 498 499 typedef struct _MHW_VDBOX_HCP_BSD_PARAMS 500 { 501 uint32_t dwBsdDataLength; 502 uint32_t dwBsdDataStartOffset; 503 } MHW_VDBOX_HCP_BSD_PARAMS, *PMHW_VDBOX_HCP_BSD_PARAMS; 504 505 typedef struct _MHW_VDBOX_ROWSTORE_PARAMS 506 { 507 uint32_t Mode; 508 uint32_t dwPicWidth; 509 uint32_t bMbaff; 510 bool bIsFrame; 511 uint8_t ucBitDepthMinus8; 512 uint8_t ucChromaFormat; 513 uint8_t ucLCUSize; 514 } MHW_VDBOX_ROWSTORE_PARAMS, *PMHW_VDBOX_ROWSTORE_PARAMS; 515 516 typedef struct _MHW_VDBOX_ROWSTORE_CACHE 517 { 518 bool bSupported; 519 bool bEnabled; 520 uint32_t dwAddress; 521 } MHW_VDBOX_ROWSTORE_CACHE, *PMHW_VDBOX_ROWSTORE_CACHE; 522 523 struct MHW_VDBOX_STATE_CMDSIZE_PARAMS 524 { 525 bool bShortFormat = false; 526 bool bHucDummyStream = false; 527 bool bSfcInUse = false; ~MHW_VDBOX_STATE_CMDSIZE_PARAMSMHW_VDBOX_STATE_CMDSIZE_PARAMS528 virtual ~MHW_VDBOX_STATE_CMDSIZE_PARAMS() {} 529 }; 530 using PMHW_VDBOX_STATE_CMDSIZE_PARAMS = MHW_VDBOX_STATE_CMDSIZE_PARAMS * ; 531 532 typedef struct _MHW_VDBOX_AVC_SLICE_STATE 533 { 534 PCODEC_PIC_ID pAvcPicIdx; 535 PMOS_RESOURCE presDataBuffer; 536 uint32_t dwDataBufferOffset; 537 uint32_t dwOffset; 538 uint32_t dwLength; 539 uint32_t dwSliceIndex; 540 bool bLastSlice; 541 uint32_t dwTotalBytesConsumed; 542 543 // Decoding Only 544 PCODEC_AVC_PIC_PARAMS pAvcPicParams; 545 PCODEC_MVC_EXT_PIC_PARAMS pMvcExtPicParams; 546 PCODEC_AVC_SLICE_PARAMS pAvcSliceParams; 547 uint32_t dwNextOffset; 548 uint32_t dwNextLength; 549 bool bIntelEntrypointInUse; 550 bool bPicIdRemappingInUse; 551 bool bShortFormatInUse; 552 bool bPhantomSlice; 553 uint8_t ucDisableDeblockingFilterIdc; 554 uint8_t ucSliceBetaOffsetDiv2; 555 uint8_t ucSliceAlphaC0OffsetDiv2; 556 557 // Encoding Only 558 PCODEC_AVC_ENCODE_SEQUENCE_PARAMS pEncodeAvcSeqParams; 559 PCODEC_AVC_ENCODE_PIC_PARAMS pEncodeAvcPicParams; 560 PCODEC_AVC_ENCODE_SLICE_PARAMS pEncodeAvcSliceParams; 561 PBSBuffer pBsBuffer; 562 PCODECHAL_NAL_UNIT_PARAMS *ppNalUnitParams; 563 PMHW_BATCH_BUFFER pBatchBufferForPakSlices; 564 bool bSingleTaskPhaseSupported; 565 bool bFirstPass; 566 bool bLastPass; 567 bool bBrcEnabled; 568 bool bRCPanicEnable; 569 bool bInsertBeforeSliceHeaders; 570 bool bAcceleratorHeaderPackingCaps; 571 uint32_t dwBatchBufferForPakSlicesStartOffset; 572 uint32_t uiSkipEmulationCheckCount; 573 uint32_t dwRoundingValue; 574 uint32_t dwRoundingIntraValue; 575 bool bRoundingInterEnable; 576 uint16_t wFrameFieldHeightInMB; // Frame/field Height in MB 577 bool bVdencInUse; 578 bool bVdencNoTailInsertion; 579 bool oneOnOneMapping = false; 580 bool bFullFrameData; 581 } MHW_VDBOX_AVC_SLICE_STATE, *PMHW_VDBOX_AVC_SLICE_STATE; 582 583 #endif 584