1 /*
2 * Copyright (c) 2019, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include "Mirror_H_YUVA.h"
23
24 const ushort R[8] = {
25 0, 0, 0, 0,
26 0, 0, 0, 0,
27 };
28 const ushort C[8] = {
29 7, 6, 5, 4,
30 3, 2, 1, 0,
31 };
32
Mirror_H_YUVA(CURBE_INPUT_OUTPUT,GLOBAL_BUFFER_INPUT_OUTPUT)33 _GENX_MAIN_ _CM_CALLABLE_ void Mirror_H_YUVA(
34 CURBE_INPUT_OUTPUT,
35 GLOBAL_BUFFER_INPUT_OUTPUT)
36 {
37 /*
38 Buffer layout after shuffle
39 _________________________________________________
40 |_______Block0__________|_______Block1__________|
41 |_______Block2__________|_______Block3__________|
42 |_______Block4__________|_______Block5__________|
43 |_______Block6__________|_______Block7__________|
44
45 Write back buffer layout correlate to the block number#, each box stands for 1 GRF
46 _______________________________________________
47 |____R0_________R1_____|____R2_________R3_____|
48 |____G0_________G1_____|____G2_________G3_____|
49 |____B0_________B1_____|____B2_________B3_____|
50 |____A0_________A1_____|____A2_________A3_____|
51 |____R4_________R5_____|____R6_________R7_____|
52 |____G4_________G5_____|____G6_________G7_____|
53 |____B4_________B5_____|____B6_________B7_____|
54 |____A4_________A5_____|____A6_________A7_____|
55 */
56
57 // Using merging mirroring method to generate SIMD8/SIMD16 instructions for optimization
58 matrix_ref<ushort, 16, 16> WriteBackBuffer = DataBuffer.format<ushort, 96, 16>().select<16, 1, 16, 1>(Buffer_Index << 4, 0);
59
60
61 #pragma unroll
62 for (short j = 0; j < 4; j++)
63 {
64 vector<ushort, 8> row(R);
65 vector<ushort, 8> col(C);
66
67 vector<ushort, 8> temp;
68
69 // R/G/B/A channels
70 temp = WriteBackBuffer.select<1, 1, 8, 1>(2 * j, 0).iselect(row, col);
71 WriteBackBuffer.select<1, 1, 8, 1>(2 * j, 0) = WriteBackBuffer.select<1, 1, 8, 1>(2 * j + 8, 0).iselect(row, col);
72 WriteBackBuffer.select<1, 1, 8, 1>(2 * j + 8, 0) = temp;
73
74 temp = WriteBackBuffer.select<1, 1, 8, 1>(2 * j, 8).iselect(row, col);
75 WriteBackBuffer.select<1, 1, 8, 1>(2 * j, 8) = WriteBackBuffer.select<1, 1, 8, 1>(2 * j + 8, 8).iselect(row, col);
76 WriteBackBuffer.select<1, 1, 8, 1>(2 * j + 8, 8) = temp;
77
78 temp = WriteBackBuffer.select<1, 1, 8, 1>(2 * j + 1, 0).iselect(row, col);
79 WriteBackBuffer.select<1, 1, 8, 1>(2 * j + 1, 0) = WriteBackBuffer.select<1, 1, 8, 1>(2 * j + 9, 0).iselect(row, col);
80 WriteBackBuffer.select<1, 1, 8, 1>(2 * j + 9, 0) = temp;
81
82 temp = WriteBackBuffer.select<1, 1, 8, 1>(2 * j + 1, 8).iselect(row, col);
83 WriteBackBuffer.select<1, 1, 8, 1>(2 * j + 1, 8) = WriteBackBuffer.select<1, 1, 8, 1>(2 * j + 9, 8).iselect(row, col);
84 WriteBackBuffer.select<1, 1, 8, 1>(2 * j + 9, 8) = temp;
85 }
86 }