1 /* 2 * Copyright (c) 2009-2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file renderhal_g8.h 24 //! \brief 25 //! 26 //! 27 //! \file renderhal_g8.h 28 //! \brief header file of Gen8 hardware functions 29 //! \details Gen8 hardware functions declare 30 //! 31 #ifndef __RENDERHAL_G8_H__ 32 #define __RENDERHAL_G8_H__ 33 34 #include "renderhal_platform_interface.h" 35 #include "mhw_render_hwcmd_g8_X.h" 36 #include "mhw_state_heap_hwcmd_g8_X.h" 37 #include "mhw_mmio_g8.h" 38 39 //! 40 //! \brief L3$ registers and configuration Gen8 41 //! 42 43 44 45 46 #define RENDERHAL_SAMPLERS_AVS_G8 3 // 1 layer - One each for Y, U and V 47 48 //! 49 //! \brief L3 cache CNTLREG value with SLM disabled on BDW GT2 VP/MDF 50 //! SLM URB DC RO I/S C T 51 //! { 0, 256, 64, 448, 0, 0, 0 } 52 #define RENDERHAL_L3_CACHE_CNTL_REG_VALUE_G8 (0x0021C040) 53 54 //! \brief for BDW GT2 with WA for D0 hang 55 //! SLM URB Rest DC RO I/S C T 56 //! { 256, 128, 384, 0, 0, 0, 0, 0, } 57 #define RENDERHAL_L3_CACHE_CNTL_REG_VALUE_ALLOCATE_SLM_D0_WA_G8 (0x60000021) 58 59 //! 60 //! \brief L3 cache CNTLREG value with SLM disabled 61 //! SLM URB Rest DC RO I/S C T 62 //! { 0, 256, 512, 0, 0, 0, 0, 0 } 63 //! 64 #define RENDERHAL_L3_CACHE_CNTL_REG_SLM_DISABLE_ALL_L3_512K_G8 (0x80000040) 65 66 //! 67 //! \brief L3 cache CNTLREG value with SLM enabled 68 //! SLM URB Rest DC RO I/S C T Sum 69 //! { 192, 128, 0, 256, 128, 0, 0, 0 } 70 #define RENDERHAL_L3_CACHE_CNTL_REG_SLM_ENABLE_G8 (0x00808021) 71 72 typedef enum _RENDERHAL_MO_TARGET_CACHE_G8 73 { 74 RENDERHAL_MO_TARGET_CACHE_ELLC_G8 = 0x0, 75 RENDERHAL_MO_TARGET_CACHE_LLC_G8 = 0x1, 76 RENDERHAL_MO_TARGET_CACHE_LLC_ELLC_G8 = 0x2, 77 RENDERHAL_MO_TARGET_CACHE_L3_LLC_ELLC_G8 = 0x3 78 } RENDERHAL_MO_TARGET_CACHE_G8; 79 80 typedef enum _RENDERHAL_MO_CACHE_CONTROL_G8 81 { 82 RENDERHAL_MO_CACHE_CONTROL_USE_PTE_G8 = 0x0, 83 RENDERHAL_MO_CACHE_CONTROL_UC_G8 = 0x1, 84 RENDERHAL_MO_CACHE_CONTROL_WT_G8 = 0x2, 85 RENDERHAL_MO_CACHE_CONTROL_WB_G8 = 0x3 86 } RENDERHAL_MO_CACHE_CONTROL_G8; 87 88 class XRenderHal_Interface_g8 : public XRenderHal_Platform_Interface 89 { 90 public: XRenderHal_Interface_g8()91 XRenderHal_Interface_g8() {} ~XRenderHal_Interface_g8()92 virtual ~XRenderHal_Interface_g8() {} 93 94 //! 95 //! \brief Setup Surface State 96 //! \details Setup Surface States for Gen75/Gen8 97 //! \param PRENDERHAL_INTERFACE pRenderHal 98 //! [in] Pointer to Hardware Interface Structure 99 //! \param PRENDERHAL_SURFACE pRenderHalSurface 100 //! [in] Pointer to Render Hal Surface 101 //! \param PRENDERHAL_SURFACE_STATE_PARAMS pParams 102 //! [in] Pointer to Surface State Params 103 //! \param int32_t *piNumEntries 104 //! [out] Pointer to Number of Surface State Entries (Num Planes) 105 //! \param PRENDERHAL_SURFACE_STATE_ENTRY * ppSurfaceEntries 106 //! [out] Array of Surface State Entries 107 //! \param PRENDERHAL_OFFSET_OVERRIDE pOffsetOverride 108 //! [in] If not nullptr, provides adjustments to Y, UV plane offsets, 109 //! used for kernel WA in a few cases. nullptr is the most common usage. 110 //! \return MOS_STATUS 111 //! 112 MOS_STATUS SetupSurfaceState( 113 PRENDERHAL_INTERFACE pRenderHal, 114 PRENDERHAL_SURFACE pRenderHalSurface, 115 PRENDERHAL_SURFACE_STATE_PARAMS pParams, 116 int32_t *piNumEntries, 117 PRENDERHAL_SURFACE_STATE_ENTRY *ppSurfaceEntries, 118 PRENDERHAL_OFFSET_OVERRIDE pOffsetOverride); 119 120 //! 121 //! \brief Check if Sampler128Elements is supported 122 //! \return true of false 123 //! IsSampler128ElementsSupported()124 virtual inline bool IsSampler128ElementsSupported() { return false; } 125 126 //! 127 //! \brief Checks how per thread scratch space size bits in VFE state are interpreted by HW 128 //! \details For BDW GT1/2/3 A0 steppings, per thread scratch space size in VFE state 129 //! is 11 bits indicating [2k bytes, 2 Mbytes]: 0=2k, 1=4k, 2=8k � 10=2M 130 //! BDW+ excluding A0 step is 12 bits indicating [1k bytes, 2 Mbytes]: 0=1k, 1=2k, 2=4k, 3=8k � 11=2M 131 //! \param PRENDERHAL_INTERFACE pRenderHal 132 //! [in] Pointer to RenderHal interface 133 //! \return true if BDW A0 stepping, false otherwise 134 //! 135 bool PerThreadScratchSpaceStart2K( 136 PRENDERHAL_INTERFACE pRenderHal); 137 138 //! 139 //! \brief Encode SLM Size for Interface Descriptor 140 //! \details Setup SLM size 141 //! \param uint32_t SLMSize 142 //! [in] SLM size in 1K 143 //! \return encoded output 144 //! 145 uint32_t EncodeSLMSize(uint32_t SLMSize); 146 147 //! 148 //! \brief Set Chroma Direction 149 //! \details Setup Chroma Direction for G8 150 //! \param PRENDERHAL_INTERFACE pRenderHal 151 //! [in] Pointer to Hardware Interface 152 //! \param PRENDERHAL_SURFACE pRenderHalSurface 153 //! [in] Pointer to Render Hal Surface 154 //! \return uint8_t 155 //! 156 uint8_t SetChromaDirection( 157 PRENDERHAL_INTERFACE pRenderHal, 158 PRENDERHAL_SURFACE pRenderHalSurface); 159 160 //! 161 //! \brief Convert To Nano Seconds 162 //! \details Convert to Nano Seconds 163 //! \param PRENDERHAL_INTERFACE pRenderHal 164 //! [in] Pointer to Hardware Interface Structure 165 //! \param uint64_t iTicks 166 //! [in] Ticks 167 //! \param uint64_t *piNs 168 //! [in] Nano Seconds 169 //! \return void 170 //! 171 void ConvertToNanoSeconds( 172 PRENDERHAL_INTERFACE pRenderHal, 173 uint64_t iTicks, 174 uint64_t *piNs); 175 176 //! 177 //! \brief Initialize the State Heap Settings per platform 178 //! \param PRENDERHAL_INTERFACE pRenderHal 179 //! [out] Pointer to PRENDERHAL_INTERFACE 180 //! \return void 181 //! 182 void InitStateHeapSettings( 183 PRENDERHAL_INTERFACE pRenderHal); 184 185 //! 186 //! \brief Initialize the default surface type and advanced surface type per platform 187 //! \param PRENDERHAL_INTERFACE pRenderHal 188 //! [out] Pointer to PRENDERHAL_INTERFACE 189 //! \return void 190 //! 191 void InitSurfaceTypes( 192 PRENDERHAL_INTERFACE pRenderHal); 193 194 //! 195 //! \brief Check if YV12 Single Pass is supported 196 //! \param PRENDERHAL_INTERFACE pRenderHal 197 //! [in] Pointer to Hardware Interface 198 //! \return true of false 199 //! IsEnableYV12SinglePass(PRENDERHAL_INTERFACE pRenderHal)200 inline bool IsEnableYV12SinglePass( 201 PRENDERHAL_INTERFACE pRenderHal) 202 { 203 MOS_UNUSED(pRenderHal); 204 return false; 205 } 206 207 //! 208 //! \brief Get the Size of AVS Sampler State 209 //! \param PRENDERHAL_INTERFACE pRenderHal 210 //! [in] Pointer to Hardware Interface 211 //! \return size 212 //! GetSizeSamplerStateAvs(PRENDERHAL_INTERFACE pRenderHal)213 inline uint32_t GetSizeSamplerStateAvs( 214 PRENDERHAL_INTERFACE pRenderHal) 215 { 216 return pRenderHal->pHwSizes->dwSizeSamplerStateAvs; 217 } 218 219 //! 220 //! \brief Enables L3 cacheing flag and sets related registers/values 221 //! \param PRENDERHAL_INTERFACE pRenderHal 222 //! [in] Pointer to Hardware Interface 223 //! \param pCacheSettings 224 //! [in] L3 Cache Configurations 225 //! \return MOS_STATUS 226 //! MOS_STATUS_SUCCESS if success, else fail reason 227 //! 228 virtual MOS_STATUS EnableL3Caching( 229 PRENDERHAL_INTERFACE pRenderHal, 230 PRENDERHAL_L3_CACHE_SETTINGS pCacheSettings); 231 232 //! 233 //! \brief Get offset and/or pointer to sampler state 234 //! \details Get offset and/or pointer to sampler state in General State Heap 235 //! \param PRENDERHAL_INTERFACE pRenderHal 236 //! [in] Pointer to RenderHal Interface 237 //! \param int32_t iMediaID 238 //! [in] Media ID associated with sampler 239 //! \param int32_t iSamplerID 240 //! [in] Sampler ID 241 //! \param uint32_t *pdwSamplerOffset 242 //! [out] optional; offset of sampler state from GSH base 243 //! \param void **ppSampler 244 //! [out] optional; pointer to sampler state in GSH 245 //! \return MOS_STATUS 246 //! 247 virtual MOS_STATUS GetSamplerOffsetAndPtr_DSH( 248 PRENDERHAL_INTERFACE pRenderHal, 249 int32_t iMediaID, 250 int32_t iSamplerID, 251 PMHW_SAMPLER_STATE_PARAM pSamplerParams, 252 uint32_t *pdwSamplerOffset, 253 void **ppSampler); 254 255 //! 256 //! \brief Initialize the DSH Settings 257 //! \details Initialize the structure DynamicHeapSettings in pRenderHal 258 //! \param PRENDERHAL_INTERFACE pRenderHal 259 //! [in] Pointer to HW interface 260 //! \return void 261 //! 262 virtual void InitDynamicHeapSettings( 263 PRENDERHAL_INTERFACE pRenderHal); 264 265 //! 266 //! \brief Get the depth bit mask for buffer 267 //! \details Get the depth bit mask for buffer 268 //! \return uint32_t 269 //! depth bit mask for buffer 270 //! GetDepthBitMaskForBuffer()271 uint32_t GetDepthBitMaskForBuffer() { return MOS_MASKBITS32(21, 26); }; 272 273 //! 274 //! \brief Get the depth bit mask for raw buffer 275 //! \details Get the depth bit mask for raw buffer 276 //! \return uint32_t 277 //! depth bit mask for raw buffer 278 //! GetDepthBitMaskForRawBuffer()279 uint32_t GetDepthBitMaskForRawBuffer() { return MOS_MASKBITS32(21, 30); }; 280 281 //! 282 //! \brief Get the pointer to the MHW_VFE_PARAMS 283 //! \return MHW_VFE_PARAMS* 284 //! pointer to the MHW_VFE_PARAMS 285 //! GetVfeStateParameters()286 virtual MHW_VFE_PARAMS* GetVfeStateParameters() { return &m_vfeStateParams; } 287 288 //! 289 //! \brief Set Power Option Status 290 //! \param [in] pRenderHal 291 //! Pointer to Hardware Interface 292 //! \param [in,out] pCmdBuffer 293 //! Pointer to Command Buffer 294 //! \return MOS_STATUS 295 //! MOS_STATUS_SUCCESS if success, else fail reason 296 //! 297 virtual MOS_STATUS SetPowerOptionStatus( 298 PRENDERHAL_INTERFACE pRenderHal, 299 PMOS_COMMAND_BUFFER pCmdBuffer); 300 301 //! 302 //! \brief Set L3 cache override config parameters 303 //! \param [in] pRenderHal 304 //! Pointer to RenderHal Interface Structure 305 //! \param [in,out] pCacheSettings 306 //! Pointer to pCacheSettings 307 //! \param [in] bEnableSLM 308 //! Flag to enable SLM 309 //! \return MOS_STATUS 310 //! MOS_STATUS_SUCCESS if success. Error code otherwise 311 //! 312 virtual MOS_STATUS SetCacheOverrideParams( 313 PRENDERHAL_INTERFACE pRenderHal, 314 PRENDERHAL_L3_CACHE_SETTINGS pCacheSettings, 315 bool bEnableSLM); 316 317 //! \brief Get the size of Render Surface State Command 318 //! \return size_t 319 //! the size of render surface state command 320 virtual size_t GetSurfaceStateCmdSize(); 321 322 //! \brief Get the address of the ith Palette Data 323 //! \param [in] i 324 //! Index of the palette data 325 //! \return void * 326 //! address of the ith palette data table GetPaletteDataAddress(int i)327 virtual void* GetPaletteDataAddress(int i) {return &m_paletteData[i];} 328 329 //! \brief Get the size of Binding Table State Command 330 //! \return size_t 331 //! the size of binding table state command GetBTStateCmdSize()332 virtual size_t GetBTStateCmdSize() {return mhw_state_heap_g8_X::BINDING_TABLE_STATE_CMD::byteSize;} 333 334 //! \brief Check if compute context in use 335 //! \param PRENDERHAL_INTERFACE pRenderHal 336 //! [in] Pointer to Hardware Interface 337 //! \return true of false IsComputeContextInUse(PRENDERHAL_INTERFACE pRenderHal)338 virtual bool IsComputeContextInUse(PRENDERHAL_INTERFACE pRenderHal) 339 { 340 MOS_UNUSED(pRenderHal); 341 return false; 342 } 343 344 protected: 345 //! 346 //! \brief Get L3 control register value with SLM enabled 347 //! \return uint32_t 348 //! L3 Control Register value 349 //! 350 virtual uint32_t GetL3CacheCntlRegWithSLM() = 0; 351 352 MHW_VFE_PARAMS m_vfeStateParams; 353 mhw_render_g8_X::PALETTE_ENTRY_CMD 354 m_paletteData[RENDERHAL_PALETTE_MAX][RENDERHAL_PALETTE_ENTRIES_MAX]; 355 356 }; 357 358 #endif // __RENDERHAL_G8_H__ 359