1 /*
2 * Copyright (c) 2017, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_vdbox_huc_g9_skl.cpp
24 //! \brief Constructs VdBox Huc commands on Gen9 BXT+ platforms
25
26 #include "mhw_vdbox_huc_g9_skl.h"
27 #include "mhw_vdbox_vdenc_hwcmd_g9_skl.h"
28 #include "mhw_mmio_g9.h"
29
InitMmioRegisters()30 void MhwVdboxHucInterfaceG9Skl::InitMmioRegisters()
31 {
32 MmioRegistersHuc *mmioRegisters = &m_mmioRegisters[MHW_VDBOX_NODE_1];
33
34 mmioRegisters->hucUKernelHdrInfoRegOffset = HUC_UKERNEL_HDR_INFO_REG_OFFSET_NODE_1_INIT_G9;
35 mmioRegisters->hucStatusRegOffset = HUC_STATUS_REG_OFFSET_NODE_1_INIT_G9;
36 mmioRegisters->hucStatus2RegOffset = HUC_STATUS2_REG_OFFSET_NODE_1_INIT_G9;
37 }
38
GetHucStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)39 MOS_STATUS MhwVdboxHucInterfaceG9Skl::GetHucStateCommandSize(
40 uint32_t mode,
41 uint32_t *commandsSize,
42 uint32_t *patchListSize,
43 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
44 {
45 MHW_FUNCTION_ENTER;
46
47 MHW_MI_CHK_NULL(commandsSize);
48 MHW_MI_CHK_NULL(patchListSize);
49
50 MHW_MI_CHK_STATUS((MhwVdboxHucInterfaceGeneric<mhw_vdbox_huc_g9_skl, mhw_mi_g9_X>::
51 GetHucStateCommandSize(mode, commandsSize, patchListSize, params)));
52
53 *commandsSize += mhw_vdbox_vdenc_g9_skl::VD_PIPELINE_FLUSH_CMD::byteSize;
54 *patchListSize += PATCH_LIST_COMMAND(VD_PIPELINE_FLUSH_CMD);
55
56 return MOS_STATUS_SUCCESS;
57 }
58
59