1// SPDX-License-Identifier: GPL-2.0
2/* The pxa3xx skeleton simply augments the 2xx version */
3#include "pxa2xx.dtsi"
4
5#define MFP_PIN_PXA300(gpio)				\
6	((gpio <= 2) ? (0x00b4 + 4 * gpio) :		\
7	 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) :	\
8	 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) :	\
9	 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) :	\
10	 0)
11#define MFP_PIN_PXA300_2(gpio)				\
12	((gpio <= 1) ? (0x674 + 4 * gpio) :		\
13	 (gpio <= 6) ? (0x2dc + 4 * gpio) :		\
14	 0)
15
16#define MFP_PIN_PXA310(gpio)				\
17	((gpio <= 2) ? (0x00b4 + 4 * gpio) :		\
18	 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) :	\
19	 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) :	\
20	 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) :	\
21	 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) :	\
22	 (gpio <= 262) ? 0 :				\
23	 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) :	\
24	 0)
25#define MFP_PIN_PXA310_2(gpio)				\
26	((gpio <= 1) ? (0x674 + 4 * gpio) :		\
27	 (gpio <= 6) ? (0x2dc + 4 * gpio) :		\
28	 (gpio <= 10) ? (0x52c + 4 * gpio) :		\
29	 0)
30
31#define MFP_PIN_PXA320(gpio)				\
32	((gpio <= 4) ? (0x0124 + 4 * gpio) :		\
33	 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) :	\
34	 (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) :	\
35	 (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) :	\
36	 (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) :	\
37	 (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) :	\
38	 (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) :	\
39	 (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) :	\
40	 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) :	\
41	 0)
42#define MFP_PIN_PXA320_2(gpio)				\
43	((gpio <= 3) ? (0x674 + 4 * gpio) :		\
44	 (gpio <= 5) ? (0x284 + 4 * gpio) :		\
45	 0)
46
47/*
48 * MFP Alternate functions for pins having a gpio.
49 * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 >
50 */
51#define MFP_AF0		(0 << 0)
52#define MFP_AF1		(1 << 0)
53#define MFP_AF2		(2 << 0)
54#define MFP_AF3		(3 << 0)
55#define MFP_AF4		(4 << 0)
56#define MFP_AF5		(5 << 0)
57#define MFP_AF6		(6 << 0)
58
59/*
60 * MFP drive strength functions for pins.
61 * Example of use: pinctrl-single,drive-strength = MFP_DS03X;
62 */
63#define MFP_DSMSK	(0x7 << 10)
64#define MFP_DS01X	< (0x0 << 10) MFP_DSMSK >
65#define MFP_DS02X	< (0x1 << 10) MFP_DSMSK >
66#define MFP_DS03X	< (0x2 << 10) MFP_DSMSK >
67#define MFP_DS04X	< (0x3 << 10) MFP_DSMSK >
68#define MFP_DS06X	< (0x4 << 10) MFP_DSMSK >
69#define MFP_DS08X	< (0x5 << 10) MFP_DSMSK >
70#define MFP_DS10X	< (0x6 << 10) MFP_DSMSK >
71#define MFP_DS13X	< (0x7 << 10) MFP_DSMSK >
72
73/*
74 * MFP bias pull mode for pins.
75 * Example of use: pinctrl-single,bias-pullup = MPF_PULL_UP;
76 */
77#define MPF_PULL_MSK	(0x7 << 13)
78#define MPF_PULL_DOWN	< (0x5 << 13) (0x5 << 13) 0 MPF_PULL_MSK >
79#define MPF_PULL_UP	< (0x6 << 13) (0x6 << 13) 0 MPF_PULL_MSK >
80
81/*
82 * MFP low power mode for pins.
83 * Example of use:
84 *   pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL);
85 *
86 * Table that determines the low power modes outputs, with actual settings
87 * used in parentheses for don't-care values. Except for the float output,
88 * the configured driven and pulled levels match, so if there is a need for
89 * non-LPM pulled output, the same configuration could probably be used.
90 *
91 * Output value  sleep_oe_n  sleep_data  pullup_en  pulldown_en  pull_sel
92 *                 (bit 7)    (bit 8)    (bit 14)     (bit 13)   (bit 15)
93 *
94 * Input            0          X(0)        X(0)        X(0)       0
95 * Drive 0          0          0           0           X(1)       0
96 * Drive 1          0          1           X(1)        0	  0
97 * Pull hi (1)      1          X(1)        1           0	  0
98 * Pull lo (0)      1          X(0)        0           1	  0
99 * Z (float)        1          X(0)        0           0	  0
100 */
101#define MFP_LPM(x)		< (x) MFP_LPM_MSK >
102
103#define MFP_LPM_MSK		0xe1f0
104#define MFP_LPM_INPUT		0x0000
105#define MFP_LPM_DRIVE_LOW	0x2000
106#define MFP_LPM_DRIVE_HIGH	0x4100
107#define MFP_LPM_PULL_LOW	0x2080
108#define MFP_LPM_PULL_HIGH	0x4180
109#define MFP_LPM_FLOAT		0x0080
110
111#define MFP_LPM_EDGE_NONE	0x0000
112#define MFP_LPM_EDGE_RISE	0x0010
113#define MFP_LPM_EDGE_FALL	0x0020
114#define MFP_LPM_EDGE_BOTH	0x0030
115
116/ {
117	model = "Marvell PXA3xx familiy SoC";
118	compatible = "marvell,pxa3xx";
119
120	pxabus {
121		pdma: dma-controller@40000000 {
122			compatible = "marvell,pdma-1.0";
123			reg = <0x40000000 0x10000>;
124			interrupts = <25>;
125			#dma-channels = <32>;
126			#dma-cells = <2>;
127			#dma-requests = <100>;
128			status = "okay";
129		};
130
131		pwri2c: i2c@40f500c0 {
132			compatible = "mrvl,pwri2c";
133			reg = <0x40f500c0 0x30>;
134			interrupts = <6>;
135			clocks = <&clks CLK_PWRI2C>;
136			#address-cells = <0x1>;
137			#size-cells = <0>;
138			status = "disabled";
139		};
140
141		nand_controller: nand-controller@43100000 {
142			compatible = "marvell,pxa3xx-nand-controller";
143			reg = <0x43100000 90>;
144			interrupts = <45>;
145			clocks = <&clks CLK_NAND>;
146			clock-names = "core";
147			dmas = <&pdma 97 3>;
148			dma-names = "data";
149			#address-cells = <1>;
150			#size-cells = <0>;
151			status = "disabled";
152		};
153
154		pxairq: interrupt-controller@40d00000 {
155			marvell,intc-priority;
156			marvell,intc-nr-irqs = <56>;
157		};
158
159		pinctrl: pinctrl@40e10000 {
160			compatible = "pinconf-single";
161			reg = <0x40e10000 0xffff>;
162			#pinctrl-cells = <1>;
163			pinctrl-single,register-width = <32>;
164			pinctrl-single,function-mask = <0x7>;
165		};
166
167		gpio: gpio@40e00000 {
168			compatible = "intel,pxa3xx-gpio";
169			reg = <0x40e00000 0x10000>;
170			clocks = <&clks CLK_GPIO>;
171			gpio-ranges = <&pinctrl 0 0 128>;
172			interrupt-names = "gpio0", "gpio1", "gpio_mux";
173			interrupts = <8>, <9>, <10>;
174			gpio-controller;
175			#gpio-cells = <0x2>;
176			interrupt-controller;
177			#interrupt-cells = <0x2>;
178		};
179
180		mmc0: mmc@41100000 {
181			compatible = "marvell,pxa-mmc";
182			reg = <0x41100000 0x1000>;
183			interrupts = <23>;
184			clocks = <&clks CLK_MMC1>;
185			dmas = <&pdma 21 3
186				&pdma 22 3>;
187			dma-names = "rx", "tx";
188			status = "disabled";
189		};
190
191		mmc1: mmc@42000000 {
192			compatible = "marvell,pxa-mmc";
193			reg = <0x42000000 0x1000>;
194			interrupts = <41>;
195			clocks = <&clks CLK_MMC2>;
196			dmas = <&pdma 93 3
197				&pdma 94 3>;
198			dma-names = "rx", "tx";
199			status = "disabled";
200		};
201
202		mmc2: mmc@42500000 {
203			compatible = "marvell,pxa-mmc";
204			reg = <0x42500000 0x1000>;
205			interrupts = <55>;
206			clocks = <&clks CLK_MMC3>;
207			dmas = <&pdma 46 3
208				&pdma 47 3>;
209			dma-names = "rx", "tx";
210			status = "disabled";
211		};
212
213		usb0: usb@4c000000 {
214			compatible = "marvell,pxa-ohci";
215			reg = <0x4c000000 0x10000>;
216			interrupts = <3>;
217			clocks = <&clks CLK_USBH>;
218			status = "disabled";
219		};
220
221		pwm0: pwm@40b00000 {
222			compatible = "marvell,pxa270-pwm";
223			reg = <0x40b00000 0x10>;
224			#pwm-cells = <1>;
225			clocks = <&clks CLK_PWM0>;
226			status = "disabled";
227		};
228
229		pwm1: pwm@40b00010 {
230			compatible = "marvell,pxa270-pwm";
231			reg = <0x40b00010 0x10>;
232			#pwm-cells = <1>;
233			clocks = <&clks CLK_PWM1>;
234			status = "disabled";
235		};
236
237		pwm2: pwm@40c00000 {
238			compatible = "marvell,pxa270-pwm";
239			reg = <0x40c00000 0x10>;
240			#pwm-cells = <1>;
241			clocks = <&clks CLK_PWM0>;
242			status = "disabled";
243		};
244
245		pwm3: pwm@40c00010 {
246			compatible = "marvell,pxa270-pwm";
247			reg = <0x40c00010 0x10>;
248			#pwm-cells = <1>;
249			clocks = <&clks CLK_PWM1>;
250			status = "disabled";
251		};
252
253		ssp1: ssp@41000000 {
254			compatible = "mrvl,pxa3xx-ssp";
255			reg = <0x41000000 0x40>;
256			interrupts = <24>;
257			clocks = <&clks CLK_SSP1>;
258			status = "disabled";
259		};
260
261		ssp2: ssp@41700000 {
262			compatible = "mrvl,pxa3xx-ssp";
263			reg = <0x41700000 0x40>;
264			interrupts = <16>;
265			clocks = <&clks CLK_SSP2>;
266			status = "disabled";
267		};
268
269		ssp3: ssp@41900000 {
270			compatible = "mrvl,pxa3xx-ssp";
271			reg = <0x41900000 0x40>;
272			interrupts = <0>;
273			clocks = <&clks CLK_SSP3>;
274			status = "disabled";
275		};
276
277		ssp4: ssp@41a00000 {
278			compatible = "mrvl,pxa3xx-ssp";
279			reg = <0x41a00000 0x40>;
280			interrupts = <13>;
281			clocks = <&clks CLK_SSP4>;
282			status = "disabled";
283		};
284
285		timer@40a00000 {
286			compatible = "marvell,pxa-timer";
287			reg = <0x40a00000 0x20>;
288			interrupts = <26>;
289			clocks = <&clks CLK_OSTIMER>;
290			status = "okay";
291		};
292
293		gcu: display-controller@54000000 {
294			compatible = "marvell,pxa300-gcu";
295			reg = <0x54000000 0x1000>;
296			interrupts = <39>;
297			clocks = <&clks CLK_PXA300_GCU>;
298			status = "disabled";
299		};
300	};
301
302	clocks {
303	       /*
304		* The muxing of external clocks/internal dividers for osc* clock
305		* sources has been hidden under the carpet by now.
306		*/
307		#address-cells = <1>;
308		#size-cells = <1>;
309		ranges;
310
311		clks: clocks {
312			compatible = "marvell,pxa300-clocks";
313			#clock-cells = <1>;
314			status = "okay";
315		};
316	};
317};
318