1 // SPDX-License-Identifier: GPL-2.0-only
2 /* arch/sparc64/kernel/traps.c
3 *
4 * Copyright (C) 1995,1997,2008,2009,2012 David S. Miller (davem@davemloft.net)
5 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 /*
9 * I like traps on v9, :))))
10 */
11
12 #include <linux/extable.h>
13 #include <linux/sched/mm.h>
14 #include <linux/sched/debug.h>
15 #include <linux/linkage.h>
16 #include <linux/kernel.h>
17 #include <linux/signal.h>
18 #include <linux/smp.h>
19 #include <linux/mm.h>
20 #include <linux/init.h>
21 #include <linux/kallsyms.h>
22 #include <linux/kdebug.h>
23 #include <linux/ftrace.h>
24 #include <linux/reboot.h>
25 #include <linux/gfp.h>
26 #include <linux/context_tracking.h>
27
28 #include <asm/smp.h>
29 #include <asm/delay.h>
30 #include <asm/ptrace.h>
31 #include <asm/oplib.h>
32 #include <asm/page.h>
33 #include <asm/unistd.h>
34 #include <linux/uaccess.h>
35 #include <asm/fpumacro.h>
36 #include <asm/lsu.h>
37 #include <asm/dcu.h>
38 #include <asm/estate.h>
39 #include <asm/chafsr.h>
40 #include <asm/sfafsr.h>
41 #include <asm/psrcompat.h>
42 #include <asm/processor.h>
43 #include <asm/timer.h>
44 #include <asm/head.h>
45 #include <asm/prom.h>
46 #include <asm/memctrl.h>
47 #include <asm/cacheflush.h>
48 #include <asm/setup.h>
49
50 #include "entry.h"
51 #include "kernel.h"
52 #include "kstack.h"
53
54 /* When an irrecoverable trap occurs at tl > 0, the trap entry
55 * code logs the trap state registers at every level in the trap
56 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
57 * is as follows:
58 */
59 struct tl1_traplog {
60 struct {
61 unsigned long tstate;
62 unsigned long tpc;
63 unsigned long tnpc;
64 unsigned long tt;
65 } trapstack[4];
66 unsigned long tl;
67 };
68
dump_tl1_traplog(struct tl1_traplog * p)69 static void dump_tl1_traplog(struct tl1_traplog *p)
70 {
71 int i, limit;
72
73 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
74 "dumping track stack.\n", p->tl);
75
76 limit = (tlb_type == hypervisor) ? 2 : 4;
77 for (i = 0; i < limit; i++) {
78 printk(KERN_EMERG
79 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
80 "TNPC[%016lx] TT[%lx]\n",
81 i + 1,
82 p->trapstack[i].tstate, p->trapstack[i].tpc,
83 p->trapstack[i].tnpc, p->trapstack[i].tt);
84 printk("TRAPLOG: TPC<%pS>\n", (void *) p->trapstack[i].tpc);
85 }
86 }
87
bad_trap(struct pt_regs * regs,long lvl)88 void bad_trap(struct pt_regs *regs, long lvl)
89 {
90 char buffer[36];
91
92 if (notify_die(DIE_TRAP, "bad trap", regs,
93 0, lvl, SIGTRAP) == NOTIFY_STOP)
94 return;
95
96 if (lvl < 0x100) {
97 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
98 die_if_kernel(buffer, regs);
99 }
100
101 lvl -= 0x100;
102 if (regs->tstate & TSTATE_PRIV) {
103 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
104 die_if_kernel(buffer, regs);
105 }
106 if (test_thread_flag(TIF_32BIT)) {
107 regs->tpc &= 0xffffffff;
108 regs->tnpc &= 0xffffffff;
109 }
110 force_sig_fault(SIGILL, ILL_ILLTRP,
111 (void __user *)regs->tpc, lvl);
112 }
113
bad_trap_tl1(struct pt_regs * regs,long lvl)114 void bad_trap_tl1(struct pt_regs *regs, long lvl)
115 {
116 char buffer[36];
117
118 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
119 0, lvl, SIGTRAP) == NOTIFY_STOP)
120 return;
121
122 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
123
124 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
125 die_if_kernel (buffer, regs);
126 }
127
128 #ifdef CONFIG_DEBUG_BUGVERBOSE
do_BUG(const char * file,int line)129 void do_BUG(const char *file, int line)
130 {
131 bust_spinlocks(1);
132 printk("kernel BUG at %s:%d!\n", file, line);
133 }
134 EXPORT_SYMBOL(do_BUG);
135 #endif
136
137 static DEFINE_SPINLOCK(dimm_handler_lock);
138 static dimm_printer_t dimm_handler;
139
sprintf_dimm(int synd_code,unsigned long paddr,char * buf,int buflen)140 static int sprintf_dimm(int synd_code, unsigned long paddr, char *buf, int buflen)
141 {
142 unsigned long flags;
143 int ret = -ENODEV;
144
145 spin_lock_irqsave(&dimm_handler_lock, flags);
146 if (dimm_handler) {
147 ret = dimm_handler(synd_code, paddr, buf, buflen);
148 } else if (tlb_type == spitfire) {
149 if (prom_getunumber(synd_code, paddr, buf, buflen) == -1)
150 ret = -EINVAL;
151 else
152 ret = 0;
153 } else
154 ret = -ENODEV;
155 spin_unlock_irqrestore(&dimm_handler_lock, flags);
156
157 return ret;
158 }
159
register_dimm_printer(dimm_printer_t func)160 int register_dimm_printer(dimm_printer_t func)
161 {
162 unsigned long flags;
163 int ret = 0;
164
165 spin_lock_irqsave(&dimm_handler_lock, flags);
166 if (!dimm_handler)
167 dimm_handler = func;
168 else
169 ret = -EEXIST;
170 spin_unlock_irqrestore(&dimm_handler_lock, flags);
171
172 return ret;
173 }
174 EXPORT_SYMBOL_GPL(register_dimm_printer);
175
unregister_dimm_printer(dimm_printer_t func)176 void unregister_dimm_printer(dimm_printer_t func)
177 {
178 unsigned long flags;
179
180 spin_lock_irqsave(&dimm_handler_lock, flags);
181 if (dimm_handler == func)
182 dimm_handler = NULL;
183 spin_unlock_irqrestore(&dimm_handler_lock, flags);
184 }
185 EXPORT_SYMBOL_GPL(unregister_dimm_printer);
186
spitfire_insn_access_exception(struct pt_regs * regs,unsigned long sfsr,unsigned long sfar)187 void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
188 {
189 enum ctx_state prev_state = exception_enter();
190
191 if (notify_die(DIE_TRAP, "instruction access exception", regs,
192 0, 0x8, SIGTRAP) == NOTIFY_STOP)
193 goto out;
194
195 if (regs->tstate & TSTATE_PRIV) {
196 printk("spitfire_insn_access_exception: SFSR[%016lx] "
197 "SFAR[%016lx], going.\n", sfsr, sfar);
198 die_if_kernel("Iax", regs);
199 }
200 if (test_thread_flag(TIF_32BIT)) {
201 regs->tpc &= 0xffffffff;
202 regs->tnpc &= 0xffffffff;
203 }
204 force_sig_fault(SIGSEGV, SEGV_MAPERR,
205 (void __user *)regs->tpc, 0);
206 out:
207 exception_exit(prev_state);
208 }
209
spitfire_insn_access_exception_tl1(struct pt_regs * regs,unsigned long sfsr,unsigned long sfar)210 void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
211 {
212 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
213 0, 0x8, SIGTRAP) == NOTIFY_STOP)
214 return;
215
216 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
217 spitfire_insn_access_exception(regs, sfsr, sfar);
218 }
219
sun4v_insn_access_exception(struct pt_regs * regs,unsigned long addr,unsigned long type_ctx)220 void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
221 {
222 unsigned short type = (type_ctx >> 16);
223 unsigned short ctx = (type_ctx & 0xffff);
224
225 if (notify_die(DIE_TRAP, "instruction access exception", regs,
226 0, 0x8, SIGTRAP) == NOTIFY_STOP)
227 return;
228
229 if (regs->tstate & TSTATE_PRIV) {
230 printk("sun4v_insn_access_exception: ADDR[%016lx] "
231 "CTX[%04x] TYPE[%04x], going.\n",
232 addr, ctx, type);
233 die_if_kernel("Iax", regs);
234 }
235
236 if (test_thread_flag(TIF_32BIT)) {
237 regs->tpc &= 0xffffffff;
238 regs->tnpc &= 0xffffffff;
239 }
240 force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *) addr, 0);
241 }
242
sun4v_insn_access_exception_tl1(struct pt_regs * regs,unsigned long addr,unsigned long type_ctx)243 void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
244 {
245 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
246 0, 0x8, SIGTRAP) == NOTIFY_STOP)
247 return;
248
249 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
250 sun4v_insn_access_exception(regs, addr, type_ctx);
251 }
252
is_no_fault_exception(struct pt_regs * regs)253 bool is_no_fault_exception(struct pt_regs *regs)
254 {
255 unsigned char asi;
256 u32 insn;
257
258 if (get_user(insn, (u32 __user *)regs->tpc) == -EFAULT)
259 return false;
260
261 /*
262 * Must do a little instruction decoding here in order to
263 * decide on a course of action. The bits of interest are:
264 * insn[31:30] = op, where 3 indicates the load/store group
265 * insn[24:19] = op3, which identifies individual opcodes
266 * insn[13] indicates an immediate offset
267 * op3[4]=1 identifies alternate space instructions
268 * op3[5:4]=3 identifies floating point instructions
269 * op3[2]=1 identifies stores
270 * See "Opcode Maps" in the appendix of any Sparc V9
271 * architecture spec for full details.
272 */
273 if ((insn & 0xc0800000) == 0xc0800000) { /* op=3, op3[4]=1 */
274 if (insn & 0x2000) /* immediate offset */
275 asi = (regs->tstate >> 24); /* saved %asi */
276 else
277 asi = (insn >> 5); /* immediate asi */
278 if ((asi & 0xf6) == ASI_PNF) {
279 if (insn & 0x200000) /* op3[2], stores */
280 return false;
281 if (insn & 0x1000000) /* op3[5:4]=3 (fp) */
282 handle_ldf_stq(insn, regs);
283 else
284 handle_ld_nf(insn, regs);
285 return true;
286 }
287 }
288 return false;
289 }
290
spitfire_data_access_exception(struct pt_regs * regs,unsigned long sfsr,unsigned long sfar)291 void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
292 {
293 enum ctx_state prev_state = exception_enter();
294
295 if (notify_die(DIE_TRAP, "data access exception", regs,
296 0, 0x30, SIGTRAP) == NOTIFY_STOP)
297 goto out;
298
299 if (regs->tstate & TSTATE_PRIV) {
300 /* Test if this comes from uaccess places. */
301 const struct exception_table_entry *entry;
302
303 entry = search_exception_tables(regs->tpc);
304 if (entry) {
305 /* Ouch, somebody is trying VM hole tricks on us... */
306 #ifdef DEBUG_EXCEPTIONS
307 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
308 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
309 regs->tpc, entry->fixup);
310 #endif
311 regs->tpc = entry->fixup;
312 regs->tnpc = regs->tpc + 4;
313 goto out;
314 }
315 /* Shit... */
316 printk("spitfire_data_access_exception: SFSR[%016lx] "
317 "SFAR[%016lx], going.\n", sfsr, sfar);
318 die_if_kernel("Dax", regs);
319 }
320
321 if (is_no_fault_exception(regs))
322 return;
323
324 force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *)sfar, 0);
325 out:
326 exception_exit(prev_state);
327 }
328
spitfire_data_access_exception_tl1(struct pt_regs * regs,unsigned long sfsr,unsigned long sfar)329 void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
330 {
331 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
332 0, 0x30, SIGTRAP) == NOTIFY_STOP)
333 return;
334
335 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
336 spitfire_data_access_exception(regs, sfsr, sfar);
337 }
338
sun4v_data_access_exception(struct pt_regs * regs,unsigned long addr,unsigned long type_ctx)339 void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
340 {
341 unsigned short type = (type_ctx >> 16);
342 unsigned short ctx = (type_ctx & 0xffff);
343
344 if (notify_die(DIE_TRAP, "data access exception", regs,
345 0, 0x8, SIGTRAP) == NOTIFY_STOP)
346 return;
347
348 if (regs->tstate & TSTATE_PRIV) {
349 /* Test if this comes from uaccess places. */
350 const struct exception_table_entry *entry;
351
352 entry = search_exception_tables(regs->tpc);
353 if (entry) {
354 /* Ouch, somebody is trying VM hole tricks on us... */
355 #ifdef DEBUG_EXCEPTIONS
356 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
357 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
358 regs->tpc, entry->fixup);
359 #endif
360 regs->tpc = entry->fixup;
361 regs->tnpc = regs->tpc + 4;
362 return;
363 }
364 printk("sun4v_data_access_exception: ADDR[%016lx] "
365 "CTX[%04x] TYPE[%04x], going.\n",
366 addr, ctx, type);
367 die_if_kernel("Dax", regs);
368 }
369
370 if (test_thread_flag(TIF_32BIT)) {
371 regs->tpc &= 0xffffffff;
372 regs->tnpc &= 0xffffffff;
373 }
374 if (is_no_fault_exception(regs))
375 return;
376
377 /* MCD (Memory Corruption Detection) disabled trap (TT=0x19) in HV
378 * is vectored thorugh data access exception trap with fault type
379 * set to HV_FAULT_TYPE_MCD_DIS. Check for MCD disabled trap.
380 * Accessing an address with invalid ASI for the address, for
381 * example setting an ADI tag on an address with ASI_MCD_PRIMARY
382 * when TTE.mcd is not set for the VA, is also vectored into
383 * kerbel by HV as data access exception with fault type set to
384 * HV_FAULT_TYPE_INV_ASI.
385 */
386 switch (type) {
387 case HV_FAULT_TYPE_INV_ASI:
388 force_sig_fault(SIGILL, ILL_ILLADR, (void __user *)addr, 0);
389 break;
390 case HV_FAULT_TYPE_MCD_DIS:
391 force_sig_fault(SIGSEGV, SEGV_ACCADI, (void __user *)addr, 0);
392 break;
393 default:
394 force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *)addr, 0);
395 break;
396 }
397 }
398
sun4v_data_access_exception_tl1(struct pt_regs * regs,unsigned long addr,unsigned long type_ctx)399 void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
400 {
401 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
402 0, 0x8, SIGTRAP) == NOTIFY_STOP)
403 return;
404
405 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
406 sun4v_data_access_exception(regs, addr, type_ctx);
407 }
408
409 #ifdef CONFIG_PCI
410 #include "pci_impl.h"
411 #endif
412
413 /* When access exceptions happen, we must do this. */
spitfire_clean_and_reenable_l1_caches(void)414 static void spitfire_clean_and_reenable_l1_caches(void)
415 {
416 unsigned long va;
417
418 if (tlb_type != spitfire)
419 BUG();
420
421 /* Clean 'em. */
422 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
423 spitfire_put_icache_tag(va, 0x0);
424 spitfire_put_dcache_tag(va, 0x0);
425 }
426
427 /* Re-enable in LSU. */
428 __asm__ __volatile__("flush %%g6\n\t"
429 "membar #Sync\n\t"
430 "stxa %0, [%%g0] %1\n\t"
431 "membar #Sync"
432 : /* no outputs */
433 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
434 LSU_CONTROL_IM | LSU_CONTROL_DM),
435 "i" (ASI_LSU_CONTROL)
436 : "memory");
437 }
438
spitfire_enable_estate_errors(void)439 static void spitfire_enable_estate_errors(void)
440 {
441 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
442 "membar #Sync"
443 : /* no outputs */
444 : "r" (ESTATE_ERR_ALL),
445 "i" (ASI_ESTATE_ERROR_EN));
446 }
447
448 static char ecc_syndrome_table[] = {
449 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
450 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
451 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
452 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
453 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
454 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
455 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
456 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
457 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
458 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
459 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
460 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
461 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
462 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
463 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
464 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
465 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
466 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
467 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
468 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
469 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
470 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
471 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
472 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
473 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
474 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
475 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
476 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
477 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
478 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
479 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
480 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
481 };
482
483 static char *syndrome_unknown = "<Unknown>";
484
spitfire_log_udb_syndrome(unsigned long afar,unsigned long udbh,unsigned long udbl,unsigned long bit)485 static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
486 {
487 unsigned short scode;
488 char memmod_str[64], *p;
489
490 if (udbl & bit) {
491 scode = ecc_syndrome_table[udbl & 0xff];
492 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
493 p = syndrome_unknown;
494 else
495 p = memmod_str;
496 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
497 "Memory Module \"%s\"\n",
498 smp_processor_id(), scode, p);
499 }
500
501 if (udbh & bit) {
502 scode = ecc_syndrome_table[udbh & 0xff];
503 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
504 p = syndrome_unknown;
505 else
506 p = memmod_str;
507 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
508 "Memory Module \"%s\"\n",
509 smp_processor_id(), scode, p);
510 }
511
512 }
513
spitfire_cee_log(unsigned long afsr,unsigned long afar,unsigned long udbh,unsigned long udbl,int tl1,struct pt_regs * regs)514 static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
515 {
516
517 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
518 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
519 smp_processor_id(), afsr, afar, udbl, udbh, tl1);
520
521 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
522
523 /* We always log it, even if someone is listening for this
524 * trap.
525 */
526 notify_die(DIE_TRAP, "Correctable ECC Error", regs,
527 0, TRAP_TYPE_CEE, SIGTRAP);
528
529 /* The Correctable ECC Error trap does not disable I/D caches. So
530 * we only have to restore the ESTATE Error Enable register.
531 */
532 spitfire_enable_estate_errors();
533 }
534
spitfire_ue_log(unsigned long afsr,unsigned long afar,unsigned long udbh,unsigned long udbl,unsigned long tt,int tl1,struct pt_regs * regs)535 static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
536 {
537 printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
538 "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
539 smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
540
541 /* XXX add more human friendly logging of the error status
542 * XXX as is implemented for cheetah
543 */
544
545 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
546
547 /* We always log it, even if someone is listening for this
548 * trap.
549 */
550 notify_die(DIE_TRAP, "Uncorrectable Error", regs,
551 0, tt, SIGTRAP);
552
553 if (regs->tstate & TSTATE_PRIV) {
554 if (tl1)
555 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
556 die_if_kernel("UE", regs);
557 }
558
559 /* XXX need more intelligent processing here, such as is implemented
560 * XXX for cheetah errors, in fact if the E-cache still holds the
561 * XXX line with bad parity this will loop
562 */
563
564 spitfire_clean_and_reenable_l1_caches();
565 spitfire_enable_estate_errors();
566
567 if (test_thread_flag(TIF_32BIT)) {
568 regs->tpc &= 0xffffffff;
569 regs->tnpc &= 0xffffffff;
570 }
571 force_sig_fault(SIGBUS, BUS_OBJERR, (void *)0, 0);
572 }
573
spitfire_access_error(struct pt_regs * regs,unsigned long status_encoded,unsigned long afar)574 void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
575 {
576 unsigned long afsr, tt, udbh, udbl;
577 int tl1;
578
579 afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
580 tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
581 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
582 udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
583 udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
584
585 #ifdef CONFIG_PCI
586 if (tt == TRAP_TYPE_DAE &&
587 pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
588 spitfire_clean_and_reenable_l1_caches();
589 spitfire_enable_estate_errors();
590
591 pci_poke_faulted = 1;
592 regs->tnpc = regs->tpc + 4;
593 return;
594 }
595 #endif
596
597 if (afsr & SFAFSR_UE)
598 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
599
600 if (tt == TRAP_TYPE_CEE) {
601 /* Handle the case where we took a CEE trap, but ACK'd
602 * only the UE state in the UDB error registers.
603 */
604 if (afsr & SFAFSR_UE) {
605 if (udbh & UDBE_CE) {
606 __asm__ __volatile__(
607 "stxa %0, [%1] %2\n\t"
608 "membar #Sync"
609 : /* no outputs */
610 : "r" (udbh & UDBE_CE),
611 "r" (0x0), "i" (ASI_UDB_ERROR_W));
612 }
613 if (udbl & UDBE_CE) {
614 __asm__ __volatile__(
615 "stxa %0, [%1] %2\n\t"
616 "membar #Sync"
617 : /* no outputs */
618 : "r" (udbl & UDBE_CE),
619 "r" (0x18), "i" (ASI_UDB_ERROR_W));
620 }
621 }
622
623 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
624 }
625 }
626
627 int cheetah_pcache_forced_on;
628
cheetah_enable_pcache(void)629 void cheetah_enable_pcache(void)
630 {
631 unsigned long dcr;
632
633 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
634 smp_processor_id());
635
636 __asm__ __volatile__("ldxa [%%g0] %1, %0"
637 : "=r" (dcr)
638 : "i" (ASI_DCU_CONTROL_REG));
639 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
640 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
641 "membar #Sync"
642 : /* no outputs */
643 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
644 }
645
646 /* Cheetah error trap handling. */
647 static unsigned long ecache_flush_physbase;
648 static unsigned long ecache_flush_linesize;
649 static unsigned long ecache_flush_size;
650
651 /* This table is ordered in priority of errors and matches the
652 * AFAR overwrite policy as well.
653 */
654
655 struct afsr_error_table {
656 unsigned long mask;
657 const char *name;
658 };
659
660 static const char CHAFSR_PERR_msg[] =
661 "System interface protocol error";
662 static const char CHAFSR_IERR_msg[] =
663 "Internal processor error";
664 static const char CHAFSR_ISAP_msg[] =
665 "System request parity error on incoming address";
666 static const char CHAFSR_UCU_msg[] =
667 "Uncorrectable E-cache ECC error for ifetch/data";
668 static const char CHAFSR_UCC_msg[] =
669 "SW Correctable E-cache ECC error for ifetch/data";
670 static const char CHAFSR_UE_msg[] =
671 "Uncorrectable system bus data ECC error for read";
672 static const char CHAFSR_EDU_msg[] =
673 "Uncorrectable E-cache ECC error for stmerge/blkld";
674 static const char CHAFSR_EMU_msg[] =
675 "Uncorrectable system bus MTAG error";
676 static const char CHAFSR_WDU_msg[] =
677 "Uncorrectable E-cache ECC error for writeback";
678 static const char CHAFSR_CPU_msg[] =
679 "Uncorrectable ECC error for copyout";
680 static const char CHAFSR_CE_msg[] =
681 "HW corrected system bus data ECC error for read";
682 static const char CHAFSR_EDC_msg[] =
683 "HW corrected E-cache ECC error for stmerge/blkld";
684 static const char CHAFSR_EMC_msg[] =
685 "HW corrected system bus MTAG ECC error";
686 static const char CHAFSR_WDC_msg[] =
687 "HW corrected E-cache ECC error for writeback";
688 static const char CHAFSR_CPC_msg[] =
689 "HW corrected ECC error for copyout";
690 static const char CHAFSR_TO_msg[] =
691 "Unmapped error from system bus";
692 static const char CHAFSR_BERR_msg[] =
693 "Bus error response from system bus";
694 static const char CHAFSR_IVC_msg[] =
695 "HW corrected system bus data ECC error for ivec read";
696 static const char CHAFSR_IVU_msg[] =
697 "Uncorrectable system bus data ECC error for ivec read";
698 static struct afsr_error_table __cheetah_error_table[] = {
699 { CHAFSR_PERR, CHAFSR_PERR_msg },
700 { CHAFSR_IERR, CHAFSR_IERR_msg },
701 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
702 { CHAFSR_UCU, CHAFSR_UCU_msg },
703 { CHAFSR_UCC, CHAFSR_UCC_msg },
704 { CHAFSR_UE, CHAFSR_UE_msg },
705 { CHAFSR_EDU, CHAFSR_EDU_msg },
706 { CHAFSR_EMU, CHAFSR_EMU_msg },
707 { CHAFSR_WDU, CHAFSR_WDU_msg },
708 { CHAFSR_CPU, CHAFSR_CPU_msg },
709 { CHAFSR_CE, CHAFSR_CE_msg },
710 { CHAFSR_EDC, CHAFSR_EDC_msg },
711 { CHAFSR_EMC, CHAFSR_EMC_msg },
712 { CHAFSR_WDC, CHAFSR_WDC_msg },
713 { CHAFSR_CPC, CHAFSR_CPC_msg },
714 { CHAFSR_TO, CHAFSR_TO_msg },
715 { CHAFSR_BERR, CHAFSR_BERR_msg },
716 /* These two do not update the AFAR. */
717 { CHAFSR_IVC, CHAFSR_IVC_msg },
718 { CHAFSR_IVU, CHAFSR_IVU_msg },
719 { 0, NULL },
720 };
721 static const char CHPAFSR_DTO_msg[] =
722 "System bus unmapped error for prefetch/storequeue-read";
723 static const char CHPAFSR_DBERR_msg[] =
724 "System bus error for prefetch/storequeue-read";
725 static const char CHPAFSR_THCE_msg[] =
726 "Hardware corrected E-cache Tag ECC error";
727 static const char CHPAFSR_TSCE_msg[] =
728 "SW handled correctable E-cache Tag ECC error";
729 static const char CHPAFSR_TUE_msg[] =
730 "Uncorrectable E-cache Tag ECC error";
731 static const char CHPAFSR_DUE_msg[] =
732 "System bus uncorrectable data ECC error due to prefetch/store-fill";
733 static struct afsr_error_table __cheetah_plus_error_table[] = {
734 { CHAFSR_PERR, CHAFSR_PERR_msg },
735 { CHAFSR_IERR, CHAFSR_IERR_msg },
736 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
737 { CHAFSR_UCU, CHAFSR_UCU_msg },
738 { CHAFSR_UCC, CHAFSR_UCC_msg },
739 { CHAFSR_UE, CHAFSR_UE_msg },
740 { CHAFSR_EDU, CHAFSR_EDU_msg },
741 { CHAFSR_EMU, CHAFSR_EMU_msg },
742 { CHAFSR_WDU, CHAFSR_WDU_msg },
743 { CHAFSR_CPU, CHAFSR_CPU_msg },
744 { CHAFSR_CE, CHAFSR_CE_msg },
745 { CHAFSR_EDC, CHAFSR_EDC_msg },
746 { CHAFSR_EMC, CHAFSR_EMC_msg },
747 { CHAFSR_WDC, CHAFSR_WDC_msg },
748 { CHAFSR_CPC, CHAFSR_CPC_msg },
749 { CHAFSR_TO, CHAFSR_TO_msg },
750 { CHAFSR_BERR, CHAFSR_BERR_msg },
751 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
752 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
753 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
754 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
755 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
756 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
757 /* These two do not update the AFAR. */
758 { CHAFSR_IVC, CHAFSR_IVC_msg },
759 { CHAFSR_IVU, CHAFSR_IVU_msg },
760 { 0, NULL },
761 };
762 static const char JPAFSR_JETO_msg[] =
763 "System interface protocol error, hw timeout caused";
764 static const char JPAFSR_SCE_msg[] =
765 "Parity error on system snoop results";
766 static const char JPAFSR_JEIC_msg[] =
767 "System interface protocol error, illegal command detected";
768 static const char JPAFSR_JEIT_msg[] =
769 "System interface protocol error, illegal ADTYPE detected";
770 static const char JPAFSR_OM_msg[] =
771 "Out of range memory error has occurred";
772 static const char JPAFSR_ETP_msg[] =
773 "Parity error on L2 cache tag SRAM";
774 static const char JPAFSR_UMS_msg[] =
775 "Error due to unsupported store";
776 static const char JPAFSR_RUE_msg[] =
777 "Uncorrectable ECC error from remote cache/memory";
778 static const char JPAFSR_RCE_msg[] =
779 "Correctable ECC error from remote cache/memory";
780 static const char JPAFSR_BP_msg[] =
781 "JBUS parity error on returned read data";
782 static const char JPAFSR_WBP_msg[] =
783 "JBUS parity error on data for writeback or block store";
784 static const char JPAFSR_FRC_msg[] =
785 "Foreign read to DRAM incurring correctable ECC error";
786 static const char JPAFSR_FRU_msg[] =
787 "Foreign read to DRAM incurring uncorrectable ECC error";
788 static struct afsr_error_table __jalapeno_error_table[] = {
789 { JPAFSR_JETO, JPAFSR_JETO_msg },
790 { JPAFSR_SCE, JPAFSR_SCE_msg },
791 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
792 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
793 { CHAFSR_PERR, CHAFSR_PERR_msg },
794 { CHAFSR_IERR, CHAFSR_IERR_msg },
795 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
796 { CHAFSR_UCU, CHAFSR_UCU_msg },
797 { CHAFSR_UCC, CHAFSR_UCC_msg },
798 { CHAFSR_UE, CHAFSR_UE_msg },
799 { CHAFSR_EDU, CHAFSR_EDU_msg },
800 { JPAFSR_OM, JPAFSR_OM_msg },
801 { CHAFSR_WDU, CHAFSR_WDU_msg },
802 { CHAFSR_CPU, CHAFSR_CPU_msg },
803 { CHAFSR_CE, CHAFSR_CE_msg },
804 { CHAFSR_EDC, CHAFSR_EDC_msg },
805 { JPAFSR_ETP, JPAFSR_ETP_msg },
806 { CHAFSR_WDC, CHAFSR_WDC_msg },
807 { CHAFSR_CPC, CHAFSR_CPC_msg },
808 { CHAFSR_TO, CHAFSR_TO_msg },
809 { CHAFSR_BERR, CHAFSR_BERR_msg },
810 { JPAFSR_UMS, JPAFSR_UMS_msg },
811 { JPAFSR_RUE, JPAFSR_RUE_msg },
812 { JPAFSR_RCE, JPAFSR_RCE_msg },
813 { JPAFSR_BP, JPAFSR_BP_msg },
814 { JPAFSR_WBP, JPAFSR_WBP_msg },
815 { JPAFSR_FRC, JPAFSR_FRC_msg },
816 { JPAFSR_FRU, JPAFSR_FRU_msg },
817 /* These two do not update the AFAR. */
818 { CHAFSR_IVU, CHAFSR_IVU_msg },
819 { 0, NULL },
820 };
821 static struct afsr_error_table *cheetah_error_table;
822 static unsigned long cheetah_afsr_errors;
823
824 struct cheetah_err_info *cheetah_error_log;
825
cheetah_get_error_log(unsigned long afsr)826 static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
827 {
828 struct cheetah_err_info *p;
829 int cpu = smp_processor_id();
830
831 if (!cheetah_error_log)
832 return NULL;
833
834 p = cheetah_error_log + (cpu * 2);
835 if ((afsr & CHAFSR_TL1) != 0UL)
836 p++;
837
838 return p;
839 }
840
841 extern unsigned int tl0_icpe[], tl1_icpe[];
842 extern unsigned int tl0_dcpe[], tl1_dcpe[];
843 extern unsigned int tl0_fecc[], tl1_fecc[];
844 extern unsigned int tl0_cee[], tl1_cee[];
845 extern unsigned int tl0_iae[], tl1_iae[];
846 extern unsigned int tl0_dae[], tl1_dae[];
847 extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
848 extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
849 extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
850 extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
851 extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
852
cheetah_ecache_flush_init(void)853 void __init cheetah_ecache_flush_init(void)
854 {
855 unsigned long largest_size, smallest_linesize, order, ver;
856 int i, sz;
857
858 /* Scan all cpu device tree nodes, note two values:
859 * 1) largest E-cache size
860 * 2) smallest E-cache line size
861 */
862 largest_size = 0UL;
863 smallest_linesize = ~0UL;
864
865 for (i = 0; i < NR_CPUS; i++) {
866 unsigned long val;
867
868 val = cpu_data(i).ecache_size;
869 if (!val)
870 continue;
871
872 if (val > largest_size)
873 largest_size = val;
874
875 val = cpu_data(i).ecache_line_size;
876 if (val < smallest_linesize)
877 smallest_linesize = val;
878
879 }
880
881 if (largest_size == 0UL || smallest_linesize == ~0UL) {
882 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
883 "parameters.\n");
884 prom_halt();
885 }
886
887 ecache_flush_size = (2 * largest_size);
888 ecache_flush_linesize = smallest_linesize;
889
890 ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
891
892 if (ecache_flush_physbase == ~0UL) {
893 prom_printf("cheetah_ecache_flush_init: Cannot find %ld byte "
894 "contiguous physical memory.\n",
895 ecache_flush_size);
896 prom_halt();
897 }
898
899 /* Now allocate error trap reporting scoreboard. */
900 sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
901 for (order = 0; order < MAX_ORDER; order++) {
902 if ((PAGE_SIZE << order) >= sz)
903 break;
904 }
905 cheetah_error_log = (struct cheetah_err_info *)
906 __get_free_pages(GFP_KERNEL, order);
907 if (!cheetah_error_log) {
908 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
909 "error logging scoreboard (%d bytes).\n", sz);
910 prom_halt();
911 }
912 memset(cheetah_error_log, 0, PAGE_SIZE << order);
913
914 /* Mark all AFSRs as invalid so that the trap handler will
915 * log new new information there.
916 */
917 for (i = 0; i < 2 * NR_CPUS; i++)
918 cheetah_error_log[i].afsr = CHAFSR_INVALID;
919
920 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
921 if ((ver >> 32) == __JALAPENO_ID ||
922 (ver >> 32) == __SERRANO_ID) {
923 cheetah_error_table = &__jalapeno_error_table[0];
924 cheetah_afsr_errors = JPAFSR_ERRORS;
925 } else if ((ver >> 32) == 0x003e0015) {
926 cheetah_error_table = &__cheetah_plus_error_table[0];
927 cheetah_afsr_errors = CHPAFSR_ERRORS;
928 } else {
929 cheetah_error_table = &__cheetah_error_table[0];
930 cheetah_afsr_errors = CHAFSR_ERRORS;
931 }
932
933 /* Now patch trap tables. */
934 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
935 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
936 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
937 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
938 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
939 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
940 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
941 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
942 if (tlb_type == cheetah_plus) {
943 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
944 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
945 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
946 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
947 }
948 flushi(PAGE_OFFSET);
949 }
950
cheetah_flush_ecache(void)951 static void cheetah_flush_ecache(void)
952 {
953 unsigned long flush_base = ecache_flush_physbase;
954 unsigned long flush_linesize = ecache_flush_linesize;
955 unsigned long flush_size = ecache_flush_size;
956
957 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
958 " bne,pt %%xcc, 1b\n\t"
959 " ldxa [%2 + %0] %3, %%g0\n\t"
960 : "=&r" (flush_size)
961 : "0" (flush_size), "r" (flush_base),
962 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
963 }
964
cheetah_flush_ecache_line(unsigned long physaddr)965 static void cheetah_flush_ecache_line(unsigned long physaddr)
966 {
967 unsigned long alias;
968
969 physaddr &= ~(8UL - 1UL);
970 physaddr = (ecache_flush_physbase +
971 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
972 alias = physaddr + (ecache_flush_size >> 1UL);
973 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
974 "ldxa [%1] %2, %%g0\n\t"
975 "membar #Sync"
976 : /* no outputs */
977 : "r" (physaddr), "r" (alias),
978 "i" (ASI_PHYS_USE_EC));
979 }
980
981 /* Unfortunately, the diagnostic access to the I-cache tags we need to
982 * use to clear the thing interferes with I-cache coherency transactions.
983 *
984 * So we must only flush the I-cache when it is disabled.
985 */
__cheetah_flush_icache(void)986 static void __cheetah_flush_icache(void)
987 {
988 unsigned int icache_size, icache_line_size;
989 unsigned long addr;
990
991 icache_size = local_cpu_data().icache_size;
992 icache_line_size = local_cpu_data().icache_line_size;
993
994 /* Clear the valid bits in all the tags. */
995 for (addr = 0; addr < icache_size; addr += icache_line_size) {
996 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
997 "membar #Sync"
998 : /* no outputs */
999 : "r" (addr | (2 << 3)),
1000 "i" (ASI_IC_TAG));
1001 }
1002 }
1003
cheetah_flush_icache(void)1004 static void cheetah_flush_icache(void)
1005 {
1006 unsigned long dcu_save;
1007
1008 /* Save current DCU, disable I-cache. */
1009 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1010 "or %0, %2, %%g1\n\t"
1011 "stxa %%g1, [%%g0] %1\n\t"
1012 "membar #Sync"
1013 : "=r" (dcu_save)
1014 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
1015 : "g1");
1016
1017 __cheetah_flush_icache();
1018
1019 /* Restore DCU register */
1020 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1021 "membar #Sync"
1022 : /* no outputs */
1023 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
1024 }
1025
cheetah_flush_dcache(void)1026 static void cheetah_flush_dcache(void)
1027 {
1028 unsigned int dcache_size, dcache_line_size;
1029 unsigned long addr;
1030
1031 dcache_size = local_cpu_data().dcache_size;
1032 dcache_line_size = local_cpu_data().dcache_line_size;
1033
1034 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1035 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1036 "membar #Sync"
1037 : /* no outputs */
1038 : "r" (addr), "i" (ASI_DCACHE_TAG));
1039 }
1040 }
1041
1042 /* In order to make the even parity correct we must do two things.
1043 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
1044 * Next, we clear out all 32-bytes of data for that line. Data of
1045 * all-zero + tag parity value of zero == correct parity.
1046 */
cheetah_plus_zap_dcache_parity(void)1047 static void cheetah_plus_zap_dcache_parity(void)
1048 {
1049 unsigned int dcache_size, dcache_line_size;
1050 unsigned long addr;
1051
1052 dcache_size = local_cpu_data().dcache_size;
1053 dcache_line_size = local_cpu_data().dcache_line_size;
1054
1055 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1056 unsigned long tag = (addr >> 14);
1057 unsigned long line;
1058
1059 __asm__ __volatile__("membar #Sync\n\t"
1060 "stxa %0, [%1] %2\n\t"
1061 "membar #Sync"
1062 : /* no outputs */
1063 : "r" (tag), "r" (addr),
1064 "i" (ASI_DCACHE_UTAG));
1065 for (line = addr; line < addr + dcache_line_size; line += 8)
1066 __asm__ __volatile__("membar #Sync\n\t"
1067 "stxa %%g0, [%0] %1\n\t"
1068 "membar #Sync"
1069 : /* no outputs */
1070 : "r" (line),
1071 "i" (ASI_DCACHE_DATA));
1072 }
1073 }
1074
1075 /* Conversion tables used to frob Cheetah AFSR syndrome values into
1076 * something palatable to the memory controller driver get_unumber
1077 * routine.
1078 */
1079 #define MT0 137
1080 #define MT1 138
1081 #define MT2 139
1082 #define NONE 254
1083 #define MTC0 140
1084 #define MTC1 141
1085 #define MTC2 142
1086 #define MTC3 143
1087 #define C0 128
1088 #define C1 129
1089 #define C2 130
1090 #define C3 131
1091 #define C4 132
1092 #define C5 133
1093 #define C6 134
1094 #define C7 135
1095 #define C8 136
1096 #define M2 144
1097 #define M3 145
1098 #define M4 146
1099 #define M 147
1100 static unsigned char cheetah_ecc_syntab[] = {
1101 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1102 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1103 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1104 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1105 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1106 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1107 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1108 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1109 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1110 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1111 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1112 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1113 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1114 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1115 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1116 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1117 /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1118 /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1119 /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1120 /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1121 /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1122 /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1123 /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1124 /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1125 /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1126 /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1127 /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1128 /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1129 /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1130 /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1131 /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1132 /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1133 };
1134 static unsigned char cheetah_mtag_syntab[] = {
1135 NONE, MTC0,
1136 MTC1, NONE,
1137 MTC2, NONE,
1138 NONE, MT0,
1139 MTC3, NONE,
1140 NONE, MT1,
1141 NONE, MT2,
1142 NONE, NONE
1143 };
1144
1145 /* Return the highest priority error conditon mentioned. */
cheetah_get_hipri(unsigned long afsr)1146 static inline unsigned long cheetah_get_hipri(unsigned long afsr)
1147 {
1148 unsigned long tmp = 0;
1149 int i;
1150
1151 for (i = 0; cheetah_error_table[i].mask; i++) {
1152 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1153 return tmp;
1154 }
1155 return tmp;
1156 }
1157
cheetah_get_string(unsigned long bit)1158 static const char *cheetah_get_string(unsigned long bit)
1159 {
1160 int i;
1161
1162 for (i = 0; cheetah_error_table[i].mask; i++) {
1163 if ((bit & cheetah_error_table[i].mask) != 0UL)
1164 return cheetah_error_table[i].name;
1165 }
1166 return "???";
1167 }
1168
cheetah_log_errors(struct pt_regs * regs,struct cheetah_err_info * info,unsigned long afsr,unsigned long afar,int recoverable)1169 static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1170 unsigned long afsr, unsigned long afar, int recoverable)
1171 {
1172 unsigned long hipri;
1173 char unum[256];
1174
1175 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1176 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1177 afsr, afar,
1178 (afsr & CHAFSR_TL1) ? 1 : 0);
1179 printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1180 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1181 regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
1182 printk("%s" "ERROR(%d): ",
1183 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
1184 printk("TPC<%pS>\n", (void *) regs->tpc);
1185 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1186 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1187 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1188 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1189 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1190 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1191 hipri = cheetah_get_hipri(afsr);
1192 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1193 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1194 hipri, cheetah_get_string(hipri));
1195
1196 /* Try to get unumber if relevant. */
1197 #define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1198 CHAFSR_CPC | CHAFSR_CPU | \
1199 CHAFSR_UE | CHAFSR_CE | \
1200 CHAFSR_EDC | CHAFSR_EDU | \
1201 CHAFSR_UCC | CHAFSR_UCU | \
1202 CHAFSR_WDU | CHAFSR_WDC)
1203 #define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1204 if (afsr & ESYND_ERRORS) {
1205 int syndrome;
1206 int ret;
1207
1208 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1209 syndrome = cheetah_ecc_syntab[syndrome];
1210 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1211 if (ret != -1)
1212 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1213 (recoverable ? KERN_WARNING : KERN_CRIT),
1214 smp_processor_id(), unum);
1215 } else if (afsr & MSYND_ERRORS) {
1216 int syndrome;
1217 int ret;
1218
1219 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1220 syndrome = cheetah_mtag_syntab[syndrome];
1221 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1222 if (ret != -1)
1223 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1224 (recoverable ? KERN_WARNING : KERN_CRIT),
1225 smp_processor_id(), unum);
1226 }
1227
1228 /* Now dump the cache snapshots. */
1229 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx]\n",
1230 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1231 (int) info->dcache_index,
1232 info->dcache_tag,
1233 info->dcache_utag,
1234 info->dcache_stag);
1235 printk("%s" "ERROR(%d): D-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1236 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1237 info->dcache_data[0],
1238 info->dcache_data[1],
1239 info->dcache_data[2],
1240 info->dcache_data[3]);
1241 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx] "
1242 "u[%016llx] l[%016llx]\n",
1243 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1244 (int) info->icache_index,
1245 info->icache_tag,
1246 info->icache_utag,
1247 info->icache_stag,
1248 info->icache_upper,
1249 info->icache_lower);
1250 printk("%s" "ERROR(%d): I-cache INSN0[%016llx] INSN1[%016llx] INSN2[%016llx] INSN3[%016llx]\n",
1251 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1252 info->icache_data[0],
1253 info->icache_data[1],
1254 info->icache_data[2],
1255 info->icache_data[3]);
1256 printk("%s" "ERROR(%d): I-cache INSN4[%016llx] INSN5[%016llx] INSN6[%016llx] INSN7[%016llx]\n",
1257 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1258 info->icache_data[4],
1259 info->icache_data[5],
1260 info->icache_data[6],
1261 info->icache_data[7]);
1262 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016llx]\n",
1263 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1264 (int) info->ecache_index, info->ecache_tag);
1265 printk("%s" "ERROR(%d): E-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1266 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1267 info->ecache_data[0],
1268 info->ecache_data[1],
1269 info->ecache_data[2],
1270 info->ecache_data[3]);
1271
1272 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1273 while (afsr != 0UL) {
1274 unsigned long bit = cheetah_get_hipri(afsr);
1275
1276 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1277 (recoverable ? KERN_WARNING : KERN_CRIT),
1278 bit, cheetah_get_string(bit));
1279
1280 afsr &= ~bit;
1281 }
1282
1283 if (!recoverable)
1284 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1285 }
1286
cheetah_recheck_errors(struct cheetah_err_info * logp)1287 static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1288 {
1289 unsigned long afsr, afar;
1290 int ret = 0;
1291
1292 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1293 : "=r" (afsr)
1294 : "i" (ASI_AFSR));
1295 if ((afsr & cheetah_afsr_errors) != 0) {
1296 if (logp != NULL) {
1297 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1298 : "=r" (afar)
1299 : "i" (ASI_AFAR));
1300 logp->afsr = afsr;
1301 logp->afar = afar;
1302 }
1303 ret = 1;
1304 }
1305 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1306 "membar #Sync\n\t"
1307 : : "r" (afsr), "i" (ASI_AFSR));
1308
1309 return ret;
1310 }
1311
cheetah_fecc_handler(struct pt_regs * regs,unsigned long afsr,unsigned long afar)1312 void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1313 {
1314 struct cheetah_err_info local_snapshot, *p;
1315 int recoverable;
1316
1317 /* Flush E-cache */
1318 cheetah_flush_ecache();
1319
1320 p = cheetah_get_error_log(afsr);
1321 if (!p) {
1322 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1323 afsr, afar);
1324 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1325 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1326 prom_halt();
1327 }
1328
1329 /* Grab snapshot of logged error. */
1330 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1331
1332 /* If the current trap snapshot does not match what the
1333 * trap handler passed along into our args, big trouble.
1334 * In such a case, mark the local copy as invalid.
1335 *
1336 * Else, it matches and we mark the afsr in the non-local
1337 * copy as invalid so we may log new error traps there.
1338 */
1339 if (p->afsr != afsr || p->afar != afar)
1340 local_snapshot.afsr = CHAFSR_INVALID;
1341 else
1342 p->afsr = CHAFSR_INVALID;
1343
1344 cheetah_flush_icache();
1345 cheetah_flush_dcache();
1346
1347 /* Re-enable I-cache/D-cache */
1348 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1349 "or %%g1, %1, %%g1\n\t"
1350 "stxa %%g1, [%%g0] %0\n\t"
1351 "membar #Sync"
1352 : /* no outputs */
1353 : "i" (ASI_DCU_CONTROL_REG),
1354 "i" (DCU_DC | DCU_IC)
1355 : "g1");
1356
1357 /* Re-enable error reporting */
1358 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1359 "or %%g1, %1, %%g1\n\t"
1360 "stxa %%g1, [%%g0] %0\n\t"
1361 "membar #Sync"
1362 : /* no outputs */
1363 : "i" (ASI_ESTATE_ERROR_EN),
1364 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1365 : "g1");
1366
1367 /* Decide if we can continue after handling this trap and
1368 * logging the error.
1369 */
1370 recoverable = 1;
1371 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1372 recoverable = 0;
1373
1374 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1375 * error was logged while we had error reporting traps disabled.
1376 */
1377 if (cheetah_recheck_errors(&local_snapshot)) {
1378 unsigned long new_afsr = local_snapshot.afsr;
1379
1380 /* If we got a new asynchronous error, die... */
1381 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1382 CHAFSR_WDU | CHAFSR_CPU |
1383 CHAFSR_IVU | CHAFSR_UE |
1384 CHAFSR_BERR | CHAFSR_TO))
1385 recoverable = 0;
1386 }
1387
1388 /* Log errors. */
1389 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1390
1391 if (!recoverable)
1392 panic("Irrecoverable Fast-ECC error trap.\n");
1393
1394 /* Flush E-cache to kick the error trap handlers out. */
1395 cheetah_flush_ecache();
1396 }
1397
1398 /* Try to fix a correctable error by pushing the line out from
1399 * the E-cache. Recheck error reporting registers to see if the
1400 * problem is intermittent.
1401 */
cheetah_fix_ce(unsigned long physaddr)1402 static int cheetah_fix_ce(unsigned long physaddr)
1403 {
1404 unsigned long orig_estate;
1405 unsigned long alias1, alias2;
1406 int ret;
1407
1408 /* Make sure correctable error traps are disabled. */
1409 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1410 "andn %0, %1, %%g1\n\t"
1411 "stxa %%g1, [%%g0] %2\n\t"
1412 "membar #Sync"
1413 : "=&r" (orig_estate)
1414 : "i" (ESTATE_ERROR_CEEN),
1415 "i" (ASI_ESTATE_ERROR_EN)
1416 : "g1");
1417
1418 /* We calculate alias addresses that will force the
1419 * cache line in question out of the E-cache. Then
1420 * we bring it back in with an atomic instruction so
1421 * that we get it in some modified/exclusive state,
1422 * then we displace it again to try and get proper ECC
1423 * pushed back into the system.
1424 */
1425 physaddr &= ~(8UL - 1UL);
1426 alias1 = (ecache_flush_physbase +
1427 (physaddr & ((ecache_flush_size >> 1) - 1)));
1428 alias2 = alias1 + (ecache_flush_size >> 1);
1429 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1430 "ldxa [%1] %3, %%g0\n\t"
1431 "casxa [%2] %3, %%g0, %%g0\n\t"
1432 "ldxa [%0] %3, %%g0\n\t"
1433 "ldxa [%1] %3, %%g0\n\t"
1434 "membar #Sync"
1435 : /* no outputs */
1436 : "r" (alias1), "r" (alias2),
1437 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1438
1439 /* Did that trigger another error? */
1440 if (cheetah_recheck_errors(NULL)) {
1441 /* Try one more time. */
1442 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1443 "membar #Sync"
1444 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1445 if (cheetah_recheck_errors(NULL))
1446 ret = 2;
1447 else
1448 ret = 1;
1449 } else {
1450 /* No new error, intermittent problem. */
1451 ret = 0;
1452 }
1453
1454 /* Restore error enables. */
1455 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1456 "membar #Sync"
1457 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1458
1459 return ret;
1460 }
1461
1462 /* Return non-zero if PADDR is a valid physical memory address. */
cheetah_check_main_memory(unsigned long paddr)1463 static int cheetah_check_main_memory(unsigned long paddr)
1464 {
1465 unsigned long vaddr = PAGE_OFFSET + paddr;
1466
1467 if (vaddr > (unsigned long) high_memory)
1468 return 0;
1469
1470 return kern_addr_valid(vaddr);
1471 }
1472
cheetah_cee_handler(struct pt_regs * regs,unsigned long afsr,unsigned long afar)1473 void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1474 {
1475 struct cheetah_err_info local_snapshot, *p;
1476 int recoverable, is_memory;
1477
1478 p = cheetah_get_error_log(afsr);
1479 if (!p) {
1480 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1481 afsr, afar);
1482 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1483 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1484 prom_halt();
1485 }
1486
1487 /* Grab snapshot of logged error. */
1488 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1489
1490 /* If the current trap snapshot does not match what the
1491 * trap handler passed along into our args, big trouble.
1492 * In such a case, mark the local copy as invalid.
1493 *
1494 * Else, it matches and we mark the afsr in the non-local
1495 * copy as invalid so we may log new error traps there.
1496 */
1497 if (p->afsr != afsr || p->afar != afar)
1498 local_snapshot.afsr = CHAFSR_INVALID;
1499 else
1500 p->afsr = CHAFSR_INVALID;
1501
1502 is_memory = cheetah_check_main_memory(afar);
1503
1504 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1505 /* XXX Might want to log the results of this operation
1506 * XXX somewhere... -DaveM
1507 */
1508 cheetah_fix_ce(afar);
1509 }
1510
1511 {
1512 int flush_all, flush_line;
1513
1514 flush_all = flush_line = 0;
1515 if ((afsr & CHAFSR_EDC) != 0UL) {
1516 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1517 flush_line = 1;
1518 else
1519 flush_all = 1;
1520 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1521 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1522 flush_line = 1;
1523 else
1524 flush_all = 1;
1525 }
1526
1527 /* Trap handler only disabled I-cache, flush it. */
1528 cheetah_flush_icache();
1529
1530 /* Re-enable I-cache */
1531 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1532 "or %%g1, %1, %%g1\n\t"
1533 "stxa %%g1, [%%g0] %0\n\t"
1534 "membar #Sync"
1535 : /* no outputs */
1536 : "i" (ASI_DCU_CONTROL_REG),
1537 "i" (DCU_IC)
1538 : "g1");
1539
1540 if (flush_all)
1541 cheetah_flush_ecache();
1542 else if (flush_line)
1543 cheetah_flush_ecache_line(afar);
1544 }
1545
1546 /* Re-enable error reporting */
1547 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1548 "or %%g1, %1, %%g1\n\t"
1549 "stxa %%g1, [%%g0] %0\n\t"
1550 "membar #Sync"
1551 : /* no outputs */
1552 : "i" (ASI_ESTATE_ERROR_EN),
1553 "i" (ESTATE_ERROR_CEEN)
1554 : "g1");
1555
1556 /* Decide if we can continue after handling this trap and
1557 * logging the error.
1558 */
1559 recoverable = 1;
1560 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1561 recoverable = 0;
1562
1563 /* Re-check AFSR/AFAR */
1564 (void) cheetah_recheck_errors(&local_snapshot);
1565
1566 /* Log errors. */
1567 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1568
1569 if (!recoverable)
1570 panic("Irrecoverable Correctable-ECC error trap.\n");
1571 }
1572
cheetah_deferred_handler(struct pt_regs * regs,unsigned long afsr,unsigned long afar)1573 void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1574 {
1575 struct cheetah_err_info local_snapshot, *p;
1576 int recoverable, is_memory;
1577
1578 #ifdef CONFIG_PCI
1579 /* Check for the special PCI poke sequence. */
1580 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1581 cheetah_flush_icache();
1582 cheetah_flush_dcache();
1583
1584 /* Re-enable I-cache/D-cache */
1585 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1586 "or %%g1, %1, %%g1\n\t"
1587 "stxa %%g1, [%%g0] %0\n\t"
1588 "membar #Sync"
1589 : /* no outputs */
1590 : "i" (ASI_DCU_CONTROL_REG),
1591 "i" (DCU_DC | DCU_IC)
1592 : "g1");
1593
1594 /* Re-enable error reporting */
1595 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1596 "or %%g1, %1, %%g1\n\t"
1597 "stxa %%g1, [%%g0] %0\n\t"
1598 "membar #Sync"
1599 : /* no outputs */
1600 : "i" (ASI_ESTATE_ERROR_EN),
1601 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1602 : "g1");
1603
1604 (void) cheetah_recheck_errors(NULL);
1605
1606 pci_poke_faulted = 1;
1607 regs->tpc += 4;
1608 regs->tnpc = regs->tpc + 4;
1609 return;
1610 }
1611 #endif
1612
1613 p = cheetah_get_error_log(afsr);
1614 if (!p) {
1615 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1616 afsr, afar);
1617 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1618 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1619 prom_halt();
1620 }
1621
1622 /* Grab snapshot of logged error. */
1623 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1624
1625 /* If the current trap snapshot does not match what the
1626 * trap handler passed along into our args, big trouble.
1627 * In such a case, mark the local copy as invalid.
1628 *
1629 * Else, it matches and we mark the afsr in the non-local
1630 * copy as invalid so we may log new error traps there.
1631 */
1632 if (p->afsr != afsr || p->afar != afar)
1633 local_snapshot.afsr = CHAFSR_INVALID;
1634 else
1635 p->afsr = CHAFSR_INVALID;
1636
1637 is_memory = cheetah_check_main_memory(afar);
1638
1639 {
1640 int flush_all, flush_line;
1641
1642 flush_all = flush_line = 0;
1643 if ((afsr & CHAFSR_EDU) != 0UL) {
1644 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1645 flush_line = 1;
1646 else
1647 flush_all = 1;
1648 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1649 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1650 flush_line = 1;
1651 else
1652 flush_all = 1;
1653 }
1654
1655 cheetah_flush_icache();
1656 cheetah_flush_dcache();
1657
1658 /* Re-enable I/D caches */
1659 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1660 "or %%g1, %1, %%g1\n\t"
1661 "stxa %%g1, [%%g0] %0\n\t"
1662 "membar #Sync"
1663 : /* no outputs */
1664 : "i" (ASI_DCU_CONTROL_REG),
1665 "i" (DCU_IC | DCU_DC)
1666 : "g1");
1667
1668 if (flush_all)
1669 cheetah_flush_ecache();
1670 else if (flush_line)
1671 cheetah_flush_ecache_line(afar);
1672 }
1673
1674 /* Re-enable error reporting */
1675 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1676 "or %%g1, %1, %%g1\n\t"
1677 "stxa %%g1, [%%g0] %0\n\t"
1678 "membar #Sync"
1679 : /* no outputs */
1680 : "i" (ASI_ESTATE_ERROR_EN),
1681 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1682 : "g1");
1683
1684 /* Decide if we can continue after handling this trap and
1685 * logging the error.
1686 */
1687 recoverable = 1;
1688 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1689 recoverable = 0;
1690
1691 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1692 * error was logged while we had error reporting traps disabled.
1693 */
1694 if (cheetah_recheck_errors(&local_snapshot)) {
1695 unsigned long new_afsr = local_snapshot.afsr;
1696
1697 /* If we got a new asynchronous error, die... */
1698 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1699 CHAFSR_WDU | CHAFSR_CPU |
1700 CHAFSR_IVU | CHAFSR_UE |
1701 CHAFSR_BERR | CHAFSR_TO))
1702 recoverable = 0;
1703 }
1704
1705 /* Log errors. */
1706 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1707
1708 /* "Recoverable" here means we try to yank the page from ever
1709 * being newly used again. This depends upon a few things:
1710 * 1) Must be main memory, and AFAR must be valid.
1711 * 2) If we trapped from user, OK.
1712 * 3) Else, if we trapped from kernel we must find exception
1713 * table entry (ie. we have to have been accessing user
1714 * space).
1715 *
1716 * If AFAR is not in main memory, or we trapped from kernel
1717 * and cannot find an exception table entry, it is unacceptable
1718 * to try and continue.
1719 */
1720 if (recoverable && is_memory) {
1721 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1722 /* OK, usermode access. */
1723 recoverable = 1;
1724 } else {
1725 const struct exception_table_entry *entry;
1726
1727 entry = search_exception_tables(regs->tpc);
1728 if (entry) {
1729 /* OK, kernel access to userspace. */
1730 recoverable = 1;
1731
1732 } else {
1733 /* BAD, privileged state is corrupted. */
1734 recoverable = 0;
1735 }
1736
1737 if (recoverable) {
1738 if (pfn_valid(afar >> PAGE_SHIFT))
1739 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1740 else
1741 recoverable = 0;
1742
1743 /* Only perform fixup if we still have a
1744 * recoverable condition.
1745 */
1746 if (recoverable) {
1747 regs->tpc = entry->fixup;
1748 regs->tnpc = regs->tpc + 4;
1749 }
1750 }
1751 }
1752 } else {
1753 recoverable = 0;
1754 }
1755
1756 if (!recoverable)
1757 panic("Irrecoverable deferred error trap.\n");
1758 }
1759
1760 /* Handle a D/I cache parity error trap. TYPE is encoded as:
1761 *
1762 * Bit0: 0=dcache,1=icache
1763 * Bit1: 0=recoverable,1=unrecoverable
1764 *
1765 * The hardware has disabled both the I-cache and D-cache in
1766 * the %dcr register.
1767 */
cheetah_plus_parity_error(int type,struct pt_regs * regs)1768 void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1769 {
1770 if (type & 0x1)
1771 __cheetah_flush_icache();
1772 else
1773 cheetah_plus_zap_dcache_parity();
1774 cheetah_flush_dcache();
1775
1776 /* Re-enable I-cache/D-cache */
1777 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1778 "or %%g1, %1, %%g1\n\t"
1779 "stxa %%g1, [%%g0] %0\n\t"
1780 "membar #Sync"
1781 : /* no outputs */
1782 : "i" (ASI_DCU_CONTROL_REG),
1783 "i" (DCU_DC | DCU_IC)
1784 : "g1");
1785
1786 if (type & 0x2) {
1787 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1788 smp_processor_id(),
1789 (type & 0x1) ? 'I' : 'D',
1790 regs->tpc);
1791 printk(KERN_EMERG "TPC<%pS>\n", (void *) regs->tpc);
1792 panic("Irrecoverable Cheetah+ parity error.");
1793 }
1794
1795 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1796 smp_processor_id(),
1797 (type & 0x1) ? 'I' : 'D',
1798 regs->tpc);
1799 printk(KERN_WARNING "TPC<%pS>\n", (void *) regs->tpc);
1800 }
1801
1802 struct sun4v_error_entry {
1803 /* Unique error handle */
1804 /*0x00*/u64 err_handle;
1805
1806 /* %stick value at the time of the error */
1807 /*0x08*/u64 err_stick;
1808
1809 /*0x10*/u8 reserved_1[3];
1810
1811 /* Error type */
1812 /*0x13*/u8 err_type;
1813 #define SUN4V_ERR_TYPE_UNDEFINED 0
1814 #define SUN4V_ERR_TYPE_UNCORRECTED_RES 1
1815 #define SUN4V_ERR_TYPE_PRECISE_NONRES 2
1816 #define SUN4V_ERR_TYPE_DEFERRED_NONRES 3
1817 #define SUN4V_ERR_TYPE_SHUTDOWN_RQST 4
1818 #define SUN4V_ERR_TYPE_DUMP_CORE 5
1819 #define SUN4V_ERR_TYPE_SP_STATE_CHANGE 6
1820 #define SUN4V_ERR_TYPE_NUM 7
1821
1822 /* Error attributes */
1823 /*0x14*/u32 err_attrs;
1824 #define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1825 #define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1826 #define SUN4V_ERR_ATTRS_PIO 0x00000004
1827 #define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1828 #define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1829 #define SUN4V_ERR_ATTRS_SHUTDOWN_RQST 0x00000020
1830 #define SUN4V_ERR_ATTRS_ASR 0x00000040
1831 #define SUN4V_ERR_ATTRS_ASI 0x00000080
1832 #define SUN4V_ERR_ATTRS_PRIV_REG 0x00000100
1833 #define SUN4V_ERR_ATTRS_SPSTATE_MSK 0x00000600
1834 #define SUN4V_ERR_ATTRS_MCD 0x00000800
1835 #define SUN4V_ERR_ATTRS_SPSTATE_SHFT 9
1836 #define SUN4V_ERR_ATTRS_MODE_MSK 0x03000000
1837 #define SUN4V_ERR_ATTRS_MODE_SHFT 24
1838 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1839
1840 #define SUN4V_ERR_SPSTATE_FAULTED 0
1841 #define SUN4V_ERR_SPSTATE_AVAILABLE 1
1842 #define SUN4V_ERR_SPSTATE_NOT_PRESENT 2
1843
1844 #define SUN4V_ERR_MODE_USER 1
1845 #define SUN4V_ERR_MODE_PRIV 2
1846
1847 /* Real address of the memory region or PIO transaction */
1848 /*0x18*/u64 err_raddr;
1849
1850 /* Size of the operation triggering the error, in bytes */
1851 /*0x20*/u32 err_size;
1852
1853 /* ID of the CPU */
1854 /*0x24*/u16 err_cpu;
1855
1856 /* Grace periof for shutdown, in seconds */
1857 /*0x26*/u16 err_secs;
1858
1859 /* Value of the %asi register */
1860 /*0x28*/u8 err_asi;
1861
1862 /*0x29*/u8 reserved_2;
1863
1864 /* Value of the ASR register number */
1865 /*0x2a*/u16 err_asr;
1866 #define SUN4V_ERR_ASR_VALID 0x8000
1867
1868 /*0x2c*/u32 reserved_3;
1869 /*0x30*/u64 reserved_4;
1870 /*0x38*/u64 reserved_5;
1871 };
1872
1873 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1874 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1875
sun4v_err_type_to_str(u8 type)1876 static const char *sun4v_err_type_to_str(u8 type)
1877 {
1878 static const char *types[SUN4V_ERR_TYPE_NUM] = {
1879 "undefined",
1880 "uncorrected resumable",
1881 "precise nonresumable",
1882 "deferred nonresumable",
1883 "shutdown request",
1884 "dump core",
1885 "SP state change",
1886 };
1887
1888 if (type < SUN4V_ERR_TYPE_NUM)
1889 return types[type];
1890
1891 return "unknown";
1892 }
1893
sun4v_emit_err_attr_strings(u32 attrs)1894 static void sun4v_emit_err_attr_strings(u32 attrs)
1895 {
1896 static const char *attr_names[] = {
1897 "processor",
1898 "memory",
1899 "PIO",
1900 "int-registers",
1901 "fpu-registers",
1902 "shutdown-request",
1903 "ASR",
1904 "ASI",
1905 "priv-reg",
1906 };
1907 static const char *sp_states[] = {
1908 "sp-faulted",
1909 "sp-available",
1910 "sp-not-present",
1911 "sp-state-reserved",
1912 };
1913 static const char *modes[] = {
1914 "mode-reserved0",
1915 "user",
1916 "priv",
1917 "mode-reserved1",
1918 };
1919 u32 sp_state, mode;
1920 int i;
1921
1922 for (i = 0; i < ARRAY_SIZE(attr_names); i++) {
1923 if (attrs & (1U << i)) {
1924 const char *s = attr_names[i];
1925
1926 pr_cont("%s ", s);
1927 }
1928 }
1929
1930 sp_state = ((attrs & SUN4V_ERR_ATTRS_SPSTATE_MSK) >>
1931 SUN4V_ERR_ATTRS_SPSTATE_SHFT);
1932 pr_cont("%s ", sp_states[sp_state]);
1933
1934 mode = ((attrs & SUN4V_ERR_ATTRS_MODE_MSK) >>
1935 SUN4V_ERR_ATTRS_MODE_SHFT);
1936 pr_cont("%s ", modes[mode]);
1937
1938 if (attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL)
1939 pr_cont("res-queue-full ");
1940 }
1941
1942 /* When the report contains a real-address of "-1" it means that the
1943 * hardware did not provide the address. So we compute the effective
1944 * address of the load or store instruction at regs->tpc and report
1945 * that. Usually when this happens it's a PIO and in such a case we
1946 * are using physical addresses with bypass ASIs anyways, so what we
1947 * report here is exactly what we want.
1948 */
sun4v_report_real_raddr(const char * pfx,struct pt_regs * regs)1949 static void sun4v_report_real_raddr(const char *pfx, struct pt_regs *regs)
1950 {
1951 unsigned int insn;
1952 u64 addr;
1953
1954 if (!(regs->tstate & TSTATE_PRIV))
1955 return;
1956
1957 insn = *(unsigned int *) regs->tpc;
1958
1959 addr = compute_effective_address(regs, insn, 0);
1960
1961 printk("%s: insn effective address [0x%016llx]\n",
1962 pfx, addr);
1963 }
1964
sun4v_log_error(struct pt_regs * regs,struct sun4v_error_entry * ent,int cpu,const char * pfx,atomic_t * ocnt)1965 static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent,
1966 int cpu, const char *pfx, atomic_t *ocnt)
1967 {
1968 u64 *raw_ptr = (u64 *) ent;
1969 u32 attrs;
1970 int cnt;
1971
1972 printk("%s: Reporting on cpu %d\n", pfx, cpu);
1973 printk("%s: TPC [0x%016lx] <%pS>\n",
1974 pfx, regs->tpc, (void *) regs->tpc);
1975
1976 printk("%s: RAW [%016llx:%016llx:%016llx:%016llx\n",
1977 pfx, raw_ptr[0], raw_ptr[1], raw_ptr[2], raw_ptr[3]);
1978 printk("%s: %016llx:%016llx:%016llx:%016llx]\n",
1979 pfx, raw_ptr[4], raw_ptr[5], raw_ptr[6], raw_ptr[7]);
1980
1981 printk("%s: handle [0x%016llx] stick [0x%016llx]\n",
1982 pfx, ent->err_handle, ent->err_stick);
1983
1984 printk("%s: type [%s]\n", pfx, sun4v_err_type_to_str(ent->err_type));
1985
1986 attrs = ent->err_attrs;
1987 printk("%s: attrs [0x%08x] < ", pfx, attrs);
1988 sun4v_emit_err_attr_strings(attrs);
1989 pr_cont(">\n");
1990
1991 /* Various fields in the error report are only valid if
1992 * certain attribute bits are set.
1993 */
1994 if (attrs & (SUN4V_ERR_ATTRS_MEMORY |
1995 SUN4V_ERR_ATTRS_PIO |
1996 SUN4V_ERR_ATTRS_ASI)) {
1997 printk("%s: raddr [0x%016llx]\n", pfx, ent->err_raddr);
1998
1999 if (ent->err_raddr == ~(u64)0)
2000 sun4v_report_real_raddr(pfx, regs);
2001 }
2002
2003 if (attrs & (SUN4V_ERR_ATTRS_MEMORY | SUN4V_ERR_ATTRS_ASI))
2004 printk("%s: size [0x%x]\n", pfx, ent->err_size);
2005
2006 if (attrs & (SUN4V_ERR_ATTRS_PROCESSOR |
2007 SUN4V_ERR_ATTRS_INT_REGISTERS |
2008 SUN4V_ERR_ATTRS_FPU_REGISTERS |
2009 SUN4V_ERR_ATTRS_PRIV_REG))
2010 printk("%s: cpu[%u]\n", pfx, ent->err_cpu);
2011
2012 if (attrs & SUN4V_ERR_ATTRS_ASI)
2013 printk("%s: asi [0x%02x]\n", pfx, ent->err_asi);
2014
2015 if ((attrs & (SUN4V_ERR_ATTRS_INT_REGISTERS |
2016 SUN4V_ERR_ATTRS_FPU_REGISTERS |
2017 SUN4V_ERR_ATTRS_PRIV_REG)) &&
2018 (ent->err_asr & SUN4V_ERR_ASR_VALID) != 0)
2019 printk("%s: reg [0x%04x]\n",
2020 pfx, ent->err_asr & ~SUN4V_ERR_ASR_VALID);
2021
2022 show_regs(regs);
2023
2024 if ((cnt = atomic_read(ocnt)) != 0) {
2025 atomic_set(ocnt, 0);
2026 wmb();
2027 printk("%s: Queue overflowed %d times.\n",
2028 pfx, cnt);
2029 }
2030 }
2031
2032 /* Handle memory corruption detected error which is vectored in
2033 * through resumable error trap.
2034 */
do_mcd_err(struct pt_regs * regs,struct sun4v_error_entry ent)2035 void do_mcd_err(struct pt_regs *regs, struct sun4v_error_entry ent)
2036 {
2037 if (notify_die(DIE_TRAP, "MCD error", regs, 0, 0x34,
2038 SIGSEGV) == NOTIFY_STOP)
2039 return;
2040
2041 if (regs->tstate & TSTATE_PRIV) {
2042 /* MCD exception could happen because the task was
2043 * running a system call with MCD enabled and passed a
2044 * non-versioned pointer or pointer with bad version
2045 * tag to the system call. In such cases, hypervisor
2046 * places the address of offending instruction in the
2047 * resumable error report. This is a deferred error,
2048 * so the read/write that caused the trap was potentially
2049 * retired long time back and we may have no choice
2050 * but to send SIGSEGV to the process.
2051 */
2052 const struct exception_table_entry *entry;
2053
2054 entry = search_exception_tables(regs->tpc);
2055 if (entry) {
2056 /* Looks like a bad syscall parameter */
2057 #ifdef DEBUG_EXCEPTIONS
2058 pr_emerg("Exception: PC<%016lx> faddr<UNKNOWN>\n",
2059 regs->tpc);
2060 pr_emerg("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
2061 ent.err_raddr, entry->fixup);
2062 #endif
2063 regs->tpc = entry->fixup;
2064 regs->tnpc = regs->tpc + 4;
2065 return;
2066 }
2067 }
2068
2069 /* Send SIGSEGV to the userspace process with the right signal
2070 * code
2071 */
2072 force_sig_fault(SIGSEGV, SEGV_ADIDERR, (void __user *)ent.err_raddr,
2073 0);
2074 }
2075
2076 /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
2077 * Log the event and clear the first word of the entry.
2078 */
sun4v_resum_error(struct pt_regs * regs,unsigned long offset)2079 void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
2080 {
2081 enum ctx_state prev_state = exception_enter();
2082 struct sun4v_error_entry *ent, local_copy;
2083 struct trap_per_cpu *tb;
2084 unsigned long paddr;
2085 int cpu;
2086
2087 cpu = get_cpu();
2088
2089 tb = &trap_block[cpu];
2090 paddr = tb->resum_kernel_buf_pa + offset;
2091 ent = __va(paddr);
2092
2093 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
2094
2095 /* We have a local copy now, so release the entry. */
2096 ent->err_handle = 0;
2097 wmb();
2098
2099 put_cpu();
2100
2101 if (local_copy.err_type == SUN4V_ERR_TYPE_SHUTDOWN_RQST) {
2102 /* We should really take the seconds field of
2103 * the error report and use it for the shutdown
2104 * invocation, but for now do the same thing we
2105 * do for a DS shutdown request.
2106 */
2107 pr_info("Shutdown request, %u seconds...\n",
2108 local_copy.err_secs);
2109 orderly_poweroff(true);
2110 goto out;
2111 }
2112
2113 /* If this is a memory corruption detected error vectored in
2114 * by HV through resumable error trap, call the handler
2115 */
2116 if (local_copy.err_attrs & SUN4V_ERR_ATTRS_MCD) {
2117 do_mcd_err(regs, local_copy);
2118 return;
2119 }
2120
2121 sun4v_log_error(regs, &local_copy, cpu,
2122 KERN_ERR "RESUMABLE ERROR",
2123 &sun4v_resum_oflow_cnt);
2124 out:
2125 exception_exit(prev_state);
2126 }
2127
2128 /* If we try to printk() we'll probably make matters worse, by trying
2129 * to retake locks this cpu already holds or causing more errors. So
2130 * just bump a counter, and we'll report these counter bumps above.
2131 */
sun4v_resum_overflow(struct pt_regs * regs)2132 void sun4v_resum_overflow(struct pt_regs *regs)
2133 {
2134 atomic_inc(&sun4v_resum_oflow_cnt);
2135 }
2136
2137 /* Given a set of registers, get the virtual addressi that was being accessed
2138 * by the faulting instructions at tpc.
2139 */
sun4v_get_vaddr(struct pt_regs * regs)2140 static unsigned long sun4v_get_vaddr(struct pt_regs *regs)
2141 {
2142 unsigned int insn;
2143
2144 if (!copy_from_user(&insn, (void __user *)regs->tpc, 4)) {
2145 return compute_effective_address(regs, insn,
2146 (insn >> 25) & 0x1f);
2147 }
2148 return 0;
2149 }
2150
2151 /* Attempt to handle non-resumable errors generated from userspace.
2152 * Returns true if the signal was handled, false otherwise.
2153 */
sun4v_nonresum_error_user_handled(struct pt_regs * regs,struct sun4v_error_entry * ent)2154 bool sun4v_nonresum_error_user_handled(struct pt_regs *regs,
2155 struct sun4v_error_entry *ent) {
2156
2157 unsigned int attrs = ent->err_attrs;
2158
2159 if (attrs & SUN4V_ERR_ATTRS_MEMORY) {
2160 unsigned long addr = ent->err_raddr;
2161
2162 if (addr == ~(u64)0) {
2163 /* This seems highly unlikely to ever occur */
2164 pr_emerg("SUN4V NON-RECOVERABLE ERROR: Memory error detected in unknown location!\n");
2165 } else {
2166 unsigned long page_cnt = DIV_ROUND_UP(ent->err_size,
2167 PAGE_SIZE);
2168
2169 /* Break the unfortunate news. */
2170 pr_emerg("SUN4V NON-RECOVERABLE ERROR: Memory failed at %016lX\n",
2171 addr);
2172 pr_emerg("SUN4V NON-RECOVERABLE ERROR: Claiming %lu ages.\n",
2173 page_cnt);
2174
2175 while (page_cnt-- > 0) {
2176 if (pfn_valid(addr >> PAGE_SHIFT))
2177 get_page(pfn_to_page(addr >> PAGE_SHIFT));
2178 addr += PAGE_SIZE;
2179 }
2180 }
2181 force_sig(SIGKILL);
2182
2183 return true;
2184 }
2185 if (attrs & SUN4V_ERR_ATTRS_PIO) {
2186 force_sig_fault(SIGBUS, BUS_ADRERR,
2187 (void __user *)sun4v_get_vaddr(regs), 0);
2188 return true;
2189 }
2190
2191 /* Default to doing nothing */
2192 return false;
2193 }
2194
2195 /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
2196 * Log the event, clear the first word of the entry, and die.
2197 */
sun4v_nonresum_error(struct pt_regs * regs,unsigned long offset)2198 void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
2199 {
2200 struct sun4v_error_entry *ent, local_copy;
2201 struct trap_per_cpu *tb;
2202 unsigned long paddr;
2203 int cpu;
2204
2205 cpu = get_cpu();
2206
2207 tb = &trap_block[cpu];
2208 paddr = tb->nonresum_kernel_buf_pa + offset;
2209 ent = __va(paddr);
2210
2211 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
2212
2213 /* We have a local copy now, so release the entry. */
2214 ent->err_handle = 0;
2215 wmb();
2216
2217 put_cpu();
2218
2219 if (!(regs->tstate & TSTATE_PRIV) &&
2220 sun4v_nonresum_error_user_handled(regs, &local_copy)) {
2221 /* DON'T PANIC: This userspace error was handled. */
2222 return;
2223 }
2224
2225 #ifdef CONFIG_PCI
2226 /* Check for the special PCI poke sequence. */
2227 if (pci_poke_in_progress && pci_poke_cpu == cpu) {
2228 pci_poke_faulted = 1;
2229 regs->tpc += 4;
2230 regs->tnpc = regs->tpc + 4;
2231 return;
2232 }
2233 #endif
2234
2235 sun4v_log_error(regs, &local_copy, cpu,
2236 KERN_EMERG "NON-RESUMABLE ERROR",
2237 &sun4v_nonresum_oflow_cnt);
2238
2239 panic("Non-resumable error.");
2240 }
2241
2242 /* If we try to printk() we'll probably make matters worse, by trying
2243 * to retake locks this cpu already holds or causing more errors. So
2244 * just bump a counter, and we'll report these counter bumps above.
2245 */
sun4v_nonresum_overflow(struct pt_regs * regs)2246 void sun4v_nonresum_overflow(struct pt_regs *regs)
2247 {
2248 /* XXX Actually even this can make not that much sense. Perhaps
2249 * XXX we should just pull the plug and panic directly from here?
2250 */
2251 atomic_inc(&sun4v_nonresum_oflow_cnt);
2252 }
2253
sun4v_tlb_error(struct pt_regs * regs)2254 static void sun4v_tlb_error(struct pt_regs *regs)
2255 {
2256 die_if_kernel("TLB/TSB error", regs);
2257 }
2258
2259 unsigned long sun4v_err_itlb_vaddr;
2260 unsigned long sun4v_err_itlb_ctx;
2261 unsigned long sun4v_err_itlb_pte;
2262 unsigned long sun4v_err_itlb_error;
2263
sun4v_itlb_error_report(struct pt_regs * regs,int tl)2264 void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
2265 {
2266 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2267
2268 printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
2269 regs->tpc, tl);
2270 printk(KERN_EMERG "SUN4V-ITLB: TPC<%pS>\n", (void *) regs->tpc);
2271 printk(KERN_EMERG "SUN4V-ITLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
2272 printk(KERN_EMERG "SUN4V-ITLB: O7<%pS>\n",
2273 (void *) regs->u_regs[UREG_I7]);
2274 printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
2275 "pte[%lx] error[%lx]\n",
2276 sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
2277 sun4v_err_itlb_pte, sun4v_err_itlb_error);
2278
2279 sun4v_tlb_error(regs);
2280 }
2281
2282 unsigned long sun4v_err_dtlb_vaddr;
2283 unsigned long sun4v_err_dtlb_ctx;
2284 unsigned long sun4v_err_dtlb_pte;
2285 unsigned long sun4v_err_dtlb_error;
2286
sun4v_dtlb_error_report(struct pt_regs * regs,int tl)2287 void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
2288 {
2289 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2290
2291 printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
2292 regs->tpc, tl);
2293 printk(KERN_EMERG "SUN4V-DTLB: TPC<%pS>\n", (void *) regs->tpc);
2294 printk(KERN_EMERG "SUN4V-DTLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
2295 printk(KERN_EMERG "SUN4V-DTLB: O7<%pS>\n",
2296 (void *) regs->u_regs[UREG_I7]);
2297 printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
2298 "pte[%lx] error[%lx]\n",
2299 sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
2300 sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
2301
2302 sun4v_tlb_error(regs);
2303 }
2304
hypervisor_tlbop_error(unsigned long err,unsigned long op)2305 void hypervisor_tlbop_error(unsigned long err, unsigned long op)
2306 {
2307 printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
2308 err, op);
2309 }
2310
hypervisor_tlbop_error_xcall(unsigned long err,unsigned long op)2311 void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
2312 {
2313 printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
2314 err, op);
2315 }
2316
do_fpe_common(struct pt_regs * regs)2317 static void do_fpe_common(struct pt_regs *regs)
2318 {
2319 if (regs->tstate & TSTATE_PRIV) {
2320 regs->tpc = regs->tnpc;
2321 regs->tnpc += 4;
2322 } else {
2323 unsigned long fsr = current_thread_info()->xfsr[0];
2324 int code;
2325
2326 if (test_thread_flag(TIF_32BIT)) {
2327 regs->tpc &= 0xffffffff;
2328 regs->tnpc &= 0xffffffff;
2329 }
2330 code = FPE_FLTUNK;
2331 if ((fsr & 0x1c000) == (1 << 14)) {
2332 if (fsr & 0x10)
2333 code = FPE_FLTINV;
2334 else if (fsr & 0x08)
2335 code = FPE_FLTOVF;
2336 else if (fsr & 0x04)
2337 code = FPE_FLTUND;
2338 else if (fsr & 0x02)
2339 code = FPE_FLTDIV;
2340 else if (fsr & 0x01)
2341 code = FPE_FLTRES;
2342 }
2343 force_sig_fault(SIGFPE, code,
2344 (void __user *)regs->tpc, 0);
2345 }
2346 }
2347
do_fpieee(struct pt_regs * regs)2348 void do_fpieee(struct pt_regs *regs)
2349 {
2350 enum ctx_state prev_state = exception_enter();
2351
2352 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2353 0, 0x24, SIGFPE) == NOTIFY_STOP)
2354 goto out;
2355
2356 do_fpe_common(regs);
2357 out:
2358 exception_exit(prev_state);
2359 }
2360
do_fpother(struct pt_regs * regs)2361 void do_fpother(struct pt_regs *regs)
2362 {
2363 enum ctx_state prev_state = exception_enter();
2364 struct fpustate *f = FPUSTATE;
2365 int ret = 0;
2366
2367 if (notify_die(DIE_TRAP, "fpu exception other", regs,
2368 0, 0x25, SIGFPE) == NOTIFY_STOP)
2369 goto out;
2370
2371 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2372 case (2 << 14): /* unfinished_FPop */
2373 case (3 << 14): /* unimplemented_FPop */
2374 ret = do_mathemu(regs, f, false);
2375 break;
2376 }
2377 if (ret)
2378 goto out;
2379 do_fpe_common(regs);
2380 out:
2381 exception_exit(prev_state);
2382 }
2383
do_tof(struct pt_regs * regs)2384 void do_tof(struct pt_regs *regs)
2385 {
2386 enum ctx_state prev_state = exception_enter();
2387
2388 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2389 0, 0x26, SIGEMT) == NOTIFY_STOP)
2390 goto out;
2391
2392 if (regs->tstate & TSTATE_PRIV)
2393 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2394 if (test_thread_flag(TIF_32BIT)) {
2395 regs->tpc &= 0xffffffff;
2396 regs->tnpc &= 0xffffffff;
2397 }
2398 force_sig_fault(SIGEMT, EMT_TAGOVF,
2399 (void __user *)regs->tpc, 0);
2400 out:
2401 exception_exit(prev_state);
2402 }
2403
do_div0(struct pt_regs * regs)2404 void do_div0(struct pt_regs *regs)
2405 {
2406 enum ctx_state prev_state = exception_enter();
2407
2408 if (notify_die(DIE_TRAP, "integer division by zero", regs,
2409 0, 0x28, SIGFPE) == NOTIFY_STOP)
2410 goto out;
2411
2412 if (regs->tstate & TSTATE_PRIV)
2413 die_if_kernel("TL0: Kernel divide by zero.", regs);
2414 if (test_thread_flag(TIF_32BIT)) {
2415 regs->tpc &= 0xffffffff;
2416 regs->tnpc &= 0xffffffff;
2417 }
2418 force_sig_fault(SIGFPE, FPE_INTDIV,
2419 (void __user *)regs->tpc, 0);
2420 out:
2421 exception_exit(prev_state);
2422 }
2423
instruction_dump(unsigned int * pc)2424 static void instruction_dump(unsigned int *pc)
2425 {
2426 int i;
2427
2428 if ((((unsigned long) pc) & 3))
2429 return;
2430
2431 printk("Instruction DUMP:");
2432 for (i = -3; i < 6; i++)
2433 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2434 printk("\n");
2435 }
2436
user_instruction_dump(unsigned int __user * pc)2437 static void user_instruction_dump(unsigned int __user *pc)
2438 {
2439 int i;
2440 unsigned int buf[9];
2441
2442 if ((((unsigned long) pc) & 3))
2443 return;
2444
2445 if (copy_from_user(buf, pc - 3, sizeof(buf)))
2446 return;
2447
2448 printk("Instruction DUMP:");
2449 for (i = 0; i < 9; i++)
2450 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2451 printk("\n");
2452 }
2453
show_stack(struct task_struct * tsk,unsigned long * _ksp,const char * loglvl)2454 void show_stack(struct task_struct *tsk, unsigned long *_ksp, const char *loglvl)
2455 {
2456 unsigned long fp, ksp;
2457 struct thread_info *tp;
2458 int count = 0;
2459 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2460 int graph = 0;
2461 #endif
2462
2463 ksp = (unsigned long) _ksp;
2464 if (!tsk)
2465 tsk = current;
2466 tp = task_thread_info(tsk);
2467 if (ksp == 0UL) {
2468 if (tsk == current)
2469 asm("mov %%fp, %0" : "=r" (ksp));
2470 else
2471 ksp = tp->ksp;
2472 }
2473 if (tp == current_thread_info())
2474 flushw_all();
2475
2476 fp = ksp + STACK_BIAS;
2477
2478 printk("%sCall Trace:\n", loglvl);
2479 do {
2480 struct sparc_stackf *sf;
2481 struct pt_regs *regs;
2482 unsigned long pc;
2483
2484 if (!kstack_valid(tp, fp))
2485 break;
2486 sf = (struct sparc_stackf *) fp;
2487 regs = (struct pt_regs *) (sf + 1);
2488
2489 if (kstack_is_trap_frame(tp, regs)) {
2490 if (!(regs->tstate & TSTATE_PRIV))
2491 break;
2492 pc = regs->tpc;
2493 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
2494 } else {
2495 pc = sf->callers_pc;
2496 fp = (unsigned long)sf->fp + STACK_BIAS;
2497 }
2498
2499 print_ip_sym(loglvl, pc);
2500 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2501 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
2502 struct ftrace_ret_stack *ret_stack;
2503 ret_stack = ftrace_graph_get_ret_stack(tsk, graph);
2504 if (ret_stack) {
2505 pc = ret_stack->ret;
2506 print_ip_sym(loglvl, pc);
2507 graph++;
2508 }
2509 }
2510 #endif
2511 } while (++count < 16);
2512 }
2513
kernel_stack_up(struct reg_window * rw)2514 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2515 {
2516 unsigned long fp = rw->ins[6];
2517
2518 if (!fp)
2519 return NULL;
2520
2521 return (struct reg_window *) (fp + STACK_BIAS);
2522 }
2523
die_if_kernel(char * str,struct pt_regs * regs)2524 void __noreturn die_if_kernel(char *str, struct pt_regs *regs)
2525 {
2526 static int die_counter;
2527 int count = 0;
2528
2529 /* Amuse the user. */
2530 printk(
2531 " \\|/ ____ \\|/\n"
2532 " \"@'/ .. \\`@\"\n"
2533 " /_| \\__/ |_\\\n"
2534 " \\__U_/\n");
2535
2536 printk("%s(%d): %s [#%d]\n", current->comm, task_pid_nr(current), str, ++die_counter);
2537 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2538 __asm__ __volatile__("flushw");
2539 show_regs(regs);
2540 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
2541 if (regs->tstate & TSTATE_PRIV) {
2542 struct thread_info *tp = current_thread_info();
2543 struct reg_window *rw = (struct reg_window *)
2544 (regs->u_regs[UREG_FP] + STACK_BIAS);
2545
2546 /* Stop the back trace when we hit userland or we
2547 * find some badly aligned kernel stack.
2548 */
2549 while (rw &&
2550 count++ < 30 &&
2551 kstack_valid(tp, (unsigned long) rw)) {
2552 printk("Caller[%016lx]: %pS\n", rw->ins[7],
2553 (void *) rw->ins[7]);
2554
2555 rw = kernel_stack_up(rw);
2556 }
2557 instruction_dump ((unsigned int *) regs->tpc);
2558 } else {
2559 if (test_thread_flag(TIF_32BIT)) {
2560 regs->tpc &= 0xffffffff;
2561 regs->tnpc &= 0xffffffff;
2562 }
2563 user_instruction_dump ((unsigned int __user *) regs->tpc);
2564 }
2565 if (panic_on_oops)
2566 panic("Fatal exception");
2567 if (regs->tstate & TSTATE_PRIV)
2568 do_exit(SIGKILL);
2569 do_exit(SIGSEGV);
2570 }
2571 EXPORT_SYMBOL(die_if_kernel);
2572
2573 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2574 #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2575
do_illegal_instruction(struct pt_regs * regs)2576 void do_illegal_instruction(struct pt_regs *regs)
2577 {
2578 enum ctx_state prev_state = exception_enter();
2579 unsigned long pc = regs->tpc;
2580 unsigned long tstate = regs->tstate;
2581 u32 insn;
2582
2583 if (notify_die(DIE_TRAP, "illegal instruction", regs,
2584 0, 0x10, SIGILL) == NOTIFY_STOP)
2585 goto out;
2586
2587 if (tstate & TSTATE_PRIV)
2588 die_if_kernel("Kernel illegal instruction", regs);
2589 if (test_thread_flag(TIF_32BIT))
2590 pc = (u32)pc;
2591 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2592 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2593 if (handle_popc(insn, regs))
2594 goto out;
2595 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2596 if (handle_ldf_stq(insn, regs))
2597 goto out;
2598 } else if (tlb_type == hypervisor) {
2599 if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2600 if (!vis_emul(regs, insn))
2601 goto out;
2602 } else {
2603 struct fpustate *f = FPUSTATE;
2604
2605 /* On UltraSPARC T2 and later, FPU insns which
2606 * are not implemented in HW signal an illegal
2607 * instruction trap and do not set the FP Trap
2608 * Trap in the %fsr to unimplemented_FPop.
2609 */
2610 if (do_mathemu(regs, f, true))
2611 goto out;
2612 }
2613 }
2614 }
2615 force_sig_fault(SIGILL, ILL_ILLOPC, (void __user *)pc, 0);
2616 out:
2617 exception_exit(prev_state);
2618 }
2619
mem_address_unaligned(struct pt_regs * regs,unsigned long sfar,unsigned long sfsr)2620 void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2621 {
2622 enum ctx_state prev_state = exception_enter();
2623
2624 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2625 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2626 goto out;
2627
2628 if (regs->tstate & TSTATE_PRIV) {
2629 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2630 goto out;
2631 }
2632 if (is_no_fault_exception(regs))
2633 return;
2634
2635 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)sfar, 0);
2636 out:
2637 exception_exit(prev_state);
2638 }
2639
sun4v_do_mna(struct pt_regs * regs,unsigned long addr,unsigned long type_ctx)2640 void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
2641 {
2642 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2643 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2644 return;
2645
2646 if (regs->tstate & TSTATE_PRIV) {
2647 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2648 return;
2649 }
2650 if (is_no_fault_exception(regs))
2651 return;
2652
2653 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *) addr, 0);
2654 }
2655
2656 /* sun4v_mem_corrupt_detect_precise() - Handle precise exception on an ADI
2657 * tag mismatch.
2658 *
2659 * ADI version tag mismatch on a load from memory always results in a
2660 * precise exception. Tag mismatch on a store to memory will result in
2661 * precise exception if MCDPER or PMCDPER is set to 1.
2662 */
sun4v_mem_corrupt_detect_precise(struct pt_regs * regs,unsigned long addr,unsigned long context)2663 void sun4v_mem_corrupt_detect_precise(struct pt_regs *regs, unsigned long addr,
2664 unsigned long context)
2665 {
2666 if (notify_die(DIE_TRAP, "memory corruption precise exception", regs,
2667 0, 0x8, SIGSEGV) == NOTIFY_STOP)
2668 return;
2669
2670 if (regs->tstate & TSTATE_PRIV) {
2671 /* MCD exception could happen because the task was running
2672 * a system call with MCD enabled and passed a non-versioned
2673 * pointer or pointer with bad version tag to the system
2674 * call.
2675 */
2676 const struct exception_table_entry *entry;
2677
2678 entry = search_exception_tables(regs->tpc);
2679 if (entry) {
2680 /* Looks like a bad syscall parameter */
2681 #ifdef DEBUG_EXCEPTIONS
2682 pr_emerg("Exception: PC<%016lx> faddr<UNKNOWN>\n",
2683 regs->tpc);
2684 pr_emerg("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
2685 regs->tpc, entry->fixup);
2686 #endif
2687 regs->tpc = entry->fixup;
2688 regs->tnpc = regs->tpc + 4;
2689 return;
2690 }
2691 pr_emerg("%s: ADDR[%016lx] CTX[%lx], going.\n",
2692 __func__, addr, context);
2693 die_if_kernel("MCD precise", regs);
2694 }
2695
2696 if (test_thread_flag(TIF_32BIT)) {
2697 regs->tpc &= 0xffffffff;
2698 regs->tnpc &= 0xffffffff;
2699 }
2700 force_sig_fault(SIGSEGV, SEGV_ADIPERR, (void __user *)addr, 0);
2701 }
2702
do_privop(struct pt_regs * regs)2703 void do_privop(struct pt_regs *regs)
2704 {
2705 enum ctx_state prev_state = exception_enter();
2706
2707 if (notify_die(DIE_TRAP, "privileged operation", regs,
2708 0, 0x11, SIGILL) == NOTIFY_STOP)
2709 goto out;
2710
2711 if (test_thread_flag(TIF_32BIT)) {
2712 regs->tpc &= 0xffffffff;
2713 regs->tnpc &= 0xffffffff;
2714 }
2715 force_sig_fault(SIGILL, ILL_PRVOPC,
2716 (void __user *)regs->tpc, 0);
2717 out:
2718 exception_exit(prev_state);
2719 }
2720
do_privact(struct pt_regs * regs)2721 void do_privact(struct pt_regs *regs)
2722 {
2723 do_privop(regs);
2724 }
2725
2726 /* Trap level 1 stuff or other traps we should never see... */
do_cee(struct pt_regs * regs)2727 void do_cee(struct pt_regs *regs)
2728 {
2729 exception_enter();
2730 die_if_kernel("TL0: Cache Error Exception", regs);
2731 }
2732
do_div0_tl1(struct pt_regs * regs)2733 void do_div0_tl1(struct pt_regs *regs)
2734 {
2735 exception_enter();
2736 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2737 die_if_kernel("TL1: DIV0 Exception", regs);
2738 }
2739
do_fpieee_tl1(struct pt_regs * regs)2740 void do_fpieee_tl1(struct pt_regs *regs)
2741 {
2742 exception_enter();
2743 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2744 die_if_kernel("TL1: FPU IEEE Exception", regs);
2745 }
2746
do_fpother_tl1(struct pt_regs * regs)2747 void do_fpother_tl1(struct pt_regs *regs)
2748 {
2749 exception_enter();
2750 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2751 die_if_kernel("TL1: FPU Other Exception", regs);
2752 }
2753
do_ill_tl1(struct pt_regs * regs)2754 void do_ill_tl1(struct pt_regs *regs)
2755 {
2756 exception_enter();
2757 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2758 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2759 }
2760
do_irq_tl1(struct pt_regs * regs)2761 void do_irq_tl1(struct pt_regs *regs)
2762 {
2763 exception_enter();
2764 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2765 die_if_kernel("TL1: IRQ Exception", regs);
2766 }
2767
do_lddfmna_tl1(struct pt_regs * regs)2768 void do_lddfmna_tl1(struct pt_regs *regs)
2769 {
2770 exception_enter();
2771 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2772 die_if_kernel("TL1: LDDF Exception", regs);
2773 }
2774
do_stdfmna_tl1(struct pt_regs * regs)2775 void do_stdfmna_tl1(struct pt_regs *regs)
2776 {
2777 exception_enter();
2778 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2779 die_if_kernel("TL1: STDF Exception", regs);
2780 }
2781
do_paw(struct pt_regs * regs)2782 void do_paw(struct pt_regs *regs)
2783 {
2784 exception_enter();
2785 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2786 }
2787
do_paw_tl1(struct pt_regs * regs)2788 void do_paw_tl1(struct pt_regs *regs)
2789 {
2790 exception_enter();
2791 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2792 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2793 }
2794
do_vaw(struct pt_regs * regs)2795 void do_vaw(struct pt_regs *regs)
2796 {
2797 exception_enter();
2798 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2799 }
2800
do_vaw_tl1(struct pt_regs * regs)2801 void do_vaw_tl1(struct pt_regs *regs)
2802 {
2803 exception_enter();
2804 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2805 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2806 }
2807
do_tof_tl1(struct pt_regs * regs)2808 void do_tof_tl1(struct pt_regs *regs)
2809 {
2810 exception_enter();
2811 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2812 die_if_kernel("TL1: Tag Overflow Exception", regs);
2813 }
2814
do_getpsr(struct pt_regs * regs)2815 void do_getpsr(struct pt_regs *regs)
2816 {
2817 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2818 regs->tpc = regs->tnpc;
2819 regs->tnpc += 4;
2820 if (test_thread_flag(TIF_32BIT)) {
2821 regs->tpc &= 0xffffffff;
2822 regs->tnpc &= 0xffffffff;
2823 }
2824 }
2825
2826 u64 cpu_mondo_counter[NR_CPUS] = {0};
2827 struct trap_per_cpu trap_block[NR_CPUS];
2828 EXPORT_SYMBOL(trap_block);
2829
2830 /* This can get invoked before sched_init() so play it super safe
2831 * and use hard_smp_processor_id().
2832 */
init_cur_cpu_trap(struct thread_info * t)2833 void notrace init_cur_cpu_trap(struct thread_info *t)
2834 {
2835 int cpu = hard_smp_processor_id();
2836 struct trap_per_cpu *p = &trap_block[cpu];
2837
2838 p->thread = t;
2839 p->pgd_paddr = 0;
2840 }
2841
2842 extern void thread_info_offsets_are_bolixed_dave(void);
2843 extern void trap_per_cpu_offsets_are_bolixed_dave(void);
2844 extern void tsb_config_offsets_are_bolixed_dave(void);
2845
2846 /* Only invoked on boot processor. */
trap_init(void)2847 void __init trap_init(void)
2848 {
2849 /* Compile time sanity check. */
2850 BUILD_BUG_ON(TI_TASK != offsetof(struct thread_info, task) ||
2851 TI_FLAGS != offsetof(struct thread_info, flags) ||
2852 TI_CPU != offsetof(struct thread_info, cpu) ||
2853 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2854 TI_KSP != offsetof(struct thread_info, ksp) ||
2855 TI_FAULT_ADDR != offsetof(struct thread_info,
2856 fault_address) ||
2857 TI_KREGS != offsetof(struct thread_info, kregs) ||
2858 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2859 TI_REG_WINDOW != offsetof(struct thread_info,
2860 reg_window) ||
2861 TI_RWIN_SPTRS != offsetof(struct thread_info,
2862 rwbuf_stkptrs) ||
2863 TI_GSR != offsetof(struct thread_info, gsr) ||
2864 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2865 TI_PRE_COUNT != offsetof(struct thread_info,
2866 preempt_count) ||
2867 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2868 TI_CURRENT_DS != offsetof(struct thread_info,
2869 current_ds) ||
2870 TI_KUNA_REGS != offsetof(struct thread_info,
2871 kern_una_regs) ||
2872 TI_KUNA_INSN != offsetof(struct thread_info,
2873 kern_una_insn) ||
2874 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2875 (TI_FPREGS & (64 - 1)));
2876
2877 BUILD_BUG_ON(TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu,
2878 thread) ||
2879 (TRAP_PER_CPU_PGD_PADDR !=
2880 offsetof(struct trap_per_cpu, pgd_paddr)) ||
2881 (TRAP_PER_CPU_CPU_MONDO_PA !=
2882 offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2883 (TRAP_PER_CPU_DEV_MONDO_PA !=
2884 offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2885 (TRAP_PER_CPU_RESUM_MONDO_PA !=
2886 offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
2887 (TRAP_PER_CPU_RESUM_KBUF_PA !=
2888 offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
2889 (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2890 offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
2891 (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2892 offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
2893 (TRAP_PER_CPU_FAULT_INFO !=
2894 offsetof(struct trap_per_cpu, fault_info)) ||
2895 (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2896 offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2897 (TRAP_PER_CPU_CPU_LIST_PA !=
2898 offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2899 (TRAP_PER_CPU_TSB_HUGE !=
2900 offsetof(struct trap_per_cpu, tsb_huge)) ||
2901 (TRAP_PER_CPU_TSB_HUGE_TEMP !=
2902 offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
2903 (TRAP_PER_CPU_IRQ_WORKLIST_PA !=
2904 offsetof(struct trap_per_cpu, irq_worklist_pa)) ||
2905 (TRAP_PER_CPU_CPU_MONDO_QMASK !=
2906 offsetof(struct trap_per_cpu, cpu_mondo_qmask)) ||
2907 (TRAP_PER_CPU_DEV_MONDO_QMASK !=
2908 offsetof(struct trap_per_cpu, dev_mondo_qmask)) ||
2909 (TRAP_PER_CPU_RESUM_QMASK !=
2910 offsetof(struct trap_per_cpu, resum_qmask)) ||
2911 (TRAP_PER_CPU_NONRESUM_QMASK !=
2912 offsetof(struct trap_per_cpu, nonresum_qmask)) ||
2913 (TRAP_PER_CPU_PER_CPU_BASE !=
2914 offsetof(struct trap_per_cpu, __per_cpu_base)));
2915
2916 BUILD_BUG_ON((TSB_CONFIG_TSB !=
2917 offsetof(struct tsb_config, tsb)) ||
2918 (TSB_CONFIG_RSS_LIMIT !=
2919 offsetof(struct tsb_config, tsb_rss_limit)) ||
2920 (TSB_CONFIG_NENTRIES !=
2921 offsetof(struct tsb_config, tsb_nentries)) ||
2922 (TSB_CONFIG_REG_VAL !=
2923 offsetof(struct tsb_config, tsb_reg_val)) ||
2924 (TSB_CONFIG_MAP_VADDR !=
2925 offsetof(struct tsb_config, tsb_map_vaddr)) ||
2926 (TSB_CONFIG_MAP_PTE !=
2927 offsetof(struct tsb_config, tsb_map_pte)));
2928
2929 /* Attach to the address space of init_task. On SMP we
2930 * do this in smp.c:smp_callin for other cpus.
2931 */
2932 mmgrab(&init_mm);
2933 current->active_mm = &init_mm;
2934 }
2935