1 /*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <drm/amdgpu_drm.h>
26 #include <drm/drm_drv.h>
27 #include <drm/drm_gem.h>
28 #include <drm/drm_vblank.h>
29 #include <drm/drm_managed.h>
30 #include "amdgpu_drv.h"
31
32 #include <drm/drm_pciids.h>
33 #include <linux/console.h>
34 #include <linux/module.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_probe_helper.h>
38 #include <linux/mmu_notifier.h>
39 #include <linux/suspend.h>
40
41 #include "amdgpu.h"
42 #include "amdgpu_irq.h"
43 #include "amdgpu_dma_buf.h"
44 #include "amdgpu_sched.h"
45
46 #include "amdgpu_amdkfd.h"
47
48 #include "amdgpu_ras.h"
49 #include "amdgpu_xgmi.h"
50 #include "amdgpu_reset.h"
51
52 /*
53 * KMS wrapper.
54 * - 3.0.0 - initial driver
55 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
56 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
57 * at the end of IBs.
58 * - 3.3.0 - Add VM support for UVD on supported hardware.
59 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
60 * - 3.5.0 - Add support for new UVD_NO_OP register.
61 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
62 * - 3.7.0 - Add support for VCE clock list packet
63 * - 3.8.0 - Add support raster config init in the kernel
64 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
65 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
66 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
67 * - 3.12.0 - Add query for double offchip LDS buffers
68 * - 3.13.0 - Add PRT support
69 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
70 * - 3.15.0 - Export more gpu info for gfx9
71 * - 3.16.0 - Add reserved vmid support
72 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
73 * - 3.18.0 - Export gpu always on cu bitmap
74 * - 3.19.0 - Add support for UVD MJPEG decode
75 * - 3.20.0 - Add support for local BOs
76 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
77 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
78 * - 3.23.0 - Add query for VRAM lost counter
79 * - 3.24.0 - Add high priority compute support for gfx9
80 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
81 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
82 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
83 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
84 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
85 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
86 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
87 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
88 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
89 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
90 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
91 * - 3.36.0 - Allow reading more status registers on si/cik
92 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
93 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
94 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
95 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
96 * - 3.41.0 - Add video codec query
97 */
98 #define KMS_DRIVER_MAJOR 3
99 #define KMS_DRIVER_MINOR 41
100 #define KMS_DRIVER_PATCHLEVEL 0
101
102 int amdgpu_vram_limit;
103 int amdgpu_vis_vram_limit;
104 int amdgpu_gart_size = -1; /* auto */
105 int amdgpu_gtt_size = -1; /* auto */
106 int amdgpu_moverate = -1; /* auto */
107 int amdgpu_benchmarking;
108 int amdgpu_testing;
109 int amdgpu_audio = -1;
110 int amdgpu_disp_priority;
111 int amdgpu_hw_i2c;
112 int amdgpu_pcie_gen2 = -1;
113 int amdgpu_msi = -1;
114 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
115 int amdgpu_dpm = -1;
116 int amdgpu_fw_load_type = -1;
117 int amdgpu_aspm = -1;
118 int amdgpu_runtime_pm = -1;
119 uint amdgpu_ip_block_mask = 0xffffffff;
120 int amdgpu_bapm = -1;
121 int amdgpu_deep_color;
122 int amdgpu_vm_size = -1;
123 int amdgpu_vm_fragment_size = -1;
124 int amdgpu_vm_block_size = -1;
125 int amdgpu_vm_fault_stop;
126 int amdgpu_vm_debug;
127 int amdgpu_vm_update_mode = -1;
128 int amdgpu_exp_hw_support;
129 int amdgpu_dc = -1;
130 int amdgpu_sched_jobs = 32;
131 int amdgpu_sched_hw_submission = 2;
132 uint amdgpu_pcie_gen_cap;
133 uint amdgpu_pcie_lane_cap;
134 uint amdgpu_cg_mask = 0xffffffff;
135 uint amdgpu_pg_mask = 0xffffffff;
136 uint amdgpu_sdma_phase_quantum = 32;
137 char *amdgpu_disable_cu = NULL;
138 char *amdgpu_virtual_display = NULL;
139
140 /*
141 * OverDrive(bit 14) disabled by default
142 * GFX DCS(bit 19) disabled by default
143 */
144 uint amdgpu_pp_feature_mask = 0xfff7bfff;
145 uint amdgpu_force_long_training;
146 int amdgpu_job_hang_limit;
147 int amdgpu_lbpw = -1;
148 int amdgpu_compute_multipipe = -1;
149 int amdgpu_gpu_recovery = -1; /* auto */
150 int amdgpu_emu_mode;
151 uint amdgpu_smu_memory_pool_size;
152 int amdgpu_smu_pptable_id = -1;
153 /*
154 * FBC (bit 0) disabled by default
155 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
156 * - With this, for multiple monitors in sync(e.g. with the same model),
157 * mclk switching will be allowed. And the mclk will be not foced to the
158 * highest. That helps saving some idle power.
159 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
160 * PSR (bit 3) disabled by default
161 */
162 uint amdgpu_dc_feature_mask = 2;
163 uint amdgpu_dc_debug_mask;
164 int amdgpu_async_gfx_ring = 1;
165 int amdgpu_mcbp;
166 int amdgpu_discovery = -1;
167 int amdgpu_mes;
168 int amdgpu_noretry = -1;
169 int amdgpu_force_asic_type = -1;
170 int amdgpu_tmz = -1; /* auto */
171 uint amdgpu_freesync_vid_mode;
172 int amdgpu_reset_method = -1; /* auto */
173 int amdgpu_num_kcq = -1;
174
175 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
176
177 struct amdgpu_mgpu_info mgpu_info = {
178 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
179 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
180 mgpu_info.delayed_reset_work,
181 amdgpu_drv_delayed_reset_work_handler, 0),
182 };
183 int amdgpu_ras_enable = -1;
184 uint amdgpu_ras_mask = 0xffffffff;
185 int amdgpu_bad_page_threshold = -1;
186 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
187 .timeout_fatal_disable = false,
188 .period = 0x0, /* default to 0x0 (timeout disable) */
189 };
190
191 /**
192 * DOC: vramlimit (int)
193 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
194 */
195 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
196 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
197
198 /**
199 * DOC: vis_vramlimit (int)
200 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
201 */
202 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
203 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
204
205 /**
206 * DOC: gartsize (uint)
207 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
208 */
209 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
210 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
211
212 /**
213 * DOC: gttsize (int)
214 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
215 * otherwise 3/4 RAM size).
216 */
217 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
218 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
219
220 /**
221 * DOC: moverate (int)
222 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
223 */
224 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
225 module_param_named(moverate, amdgpu_moverate, int, 0600);
226
227 /**
228 * DOC: benchmark (int)
229 * Run benchmarks. The default is 0 (Skip benchmarks).
230 */
231 MODULE_PARM_DESC(benchmark, "Run benchmark");
232 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
233
234 /**
235 * DOC: test (int)
236 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
237 */
238 MODULE_PARM_DESC(test, "Run tests");
239 module_param_named(test, amdgpu_testing, int, 0444);
240
241 /**
242 * DOC: audio (int)
243 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
244 */
245 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
246 module_param_named(audio, amdgpu_audio, int, 0444);
247
248 /**
249 * DOC: disp_priority (int)
250 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
251 */
252 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
253 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
254
255 /**
256 * DOC: hw_i2c (int)
257 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
258 */
259 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
260 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
261
262 /**
263 * DOC: pcie_gen2 (int)
264 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
265 */
266 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
267 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
268
269 /**
270 * DOC: msi (int)
271 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
272 */
273 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
274 module_param_named(msi, amdgpu_msi, int, 0444);
275
276 /**
277 * DOC: lockup_timeout (string)
278 * Set GPU scheduler timeout value in ms.
279 *
280 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
281 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
282 * to the default timeout.
283 *
284 * - With one value specified, the setting will apply to all non-compute jobs.
285 * - With multiple values specified, the first one will be for GFX.
286 * The second one is for Compute. The third and fourth ones are
287 * for SDMA and Video.
288 *
289 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
290 * jobs is 10000. And there is no timeout enforced on compute jobs.
291 */
292 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; "
293 "for passthrough or sriov, 10000 for all jobs."
294 " 0: keep default value. negative: infinity timeout), "
295 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
296 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
297 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
298
299 /**
300 * DOC: dpm (int)
301 * Override for dynamic power management setting
302 * (0 = disable, 1 = enable)
303 * The default is -1 (auto).
304 */
305 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
306 module_param_named(dpm, amdgpu_dpm, int, 0444);
307
308 /**
309 * DOC: fw_load_type (int)
310 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto).
311 */
312 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
313 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
314
315 /**
316 * DOC: aspm (int)
317 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
318 */
319 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
320 module_param_named(aspm, amdgpu_aspm, int, 0444);
321
322 /**
323 * DOC: runpm (int)
324 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down
325 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.
326 */
327 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)");
328 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
329
330 /**
331 * DOC: ip_block_mask (uint)
332 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
333 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
334 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
335 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
336 */
337 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
338 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
339
340 /**
341 * DOC: bapm (int)
342 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
343 * The default -1 (auto, enabled)
344 */
345 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
346 module_param_named(bapm, amdgpu_bapm, int, 0444);
347
348 /**
349 * DOC: deep_color (int)
350 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
351 */
352 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
353 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
354
355 /**
356 * DOC: vm_size (int)
357 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
358 */
359 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
360 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
361
362 /**
363 * DOC: vm_fragment_size (int)
364 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
365 */
366 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
367 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
368
369 /**
370 * DOC: vm_block_size (int)
371 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
372 */
373 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
374 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
375
376 /**
377 * DOC: vm_fault_stop (int)
378 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
379 */
380 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
381 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
382
383 /**
384 * DOC: vm_debug (int)
385 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
386 */
387 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
388 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
389
390 /**
391 * DOC: vm_update_mode (int)
392 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
393 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
394 */
395 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
396 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
397
398 /**
399 * DOC: exp_hw_support (int)
400 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
401 */
402 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
403 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
404
405 /**
406 * DOC: dc (int)
407 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
408 */
409 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
410 module_param_named(dc, amdgpu_dc, int, 0444);
411
412 /**
413 * DOC: sched_jobs (int)
414 * Override the max number of jobs supported in the sw queue. The default is 32.
415 */
416 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
417 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
418
419 /**
420 * DOC: sched_hw_submission (int)
421 * Override the max number of HW submissions. The default is 2.
422 */
423 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
424 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
425
426 /**
427 * DOC: ppfeaturemask (hexint)
428 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
429 * The default is the current set of stable power features.
430 */
431 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
432 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
433
434 /**
435 * DOC: forcelongtraining (uint)
436 * Force long memory training in resume.
437 * The default is zero, indicates short training in resume.
438 */
439 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
440 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
441
442 /**
443 * DOC: pcie_gen_cap (uint)
444 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
445 * The default is 0 (automatic for each asic).
446 */
447 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
448 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
449
450 /**
451 * DOC: pcie_lane_cap (uint)
452 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
453 * The default is 0 (automatic for each asic).
454 */
455 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
456 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
457
458 /**
459 * DOC: cg_mask (uint)
460 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
461 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
462 */
463 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
464 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
465
466 /**
467 * DOC: pg_mask (uint)
468 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
469 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
470 */
471 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
472 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
473
474 /**
475 * DOC: sdma_phase_quantum (uint)
476 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
477 */
478 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
479 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
480
481 /**
482 * DOC: disable_cu (charp)
483 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
484 */
485 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
486 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
487
488 /**
489 * DOC: virtual_display (charp)
490 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
491 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
492 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
493 * device at 26:00.0. The default is NULL.
494 */
495 MODULE_PARM_DESC(virtual_display,
496 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
497 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
498
499 /**
500 * DOC: job_hang_limit (int)
501 * Set how much time allow a job hang and not drop it. The default is 0.
502 */
503 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
504 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
505
506 /**
507 * DOC: lbpw (int)
508 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
509 */
510 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
511 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
512
513 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
514 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
515
516 /**
517 * DOC: gpu_recovery (int)
518 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
519 */
520 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)");
521 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
522
523 /**
524 * DOC: emu_mode (int)
525 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
526 */
527 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
528 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
529
530 /**
531 * DOC: ras_enable (int)
532 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
533 */
534 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
535 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
536
537 /**
538 * DOC: ras_mask (uint)
539 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
540 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
541 */
542 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
543 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
544
545 /**
546 * DOC: timeout_fatal_disable (bool)
547 * Disable Watchdog timeout fatal error event
548 */
549 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
550 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
551
552 /**
553 * DOC: timeout_period (uint)
554 * Modify the watchdog timeout max_cycles as (1 << period)
555 */
556 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
557 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
558
559 /**
560 * DOC: si_support (int)
561 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
562 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
563 * otherwise using amdgpu driver.
564 */
565 #ifdef CONFIG_DRM_AMDGPU_SI
566
567 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
568 int amdgpu_si_support = 0;
569 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
570 #else
571 int amdgpu_si_support = 1;
572 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
573 #endif
574
575 module_param_named(si_support, amdgpu_si_support, int, 0444);
576 #endif
577
578 /**
579 * DOC: cik_support (int)
580 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
581 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
582 * otherwise using amdgpu driver.
583 */
584 #ifdef CONFIG_DRM_AMDGPU_CIK
585
586 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
587 int amdgpu_cik_support = 0;
588 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
589 #else
590 int amdgpu_cik_support = 1;
591 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
592 #endif
593
594 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
595 #endif
596
597 /**
598 * DOC: smu_memory_pool_size (uint)
599 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
600 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
601 */
602 MODULE_PARM_DESC(smu_memory_pool_size,
603 "reserve gtt for smu debug usage, 0 = disable,"
604 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
605 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
606
607 /**
608 * DOC: async_gfx_ring (int)
609 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
610 */
611 MODULE_PARM_DESC(async_gfx_ring,
612 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
613 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
614
615 /**
616 * DOC: mcbp (int)
617 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
618 */
619 MODULE_PARM_DESC(mcbp,
620 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
621 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
622
623 /**
624 * DOC: discovery (int)
625 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
626 * (-1 = auto (default), 0 = disabled, 1 = enabled)
627 */
628 MODULE_PARM_DESC(discovery,
629 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
630 module_param_named(discovery, amdgpu_discovery, int, 0444);
631
632 /**
633 * DOC: mes (int)
634 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
635 * (0 = disabled (default), 1 = enabled)
636 */
637 MODULE_PARM_DESC(mes,
638 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
639 module_param_named(mes, amdgpu_mes, int, 0444);
640
641 /**
642 * DOC: noretry (int)
643 * Disable retry faults in the GPU memory controller.
644 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
645 */
646 MODULE_PARM_DESC(noretry,
647 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
648 module_param_named(noretry, amdgpu_noretry, int, 0644);
649
650 /**
651 * DOC: force_asic_type (int)
652 * A non negative value used to specify the asic type for all supported GPUs.
653 */
654 MODULE_PARM_DESC(force_asic_type,
655 "A non negative value used to specify the asic type for all supported GPUs");
656 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
657
658
659
660 #ifdef CONFIG_HSA_AMD
661 /**
662 * DOC: sched_policy (int)
663 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
664 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
665 * assigns queues to HQDs.
666 */
667 int sched_policy = KFD_SCHED_POLICY_HWS;
668 module_param(sched_policy, int, 0444);
669 MODULE_PARM_DESC(sched_policy,
670 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
671
672 /**
673 * DOC: hws_max_conc_proc (int)
674 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
675 * number of VMIDs assigned to the HWS, which is also the default.
676 */
677 int hws_max_conc_proc = 8;
678 module_param(hws_max_conc_proc, int, 0444);
679 MODULE_PARM_DESC(hws_max_conc_proc,
680 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
681
682 /**
683 * DOC: cwsr_enable (int)
684 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
685 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
686 * disables it.
687 */
688 int cwsr_enable = 1;
689 module_param(cwsr_enable, int, 0444);
690 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
691
692 /**
693 * DOC: max_num_of_queues_per_device (int)
694 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
695 * is 4096.
696 */
697 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
698 module_param(max_num_of_queues_per_device, int, 0444);
699 MODULE_PARM_DESC(max_num_of_queues_per_device,
700 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
701
702 /**
703 * DOC: send_sigterm (int)
704 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
705 * but just print errors on dmesg. Setting 1 enables sending sigterm.
706 */
707 int send_sigterm;
708 module_param(send_sigterm, int, 0444);
709 MODULE_PARM_DESC(send_sigterm,
710 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
711
712 /**
713 * DOC: debug_largebar (int)
714 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
715 * system. This limits the VRAM size reported to ROCm applications to the visible
716 * size, usually 256MB.
717 * Default value is 0, diabled.
718 */
719 int debug_largebar;
720 module_param(debug_largebar, int, 0444);
721 MODULE_PARM_DESC(debug_largebar,
722 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
723
724 /**
725 * DOC: ignore_crat (int)
726 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
727 * table to get information about AMD APUs. This option can serve as a workaround on
728 * systems with a broken CRAT table.
729 *
730 * Default is auto (according to asic type, iommu_v2, and crat table, to decide
731 * whehter use CRAT)
732 */
733 int ignore_crat;
734 module_param(ignore_crat, int, 0444);
735 MODULE_PARM_DESC(ignore_crat,
736 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
737
738 /**
739 * DOC: halt_if_hws_hang (int)
740 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
741 * Setting 1 enables halt on hang.
742 */
743 int halt_if_hws_hang;
744 module_param(halt_if_hws_hang, int, 0644);
745 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
746
747 /**
748 * DOC: hws_gws_support(bool)
749 * Assume that HWS supports GWS barriers regardless of what firmware version
750 * check says. Default value: false (rely on MEC2 firmware version check).
751 */
752 bool hws_gws_support;
753 module_param(hws_gws_support, bool, 0444);
754 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
755
756 /**
757 * DOC: queue_preemption_timeout_ms (int)
758 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
759 */
760 int queue_preemption_timeout_ms = 9000;
761 module_param(queue_preemption_timeout_ms, int, 0644);
762 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
763
764 /**
765 * DOC: debug_evictions(bool)
766 * Enable extra debug messages to help determine the cause of evictions
767 */
768 bool debug_evictions;
769 module_param(debug_evictions, bool, 0644);
770 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
771
772 /**
773 * DOC: no_system_mem_limit(bool)
774 * Disable system memory limit, to support multiple process shared memory
775 */
776 bool no_system_mem_limit;
777 module_param(no_system_mem_limit, bool, 0644);
778 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
779
780 /**
781 * DOC: no_queue_eviction_on_vm_fault (int)
782 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
783 */
784 int amdgpu_no_queue_eviction_on_vm_fault = 0;
785 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
786 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
787 #endif
788
789 /**
790 * DOC: dcfeaturemask (uint)
791 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
792 * The default is the current set of stable display features.
793 */
794 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
795 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
796
797 /**
798 * DOC: dcdebugmask (uint)
799 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
800 */
801 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
802 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
803
804 /**
805 * DOC: abmlevel (uint)
806 * Override the default ABM (Adaptive Backlight Management) level used for DC
807 * enabled hardware. Requires DMCU to be supported and loaded.
808 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
809 * default. Values 1-4 control the maximum allowable brightness reduction via
810 * the ABM algorithm, with 1 being the least reduction and 4 being the most
811 * reduction.
812 *
813 * Defaults to 0, or disabled. Userspace can still override this level later
814 * after boot.
815 */
816 uint amdgpu_dm_abm_level;
817 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
818 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
819
820 int amdgpu_backlight = -1;
821 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
822 module_param_named(backlight, amdgpu_backlight, bint, 0444);
823
824 /**
825 * DOC: tmz (int)
826 * Trusted Memory Zone (TMZ) is a method to protect data being written
827 * to or read from memory.
828 *
829 * The default value: 0 (off). TODO: change to auto till it is completed.
830 */
831 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
832 module_param_named(tmz, amdgpu_tmz, int, 0444);
833
834 /**
835 * DOC: freesync_video (uint)
836 * Enabled the optimization to adjust front porch timing to achieve seamless mode change experience
837 * when setting a freesync supported mode for which full modeset is not needed.
838 * The default value: 0 (off).
839 */
840 MODULE_PARM_DESC(
841 freesync_video,
842 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
843 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
844
845 /**
846 * DOC: reset_method (int)
847 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci)
848 */
849 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)");
850 module_param_named(reset_method, amdgpu_reset_method, int, 0444);
851
852 /**
853 * DOC: bad_page_threshold (int)
854 * Bad page threshold is to specify the threshold value of faulty pages
855 * detected by RAS ECC, that may result in GPU entering bad status if total
856 * faulty pages by ECC exceed threshold value and leave it for user's further
857 * check.
858 */
859 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)");
860 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
861
862 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
863 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
864
865 /**
866 * DOC: smu_pptable_id (int)
867 * Used to override pptable id. id = 0 use VBIOS pptable.
868 * id > 0 use the soft pptable with specicfied id.
869 */
870 MODULE_PARM_DESC(smu_pptable_id,
871 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
872 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
873
874 static const struct pci_device_id pciidlist[] = {
875 #ifdef CONFIG_DRM_AMDGPU_SI
876 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
877 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
878 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
879 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
880 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
881 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
882 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
883 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
884 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
885 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
886 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
887 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
888 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
889 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
890 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
891 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
892 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
893 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
894 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
895 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
896 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
897 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
898 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
899 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
900 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
901 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
902 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
903 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
904 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
905 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
906 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
907 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
908 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
909 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
910 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
911 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
912 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
913 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
914 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
915 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
916 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
917 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
918 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
919 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
920 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
921 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
922 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
923 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
924 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
925 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
926 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
927 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
928 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
929 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
930 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
931 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
932 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
933 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
934 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
935 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
936 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
937 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
938 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
939 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
940 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
941 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
942 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
943 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
944 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
945 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
946 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
947 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
948 #endif
949 #ifdef CONFIG_DRM_AMDGPU_CIK
950 /* Kaveri */
951 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
952 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
953 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
954 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
955 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
956 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
957 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
958 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
959 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
960 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
961 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
962 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
963 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
964 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
965 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
966 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
967 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
968 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
969 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
970 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
971 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
972 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
973 /* Bonaire */
974 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
975 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
976 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
977 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
978 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
979 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
980 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
981 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
982 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
983 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
984 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
985 /* Hawaii */
986 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
987 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
988 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
989 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
990 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
991 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
992 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
993 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
994 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
995 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
996 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
997 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
998 /* Kabini */
999 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1000 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1001 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1002 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1003 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1004 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1005 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1006 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1007 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1008 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1009 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1010 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1011 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1012 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1013 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1014 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1015 /* mullins */
1016 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1017 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1018 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1019 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1020 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1021 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1022 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1023 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1024 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1025 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1026 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1027 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1028 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1029 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1030 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1031 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1032 #endif
1033 /* topaz */
1034 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1035 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1036 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1037 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1038 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1039 /* tonga */
1040 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1041 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1042 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1043 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1044 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1045 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1046 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1047 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1048 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1049 /* fiji */
1050 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1051 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1052 /* carrizo */
1053 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1054 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1055 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1056 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1057 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1058 /* stoney */
1059 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1060 /* Polaris11 */
1061 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1062 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1063 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1064 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1065 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1066 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1067 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1068 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1069 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1070 /* Polaris10 */
1071 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1072 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1073 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1074 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1075 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1076 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1077 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1078 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1079 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1080 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1081 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1082 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1083 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1084 /* Polaris12 */
1085 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1086 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1087 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1088 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1089 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1090 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1091 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1092 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1093 /* VEGAM */
1094 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1095 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1096 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1097 /* Vega 10 */
1098 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1099 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1100 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1101 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1102 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1103 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1104 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1105 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1106 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1107 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1108 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1109 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1110 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1111 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1112 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1113 /* Vega 12 */
1114 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1115 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1116 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1117 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1118 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1119 /* Vega 20 */
1120 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1121 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1122 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1123 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1124 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1125 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1126 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1127 /* Raven */
1128 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1129 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1130 /* Arcturus */
1131 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1132 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1133 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1134 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1135 /* Navi10 */
1136 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1137 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1138 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1139 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1140 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1141 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1142 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1143 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1144 /* Navi14 */
1145 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1146 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1147 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1148 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1149
1150 /* Renoir */
1151 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1152 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1153 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1154
1155 /* Navi12 */
1156 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1157 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1158
1159 /* Sienna_Cichlid */
1160 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1161 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1162 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1163 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1164 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1165 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1166 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1167 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1168
1169 /* Van Gogh */
1170 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
1171
1172 /* Navy_Flounder */
1173 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1174 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1175 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1176 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1177
1178 /* DIMGREY_CAVEFISH */
1179 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1180 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1181 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1182 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1183
1184 /* Aldebaran */
1185 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1186 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1187 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1188
1189 {0, 0, 0}
1190 };
1191
1192 MODULE_DEVICE_TABLE(pci, pciidlist);
1193
1194 static const struct drm_driver amdgpu_kms_driver;
1195
amdgpu_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1196 static int amdgpu_pci_probe(struct pci_dev *pdev,
1197 const struct pci_device_id *ent)
1198 {
1199 struct drm_device *ddev;
1200 struct amdgpu_device *adev;
1201 unsigned long flags = ent->driver_data;
1202 int ret, retry = 0;
1203 bool supports_atomic = false;
1204
1205 if (!amdgpu_virtual_display &&
1206 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
1207 supports_atomic = true;
1208
1209 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
1210 DRM_INFO("This hardware requires experimental hardware support.\n"
1211 "See modparam exp_hw_support\n");
1212 return -ENODEV;
1213 }
1214
1215 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
1216 * however, SME requires an indirect IOMMU mapping because the encryption
1217 * bit is beyond the DMA mask of the chip.
1218 */
1219 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
1220 dev_info(&pdev->dev,
1221 "SME is not compatible with RAVEN\n");
1222 return -ENOTSUPP;
1223 }
1224
1225 #ifdef CONFIG_DRM_AMDGPU_SI
1226 if (!amdgpu_si_support) {
1227 switch (flags & AMD_ASIC_MASK) {
1228 case CHIP_TAHITI:
1229 case CHIP_PITCAIRN:
1230 case CHIP_VERDE:
1231 case CHIP_OLAND:
1232 case CHIP_HAINAN:
1233 dev_info(&pdev->dev,
1234 "SI support provided by radeon.\n");
1235 dev_info(&pdev->dev,
1236 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
1237 );
1238 return -ENODEV;
1239 }
1240 }
1241 #endif
1242 #ifdef CONFIG_DRM_AMDGPU_CIK
1243 if (!amdgpu_cik_support) {
1244 switch (flags & AMD_ASIC_MASK) {
1245 case CHIP_KAVERI:
1246 case CHIP_BONAIRE:
1247 case CHIP_HAWAII:
1248 case CHIP_KABINI:
1249 case CHIP_MULLINS:
1250 dev_info(&pdev->dev,
1251 "CIK support provided by radeon.\n");
1252 dev_info(&pdev->dev,
1253 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
1254 );
1255 return -ENODEV;
1256 }
1257 }
1258 #endif
1259
1260 /* Get rid of things like offb */
1261 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb");
1262 if (ret)
1263 return ret;
1264
1265 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
1266 if (IS_ERR(adev))
1267 return PTR_ERR(adev);
1268
1269 adev->dev = &pdev->dev;
1270 adev->pdev = pdev;
1271 ddev = adev_to_drm(adev);
1272
1273 if (!supports_atomic)
1274 ddev->driver_features &= ~DRIVER_ATOMIC;
1275
1276 ret = pci_enable_device(pdev);
1277 if (ret)
1278 return ret;
1279
1280 pci_set_drvdata(pdev, ddev);
1281
1282 ret = amdgpu_driver_load_kms(adev, ent->driver_data);
1283 if (ret)
1284 goto err_pci;
1285
1286 retry_init:
1287 ret = drm_dev_register(ddev, ent->driver_data);
1288 if (ret == -EAGAIN && ++retry <= 3) {
1289 DRM_INFO("retry init %d\n", retry);
1290 /* Don't request EX mode too frequently which is attacking */
1291 msleep(5000);
1292 goto retry_init;
1293 } else if (ret) {
1294 goto err_pci;
1295 }
1296
1297 ret = amdgpu_debugfs_init(adev);
1298 if (ret)
1299 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
1300
1301 return 0;
1302
1303 err_pci:
1304 pci_disable_device(pdev);
1305 return ret;
1306 }
1307
1308 static void
amdgpu_pci_remove(struct pci_dev * pdev)1309 amdgpu_pci_remove(struct pci_dev *pdev)
1310 {
1311 struct drm_device *dev = pci_get_drvdata(pdev);
1312
1313 #ifdef MODULE
1314 if (THIS_MODULE->state != MODULE_STATE_GOING)
1315 #endif
1316 DRM_ERROR("Hotplug removal is not supported\n");
1317 drm_dev_unplug(dev);
1318 amdgpu_driver_unload_kms(dev);
1319 pci_disable_device(pdev);
1320 pci_set_drvdata(pdev, NULL);
1321 }
1322
1323 static void
amdgpu_pci_shutdown(struct pci_dev * pdev)1324 amdgpu_pci_shutdown(struct pci_dev *pdev)
1325 {
1326 struct drm_device *dev = pci_get_drvdata(pdev);
1327 struct amdgpu_device *adev = drm_to_adev(dev);
1328
1329 if (amdgpu_ras_intr_triggered())
1330 return;
1331
1332 /* if we are running in a VM, make sure the device
1333 * torn down properly on reboot/shutdown.
1334 * unfortunately we can't detect certain
1335 * hypervisors so just do this all the time.
1336 */
1337 if (!amdgpu_passthrough(adev))
1338 adev->mp1_state = PP_MP1_STATE_UNLOAD;
1339 amdgpu_device_ip_suspend(adev);
1340 adev->mp1_state = PP_MP1_STATE_NONE;
1341 }
1342
1343 /**
1344 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
1345 *
1346 * @work: work_struct.
1347 */
amdgpu_drv_delayed_reset_work_handler(struct work_struct * work)1348 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
1349 {
1350 struct list_head device_list;
1351 struct amdgpu_device *adev;
1352 int i, r;
1353 struct amdgpu_reset_context reset_context;
1354
1355 memset(&reset_context, 0, sizeof(reset_context));
1356
1357 mutex_lock(&mgpu_info.mutex);
1358 if (mgpu_info.pending_reset == true) {
1359 mutex_unlock(&mgpu_info.mutex);
1360 return;
1361 }
1362 mgpu_info.pending_reset = true;
1363 mutex_unlock(&mgpu_info.mutex);
1364
1365 /* Use a common context, just need to make sure full reset is done */
1366 reset_context.method = AMD_RESET_METHOD_NONE;
1367 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
1368
1369 for (i = 0; i < mgpu_info.num_dgpu; i++) {
1370 adev = mgpu_info.gpu_ins[i].adev;
1371 reset_context.reset_req_dev = adev;
1372 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
1373 if (r) {
1374 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
1375 r, adev_to_drm(adev)->unique);
1376 }
1377 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
1378 r = -EALREADY;
1379 }
1380 for (i = 0; i < mgpu_info.num_dgpu; i++) {
1381 adev = mgpu_info.gpu_ins[i].adev;
1382 flush_work(&adev->xgmi_reset_work);
1383 adev->gmc.xgmi.pending_reset = false;
1384 }
1385
1386 /* reset function will rebuild the xgmi hive info , clear it now */
1387 for (i = 0; i < mgpu_info.num_dgpu; i++)
1388 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
1389
1390 INIT_LIST_HEAD(&device_list);
1391
1392 for (i = 0; i < mgpu_info.num_dgpu; i++)
1393 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
1394
1395 /* unregister the GPU first, reset function will add them back */
1396 list_for_each_entry(adev, &device_list, reset_list)
1397 amdgpu_unregister_gpu_instance(adev);
1398
1399 /* Use a common context, just need to make sure full reset is done */
1400 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
1401 r = amdgpu_do_asic_reset(&device_list, &reset_context);
1402
1403 if (r) {
1404 DRM_ERROR("reinit gpus failure");
1405 return;
1406 }
1407 for (i = 0; i < mgpu_info.num_dgpu; i++) {
1408 adev = mgpu_info.gpu_ins[i].adev;
1409 if (!adev->kfd.init_complete)
1410 amdgpu_amdkfd_device_init(adev);
1411 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1412 }
1413 return;
1414 }
1415
amdgpu_pmops_prepare(struct device * dev)1416 static int amdgpu_pmops_prepare(struct device *dev)
1417 {
1418 struct drm_device *drm_dev = dev_get_drvdata(dev);
1419
1420 /* Return a positive number here so
1421 * DPM_FLAG_SMART_SUSPEND works properly
1422 */
1423 if (amdgpu_device_supports_boco(drm_dev))
1424 return pm_runtime_suspended(dev) &&
1425 pm_suspend_via_firmware();
1426
1427 return 0;
1428 }
1429
amdgpu_pmops_complete(struct device * dev)1430 static void amdgpu_pmops_complete(struct device *dev)
1431 {
1432 /* nothing to do */
1433 }
1434
amdgpu_pmops_suspend(struct device * dev)1435 static int amdgpu_pmops_suspend(struct device *dev)
1436 {
1437 struct drm_device *drm_dev = dev_get_drvdata(dev);
1438 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1439 int r;
1440
1441 if (amdgpu_acpi_is_s0ix_supported(adev))
1442 adev->in_s0ix = true;
1443 adev->in_s3 = true;
1444 r = amdgpu_device_suspend(drm_dev, true);
1445 adev->in_s3 = false;
1446
1447 return r;
1448 }
1449
amdgpu_pmops_resume(struct device * dev)1450 static int amdgpu_pmops_resume(struct device *dev)
1451 {
1452 struct drm_device *drm_dev = dev_get_drvdata(dev);
1453 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1454 int r;
1455
1456 r = amdgpu_device_resume(drm_dev, true);
1457 if (amdgpu_acpi_is_s0ix_supported(adev))
1458 adev->in_s0ix = false;
1459 return r;
1460 }
1461
amdgpu_pmops_freeze(struct device * dev)1462 static int amdgpu_pmops_freeze(struct device *dev)
1463 {
1464 struct drm_device *drm_dev = dev_get_drvdata(dev);
1465 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1466 int r;
1467
1468 adev->in_s4 = true;
1469 r = amdgpu_device_suspend(drm_dev, true);
1470 adev->in_s4 = false;
1471 if (r)
1472 return r;
1473 return amdgpu_asic_reset(adev);
1474 }
1475
amdgpu_pmops_thaw(struct device * dev)1476 static int amdgpu_pmops_thaw(struct device *dev)
1477 {
1478 struct drm_device *drm_dev = dev_get_drvdata(dev);
1479
1480 return amdgpu_device_resume(drm_dev, true);
1481 }
1482
amdgpu_pmops_poweroff(struct device * dev)1483 static int amdgpu_pmops_poweroff(struct device *dev)
1484 {
1485 struct drm_device *drm_dev = dev_get_drvdata(dev);
1486
1487 return amdgpu_device_suspend(drm_dev, true);
1488 }
1489
amdgpu_pmops_restore(struct device * dev)1490 static int amdgpu_pmops_restore(struct device *dev)
1491 {
1492 struct drm_device *drm_dev = dev_get_drvdata(dev);
1493
1494 return amdgpu_device_resume(drm_dev, true);
1495 }
1496
amdgpu_pmops_runtime_suspend(struct device * dev)1497 static int amdgpu_pmops_runtime_suspend(struct device *dev)
1498 {
1499 struct pci_dev *pdev = to_pci_dev(dev);
1500 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1501 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1502 int ret, i;
1503
1504 if (!adev->runpm) {
1505 pm_runtime_forbid(dev);
1506 return -EBUSY;
1507 }
1508
1509 /* wait for all rings to drain before suspending */
1510 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1511 struct amdgpu_ring *ring = adev->rings[i];
1512 if (ring && ring->sched.ready) {
1513 ret = amdgpu_fence_wait_empty(ring);
1514 if (ret)
1515 return -EBUSY;
1516 }
1517 }
1518
1519 adev->in_runpm = true;
1520 if (amdgpu_device_supports_px(drm_dev))
1521 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1522
1523 ret = amdgpu_device_suspend(drm_dev, false);
1524 if (ret) {
1525 adev->in_runpm = false;
1526 return ret;
1527 }
1528
1529 if (amdgpu_device_supports_px(drm_dev)) {
1530 /* Only need to handle PCI state in the driver for ATPX
1531 * PCI core handles it for _PR3.
1532 */
1533 amdgpu_device_cache_pci_state(pdev);
1534 pci_disable_device(pdev);
1535 pci_ignore_hotplug(pdev);
1536 pci_set_power_state(pdev, PCI_D3cold);
1537 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1538 } else if (amdgpu_device_supports_baco(drm_dev)) {
1539 amdgpu_device_baco_enter(drm_dev);
1540 }
1541
1542 return 0;
1543 }
1544
amdgpu_pmops_runtime_resume(struct device * dev)1545 static int amdgpu_pmops_runtime_resume(struct device *dev)
1546 {
1547 struct pci_dev *pdev = to_pci_dev(dev);
1548 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1549 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1550 int ret;
1551
1552 if (!adev->runpm)
1553 return -EINVAL;
1554
1555 if (amdgpu_device_supports_px(drm_dev)) {
1556 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1557
1558 /* Only need to handle PCI state in the driver for ATPX
1559 * PCI core handles it for _PR3.
1560 */
1561 pci_set_power_state(pdev, PCI_D0);
1562 amdgpu_device_load_pci_state(pdev);
1563 ret = pci_enable_device(pdev);
1564 if (ret)
1565 return ret;
1566 pci_set_master(pdev);
1567 } else if (amdgpu_device_supports_boco(drm_dev)) {
1568 /* Only need to handle PCI state in the driver for ATPX
1569 * PCI core handles it for _PR3.
1570 */
1571 pci_set_master(pdev);
1572 } else if (amdgpu_device_supports_baco(drm_dev)) {
1573 amdgpu_device_baco_exit(drm_dev);
1574 }
1575 ret = amdgpu_device_resume(drm_dev, false);
1576 if (ret)
1577 return ret;
1578
1579 if (amdgpu_device_supports_px(drm_dev))
1580 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1581 adev->in_runpm = false;
1582 return 0;
1583 }
1584
amdgpu_pmops_runtime_idle(struct device * dev)1585 static int amdgpu_pmops_runtime_idle(struct device *dev)
1586 {
1587 struct drm_device *drm_dev = dev_get_drvdata(dev);
1588 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1589 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1590 int ret = 1;
1591
1592 if (!adev->runpm) {
1593 pm_runtime_forbid(dev);
1594 return -EBUSY;
1595 }
1596
1597 if (amdgpu_device_has_dc_support(adev)) {
1598 struct drm_crtc *crtc;
1599
1600 drm_modeset_lock_all(drm_dev);
1601
1602 drm_for_each_crtc(crtc, drm_dev) {
1603 if (crtc->state->active) {
1604 ret = -EBUSY;
1605 break;
1606 }
1607 }
1608
1609 drm_modeset_unlock_all(drm_dev);
1610
1611 } else {
1612 struct drm_connector *list_connector;
1613 struct drm_connector_list_iter iter;
1614
1615 mutex_lock(&drm_dev->mode_config.mutex);
1616 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
1617
1618 drm_connector_list_iter_begin(drm_dev, &iter);
1619 drm_for_each_connector_iter(list_connector, &iter) {
1620 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
1621 ret = -EBUSY;
1622 break;
1623 }
1624 }
1625
1626 drm_connector_list_iter_end(&iter);
1627
1628 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
1629 mutex_unlock(&drm_dev->mode_config.mutex);
1630 }
1631
1632 if (ret == -EBUSY)
1633 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1634
1635 pm_runtime_mark_last_busy(dev);
1636 pm_runtime_autosuspend(dev);
1637 return ret;
1638 }
1639
amdgpu_drm_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)1640 long amdgpu_drm_ioctl(struct file *filp,
1641 unsigned int cmd, unsigned long arg)
1642 {
1643 struct drm_file *file_priv = filp->private_data;
1644 struct drm_device *dev;
1645 long ret;
1646 dev = file_priv->minor->dev;
1647 ret = pm_runtime_get_sync(dev->dev);
1648 if (ret < 0)
1649 goto out;
1650
1651 ret = drm_ioctl(filp, cmd, arg);
1652
1653 pm_runtime_mark_last_busy(dev->dev);
1654 out:
1655 pm_runtime_put_autosuspend(dev->dev);
1656 return ret;
1657 }
1658
1659 static const struct dev_pm_ops amdgpu_pm_ops = {
1660 .prepare = amdgpu_pmops_prepare,
1661 .complete = amdgpu_pmops_complete,
1662 .suspend = amdgpu_pmops_suspend,
1663 .resume = amdgpu_pmops_resume,
1664 .freeze = amdgpu_pmops_freeze,
1665 .thaw = amdgpu_pmops_thaw,
1666 .poweroff = amdgpu_pmops_poweroff,
1667 .restore = amdgpu_pmops_restore,
1668 .runtime_suspend = amdgpu_pmops_runtime_suspend,
1669 .runtime_resume = amdgpu_pmops_runtime_resume,
1670 .runtime_idle = amdgpu_pmops_runtime_idle,
1671 };
1672
amdgpu_flush(struct file * f,fl_owner_t id)1673 static int amdgpu_flush(struct file *f, fl_owner_t id)
1674 {
1675 struct drm_file *file_priv = f->private_data;
1676 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1677 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
1678
1679 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
1680 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
1681
1682 return timeout >= 0 ? 0 : timeout;
1683 }
1684
1685 static const struct file_operations amdgpu_driver_kms_fops = {
1686 .owner = THIS_MODULE,
1687 .open = drm_open,
1688 .flush = amdgpu_flush,
1689 .release = drm_release,
1690 .unlocked_ioctl = amdgpu_drm_ioctl,
1691 .mmap = amdgpu_mmap,
1692 .poll = drm_poll,
1693 .read = drm_read,
1694 #ifdef CONFIG_COMPAT
1695 .compat_ioctl = amdgpu_kms_compat_ioctl,
1696 #endif
1697 };
1698
amdgpu_file_to_fpriv(struct file * filp,struct amdgpu_fpriv ** fpriv)1699 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
1700 {
1701 struct drm_file *file;
1702
1703 if (!filp)
1704 return -EINVAL;
1705
1706 if (filp->f_op != &amdgpu_driver_kms_fops) {
1707 return -EINVAL;
1708 }
1709
1710 file = filp->private_data;
1711 *fpriv = file->driver_priv;
1712 return 0;
1713 }
1714
1715 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1716 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1717 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1718 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1719 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1720 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1721 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1722 /* KMS */
1723 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1724 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1725 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1726 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1727 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1728 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1729 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1730 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1731 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1732 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1733 };
1734
1735 static const struct drm_driver amdgpu_kms_driver = {
1736 .driver_features =
1737 DRIVER_ATOMIC |
1738 DRIVER_GEM |
1739 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
1740 DRIVER_SYNCOBJ_TIMELINE,
1741 .open = amdgpu_driver_open_kms,
1742 .postclose = amdgpu_driver_postclose_kms,
1743 .lastclose = amdgpu_driver_lastclose_kms,
1744 .irq_handler = amdgpu_irq_handler,
1745 .ioctls = amdgpu_ioctls_kms,
1746 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
1747 .dumb_create = amdgpu_mode_dumb_create,
1748 .dumb_map_offset = amdgpu_mode_dumb_mmap,
1749 .fops = &amdgpu_driver_kms_fops,
1750
1751 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1752 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1753 .gem_prime_import = amdgpu_gem_prime_import,
1754 .gem_prime_mmap = amdgpu_gem_prime_mmap,
1755
1756 .name = DRIVER_NAME,
1757 .desc = DRIVER_DESC,
1758 .date = DRIVER_DATE,
1759 .major = KMS_DRIVER_MAJOR,
1760 .minor = KMS_DRIVER_MINOR,
1761 .patchlevel = KMS_DRIVER_PATCHLEVEL,
1762 };
1763
1764 static struct pci_error_handlers amdgpu_pci_err_handler = {
1765 .error_detected = amdgpu_pci_error_detected,
1766 .mmio_enabled = amdgpu_pci_mmio_enabled,
1767 .slot_reset = amdgpu_pci_slot_reset,
1768 .resume = amdgpu_pci_resume,
1769 };
1770
1771 static struct pci_driver amdgpu_kms_pci_driver = {
1772 .name = DRIVER_NAME,
1773 .id_table = pciidlist,
1774 .probe = amdgpu_pci_probe,
1775 .remove = amdgpu_pci_remove,
1776 .shutdown = amdgpu_pci_shutdown,
1777 .driver.pm = &amdgpu_pm_ops,
1778 .err_handler = &amdgpu_pci_err_handler,
1779 };
1780
amdgpu_init(void)1781 static int __init amdgpu_init(void)
1782 {
1783 int r;
1784
1785 if (vgacon_text_force()) {
1786 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
1787 return -EINVAL;
1788 }
1789
1790 r = amdgpu_sync_init();
1791 if (r)
1792 goto error_sync;
1793
1794 r = amdgpu_fence_slab_init();
1795 if (r)
1796 goto error_fence;
1797
1798 DRM_INFO("amdgpu kernel modesetting enabled.\n");
1799 amdgpu_register_atpx_handler();
1800
1801 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
1802 amdgpu_amdkfd_init();
1803
1804 /* let modprobe override vga console setting */
1805 return pci_register_driver(&amdgpu_kms_pci_driver);
1806
1807 error_fence:
1808 amdgpu_sync_fini();
1809
1810 error_sync:
1811 return r;
1812 }
1813
amdgpu_exit(void)1814 static void __exit amdgpu_exit(void)
1815 {
1816 amdgpu_amdkfd_fini();
1817 pci_unregister_driver(&amdgpu_kms_pci_driver);
1818 amdgpu_unregister_atpx_handler();
1819 amdgpu_sync_fini();
1820 amdgpu_fence_slab_fini();
1821 mmu_notifier_synchronize();
1822 }
1823
1824 module_init(amdgpu_init);
1825 module_exit(amdgpu_exit);
1826
1827 MODULE_AUTHOR(DRIVER_AUTHOR);
1828 MODULE_DESCRIPTION(DRIVER_DESC);
1829 MODULE_LICENSE("GPL and additional rights");
1830