1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DAL_DC_DCN30_CLK_MGR_SMU_MSG_H_ 27 #define DAL_DC_DCN30_CLK_MGR_SMU_MSG_H_ 28 29 #include "core_types.h" 30 31 #define SMU11_DRIVER_IF_VERSION 0x1F 32 33 typedef enum { 34 PPCLK_GFXCLK = 0, 35 PPCLK_SOCCLK, 36 PPCLK_UCLK, 37 PPCLK_FCLK, 38 PPCLK_DCLK_0, 39 PPCLK_VCLK_0, 40 PPCLK_DCLK_1, 41 PPCLK_VCLK_1, 42 PPCLK_DCEFCLK, 43 PPCLK_DISPCLK, 44 PPCLK_PIXCLK, 45 PPCLK_PHYCLK, 46 PPCLK_DTBCLK, 47 PPCLK_COUNT, 48 } PPCLK_e; 49 50 typedef struct { 51 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) 52 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) 53 uint16_t MinUclk; 54 uint16_t MaxUclk; 55 56 uint8_t WmSetting; 57 uint8_t Flags; 58 uint8_t Padding[2]; 59 60 } WatermarkRowGeneric_t; 61 62 #define NUM_WM_RANGES 4 63 64 typedef enum { 65 WM_SOCCLK = 0, 66 WM_DCEFCLK, 67 WM_COUNT, 68 } WM_CLOCK_e; 69 70 typedef enum { 71 WATERMARKS_CLOCK_RANGE = 0, 72 WATERMARKS_DUMMY_PSTATE, 73 WATERMARKS_MALL, 74 WATERMARKS_COUNT, 75 } WATERMARKS_FLAGS_e; 76 77 typedef struct { 78 // Watermarks 79 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 80 } Watermarks_t; 81 82 typedef struct { 83 Watermarks_t Watermarks; 84 85 uint32_t MmHubPadding[8]; // SMU internal use 86 } WatermarksExternal_t; 87 88 #define TABLE_WATERMARKS 1 89 90 struct clk_mgr_internal; 91 92 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input); 93 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version); 94 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr); 95 bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr); 96 void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); 97 void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low); 98 void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr); 99 void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); 100 unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz); 101 unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz); 102 unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint8_t dpm_level); 103 unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk); 104 void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz); 105 void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays); 106 void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale); 107 void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable); 108 void dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr); 109 110 #endif /* DAL_DC_DCN30_CLK_MGR_SMU_MSG_H_ */ 111