1 /*
2  * Copyright (C) 2020  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef _dcn_3_0_1_OFFSET_HEADER
22 #define _dcn_3_0_1_OFFSET_HEADER
23 
24 
25 
26 // addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
27 // base address: 0x48
28 #define mmVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
29 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
30 #define mmVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
31 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
32 
33 
34 // addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
35 // base address: 0x3b4
36 #define mmCRTC8_IDX                                                                                    0x002d
37 #define mmCRTC8_IDX_BASE_IDX                                                                           1
38 #define mmCRTC8_DATA                                                                                   0x002d
39 #define mmCRTC8_DATA_BASE_IDX                                                                          1
40 #define mmGENFC_WT                                                                                     0x002e
41 #define mmGENFC_WT_BASE_IDX                                                                            1
42 #define mmGENS1                                                                                        0x002e
43 #define mmGENS1_BASE_IDX                                                                               1
44 #define mmATTRDW                                                                                       0x0030
45 #define mmATTRDW_BASE_IDX                                                                              1
46 #define mmATTRX                                                                                        0x0030
47 #define mmATTRX_BASE_IDX                                                                               1
48 #define mmATTRDR                                                                                       0x0030
49 #define mmATTRDR_BASE_IDX                                                                              1
50 #define mmGENMO_WT                                                                                     0x0030
51 #define mmGENMO_WT_BASE_IDX                                                                            1
52 #define mmGENS0                                                                                        0x0030
53 #define mmGENS0_BASE_IDX                                                                               1
54 #define mmGENENB                                                                                       0x0030
55 #define mmGENENB_BASE_IDX                                                                              1
56 #define mmSEQ8_IDX                                                                                     0x0031
57 #define mmSEQ8_IDX_BASE_IDX                                                                            1
58 #define mmSEQ8_DATA                                                                                    0x0031
59 #define mmSEQ8_DATA_BASE_IDX                                                                           1
60 #define mmDAC_MASK                                                                                     0x0031
61 #define mmDAC_MASK_BASE_IDX                                                                            1
62 #define mmDAC_R_INDEX                                                                                  0x0031
63 #define mmDAC_R_INDEX_BASE_IDX                                                                         1
64 #define mmDAC_W_INDEX                                                                                  0x0032
65 #define mmDAC_W_INDEX_BASE_IDX                                                                         1
66 #define mmDAC_DATA                                                                                     0x0032
67 #define mmDAC_DATA_BASE_IDX                                                                            1
68 #define mmGENFC_RD                                                                                     0x0032
69 #define mmGENFC_RD_BASE_IDX                                                                            1
70 #define mmGENMO_RD                                                                                     0x0033
71 #define mmGENMO_RD_BASE_IDX                                                                            1
72 #define mmGRPH8_IDX                                                                                    0x0033
73 #define mmGRPH8_IDX_BASE_IDX                                                                           1
74 #define mmGRPH8_DATA                                                                                   0x0033
75 #define mmGRPH8_DATA_BASE_IDX                                                                          1
76 #define mmCRTC8_IDX_1                                                                                  0x0035
77 #define mmCRTC8_IDX_1_BASE_IDX                                                                         1
78 #define mmCRTC8_DATA_1                                                                                 0x0035
79 #define mmCRTC8_DATA_1_BASE_IDX                                                                        1
80 #define mmGENFC_WT_1                                                                                   0x0036
81 #define mmGENFC_WT_1_BASE_IDX                                                                          1
82 #define mmGENS1_1                                                                                      0x0036
83 #define mmGENS1_1_BASE_IDX                                                                             1
84 
85 
86 // addressBlock: dce_dc_hda_azcontroller_azdec
87 // base address: 0x0
88 #define mmCORB_WRITE_POINTER                                                                           0x0000
89 #define mmCORB_WRITE_POINTER_BASE_IDX                                                                  0
90 #define mmCORB_READ_POINTER                                                                            0x0000
91 #define mmCORB_READ_POINTER_BASE_IDX                                                                   0
92 #define mmCORB_CONTROL                                                                                 0x0001
93 #define mmCORB_CONTROL_BASE_IDX                                                                        0
94 #define mmCORB_STATUS                                                                                  0x0001
95 #define mmCORB_STATUS_BASE_IDX                                                                         0
96 #define mmCORB_SIZE                                                                                    0x0001
97 #define mmCORB_SIZE_BASE_IDX                                                                           0
98 #define mmRIRB_LOWER_BASE_ADDRESS                                                                      0x0002
99 #define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX                                                             0
100 #define mmRIRB_UPPER_BASE_ADDRESS                                                                      0x0003
101 #define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX                                                             0
102 #define mmRIRB_WRITE_POINTER                                                                           0x0004
103 #define mmRIRB_WRITE_POINTER_BASE_IDX                                                                  0
104 #define mmRESPONSE_INTERRUPT_COUNT                                                                     0x0004
105 #define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX                                                            0
106 #define mmRIRB_CONTROL                                                                                 0x0005
107 #define mmRIRB_CONTROL_BASE_IDX                                                                        0
108 #define mmRIRB_STATUS                                                                                  0x0005
109 #define mmRIRB_STATUS_BASE_IDX                                                                         0
110 #define mmRIRB_SIZE                                                                                    0x0005
111 #define mmRIRB_SIZE_BASE_IDX                                                                           0
112 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                                           0x0006
113 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                                  0
114 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                                      0x0006
115 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                             0
116 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                                     0x0006
117 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                            0
118 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE                                                           0x0007
119 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                                  0
120 #define mmIMMEDIATE_COMMAND_STATUS                                                                     0x0008
121 #define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX                                                            0
122 #define mmDMA_POSITION_LOWER_BASE_ADDRESS                                                              0x000a
123 #define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                                     0
124 #define mmDMA_POSITION_UPPER_BASE_ADDRESS                                                              0x000b
125 #define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                                     0
126 #define mmWALL_CLOCK_COUNTER_ALIAS                                                                     0x074c
127 #define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                                            1
128 
129 
130 // addressBlock: dce_dc_hda_azendpoint_azdec
131 // base address: 0x0
132 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                           0x0006
133 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                  0
134 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                          0x0006
135 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                 0
136 
137 
138 // addressBlock: dce_dc_hda_azinputendpoint_azdec
139 // base address: 0x0
140 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                                            0x0006
141 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                                   0
142 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                                           0x0006
143 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                                  0
144 
145 
146 // addressBlock: dce_dc_mmhubbub_vga_dispdec
147 // base address: 0x0
148 #define mmVGA_RENDER_CONTROL                                                                           0x0000
149 #define mmVGA_RENDER_CONTROL_BASE_IDX                                                                  1
150 #define mmVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
151 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
152 #define mmVGA_MODE_CONTROL                                                                             0x0002
153 #define mmVGA_MODE_CONTROL_BASE_IDX                                                                    1
154 #define mmVGA_SURFACE_PITCH_SELECT                                                                     0x0003
155 #define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
156 #define mmVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
157 #define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
158 #define mmVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
159 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
160 #define mmVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
161 #define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
162 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
163 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
164 #define mmVGA_HDP_CONTROL                                                                              0x000a
165 #define mmVGA_HDP_CONTROL_BASE_IDX                                                                     1
166 #define mmVGA_CACHE_CONTROL                                                                            0x000b
167 #define mmVGA_CACHE_CONTROL_BASE_IDX                                                                   1
168 #define mmD1VGA_CONTROL                                                                                0x000c
169 #define mmD1VGA_CONTROL_BASE_IDX                                                                       1
170 #define mmD2VGA_CONTROL                                                                                0x000e
171 #define mmD2VGA_CONTROL_BASE_IDX                                                                       1
172 #define mmVGA_STATUS                                                                                   0x0010
173 #define mmVGA_STATUS_BASE_IDX                                                                          1
174 #define mmVGA_INTERRUPT_CONTROL                                                                        0x0011
175 #define mmVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
176 #define mmVGA_STATUS_CLEAR                                                                             0x0012
177 #define mmVGA_STATUS_CLEAR_BASE_IDX                                                                    1
178 #define mmVGA_INTERRUPT_STATUS                                                                         0x0013
179 #define mmVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
180 #define mmVGA_MAIN_CONTROL                                                                             0x0014
181 #define mmVGA_MAIN_CONTROL_BASE_IDX                                                                    1
182 #define mmVGA_TEST_CONTROL                                                                             0x0015
183 #define mmVGA_TEST_CONTROL_BASE_IDX                                                                    1
184 #define mmVGA_QOS_CTRL                                                                                 0x0018
185 #define mmVGA_QOS_CTRL_BASE_IDX                                                                        1
186 #define mmD3VGA_CONTROL                                                                                0x0038
187 #define mmD3VGA_CONTROL_BASE_IDX                                                                       1
188 #define mmD4VGA_CONTROL                                                                                0x0039
189 #define mmD4VGA_CONTROL_BASE_IDX                                                                       1
190 #define mmD5VGA_CONTROL                                                                                0x003a
191 #define mmD5VGA_CONTROL_BASE_IDX                                                                       1
192 #define mmD6VGA_CONTROL                                                                                0x003b
193 #define mmD6VGA_CONTROL_BASE_IDX                                                                       1
194 #define mmVGA_SOURCE_SELECT                                                                            0x003c
195 #define mmVGA_SOURCE_SELECT_BASE_IDX                                                                   1
196 
197 
198 // addressBlock: dce_dc_dccg_dccg_dispdec
199 // base address: 0x0
200 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
201 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
202 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
203 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
204 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
205 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
206 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
207 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
208 #define mmDP_DTO_DBUF_EN                                                                               0x0044
209 #define mmDP_DTO_DBUF_EN_BASE_IDX                                                                      1
210 #define mmDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
211 #define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
212 #define mmREFCLK_CNTL                                                                                  0x0049
213 #define mmREFCLK_CNTL_BASE_IDX                                                                         1
214 #define mmREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
215 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
216 #define mmDCCG_PERFMON_CNTL2                                                                           0x004e
217 #define mmDCCG_PERFMON_CNTL2_BASE_IDX                                                                  1
218 #define mmDCCG_DS_DTO_INCR                                                                             0x0053
219 #define mmDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
220 #define mmDCCG_DS_DTO_MODULO                                                                           0x0054
221 #define mmDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
222 #define mmDCCG_DS_CNTL                                                                                 0x0055
223 #define mmDCCG_DS_CNTL_BASE_IDX                                                                        1
224 #define mmDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
225 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
226 #define mmDPREFCLK_CNTL                                                                                0x0058
227 #define mmDPREFCLK_CNTL_BASE_IDX                                                                       1
228 #define mmDCE_VERSION                                                                                  0x005e
229 #define mmDCE_VERSION_BASE_IDX                                                                         1
230 #define mmDCCG_GTC_CNTL                                                                                0x0060
231 #define mmDCCG_GTC_CNTL_BASE_IDX                                                                       1
232 #define mmDCCG_GTC_DTO_INCR                                                                            0x0061
233 #define mmDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
234 #define mmDCCG_GTC_DTO_MODULO                                                                          0x0062
235 #define mmDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
236 #define mmDCCG_GTC_CURRENT                                                                             0x0063
237 #define mmDCCG_GTC_CURRENT_BASE_IDX                                                                    1
238 #define mmDSCCLK0_DTO_PARAM                                                                            0x006c
239 #define mmDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
240 #define mmDSCCLK1_DTO_PARAM                                                                            0x006d
241 #define mmDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
242 #define mmDSCCLK2_DTO_PARAM                                                                            0x006e
243 #define mmDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
244 #define mmMILLISECOND_TIME_BASE_DIV                                                                    0x0070
245 #define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
246 #define mmDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
247 #define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
248 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
249 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
250 #define mmDCCG_PERFMON_CNTL                                                                            0x0073
251 #define mmDCCG_PERFMON_CNTL_BASE_IDX                                                                   1
252 #define mmDCCG_GATE_DISABLE_CNTL                                                                       0x0074
253 #define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
254 #define mmDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
255 #define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
256 #define mmSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
257 #define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
258 #define mmDCCG_CAC_STATUS                                                                              0x0077
259 #define mmDCCG_CAC_STATUS_BASE_IDX                                                                     1
260 #define mmMICROSECOND_TIME_BASE_DIV                                                                    0x007b
261 #define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
262 #define mmDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
263 #define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
264 #define mmSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
265 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
266 #define mmDCCG_DISP_CNTL_REG                                                                           0x007f
267 #define mmDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
268 #define mmOTG0_PIXEL_RATE_CNTL                                                                         0x0080
269 #define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
270 #define mmDP_DTO0_PHASE                                                                                0x0081
271 #define mmDP_DTO0_PHASE_BASE_IDX                                                                       1
272 #define mmDP_DTO0_MODULO                                                                               0x0082
273 #define mmDP_DTO0_MODULO_BASE_IDX                                                                      1
274 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
275 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
276 #define mmOTG1_PIXEL_RATE_CNTL                                                                         0x0084
277 #define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
278 #define mmDP_DTO1_PHASE                                                                                0x0085
279 #define mmDP_DTO1_PHASE_BASE_IDX                                                                       1
280 #define mmDP_DTO1_MODULO                                                                               0x0086
281 #define mmDP_DTO1_MODULO_BASE_IDX                                                                      1
282 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
283 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
284 #define mmOTG2_PIXEL_RATE_CNTL                                                                         0x0088
285 #define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
286 #define mmDP_DTO2_PHASE                                                                                0x0089
287 #define mmDP_DTO2_PHASE_BASE_IDX                                                                       1
288 #define mmDP_DTO2_MODULO                                                                               0x008a
289 #define mmDP_DTO2_MODULO_BASE_IDX                                                                      1
290 #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
291 #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
292 #define mmOTG3_PIXEL_RATE_CNTL                                                                         0x008c
293 #define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
294 #define mmDP_DTO3_PHASE                                                                                0x008d
295 #define mmDP_DTO3_PHASE_BASE_IDX                                                                       1
296 #define mmDP_DTO3_MODULO                                                                               0x008e
297 #define mmDP_DTO3_MODULO_BASE_IDX                                                                      1
298 #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
299 #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
300 #define mmDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
301 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
302 #define mmDPPCLK0_DTO_PARAM                                                                            0x0099
303 #define mmDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
304 #define mmDPPCLK1_DTO_PARAM                                                                            0x009a
305 #define mmDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
306 #define mmDPPCLK2_DTO_PARAM                                                                            0x009b
307 #define mmDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
308 #define mmDPPCLK3_DTO_PARAM                                                                            0x009c
309 #define mmDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
310 #define mmDCCG_CAC_STATUS2                                                                             0x009f
311 #define mmDCCG_CAC_STATUS2_BASE_IDX                                                                    1
312 #define mmSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
313 #define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
314 #define mmSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
315 #define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
316 #define mmSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
317 #define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
318 #define mmSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
319 #define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
320 #define mmDCCG_SOFT_RESET                                                                              0x00a6
321 #define mmDCCG_SOFT_RESET_BASE_IDX                                                                     1
322 #define mmDSCCLK_DTO_CTRL                                                                              0x00a7
323 #define mmDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
324 #define mmDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
325 #define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
326 #define mmDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
327 #define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
328 #define mmDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
329 #define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
330 #define mmDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
331 #define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
332 #define mmDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
333 #define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
334 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
335 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
336 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
337 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
338 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
339 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
340 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
341 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
342 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
343 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
344 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
345 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
346 #define mmDPPCLK_DTO_CTRL                                                                              0x00b6
347 #define mmDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
348 #define mmDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
349 #define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
350 #define mmDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
351 #define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
352 #define mmFORCE_SYMCLK_DISABLE                                                                         0x00ba
353 #define mmFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
354 #define mmPHYASYMCLK_CLOCK_CNTL                                                                        0x0052
355 #define mmPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
356 #define mmPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053
357 #define mmPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
358 #define mmPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054
359 #define mmPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
360 #define mmPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055
361 #define mmPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
362 
363 
364 // addressBlock: dce_dc_dccg_dccg_dfs_dispdec
365 // base address: 0x0
366 #define mmDENTIST_DISPCLK_CNTL                                                                         0x0064
367 #define mmDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
368 
369 
370 // addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
371 // base address: 0x0
372 #define mmDC_PERFMON0_PERFCOUNTER_CNTL                                                                 0x0000
373 #define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX                                                        2
374 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2                                                                0x0001
375 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
376 #define mmDC_PERFMON0_PERFCOUNTER_STATE                                                                0x0002
377 #define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX                                                       2
378 #define mmDC_PERFMON0_PERFMON_CNTL                                                                     0x0003
379 #define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX                                                            2
380 #define mmDC_PERFMON0_PERFMON_CNTL2                                                                    0x0004
381 #define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX                                                           2
382 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                                          0x0005
383 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
384 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW                                                               0x0006
385 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
386 #define mmDC_PERFMON0_PERFMON_HI                                                                       0x0007
387 #define mmDC_PERFMON0_PERFMON_HI_BASE_IDX                                                              2
388 #define mmDC_PERFMON0_PERFMON_LOW                                                                      0x0008
389 #define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX                                                             2
390 
391 
392 // addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
393 // base address: 0x30
394 #define mmDC_PERFMON1_PERFCOUNTER_CNTL                                                                 0x000c
395 #define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX                                                        2
396 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2                                                                0x000d
397 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
398 #define mmDC_PERFMON1_PERFCOUNTER_STATE                                                                0x000e
399 #define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX                                                       2
400 #define mmDC_PERFMON1_PERFMON_CNTL                                                                     0x000f
401 #define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX                                                            2
402 #define mmDC_PERFMON1_PERFMON_CNTL2                                                                    0x0010
403 #define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX                                                           2
404 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                                          0x0011
405 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
406 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW                                                               0x0012
407 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
408 #define mmDC_PERFMON1_PERFMON_HI                                                                       0x0013
409 #define mmDC_PERFMON1_PERFMON_HI_BASE_IDX                                                              2
410 #define mmDC_PERFMON1_PERFMON_LOW                                                                      0x0014
411 #define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX                                                             2
412 
413 
414 // addressBlock: dce_dc_dmu_dc_pg_dispdec
415 // base address: 0x0
416 #define mmDOMAIN0_PG_CONFIG                                                                            0x0080
417 #define mmDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
418 #define mmDOMAIN0_PG_STATUS                                                                            0x0081
419 #define mmDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
420 #define mmDOMAIN1_PG_CONFIG                                                                            0x0082
421 #define mmDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
422 #define mmDOMAIN1_PG_STATUS                                                                            0x0083
423 #define mmDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
424 #define mmDOMAIN2_PG_CONFIG                                                                            0x0084
425 #define mmDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
426 #define mmDOMAIN2_PG_STATUS                                                                            0x0085
427 #define mmDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
428 #define mmDOMAIN3_PG_CONFIG                                                                            0x0086
429 #define mmDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
430 #define mmDOMAIN3_PG_STATUS                                                                            0x0087
431 #define mmDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
432 #define mmDOMAIN4_PG_CONFIG                                                                            0x0088
433 #define mmDOMAIN4_PG_CONFIG_BASE_IDX                                                                   2
434 #define mmDOMAIN4_PG_STATUS                                                                            0x0089
435 #define mmDOMAIN4_PG_STATUS_BASE_IDX                                                                   2
436 #define mmDOMAIN5_PG_CONFIG                                                                            0x008a
437 #define mmDOMAIN5_PG_CONFIG_BASE_IDX                                                                   2
438 #define mmDOMAIN5_PG_STATUS                                                                            0x008b
439 #define mmDOMAIN5_PG_STATUS_BASE_IDX                                                                   2
440 #define mmDOMAIN6_PG_CONFIG                                                                            0x008c
441 #define mmDOMAIN6_PG_CONFIG_BASE_IDX                                                                   2
442 #define mmDOMAIN6_PG_STATUS                                                                            0x008d
443 #define mmDOMAIN6_PG_STATUS_BASE_IDX                                                                   2
444 #define mmDOMAIN7_PG_CONFIG                                                                            0x008e
445 #define mmDOMAIN7_PG_CONFIG_BASE_IDX                                                                   2
446 #define mmDOMAIN7_PG_STATUS                                                                            0x008f
447 #define mmDOMAIN7_PG_STATUS_BASE_IDX                                                                   2
448 #define mmDOMAIN16_PG_CONFIG                                                                           0x00a1
449 #define mmDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
450 #define mmDOMAIN16_PG_STATUS                                                                           0x00a2
451 #define mmDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
452 #define mmDOMAIN17_PG_CONFIG                                                                           0x00a3
453 #define mmDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
454 #define mmDOMAIN17_PG_STATUS                                                                           0x00a4
455 #define mmDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
456 #define mmDOMAIN18_PG_CONFIG                                                                           0x00a5
457 #define mmDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
458 #define mmDOMAIN18_PG_STATUS                                                                           0x00a6
459 #define mmDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
460 #define mmDCPG_INTERRUPT_STATUS                                                                        0x00ad
461 #define mmDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
462 #define mmDCPG_INTERRUPT_STATUS_2                                                                      0x00ae
463 #define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
464 #define mmDCPG_INTERRUPT_CONTROL_1                                                                     0x00af
465 #define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
466 #define mmDCPG_INTERRUPT_CONTROL_2                                                                     0x00b0
467 #define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX                                                            2
468 #define mmDCPG_INTERRUPT_CONTROL_3                                                                     0x00b1
469 #define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
470 #define mmDC_IP_REQUEST_CNTL                                                                           0x00b2
471 #define mmDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
472 
473 
474 // addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
475 // base address: 0x2f8
476 #define mmDC_PERFMON2_PERFCOUNTER_CNTL                                                                 0x00be
477 #define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX                                                        2
478 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2                                                                0x00bf
479 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
480 #define mmDC_PERFMON2_PERFCOUNTER_STATE                                                                0x00c0
481 #define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX                                                       2
482 #define mmDC_PERFMON2_PERFMON_CNTL                                                                     0x00c1
483 #define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX                                                            2
484 #define mmDC_PERFMON2_PERFMON_CNTL2                                                                    0x00c2
485 #define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX                                                           2
486 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                                          0x00c3
487 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
488 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW                                                               0x00c4
489 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
490 #define mmDC_PERFMON2_PERFMON_HI                                                                       0x00c5
491 #define mmDC_PERFMON2_PERFMON_HI_BASE_IDX                                                              2
492 #define mmDC_PERFMON2_PERFMON_LOW                                                                      0x00c6
493 #define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX                                                             2
494 
495 
496 // addressBlock: dce_dc_dmu_dmu_misc_dispdec
497 // base address: 0x0
498 #define mmCC_DC_PIPE_DIS                                                                               0x00ca
499 #define mmCC_DC_PIPE_DIS_BASE_IDX                                                                      2
500 #define mmDMU_CLK_CNTL                                                                                 0x00cb
501 #define mmDMU_CLK_CNTL_BASE_IDX                                                                        2
502 #define mmDMU_MEM_PWR_CNTL                                                                             0x00cc
503 #define mmDMU_MEM_PWR_CNTL_BASE_IDX                                                                    2
504 #define mmDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
505 #define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
506 
507 
508 // addressBlock: dce_dc_dmu_dmcu_dispdec
509 // base address: 0x0
510 #define mmDMCU_CTRL                                                                                    0x00da
511 #define mmDMCU_CTRL_BASE_IDX                                                                           2
512 #define mmDMCU_STATUS                                                                                  0x00db
513 #define mmDMCU_STATUS_BASE_IDX                                                                         2
514 #define mmDMCU_PC_START_ADDR                                                                           0x00dc
515 #define mmDMCU_PC_START_ADDR_BASE_IDX                                                                  2
516 #define mmDMCU_FW_START_ADDR                                                                           0x00dd
517 #define mmDMCU_FW_START_ADDR_BASE_IDX                                                                  2
518 #define mmDMCU_FW_END_ADDR                                                                             0x00de
519 #define mmDMCU_FW_END_ADDR_BASE_IDX                                                                    2
520 #define mmDMCU_FW_ISR_START_ADDR                                                                       0x00df
521 #define mmDMCU_FW_ISR_START_ADDR_BASE_IDX                                                              2
522 #define mmDMCU_FW_CS_HI                                                                                0x00e0
523 #define mmDMCU_FW_CS_HI_BASE_IDX                                                                       2
524 #define mmDMCU_FW_CS_LO                                                                                0x00e1
525 #define mmDMCU_FW_CS_LO_BASE_IDX                                                                       2
526 #define mmDMCU_RAM_ACCESS_CTRL                                                                         0x00e2
527 #define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX                                                                2
528 #define mmDMCU_ERAM_WR_CTRL                                                                            0x00e3
529 #define mmDMCU_ERAM_WR_CTRL_BASE_IDX                                                                   2
530 #define mmDMCU_ERAM_WR_DATA                                                                            0x00e4
531 #define mmDMCU_ERAM_WR_DATA_BASE_IDX                                                                   2
532 #define mmDMCU_ERAM_RD_CTRL                                                                            0x00e5
533 #define mmDMCU_ERAM_RD_CTRL_BASE_IDX                                                                   2
534 #define mmDMCU_ERAM_RD_DATA                                                                            0x00e6
535 #define mmDMCU_ERAM_RD_DATA_BASE_IDX                                                                   2
536 #define mmDMCU_IRAM_WR_CTRL                                                                            0x00e7
537 #define mmDMCU_IRAM_WR_CTRL_BASE_IDX                                                                   2
538 #define mmDMCU_IRAM_WR_DATA                                                                            0x00e8
539 #define mmDMCU_IRAM_WR_DATA_BASE_IDX                                                                   2
540 #define mmDMCU_IRAM_RD_CTRL                                                                            0x00e9
541 #define mmDMCU_IRAM_RD_CTRL_BASE_IDX                                                                   2
542 #define mmDMCU_IRAM_RD_DATA                                                                            0x00ea
543 #define mmDMCU_IRAM_RD_DATA_BASE_IDX                                                                   2
544 #define mmDMCU_EVENT_TRIGGER                                                                           0x00eb
545 #define mmDMCU_EVENT_TRIGGER_BASE_IDX                                                                  2
546 #define mmDMCU_UC_INTERNAL_INT_STATUS                                                                  0x00ec
547 #define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX                                                         2
548 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS                                                                0x00ed
549 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX                                                       2
550 #define mmDMCU_INTERRUPT_STATUS                                                                        0x00ee
551 #define mmDMCU_INTERRUPT_STATUS_BASE_IDX                                                               2
552 #define mmDMCU_INTERRUPT_STATUS_1                                                                      0x00ef
553 #define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX                                                             2
554 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                                               0x00f0
555 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX                                                      2
556 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK                                                                 0x00f1
557 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2
558 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1                                                               0x00f2
559 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX                                                      2
560 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                                            0x00f3
561 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2
562 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1                                                          0x00f4
563 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX                                                 2
564 #define mmDC_DMCU_SCRATCH                                                                              0x00f5
565 #define mmDC_DMCU_SCRATCH_BASE_IDX                                                                     2
566 #define mmDMCU_INT_CNT                                                                                 0x00f6
567 #define mmDMCU_INT_CNT_BASE_IDX                                                                        2
568 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                                               0x00f7
569 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX                                                      2
570 #define mmDMCU_UC_CLK_GATING_CNTL                                                                      0x00f8
571 #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2
572 #define mmMASTER_COMM_DATA_REG1                                                                        0x00f9
573 #define mmMASTER_COMM_DATA_REG1_BASE_IDX                                                               2
574 #define mmMASTER_COMM_DATA_REG2                                                                        0x00fa
575 #define mmMASTER_COMM_DATA_REG2_BASE_IDX                                                               2
576 #define mmMASTER_COMM_DATA_REG3                                                                        0x00fb
577 #define mmMASTER_COMM_DATA_REG3_BASE_IDX                                                               2
578 #define mmMASTER_COMM_CMD_REG                                                                          0x00fc
579 #define mmMASTER_COMM_CMD_REG_BASE_IDX                                                                 2
580 #define mmMASTER_COMM_CNTL_REG                                                                         0x00fd
581 #define mmMASTER_COMM_CNTL_REG_BASE_IDX                                                                2
582 #define mmSLAVE_COMM_DATA_REG1                                                                         0x00fe
583 #define mmSLAVE_COMM_DATA_REG1_BASE_IDX                                                                2
584 #define mmSLAVE_COMM_DATA_REG2                                                                         0x00ff
585 #define mmSLAVE_COMM_DATA_REG2_BASE_IDX                                                                2
586 #define mmSLAVE_COMM_DATA_REG3                                                                         0x0100
587 #define mmSLAVE_COMM_DATA_REG3_BASE_IDX                                                                2
588 #define mmSLAVE_COMM_CMD_REG                                                                           0x0101
589 #define mmSLAVE_COMM_CMD_REG_BASE_IDX                                                                  2
590 #define mmSLAVE_COMM_CNTL_REG                                                                          0x0102
591 #define mmSLAVE_COMM_CNTL_REG_BASE_IDX                                                                 2
592 #define mmDMCU_PERFMON_INTERRUPT_STATUS1                                                               0x0105
593 #define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX                                                      2
594 #define mmDMCU_PERFMON_INTERRUPT_STATUS2                                                               0x0106
595 #define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX                                                      2
596 #define mmDMCU_PERFMON_INTERRUPT_STATUS3                                                               0x0107
597 #define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX                                                      2
598 #define mmDMCU_PERFMON_INTERRUPT_STATUS4                                                               0x0108
599 #define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX                                                      2
600 #define mmDMCU_PERFMON_INTERRUPT_STATUS5                                                               0x0109
601 #define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX                                                      2
602 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                                        0x010a
603 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                               2
604 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                                        0x010b
605 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX                                               2
606 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                                        0x010c
607 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX                                               2
608 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                                        0x010d
609 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX                                               2
610 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                                        0x010e
611 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX                                               2
612 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                   0x010f
613 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                          2
614 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                                                   0x0110
615 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX                                          2
616 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                                                   0x0111
617 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX                                          2
618 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                                                   0x0112
619 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX                                          2
620 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                                                   0x0113
621 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX                                          2
622 #define mmDMCU_DPRX_INTERRUPT_STATUS1                                                                  0x0114
623 #define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX                                                         2
624 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                                           0x0115
625 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                                  2
626 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                      0x0116
627 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                             2
628 #define mmDMCU_INTERRUPT_STATUS_CONTINUE                                                               0x0119
629 #define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
630 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE                                                        0x011a
631 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX                                               2
632 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE                                                   0x011b
633 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX                                          2
634 #define mmDMCU_INT_CNT_CONTINUE                                                                        0x011c
635 #define mmDMCU_INT_CNT_CONTINUE_BASE_IDX                                                               2
636 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2                                                      0x011d
637 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX                                             2
638 #define mmDMCU_INTERRUPT_STATUS_2                                                                      0x011e
639 #define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX                                                             2
640 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2                                                               0x011f
641 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX                                                      2
642 #define mmDMCU_INT_CNT_CONT2                                                                           0x0120
643 #define mmDMCU_INT_CNT_CONT2_BASE_IDX                                                                  2
644 #define mmDMCU_INT_CNT_CONT3                                                                           0x0121
645 #define mmDMCU_INT_CNT_CONT3_BASE_IDX                                                                  2
646 
647 
648 // addressBlock: dce_dc_dmu_ihc_dispdec
649 // base address: 0x0
650 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
651 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
652 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
653 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
654 #define mmDC_GPU_TIMER_READ                                                                            0x0128
655 #define mmDC_GPU_TIMER_READ_BASE_IDX                                                                   2
656 #define mmDC_GPU_TIMER_READ_CNTL                                                                       0x0129
657 #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
658 #define mmDISP_INTERRUPT_STATUS                                                                        0x012a
659 #define mmDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
660 #define mmDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
661 #define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
662 #define mmDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
663 #define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
664 #define mmDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
665 #define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
666 #define mmDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
667 #define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
668 #define mmDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
669 #define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
670 #define mmDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
671 #define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
672 #define mmDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
673 #define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
674 #define mmDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
675 #define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
676 #define mmDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
677 #define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
678 #define mmDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
679 #define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
680 #define mmDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
681 #define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
682 #define mmDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
683 #define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
684 #define mmDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
685 #define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
686 #define mmDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
687 #define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
688 #define mmDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
689 #define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
690 #define mmDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
691 #define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
692 #define mmDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
693 #define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
694 #define mmDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
695 #define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
696 #define mmDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
697 #define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
698 #define mmDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
699 #define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
700 #define mmDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
701 #define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
702 #define mmDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
703 #define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
704 #define mmDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
705 #define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
706 #define mmDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
707 #define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
708 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
709 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
710 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
711 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
712 #define mmDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
713 #define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
714 #define mmDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
715 #define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
716 #define mmDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147
717 #define mmDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2
718 #define mmDCCG_INTERRUPT_DEST                                                                          0x0148
719 #define mmDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
720 #define mmDMU_INTERRUPT_DEST                                                                           0x0149
721 #define mmDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
722 #define mmDMU_INTERRUPT_DEST2                                                                          0x014a
723 #define mmDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2
724 #define mmDCPG_INTERRUPT_DEST                                                                          0x014b
725 #define mmDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
726 #define mmDCPG_INTERRUPT_DEST2                                                                         0x014c
727 #define mmDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
728 #define mmMMHUBBUB_INTERRUPT_DEST                                                                      0x014d
729 #define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
730 #define mmWB_INTERRUPT_DEST                                                                            0x014e
731 #define mmWB_INTERRUPT_DEST_BASE_IDX                                                                   2
732 #define mmDCHUB_INTERRUPT_DEST                                                                         0x014f
733 #define mmDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
734 #define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150
735 #define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
736 #define mmDCHUB_INTERRUPT_DEST2                                                                        0x0151
737 #define mmDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
738 #define mmDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152
739 #define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
740 #define mmMPC_INTERRUPT_DEST                                                                           0x0153
741 #define mmMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
742 #define mmOPP_INTERRUPT_DEST                                                                           0x0154
743 #define mmOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
744 #define mmOPTC_INTERRUPT_DEST                                                                          0x0155
745 #define mmOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
746 #define mmOTG0_INTERRUPT_DEST                                                                          0x0156
747 #define mmOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
748 #define mmOTG1_INTERRUPT_DEST                                                                          0x0157
749 #define mmOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
750 #define mmOTG2_INTERRUPT_DEST                                                                          0x0158
751 #define mmOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
752 #define mmOTG3_INTERRUPT_DEST                                                                          0x0159
753 #define mmOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
754 #define mmOTG4_INTERRUPT_DEST                                                                          0x015a
755 #define mmOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
756 #define mmOTG5_INTERRUPT_DEST                                                                          0x015b
757 #define mmOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
758 #define mmDIG_INTERRUPT_DEST                                                                           0x015c
759 #define mmDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
760 #define mmI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d
761 #define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
762 #define mmDIO_INTERRUPT_DEST                                                                           0x015f
763 #define mmDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
764 #define mmDCIO_INTERRUPT_DEST                                                                          0x0160
765 #define mmDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
766 #define mmHPD_INTERRUPT_DEST                                                                           0x0161
767 #define mmHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
768 #define mmAZ_INTERRUPT_DEST                                                                            0x0162
769 #define mmAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
770 #define mmAUX_INTERRUPT_DEST                                                                           0x0163
771 #define mmAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
772 #define mmDSC_INTERRUPT_DEST                                                                           0x0164
773 #define mmDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
774 
775 
776 // addressBlock: dce_dc_dmu_fgsec_dispdec
777 // base address: 0x0
778 #define mmDMCUB_RBBMIF_SEC_CNTL                                                                        0x017a
779 #define mmDMCUB_RBBMIF_SEC_CNTL_BASE_IDX                                                               2
780 
781 
782 // addressBlock: dce_dc_dmu_rbbmif_dispdec
783 // base address: 0x0
784 #define mmRBBMIF_TIMEOUT                                                                               0x017f
785 #define mmRBBMIF_TIMEOUT_BASE_IDX                                                                      2
786 #define mmRBBMIF_STATUS                                                                                0x0180
787 #define mmRBBMIF_STATUS_BASE_IDX                                                                       2
788 #define mmRBBMIF_STATUS_2                                                                              0x0181
789 #define mmRBBMIF_STATUS_2_BASE_IDX                                                                     2
790 #define mmRBBMIF_INT_STATUS                                                                            0x0182
791 #define mmRBBMIF_INT_STATUS_BASE_IDX                                                                   2
792 #define mmRBBMIF_TIMEOUT_DIS                                                                           0x0183
793 #define mmRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
794 #define mmRBBMIF_TIMEOUT_DIS_2                                                                         0x0184
795 #define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
796 #define mmRBBMIF_STATUS_FLAG                                                                           0x0185
797 #define mmRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
798 
799 
800 // addressBlock: dce_dc_dmu_dmcub_dispdec
801 // base address: 0x0
802 #define mmDMCUB_REGION0_OFFSET                                                                         0x018e
803 #define mmDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
804 #define mmDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f
805 #define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
806 #define mmDMCUB_REGION1_OFFSET                                                                         0x0190
807 #define mmDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
808 #define mmDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191
809 #define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
810 #define mmDMCUB_REGION2_OFFSET                                                                         0x0192
811 #define mmDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
812 #define mmDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193
813 #define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
814 #define mmDMCUB_REGION4_OFFSET                                                                         0x0196
815 #define mmDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
816 #define mmDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197
817 #define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
818 #define mmDMCUB_REGION5_OFFSET                                                                         0x0198
819 #define mmDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
820 #define mmDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199
821 #define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
822 #define mmDMCUB_REGION6_OFFSET                                                                         0x019a
823 #define mmDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
824 #define mmDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b
825 #define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
826 #define mmDMCUB_REGION7_OFFSET                                                                         0x019c
827 #define mmDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
828 #define mmDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d
829 #define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
830 #define mmDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e
831 #define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
832 #define mmDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f
833 #define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
834 #define mmDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0
835 #define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
836 #define mmDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1
837 #define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
838 #define mmDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2
839 #define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
840 #define mmDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3
841 #define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
842 #define mmDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4
843 #define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
844 #define mmDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5
845 #define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
846 #define mmDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6
847 #define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
848 #define mmDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7
849 #define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
850 #define mmDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8
851 #define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
852 #define mmDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9
853 #define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
854 #define mmDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa
855 #define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
856 #define mmDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab
857 #define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
858 #define mmDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac
859 #define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
860 #define mmDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad
861 #define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
862 #define mmDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae
863 #define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
864 #define mmDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af
865 #define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
866 #define mmDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0
867 #define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
868 #define mmDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1
869 #define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
870 #define mmDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2
871 #define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
872 #define mmDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3
873 #define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
874 #define mmDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4
875 #define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
876 #define mmDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5
877 #define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
878 #define mmDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6
879 #define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
880 #define mmDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7
881 #define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
882 #define mmDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8
883 #define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
884 #define mmDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9
885 #define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
886 #define mmDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba
887 #define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
888 #define mmDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb
889 #define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
890 #define mmDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc
891 #define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
892 #define mmDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd
893 #define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
894 #define mmDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be
895 #define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
896 #define mmDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf
897 #define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
898 #define mmDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0
899 #define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
900 #define mmDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1
901 #define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
902 #define mmDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2
903 #define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
904 #define mmDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3
905 #define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
906 #define mmDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4
907 #define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
908 #define mmDMCUB_INTERRUPT_ENABLE                                                                       0x01c5
909 #define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
910 #define mmDMCUB_INTERRUPT_ACK                                                                          0x01c6
911 #define mmDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
912 #define mmDMCUB_INTERRUPT_STATUS                                                                       0x01c7
913 #define mmDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
914 #define mmDMCUB_INTERRUPT_TYPE                                                                         0x01c8
915 #define mmDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
916 #define mmDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9
917 #define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
918 #define mmDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca
919 #define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
920 #define mmDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb
921 #define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
922 #define mmDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc
923 #define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
924 #define mmDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd
925 #define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
926 #define mmDMCUB_SEC_CNTL                                                                               0x01ce
927 #define mmDMCUB_SEC_CNTL_BASE_IDX                                                                      2
928 #define mmDMCUB_MEM_CNTL                                                                               0x01cf
929 #define mmDMCUB_MEM_CNTL_BASE_IDX                                                                      2
930 #define mmDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0
931 #define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
932 #define mmDMCUB_INBOX0_SIZE                                                                            0x01d1
933 #define mmDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
934 #define mmDMCUB_INBOX0_WPTR                                                                            0x01d2
935 #define mmDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
936 #define mmDMCUB_INBOX0_RPTR                                                                            0x01d3
937 #define mmDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
938 #define mmDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4
939 #define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
940 #define mmDMCUB_INBOX1_SIZE                                                                            0x01d5
941 #define mmDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
942 #define mmDMCUB_INBOX1_WPTR                                                                            0x01d6
943 #define mmDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
944 #define mmDMCUB_INBOX1_RPTR                                                                            0x01d7
945 #define mmDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
946 #define mmDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8
947 #define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
948 #define mmDMCUB_OUTBOX0_SIZE                                                                           0x01d9
949 #define mmDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
950 #define mmDMCUB_OUTBOX0_WPTR                                                                           0x01da
951 #define mmDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
952 #define mmDMCUB_OUTBOX0_RPTR                                                                           0x01db
953 #define mmDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
954 #define mmDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc
955 #define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
956 #define mmDMCUB_OUTBOX1_SIZE                                                                           0x01dd
957 #define mmDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
958 #define mmDMCUB_OUTBOX1_WPTR                                                                           0x01de
959 #define mmDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
960 #define mmDMCUB_OUTBOX1_RPTR                                                                           0x01df
961 #define mmDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
962 #define mmDMCUB_TIMER_TRIGGER0                                                                         0x01e0
963 #define mmDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
964 #define mmDMCUB_TIMER_TRIGGER1                                                                         0x01e1
965 #define mmDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
966 #define mmDMCUB_TIMER_WINDOW                                                                           0x01e2
967 #define mmDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
968 #define mmDMCUB_SCRATCH0                                                                               0x01e3
969 #define mmDMCUB_SCRATCH0_BASE_IDX                                                                      2
970 #define mmDMCUB_SCRATCH1                                                                               0x01e4
971 #define mmDMCUB_SCRATCH1_BASE_IDX                                                                      2
972 #define mmDMCUB_SCRATCH2                                                                               0x01e5
973 #define mmDMCUB_SCRATCH2_BASE_IDX                                                                      2
974 #define mmDMCUB_SCRATCH3                                                                               0x01e6
975 #define mmDMCUB_SCRATCH3_BASE_IDX                                                                      2
976 #define mmDMCUB_SCRATCH4                                                                               0x01e7
977 #define mmDMCUB_SCRATCH4_BASE_IDX                                                                      2
978 #define mmDMCUB_SCRATCH5                                                                               0x01e8
979 #define mmDMCUB_SCRATCH5_BASE_IDX                                                                      2
980 #define mmDMCUB_SCRATCH6                                                                               0x01e9
981 #define mmDMCUB_SCRATCH6_BASE_IDX                                                                      2
982 #define mmDMCUB_SCRATCH7                                                                               0x01ea
983 #define mmDMCUB_SCRATCH7_BASE_IDX                                                                      2
984 #define mmDMCUB_SCRATCH8                                                                               0x01eb
985 #define mmDMCUB_SCRATCH8_BASE_IDX                                                                      2
986 #define mmDMCUB_SCRATCH9                                                                               0x01ec
987 #define mmDMCUB_SCRATCH9_BASE_IDX                                                                      2
988 #define mmDMCUB_SCRATCH10                                                                              0x01ed
989 #define mmDMCUB_SCRATCH10_BASE_IDX                                                                     2
990 #define mmDMCUB_SCRATCH11                                                                              0x01ee
991 #define mmDMCUB_SCRATCH11_BASE_IDX                                                                     2
992 #define mmDMCUB_SCRATCH12                                                                              0x01ef
993 #define mmDMCUB_SCRATCH12_BASE_IDX                                                                     2
994 #define mmDMCUB_SCRATCH13                                                                              0x01f0
995 #define mmDMCUB_SCRATCH13_BASE_IDX                                                                     2
996 #define mmDMCUB_SCRATCH14                                                                              0x01f1
997 #define mmDMCUB_SCRATCH14_BASE_IDX                                                                     2
998 #define mmDMCUB_SCRATCH15                                                                              0x01f2
999 #define mmDMCUB_SCRATCH15_BASE_IDX                                                                     2
1000 #define mmDMCUB_CNTL                                                                                   0x01f6
1001 #define mmDMCUB_CNTL_BASE_IDX                                                                          2
1002 #define mmDMCUB_GPINT_DATAIN0                                                                          0x01f7
1003 #define mmDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
1004 #define mmDMCUB_GPINT_DATAIN1                                                                          0x01f8
1005 #define mmDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
1006 #define mmDMCUB_GPINT_DATAOUT                                                                          0x01f9
1007 #define mmDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
1008 #define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa
1009 #define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
1010 #define mmDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb
1011 #define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
1012 #define mmDMCUB_MEM_PWR_CNTL                                                                           0x01fc
1013 #define mmDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
1014 #define mmDMCUB_TIMER_CURRENT                                                                          0x01fd
1015 #define mmDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
1016 #define mmDMCUB_PROC_ID                                                                                0x01ff
1017 #define mmDMCUB_PROC_ID_BASE_IDX                                                                       2
1018 
1019 
1020 // addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
1021 // base address: 0x0
1022 #define mmMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272
1023 #define mmMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2
1024 #define mmMCIF_WB_BUFMGR_STATUS                                                                        0x0274
1025 #define mmMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2
1026 #define mmMCIF_WB_BUF_PITCH                                                                            0x0275
1027 #define mmMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2
1028 #define mmMCIF_WB_BUF_1_STATUS                                                                         0x0276
1029 #define mmMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2
1030 #define mmMCIF_WB_BUF_1_STATUS2                                                                        0x0277
1031 #define mmMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2
1032 #define mmMCIF_WB_BUF_2_STATUS                                                                         0x0278
1033 #define mmMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2
1034 #define mmMCIF_WB_BUF_2_STATUS2                                                                        0x0279
1035 #define mmMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2
1036 #define mmMCIF_WB_BUF_3_STATUS                                                                         0x027a
1037 #define mmMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2
1038 #define mmMCIF_WB_BUF_3_STATUS2                                                                        0x027b
1039 #define mmMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2
1040 #define mmMCIF_WB_BUF_4_STATUS                                                                         0x027c
1041 #define mmMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2
1042 #define mmMCIF_WB_BUF_4_STATUS2                                                                        0x027d
1043 #define mmMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2
1044 #define mmMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e
1045 #define mmMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2
1046 #define mmMCIF_WB_SCLK_CHANGE                                                                          0x027f
1047 #define mmMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2
1048 #define mmMCIF_WB_TEST_DEBUG_INDEX                                                                     0x0280
1049 #define mmMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                            2
1050 #define mmMCIF_WB_TEST_DEBUG_DATA                                                                      0x0281
1051 #define mmMCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                             2
1052 #define mmMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282
1053 #define mmMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2
1054 #define mmMCIF_WB_BUF_1_ADDR_C                                                                         0x0284
1055 #define mmMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2
1056 #define mmMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286
1057 #define mmMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2
1058 #define mmMCIF_WB_BUF_2_ADDR_C                                                                         0x0288
1059 #define mmMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2
1060 #define mmMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a
1061 #define mmMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2
1062 #define mmMCIF_WB_BUF_3_ADDR_C                                                                         0x028c
1063 #define mmMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2
1064 #define mmMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e
1065 #define mmMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2
1066 #define mmMCIF_WB_BUF_4_ADDR_C                                                                         0x0290
1067 #define mmMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2
1068 #define mmMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292
1069 #define mmMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2
1070 #define mmMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293
1071 #define mmMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2
1072 #define mmMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294
1073 #define mmMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2
1074 #define mmMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296
1075 #define mmMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2
1076 #define mmMULTI_LEVEL_QOS_CTRL                                                                         0x0297
1077 #define mmMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2
1078 #define mmMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299
1079 #define mmMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2
1080 #define mmMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a
1081 #define mmMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2
1082 #define mmMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b
1083 #define mmMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2
1084 #define mmMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c
1085 #define mmMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2
1086 #define mmMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d
1087 #define mmMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2
1088 #define mmMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e
1089 #define mmMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2
1090 #define mmMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f
1091 #define mmMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2
1092 #define mmMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0
1093 #define mmMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2
1094 #define mmMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1
1095 #define mmMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2
1096 #define mmMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2
1097 #define mmMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2
1098 #define mmMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3
1099 #define mmMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2
1100 #define mmMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4
1101 #define mmMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2
1102 #define mmMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5
1103 #define mmMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2
1104 #define mmMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6
1105 #define mmMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2
1106 #define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI                                                       0x02a7
1107 #define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX                                              2
1108 #define mmMCIF_WB_VMID_CONTROL                                                                         0x02a8
1109 #define mmMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2
1110 #define mmMCIF_WB_MIN_TTO                                                                              0x02a9
1111 #define mmMCIF_WB_MIN_TTO_BASE_IDX                                                                     2
1112 
1113 
1114 // addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
1115 // base address: 0x0
1116 #define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa
1117 #define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2
1118 #define mmMCIF_WB_WATERMARK                                                                            0x02ab
1119 #define mmMCIF_WB_WATERMARK_BASE_IDX                                                                   2
1120 #define mmMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac
1121 #define mmMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2
1122 #define mmMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad
1123 #define mmMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2
1124 #define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae
1125 #define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2
1126 #define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af
1127 #define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2
1128 #define mmMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0
1129 #define mmMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2
1130 #define mmMMHUBBUB_MIN_TTO                                                                             0x02b1
1131 #define mmMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2
1132 #define mmWBIF0_MISC_CTRL                                                                              0x0334
1133 #define mmWBIF0_MISC_CTRL_BASE_IDX                                                                     2
1134 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0335
1135 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
1136 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0336
1137 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
1138 #define mmVGA_SRC_SPLIT_CNTL                                                                           0x033d
1139 #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
1140 #define mmMMHUBBUB_MEM_PWR_STATUS                                                                      0x033e
1141 #define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
1142 #define mmMMHUBBUB_MEM_PWR_CNTL                                                                        0x033f
1143 #define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
1144 #define mmMMHUBBUB_CLOCK_CNTL                                                                          0x0340
1145 #define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
1146 #define mmMMHUBBUB_SOFT_RESET                                                                          0x0341
1147 #define mmMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
1148 #define mmDMU_IF_ERR_STATUS                                                                            0x0345
1149 #define mmDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
1150 #define mmMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0346
1151 #define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
1152 #define mmMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0348
1153 #define mmMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2
1154 
1155 
1156 // addressBlock: dce_dc_mmhubbub_vgaif_dispdec
1157 // base address: 0x0
1158 #define mmMCIF_CONTROL                                                                                 0x034a
1159 #define mmMCIF_CONTROL_BASE_IDX                                                                        2
1160 #define mmMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
1161 #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
1162 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
1163 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
1164 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
1165 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
1166 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
1167 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
1168 
1169 
1170 // addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
1171 // base address: 0xd48
1172 #define mmDC_PERFMON3_PERFCOUNTER_CNTL                                                                 0x0352
1173 #define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX                                                        2
1174 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2                                                                0x0353
1175 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
1176 #define mmDC_PERFMON3_PERFCOUNTER_STATE                                                                0x0354
1177 #define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX                                                       2
1178 #define mmDC_PERFMON3_PERFMON_CNTL                                                                     0x0355
1179 #define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX                                                            2
1180 #define mmDC_PERFMON3_PERFMON_CNTL2                                                                    0x0356
1181 #define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX                                                           2
1182 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                                          0x0357
1183 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
1184 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW                                                               0x0358
1185 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
1186 #define mmDC_PERFMON3_PERFMON_HI                                                                       0x0359
1187 #define mmDC_PERFMON3_PERFMON_HI_BASE_IDX                                                              2
1188 #define mmDC_PERFMON3_PERFMON_LOW                                                                      0x035a
1189 #define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX                                                             2
1190 
1191 
1192 // addressBlock: dce_dc_hda_azf0stream0_dispdec
1193 // base address: 0x0
1194 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
1195 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1196 #define mmAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
1197 #define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1198 
1199 
1200 // addressBlock: dce_dc_hda_azf0stream1_dispdec
1201 // base address: 0x8
1202 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
1203 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1204 #define mmAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
1205 #define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1206 
1207 
1208 // addressBlock: dce_dc_hda_azf0stream2_dispdec
1209 // base address: 0x10
1210 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
1211 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1212 #define mmAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
1213 #define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1214 
1215 
1216 // addressBlock: dce_dc_hda_azf0stream3_dispdec
1217 // base address: 0x18
1218 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
1219 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1220 #define mmAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
1221 #define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1222 
1223 
1224 // addressBlock: dce_dc_hda_azf0stream4_dispdec
1225 // base address: 0x20
1226 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
1227 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1228 #define mmAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
1229 #define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1230 
1231 
1232 // addressBlock: dce_dc_hda_azf0stream5_dispdec
1233 // base address: 0x28
1234 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
1235 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1236 #define mmAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
1237 #define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1238 
1239 
1240 // addressBlock: dce_dc_hda_azf0stream6_dispdec
1241 // base address: 0x30
1242 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
1243 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1244 #define mmAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
1245 #define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1246 
1247 
1248 // addressBlock: dce_dc_hda_azf0stream7_dispdec
1249 // base address: 0x38
1250 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
1251 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1252 #define mmAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
1253 #define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1254 
1255 
1256 // addressBlock: dce_dc_hda_az_misc_dispdec
1257 // base address: 0x0
1258 #define mmAZ_CLOCK_CNTL                                                                                0x0372
1259 #define mmAZ_CLOCK_CNTL_BASE_IDX                                                                       2
1260 
1261 
1262 // addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
1263 // base address: 0xde8
1264 #define mmDC_PERFMON4_PERFCOUNTER_CNTL                                                                 0x037a
1265 #define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX                                                        2
1266 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2                                                                0x037b
1267 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
1268 #define mmDC_PERFMON4_PERFCOUNTER_STATE                                                                0x037c
1269 #define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX                                                       2
1270 #define mmDC_PERFMON4_PERFMON_CNTL                                                                     0x037d
1271 #define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX                                                            2
1272 #define mmDC_PERFMON4_PERFMON_CNTL2                                                                    0x037e
1273 #define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX                                                           2
1274 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                                          0x037f
1275 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
1276 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW                                                               0x0380
1277 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
1278 #define mmDC_PERFMON4_PERFMON_HI                                                                       0x0381
1279 #define mmDC_PERFMON4_PERFMON_HI_BASE_IDX                                                              2
1280 #define mmDC_PERFMON4_PERFMON_LOW                                                                      0x0382
1281 #define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX                                                             2
1282 
1283 
1284 // addressBlock: dce_dc_hda_azf0endpoint0_dispdec
1285 // base address: 0x0
1286 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
1287 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1288 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
1289 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1290 
1291 
1292 // addressBlock: dce_dc_hda_azf0endpoint1_dispdec
1293 // base address: 0x18
1294 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
1295 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1296 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
1297 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1298 
1299 
1300 // addressBlock: dce_dc_hda_azf0endpoint2_dispdec
1301 // base address: 0x30
1302 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
1303 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1304 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
1305 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1306 
1307 
1308 // addressBlock: dce_dc_hda_azf0endpoint3_dispdec
1309 // base address: 0x48
1310 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
1311 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1312 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
1313 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1314 
1315 
1316 // addressBlock: dce_dc_hda_azf0endpoint4_dispdec
1317 // base address: 0x60
1318 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
1319 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1320 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
1321 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1322 
1323 
1324 // addressBlock: dce_dc_hda_azf0endpoint5_dispdec
1325 // base address: 0x78
1326 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
1327 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1328 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
1329 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1330 
1331 
1332 // addressBlock: dce_dc_hda_azf0endpoint6_dispdec
1333 // base address: 0x90
1334 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
1335 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1336 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
1337 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1338 
1339 
1340 // addressBlock: dce_dc_hda_azf0endpoint7_dispdec
1341 // base address: 0xa8
1342 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
1343 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1344 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
1345 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1346 
1347 
1348 // addressBlock: dce_dc_hda_azf0controller_dispdec
1349 // base address: 0x0
1350 #define mmAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
1351 #define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
1352 #define mmAZALIA_AUDIO_DTO                                                                             0x03c3
1353 #define mmAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
1354 #define mmAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
1355 #define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
1356 #define mmAZALIA_SOCCLK_CONTROL                                                                        0x03c5
1357 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
1358 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
1359 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
1360 #define mmAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
1361 #define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
1362 #define mmAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
1363 #define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
1364 #define mmAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
1365 #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
1366 #define mmAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
1367 #define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
1368 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
1369 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
1370 #define mmAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
1371 #define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
1372 #define mmAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
1373 #define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
1374 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
1375 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
1376 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
1377 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
1378 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
1379 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
1380 #define mmAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
1381 #define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
1382 #define mmAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
1383 #define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
1384 #define mmAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
1385 #define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
1386 #define mmAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
1387 #define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
1388 #define mmAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
1389 #define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
1390 #define mmAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
1391 #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
1392 #define mmAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
1393 #define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
1394 #define mmAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
1395 #define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
1396 #define mmAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
1397 #define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
1398 #define mmAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
1399 #define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
1400 #define mmAZALIA_CRC0_CONTROL0                                                                         0x03e3
1401 #define mmAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
1402 #define mmAZALIA_CRC0_CONTROL1                                                                         0x03e4
1403 #define mmAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
1404 #define mmAZALIA_CRC0_CONTROL2                                                                         0x03e5
1405 #define mmAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
1406 #define mmAZALIA_CRC0_CONTROL3                                                                         0x03e6
1407 #define mmAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
1408 #define mmAZALIA_CRC0_RESULT                                                                           0x03e7
1409 #define mmAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
1410 #define mmAZALIA_CRC1_CONTROL0                                                                         0x03e8
1411 #define mmAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
1412 #define mmAZALIA_CRC1_CONTROL1                                                                         0x03e9
1413 #define mmAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
1414 #define mmAZALIA_CRC1_CONTROL2                                                                         0x03ea
1415 #define mmAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
1416 #define mmAZALIA_CRC1_CONTROL3                                                                         0x03eb
1417 #define mmAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
1418 #define mmAZALIA_CRC1_RESULT                                                                           0x03ec
1419 #define mmAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
1420 #define mmAZALIA_MEM_PWR_CTRL                                                                          0x03ee
1421 #define mmAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
1422 #define mmAZALIA_MEM_PWR_STATUS                                                                        0x03ef
1423 #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
1424 
1425 
1426 // addressBlock: dce_dc_hda_azf0root_dispdec
1427 // base address: 0x0
1428 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
1429 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
1430 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
1431 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
1432 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
1433 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
1434 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
1435 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
1436 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
1437 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
1438 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
1439 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
1440 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
1441 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
1442 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
1443 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
1444 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
1445 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
1446 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
1447 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
1448 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
1449 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
1450 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
1451 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
1452 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
1453 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
1454 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
1455 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
1456 #define mmAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
1457 #define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
1458 #define mmAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
1459 #define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
1460 #define mmAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
1461 #define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
1462 #define mmAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
1463 #define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
1464 #define mmAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
1465 #define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
1466 #define mmAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
1467 #define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
1468 #define mmAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
1469 #define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
1470 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
1471 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
1472 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
1473 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
1474 
1475 
1476 // addressBlock: dce_dc_hda_azf0stream8_dispdec
1477 // base address: 0x320
1478 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
1479 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1480 #define mmAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
1481 #define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1482 
1483 
1484 // addressBlock: dce_dc_hda_azf0stream9_dispdec
1485 // base address: 0x328
1486 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
1487 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1488 #define mmAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
1489 #define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1490 
1491 
1492 // addressBlock: dce_dc_hda_azf0stream10_dispdec
1493 // base address: 0x330
1494 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
1495 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1496 #define mmAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
1497 #define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1498 
1499 
1500 // addressBlock: dce_dc_hda_azf0stream11_dispdec
1501 // base address: 0x338
1502 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
1503 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1504 #define mmAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
1505 #define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1506 
1507 
1508 // addressBlock: dce_dc_hda_azf0stream12_dispdec
1509 // base address: 0x340
1510 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
1511 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1512 #define mmAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
1513 #define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1514 
1515 
1516 // addressBlock: dce_dc_hda_azf0stream13_dispdec
1517 // base address: 0x348
1518 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
1519 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1520 #define mmAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
1521 #define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1522 
1523 
1524 // addressBlock: dce_dc_hda_azf0stream14_dispdec
1525 // base address: 0x350
1526 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
1527 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1528 #define mmAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
1529 #define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1530 
1531 
1532 // addressBlock: dce_dc_hda_azf0stream15_dispdec
1533 // base address: 0x358
1534 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
1535 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1536 #define mmAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
1537 #define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1538 
1539 
1540 // addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
1541 // base address: 0x0
1542 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
1543 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1544 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
1545 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1546 
1547 
1548 // addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
1549 // base address: 0x10
1550 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
1551 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1552 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
1553 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1554 
1555 
1556 // addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
1557 // base address: 0x20
1558 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
1559 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1560 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
1561 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1562 
1563 
1564 // addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
1565 // base address: 0x30
1566 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
1567 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1568 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
1569 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1570 
1571 
1572 // addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
1573 // base address: 0x40
1574 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
1575 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1576 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
1577 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1578 
1579 
1580 // addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
1581 // base address: 0x50
1582 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
1583 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1584 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
1585 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1586 
1587 
1588 // addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
1589 // base address: 0x60
1590 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
1591 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1592 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
1593 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1594 
1595 
1596 // addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
1597 // base address: 0x70
1598 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
1599 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1600 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
1601 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1602 
1603 
1604 // addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
1605 // base address: 0x0
1606 #define mmDCHUBBUB_SDPIF_CFG0                                                                          0x048f
1607 #define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
1608 #define mmVM_REQUEST_PHYSICAL                                                                          0x0490
1609 #define mmVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
1610 #define mmDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0491
1611 #define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
1612 #define mmDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0492
1613 #define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
1614 #define mmDCN_VM_FB_LOCATION_BASE                                                                      0x0493
1615 #define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
1616 #define mmDCN_VM_FB_LOCATION_TOP                                                                       0x0494
1617 #define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
1618 #define mmDCN_VM_FB_OFFSET                                                                             0x0495
1619 #define mmDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
1620 #define mmDCN_VM_AGP_BOT                                                                               0x0496
1621 #define mmDCN_VM_AGP_BOT_BASE_IDX                                                                      2
1622 #define mmDCN_VM_AGP_TOP                                                                               0x0497
1623 #define mmDCN_VM_AGP_TOP_BASE_IDX                                                                      2
1624 #define mmDCN_VM_AGP_BASE                                                                              0x0498
1625 #define mmDCN_VM_AGP_BASE_BASE_IDX                                                                     2
1626 #define mmDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x0499
1627 #define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
1628 #define mmDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x049a
1629 #define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
1630 #define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x049b
1631 #define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
1632 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x04ba
1633 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
1634 #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x04bb
1635 #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2
1636 #define mmDCHUBBUB_SDPIF_CFG1                                                                          0x04bf
1637 #define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
1638 #define mmDCHUBBUB_SDPIF_CFG2                                                                          0x04c0
1639 #define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
1640 
1641 
1642 // addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
1643 // base address: 0x0
1644 #define mmDCHUBBUB_RET_PATH_DCC_CFG                                                                    0x04cf
1645 #define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX                                                           2
1646 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0                                                                 0x04d0
1647 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX                                                        2
1648 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1                                                                 0x04d1
1649 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX                                                        2
1650 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0                                                                 0x04d2
1651 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX                                                        2
1652 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1                                                                 0x04d3
1653 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX                                                        2
1654 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0                                                                 0x04d4
1655 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX                                                        2
1656 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1                                                                 0x04d5
1657 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX                                                        2
1658 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0                                                                 0x04d6
1659 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX                                                        2
1660 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1                                                                 0x04d7
1661 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX                                                        2
1662 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0                                                                 0x04d8
1663 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX                                                        2
1664 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1                                                                 0x04d9
1665 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX                                                        2
1666 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0                                                                 0x04da
1667 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX                                                        2
1668 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1                                                                 0x04db
1669 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX                                                        2
1670 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0                                                                 0x04dc
1671 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX                                                        2
1672 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1                                                                 0x04dd
1673 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX                                                        2
1674 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0                                                                 0x04de
1675 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX                                                        2
1676 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1                                                                 0x04df
1677 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX                                                        2
1678 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04ef
1679 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
1680 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04f0
1681 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
1682 #define mmDCHUBBUB_CRC_CTRL                                                                            0x04f1
1683 #define mmDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
1684 #define mmDCHUBBUB_CRC0_VAL_R_G                                                                        0x04f2
1685 #define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
1686 #define mmDCHUBBUB_CRC0_VAL_B_A                                                                        0x04f3
1687 #define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
1688 #define mmDCHUBBUB_CRC1_VAL_R_G                                                                        0x04f4
1689 #define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
1690 #define mmDCHUBBUB_CRC1_VAL_B_A                                                                        0x04f5
1691 #define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
1692 
1693 
1694 // addressBlock: dce_dc_dchubbub_hubbub_dispdec
1695 // base address: 0x0
1696 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x0505
1697 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
1698 #define mmDCHUBBUB_ARB_SAT_LEVEL                                                                       0x0506
1699 #define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
1700 #define mmDCHUBBUB_ARB_QOS_FORCE                                                                       0x0507
1701 #define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
1702 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x0508
1703 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
1704 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x0509
1705 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
1706 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x050a
1707 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
1708 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x050b
1709 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
1710 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x050c
1711 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
1712 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A                                               0x050d
1713 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX                                      2
1714 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x050e
1715 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
1716 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x050f
1717 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
1718 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x0510
1719 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
1720 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x0511
1721 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
1722 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B                                               0x0512
1723 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX                                      2
1724 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0513
1725 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
1726 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0514
1727 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
1728 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0515
1729 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
1730 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0516
1731 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
1732 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C                                               0x0517
1733 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX                                      2
1734 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0518
1735 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
1736 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x0519
1737 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
1738 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051a
1739 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
1740 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051b
1741 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
1742 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D                                               0x051c
1743 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX                                      2
1744 #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x051d
1745 #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
1746 #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x051e
1747 #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
1748 #define mmDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x051f
1749 #define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
1750 #define mmSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0520
1751 #define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
1752 #define mmSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0521
1753 #define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
1754 #define mmSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0522
1755 #define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
1756 #define mmSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0523
1757 #define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
1758 #define mmSURFACE_CHECK2_ADDRESS_LSB                                                                   0x0524
1759 #define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
1760 #define mmSURFACE_CHECK2_ADDRESS_MSB                                                                   0x0525
1761 #define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
1762 #define mmSURFACE_CHECK3_ADDRESS_LSB                                                                   0x0526
1763 #define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
1764 #define mmSURFACE_CHECK3_ADDRESS_MSB                                                                   0x0527
1765 #define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
1766 #define mmVTG0_CONTROL                                                                                 0x0528
1767 #define mmVTG0_CONTROL_BASE_IDX                                                                        2
1768 #define mmVTG1_CONTROL                                                                                 0x0529
1769 #define mmVTG1_CONTROL_BASE_IDX                                                                        2
1770 #define mmVTG2_CONTROL                                                                                 0x052a
1771 #define mmVTG2_CONTROL_BASE_IDX                                                                        2
1772 #define mmVTG3_CONTROL                                                                                 0x052b
1773 #define mmVTG3_CONTROL_BASE_IDX                                                                        2
1774 #define mmDCHUBBUB_SOFT_RESET                                                                          0x052e
1775 #define mmDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
1776 #define mmDCHUBBUB_CLOCK_CNTL                                                                          0x052f
1777 #define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
1778 #define mmDCFCLK_CNTL                                                                                  0x0530
1779 #define mmDCFCLK_CNTL_BASE_IDX                                                                         2
1780 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0531
1781 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
1782 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0532
1783 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
1784 #define mmDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0533
1785 #define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
1786 #define mmDCHUBBUB_CTRL_STATUS                                                                         0x0534
1787 #define mmDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
1788 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053a
1789 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
1790 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053b
1791 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
1792 #define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x053c
1793 #define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
1794 #define mmDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x053d
1795 #define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2
1796 #define mmDCHUBBUB_TEST_DEBUG_DATA                                                                     0x053e
1797 #define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2
1798 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x053f
1799 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
1800 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0540
1801 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
1802 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x0541
1803 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
1804 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x0542
1805 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
1806 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0543
1807 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
1808 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0544
1809 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
1810 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0545
1811 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
1812 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0546
1813 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
1814 #define mmDCHUBBUB_ARB_HOSTVM_CNTL                                                                     0x0547
1815 #define mmDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX                                                            2
1816 #define mmFMON_CTRL                                                                                    0x0548
1817 #define mmFMON_CTRL_BASE_IDX                                                                           2
1818 #define mmFMON_CTRL_1                                                                                  0x0548
1819 #define mmFMON_CTRL_1_BASE_IDX                                                                         2
1820 
1821 
1822 // addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
1823 // base address: 0x1534
1824 #define mmDC_PERFMON5_PERFCOUNTER_CNTL                                                                 0x054d
1825 #define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX                                                        2
1826 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2                                                                0x054e
1827 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
1828 #define mmDC_PERFMON5_PERFCOUNTER_STATE                                                                0x054f
1829 #define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX                                                       2
1830 #define mmDC_PERFMON5_PERFMON_CNTL                                                                     0x0550
1831 #define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX                                                            2
1832 #define mmDC_PERFMON5_PERFMON_CNTL2                                                                    0x0551
1833 #define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX                                                           2
1834 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                                          0x0552
1835 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
1836 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW                                                               0x0553
1837 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
1838 #define mmDC_PERFMON5_PERFMON_HI                                                                       0x0554
1839 #define mmDC_PERFMON5_PERFMON_HI_BASE_IDX                                                              2
1840 #define mmDC_PERFMON5_PERFMON_LOW                                                                      0x0555
1841 #define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX                                                             2
1842 
1843 
1844 // addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
1845 // base address: 0x0
1846 #define mmDCN_VM_CONTEXT0_CNTL                                                                         0x0559
1847 #define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
1848 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
1849 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1850 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
1851 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1852 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
1853 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1854 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
1855 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1856 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
1857 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1858 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
1859 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1860 #define mmDCN_VM_CONTEXT1_CNTL                                                                         0x0560
1861 #define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
1862 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
1863 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1864 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
1865 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1866 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
1867 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1868 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
1869 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1870 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
1871 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1872 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
1873 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1874 #define mmDCN_VM_CONTEXT2_CNTL                                                                         0x0567
1875 #define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
1876 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
1877 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1878 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
1879 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1880 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
1881 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1882 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
1883 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1884 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
1885 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1886 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
1887 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1888 #define mmDCN_VM_CONTEXT3_CNTL                                                                         0x056e
1889 #define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
1890 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
1891 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1892 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
1893 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1894 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
1895 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1896 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
1897 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1898 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
1899 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1900 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
1901 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1902 #define mmDCN_VM_CONTEXT4_CNTL                                                                         0x0575
1903 #define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
1904 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
1905 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1906 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
1907 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1908 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
1909 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1910 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
1911 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1912 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
1913 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1914 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
1915 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1916 #define mmDCN_VM_CONTEXT5_CNTL                                                                         0x057c
1917 #define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
1918 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
1919 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1920 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
1921 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1922 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
1923 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1924 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
1925 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1926 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
1927 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1928 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
1929 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1930 #define mmDCN_VM_CONTEXT6_CNTL                                                                         0x0583
1931 #define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
1932 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
1933 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1934 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
1935 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1936 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
1937 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1938 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
1939 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1940 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
1941 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1942 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
1943 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1944 #define mmDCN_VM_CONTEXT7_CNTL                                                                         0x058a
1945 #define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
1946 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
1947 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1948 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
1949 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1950 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
1951 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1952 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
1953 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1954 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
1955 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1956 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
1957 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1958 #define mmDCN_VM_CONTEXT8_CNTL                                                                         0x0591
1959 #define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
1960 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
1961 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1962 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
1963 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1964 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
1965 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1966 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
1967 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1968 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
1969 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1970 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
1971 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1972 #define mmDCN_VM_CONTEXT9_CNTL                                                                         0x0598
1973 #define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
1974 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
1975 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1976 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
1977 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1978 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
1979 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1980 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
1981 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1982 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
1983 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1984 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
1985 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1986 #define mmDCN_VM_CONTEXT10_CNTL                                                                        0x059f
1987 #define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
1988 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
1989 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
1990 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
1991 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
1992 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
1993 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
1994 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
1995 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
1996 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
1997 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
1998 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
1999 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2000 #define mmDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
2001 #define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
2002 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
2003 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2004 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
2005 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2006 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
2007 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2008 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
2009 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2010 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
2011 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2012 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
2013 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2014 #define mmDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
2015 #define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
2016 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
2017 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2018 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
2019 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2020 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
2021 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2022 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
2023 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2024 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
2025 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2026 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
2027 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2028 #define mmDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
2029 #define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
2030 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
2031 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2032 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
2033 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2034 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
2035 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2036 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
2037 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2038 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
2039 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2040 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
2041 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2042 #define mmDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
2043 #define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
2044 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
2045 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2046 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
2047 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2048 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
2049 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2050 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
2051 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2052 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
2053 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2054 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
2055 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2056 #define mmDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
2057 #define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
2058 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
2059 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2060 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
2061 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2062 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
2063 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2064 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
2065 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2066 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
2067 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2068 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
2069 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2070 #define mmDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
2071 #define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
2072 #define mmDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
2073 #define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
2074 #define mmDCN_VM_FAULT_CNTL                                                                            0x05cb
2075 #define mmDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
2076 #define mmDCN_VM_FAULT_STATUS                                                                          0x05cc
2077 #define mmDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
2078 #define mmDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
2079 #define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
2080 #define mmDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
2081 #define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2
2082 
2083 
2084 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
2085 // base address: 0x0
2086 #define mmHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
2087 #define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
2088 #define mmHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
2089 #define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
2090 #define mmHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
2091 #define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
2092 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
2093 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
2094 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
2095 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2096 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
2097 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
2098 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
2099 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2100 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
2101 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
2102 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
2103 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2104 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
2105 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
2106 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
2107 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2108 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
2109 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
2110 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
2111 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
2112 #define mmHUBP0_DCHUBP_CNTL                                                                            0x05f3
2113 #define mmHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
2114 #define mmHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
2115 #define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
2116 #define mmHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
2117 #define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
2118 #define mmHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f6
2119 #define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
2120 #define mmHUBP0_HUBPREQ_DEBUG                                                                          0x05f7
2121 #define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
2122 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fb
2123 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
2124 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fc
2125 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
2126 
2127 
2128 // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
2129 // base address: 0x0
2130 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
2131 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
2132 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
2133 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
2134 #define mmHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
2135 #define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
2136 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
2137 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
2138 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
2139 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
2140 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
2141 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
2142 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
2143 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
2144 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
2145 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
2146 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
2147 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
2148 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
2149 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
2150 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
2151 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
2152 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
2153 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
2154 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
2155 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
2156 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
2157 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
2158 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
2159 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
2160 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
2161 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
2162 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
2163 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
2164 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
2165 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
2166 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
2167 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
2168 #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
2169 #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
2170 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
2171 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
2172 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
2173 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
2174 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x0620
2175 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
2176 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0621
2177 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
2178 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0622
2179 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
2180 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0623
2181 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
2182 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0624
2183 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
2184 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0625
2185 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
2186 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0626
2187 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
2188 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0627
2189 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
2190 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0628
2191 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
2192 #define mmHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0629
2193 #define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
2194 #define mmHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x062a
2195 #define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
2196 #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062b
2197 #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
2198 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062c
2199 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
2200 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062d
2201 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
2202 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062e
2203 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
2204 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062f
2205 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
2206 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x0630
2207 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
2208 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0631
2209 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
2210 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0632
2211 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
2212 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0633
2213 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
2214 #define mmHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0634
2215 #define mmHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
2216 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0635
2217 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
2218 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0636
2219 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
2220 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0643
2221 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
2222 #define mmHUBPREQ0_BLANK_OFFSET_0                                                                      0x0644
2223 #define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
2224 #define mmHUBPREQ0_BLANK_OFFSET_1                                                                      0x0645
2225 #define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
2226 #define mmHUBPREQ0_DST_DIMENSIONS                                                                      0x0646
2227 #define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
2228 #define mmHUBPREQ0_DST_AFTER_SCALER                                                                    0x0647
2229 #define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
2230 #define mmHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0648
2231 #define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
2232 #define mmHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0649
2233 #define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
2234 #define mmHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x064a
2235 #define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
2236 #define mmHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064b
2237 #define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
2238 #define mmHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064c
2239 #define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
2240 #define mmHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064d
2241 #define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
2242 #define mmHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064e
2243 #define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
2244 #define mmHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064f
2245 #define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
2246 #define mmHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x0650
2247 #define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
2248 #define mmHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0651
2249 #define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
2250 #define mmHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0652
2251 #define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
2252 #define mmHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0653
2253 #define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
2254 #define mmHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0654
2255 #define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
2256 #define mmHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0655
2257 #define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
2258 #define mmHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0656
2259 #define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
2260 #define mmHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0657
2261 #define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
2262 #define mmHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0658
2263 #define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
2264 #define mmHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0659
2265 #define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
2266 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x065a
2267 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
2268 #define mmHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065b
2269 #define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
2270 #define mmHUBPREQ0_CURSOR_SETTINGS                                                                     0x065c
2271 #define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
2272 #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065d
2273 #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
2274 #define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065e
2275 #define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
2276 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065f
2277 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
2278 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x0660
2279 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
2280 #define mmHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0663
2281 #define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
2282 #define mmHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0664
2283 #define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
2284 #define mmHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0665
2285 #define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
2286 #define mmHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0666
2287 #define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
2288 #define mmHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0667
2289 #define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
2290 #define mmHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0668
2291 #define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
2292 
2293 
2294 // addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
2295 // base address: 0x0
2296 #define mmHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
2297 #define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
2298 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
2299 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
2300 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
2301 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
2302 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
2303 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
2304 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
2305 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
2306 #define mmHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
2307 #define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
2308 #define mmHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
2309 #define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
2310 #define mmHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
2311 #define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
2312 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
2313 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
2314 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
2315 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
2316 
2317 
2318 // addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
2319 // base address: 0x0
2320 #define mmCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
2321 #define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
2322 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
2323 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
2324 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
2325 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
2326 #define mmCURSOR0_0_CURSOR_SIZE                                                                        0x067b
2327 #define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
2328 #define mmCURSOR0_0_CURSOR_POSITION                                                                    0x067c
2329 #define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
2330 #define mmCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
2331 #define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
2332 #define mmCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
2333 #define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
2334 #define mmCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
2335 #define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
2336 #define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
2337 #define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
2338 #define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
2339 #define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
2340 #define mmCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
2341 #define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
2342 #define mmCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
2343 #define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
2344 #define mmCURSOR0_0_DMDATA_CNTL                                                                        0x0684
2345 #define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
2346 #define mmCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
2347 #define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
2348 #define mmCURSOR0_0_DMDATA_STATUS                                                                      0x0686
2349 #define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
2350 #define mmCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
2351 #define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
2352 #define mmCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
2353 #define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2
2354 
2355 
2356 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
2357 // base address: 0x1a74
2358 #define mmDC_PERFMON6_PERFCOUNTER_CNTL                                                                 0x069d
2359 #define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX                                                        2
2360 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2                                                                0x069e
2361 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
2362 #define mmDC_PERFMON6_PERFCOUNTER_STATE                                                                0x069f
2363 #define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX                                                       2
2364 #define mmDC_PERFMON6_PERFMON_CNTL                                                                     0x06a0
2365 #define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX                                                            2
2366 #define mmDC_PERFMON6_PERFMON_CNTL2                                                                    0x06a1
2367 #define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX                                                           2
2368 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                                          0x06a2
2369 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
2370 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW                                                               0x06a3
2371 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
2372 #define mmDC_PERFMON6_PERFMON_HI                                                                       0x06a4
2373 #define mmDC_PERFMON6_PERFMON_HI_BASE_IDX                                                              2
2374 #define mmDC_PERFMON6_PERFMON_LOW                                                                      0x06a5
2375 #define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX                                                             2
2376 
2377 
2378 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
2379 // base address: 0x370
2380 #define mmHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
2381 #define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
2382 #define mmHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
2383 #define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
2384 #define mmHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
2385 #define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
2386 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
2387 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
2388 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
2389 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2390 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
2391 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
2392 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
2393 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2394 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
2395 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
2396 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
2397 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2398 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
2399 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
2400 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
2401 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2402 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
2403 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
2404 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
2405 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
2406 #define mmHUBP1_DCHUBP_CNTL                                                                            0x06cf
2407 #define mmHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
2408 #define mmHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
2409 #define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
2410 #define mmHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
2411 #define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
2412 #define mmHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d2
2413 #define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
2414 #define mmHUBP1_HUBPREQ_DEBUG                                                                          0x06d3
2415 #define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
2416 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d7
2417 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
2418 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06d8
2419 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
2420 
2421 
2422 // addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
2423 // base address: 0x370
2424 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
2425 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
2426 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
2427 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
2428 #define mmHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
2429 #define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
2430 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
2431 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
2432 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
2433 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
2434 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
2435 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
2436 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
2437 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
2438 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
2439 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
2440 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
2441 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
2442 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
2443 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
2444 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
2445 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
2446 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
2447 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
2448 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
2449 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
2450 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
2451 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
2452 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
2453 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
2454 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
2455 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
2456 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
2457 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
2458 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
2459 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
2460 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
2461 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
2462 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
2463 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
2464 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
2465 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
2466 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
2467 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
2468 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fc
2469 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
2470 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fd
2471 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
2472 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fe
2473 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
2474 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06ff
2475 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
2476 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0700
2477 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
2478 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0701
2479 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
2480 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0702
2481 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
2482 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0703
2483 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
2484 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0704
2485 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
2486 #define mmHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0705
2487 #define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
2488 #define mmHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0706
2489 #define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
2490 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0707
2491 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
2492 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0708
2493 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
2494 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0709
2495 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
2496 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x070a
2497 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
2498 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070b
2499 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
2500 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070c
2501 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
2502 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070d
2503 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
2504 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070e
2505 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
2506 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070f
2507 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
2508 #define mmHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x0710
2509 #define mmHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
2510 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0711
2511 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
2512 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0712
2513 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
2514 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071f
2515 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
2516 #define mmHUBPREQ1_BLANK_OFFSET_0                                                                      0x0720
2517 #define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
2518 #define mmHUBPREQ1_BLANK_OFFSET_1                                                                      0x0721
2519 #define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
2520 #define mmHUBPREQ1_DST_DIMENSIONS                                                                      0x0722
2521 #define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
2522 #define mmHUBPREQ1_DST_AFTER_SCALER                                                                    0x0723
2523 #define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
2524 #define mmHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0724
2525 #define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
2526 #define mmHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0725
2527 #define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
2528 #define mmHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0726
2529 #define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
2530 #define mmHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0727
2531 #define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
2532 #define mmHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0728
2533 #define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
2534 #define mmHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0729
2535 #define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
2536 #define mmHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x072a
2537 #define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
2538 #define mmHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072b
2539 #define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
2540 #define mmHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072c
2541 #define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
2542 #define mmHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072d
2543 #define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
2544 #define mmHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072e
2545 #define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
2546 #define mmHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072f
2547 #define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
2548 #define mmHUBPREQ1_NOM_PARAMETERS_2                                                                    0x0730
2549 #define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
2550 #define mmHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0731
2551 #define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
2552 #define mmHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0732
2553 #define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
2554 #define mmHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0733
2555 #define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
2556 #define mmHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0734
2557 #define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
2558 #define mmHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0735
2559 #define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
2560 #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0736
2561 #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
2562 #define mmHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0737
2563 #define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
2564 #define mmHUBPREQ1_CURSOR_SETTINGS                                                                     0x0738
2565 #define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
2566 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0739
2567 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
2568 #define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x073a
2569 #define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
2570 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073b
2571 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
2572 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073c
2573 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
2574 #define mmHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073f
2575 #define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
2576 #define mmHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x0740
2577 #define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
2578 #define mmHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0741
2579 #define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
2580 #define mmHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0742
2581 #define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
2582 #define mmHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0743
2583 #define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
2584 #define mmHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0744
2585 #define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
2586 
2587 
2588 // addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
2589 // base address: 0x370
2590 #define mmHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
2591 #define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
2592 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
2593 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
2594 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
2595 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
2596 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
2597 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
2598 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
2599 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
2600 #define mmHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
2601 #define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
2602 #define mmHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
2603 #define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
2604 #define mmHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
2605 #define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
2606 #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
2607 #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
2608 #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
2609 #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
2610 
2611 
2612 // addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
2613 // base address: 0x370
2614 #define mmCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
2615 #define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
2616 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
2617 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
2618 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
2619 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
2620 #define mmCURSOR0_1_CURSOR_SIZE                                                                        0x0757
2621 #define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
2622 #define mmCURSOR0_1_CURSOR_POSITION                                                                    0x0758
2623 #define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
2624 #define mmCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
2625 #define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
2626 #define mmCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
2627 #define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
2628 #define mmCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
2629 #define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
2630 #define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
2631 #define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
2632 #define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
2633 #define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
2634 #define mmCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
2635 #define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
2636 #define mmCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
2637 #define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
2638 #define mmCURSOR0_1_DMDATA_CNTL                                                                        0x0760
2639 #define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
2640 #define mmCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
2641 #define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
2642 #define mmCURSOR0_1_DMDATA_STATUS                                                                      0x0762
2643 #define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
2644 #define mmCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
2645 #define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
2646 #define mmCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
2647 #define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2
2648 
2649 
2650 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
2651 // base address: 0x1de4
2652 #define mmDC_PERFMON7_PERFCOUNTER_CNTL                                                                 0x0779
2653 #define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX                                                        2
2654 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2                                                                0x077a
2655 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
2656 #define mmDC_PERFMON7_PERFCOUNTER_STATE                                                                0x077b
2657 #define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX                                                       2
2658 #define mmDC_PERFMON7_PERFMON_CNTL                                                                     0x077c
2659 #define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX                                                            2
2660 #define mmDC_PERFMON7_PERFMON_CNTL2                                                                    0x077d
2661 #define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX                                                           2
2662 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                                          0x077e
2663 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
2664 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW                                                               0x077f
2665 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
2666 #define mmDC_PERFMON7_PERFMON_HI                                                                       0x0780
2667 #define mmDC_PERFMON7_PERFMON_HI_BASE_IDX                                                              2
2668 #define mmDC_PERFMON7_PERFMON_LOW                                                                      0x0781
2669 #define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX                                                             2
2670 
2671 
2672 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
2673 // base address: 0x6e0
2674 #define mmHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
2675 #define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
2676 #define mmHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
2677 #define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
2678 #define mmHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
2679 #define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
2680 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
2681 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
2682 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
2683 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2684 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
2685 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
2686 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
2687 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2688 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
2689 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
2690 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
2691 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2692 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
2693 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
2694 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
2695 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2696 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
2697 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
2698 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
2699 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
2700 #define mmHUBP2_DCHUBP_CNTL                                                                            0x07ab
2701 #define mmHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
2702 #define mmHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
2703 #define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
2704 #define mmHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
2705 #define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
2706 #define mmHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07ae
2707 #define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
2708 #define mmHUBP2_HUBPREQ_DEBUG                                                                          0x07af
2709 #define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
2710 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b3
2711 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
2712 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b4
2713 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
2714 
2715 
2716 // addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
2717 // base address: 0x6e0
2718 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
2719 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
2720 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
2721 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
2722 #define mmHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
2723 #define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
2724 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
2725 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
2726 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
2727 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
2728 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
2729 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
2730 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
2731 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
2732 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
2733 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
2734 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
2735 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
2736 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
2737 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
2738 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
2739 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
2740 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
2741 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
2742 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
2743 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
2744 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
2745 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
2746 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
2747 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
2748 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
2749 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
2750 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
2751 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
2752 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
2753 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
2754 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
2755 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
2756 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
2757 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
2758 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
2759 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
2760 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
2761 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
2762 #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d8
2763 #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
2764 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d9
2765 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
2766 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07da
2767 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
2768 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07db
2769 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
2770 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07dc
2771 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
2772 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dd
2773 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
2774 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07de
2775 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
2776 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07df
2777 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
2778 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07e0
2779 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
2780 #define mmHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e1
2781 #define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
2782 #define mmHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e2
2783 #define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
2784 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e3
2785 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
2786 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e4
2787 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
2788 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e5
2789 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
2790 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e6
2791 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
2792 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07e7
2793 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
2794 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07e8
2795 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
2796 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e9
2797 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
2798 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07ea
2799 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
2800 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07eb
2801 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
2802 #define mmHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07ec
2803 #define mmHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
2804 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ed
2805 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
2806 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07ee
2807 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
2808 #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fb
2809 #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
2810 #define mmHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fc
2811 #define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
2812 #define mmHUBPREQ2_BLANK_OFFSET_1                                                                      0x07fd
2813 #define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
2814 #define mmHUBPREQ2_DST_DIMENSIONS                                                                      0x07fe
2815 #define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
2816 #define mmHUBPREQ2_DST_AFTER_SCALER                                                                    0x07ff
2817 #define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
2818 #define mmHUBPREQ2_PREFETCH_SETTINGS                                                                   0x0800
2819 #define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
2820 #define mmHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0801
2821 #define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
2822 #define mmHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0802
2823 #define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
2824 #define mmHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0803
2825 #define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
2826 #define mmHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0804
2827 #define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
2828 #define mmHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0805
2829 #define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
2830 #define mmHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0806
2831 #define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
2832 #define mmHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0807
2833 #define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
2834 #define mmHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x0808
2835 #define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
2836 #define mmHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0809
2837 #define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
2838 #define mmHUBPREQ2_NOM_PARAMETERS_0                                                                    0x080a
2839 #define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
2840 #define mmHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080b
2841 #define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
2842 #define mmHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080c
2843 #define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
2844 #define mmHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080d
2845 #define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
2846 #define mmHUBPREQ2_NOM_PARAMETERS_4                                                                    0x080e
2847 #define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
2848 #define mmHUBPREQ2_NOM_PARAMETERS_5                                                                    0x080f
2849 #define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
2850 #define mmHUBPREQ2_NOM_PARAMETERS_6                                                                    0x0810
2851 #define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
2852 #define mmHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0811
2853 #define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
2854 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0812
2855 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
2856 #define mmHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0813
2857 #define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
2858 #define mmHUBPREQ2_CURSOR_SETTINGS                                                                     0x0814
2859 #define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
2860 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0815
2861 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
2862 #define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0816
2863 #define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
2864 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0817
2865 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
2866 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x0818
2867 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
2868 #define mmHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081b
2869 #define mmHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
2870 #define mmHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081c
2871 #define mmHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
2872 #define mmHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081d
2873 #define mmHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
2874 #define mmHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x081e
2875 #define mmHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
2876 #define mmHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x081f
2877 #define mmHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
2878 #define mmHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x0820
2879 #define mmHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
2880 
2881 
2882 // addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
2883 // base address: 0x6e0
2884 #define mmHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
2885 #define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
2886 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
2887 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
2888 #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
2889 #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
2890 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
2891 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
2892 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
2893 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
2894 #define mmHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
2895 #define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
2896 #define mmHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
2897 #define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
2898 #define mmHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
2899 #define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
2900 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
2901 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
2902 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
2903 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
2904 
2905 
2906 // addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
2907 // base address: 0x6e0
2908 #define mmCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
2909 #define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
2910 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
2911 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
2912 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
2913 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
2914 #define mmCURSOR0_2_CURSOR_SIZE                                                                        0x0833
2915 #define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
2916 #define mmCURSOR0_2_CURSOR_POSITION                                                                    0x0834
2917 #define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
2918 #define mmCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
2919 #define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
2920 #define mmCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
2921 #define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
2922 #define mmCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
2923 #define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
2924 #define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
2925 #define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
2926 #define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
2927 #define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
2928 #define mmCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
2929 #define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
2930 #define mmCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
2931 #define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
2932 #define mmCURSOR0_2_DMDATA_CNTL                                                                        0x083c
2933 #define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
2934 #define mmCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
2935 #define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
2936 #define mmCURSOR0_2_DMDATA_STATUS                                                                      0x083e
2937 #define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
2938 #define mmCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
2939 #define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
2940 #define mmCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
2941 #define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2
2942 
2943 
2944 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
2945 // base address: 0x2154
2946 #define mmDC_PERFMON8_PERFCOUNTER_CNTL                                                                 0x0855
2947 #define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX                                                        2
2948 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2                                                                0x0856
2949 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
2950 #define mmDC_PERFMON8_PERFCOUNTER_STATE                                                                0x0857
2951 #define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX                                                       2
2952 #define mmDC_PERFMON8_PERFMON_CNTL                                                                     0x0858
2953 #define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX                                                            2
2954 #define mmDC_PERFMON8_PERFMON_CNTL2                                                                    0x0859
2955 #define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX                                                           2
2956 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                                          0x085a
2957 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
2958 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW                                                               0x085b
2959 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
2960 #define mmDC_PERFMON8_PERFMON_HI                                                                       0x085c
2961 #define mmDC_PERFMON8_PERFMON_HI_BASE_IDX                                                              2
2962 #define mmDC_PERFMON8_PERFMON_LOW                                                                      0x085d
2963 #define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX                                                             2
2964 
2965 
2966 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
2967 // base address: 0xa50
2968 #define mmHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
2969 #define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
2970 #define mmHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
2971 #define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
2972 #define mmHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
2973 #define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
2974 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
2975 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
2976 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
2977 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2978 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
2979 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
2980 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
2981 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2982 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
2983 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
2984 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
2985 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2986 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
2987 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
2988 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
2989 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2990 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
2991 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
2992 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
2993 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
2994 #define mmHUBP3_DCHUBP_CNTL                                                                            0x0887
2995 #define mmHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
2996 #define mmHUBP3_HUBP_CLK_CNTL                                                                          0x0888
2997 #define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
2998 #define mmHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
2999 #define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
3000 #define mmHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088a
3001 #define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
3002 #define mmHUBP3_HUBPREQ_DEBUG                                                                          0x088b
3003 #define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
3004 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x088f
3005 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
3006 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0890
3007 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
3008 
3009 
3010 // addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
3011 // base address: 0xa50
3012 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
3013 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
3014 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
3015 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
3016 #define mmHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
3017 #define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
3018 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
3019 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
3020 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
3021 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
3022 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
3023 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
3024 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
3025 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
3026 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
3027 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
3028 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
3029 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
3030 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
3031 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
3032 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
3033 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
3034 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
3035 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
3036 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
3037 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
3038 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
3039 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
3040 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
3041 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
3042 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
3043 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
3044 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
3045 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
3046 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
3047 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
3048 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
3049 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
3050 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
3051 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
3052 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
3053 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
3054 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
3055 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
3056 #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b4
3057 #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
3058 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b5
3059 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
3060 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b6
3061 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
3062 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b7
3063 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
3064 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b8
3065 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
3066 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b9
3067 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
3068 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08ba
3069 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
3070 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08bb
3071 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
3072 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bc
3073 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
3074 #define mmHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08bd
3075 #define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
3076 #define mmHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08be
3077 #define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
3078 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08bf
3079 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
3080 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08c0
3081 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
3082 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c1
3083 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
3084 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c2
3085 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
3086 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c3
3087 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
3088 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c4
3089 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
3090 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c5
3091 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
3092 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c6
3093 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
3094 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08c7
3095 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
3096 #define mmHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08c8
3097 #define mmHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
3098 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c9
3099 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
3100 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08ca
3101 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
3102 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d7
3103 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
3104 #define mmHUBPREQ3_BLANK_OFFSET_0                                                                      0x08d8
3105 #define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
3106 #define mmHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d9
3107 #define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
3108 #define mmHUBPREQ3_DST_DIMENSIONS                                                                      0x08da
3109 #define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
3110 #define mmHUBPREQ3_DST_AFTER_SCALER                                                                    0x08db
3111 #define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
3112 #define mmHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08dc
3113 #define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
3114 #define mmHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08dd
3115 #define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
3116 #define mmHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08de
3117 #define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
3118 #define mmHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08df
3119 #define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
3120 #define mmHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08e0
3121 #define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
3122 #define mmHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e1
3123 #define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
3124 #define mmHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e2
3125 #define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
3126 #define mmHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e3
3127 #define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
3128 #define mmHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e4
3129 #define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
3130 #define mmHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e5
3131 #define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
3132 #define mmHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e6
3133 #define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
3134 #define mmHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e7
3135 #define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
3136 #define mmHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08e8
3137 #define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
3138 #define mmHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e9
3139 #define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
3140 #define mmHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08ea
3141 #define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
3142 #define mmHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08eb
3143 #define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
3144 #define mmHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08ec
3145 #define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
3146 #define mmHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ed
3147 #define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
3148 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08ee
3149 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
3150 #define mmHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08ef
3151 #define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
3152 #define mmHUBPREQ3_CURSOR_SETTINGS                                                                     0x08f0
3153 #define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
3154 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f1
3155 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
3156 #define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f2
3157 #define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
3158 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f3
3159 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
3160 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f4
3161 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
3162 #define mmHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f7
3163 #define mmHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
3164 #define mmHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08f8
3165 #define mmHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
3166 #define mmHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f9
3167 #define mmHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
3168 #define mmHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08fa
3169 #define mmHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
3170 #define mmHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fb
3171 #define mmHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
3172 #define mmHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fc
3173 #define mmHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
3174 
3175 
3176 // addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
3177 // base address: 0xa50
3178 #define mmHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
3179 #define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
3180 #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
3181 #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
3182 #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
3183 #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
3184 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
3185 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
3186 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
3187 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
3188 #define mmHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
3189 #define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
3190 #define mmHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
3191 #define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
3192 #define mmHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
3193 #define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
3194 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
3195 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
3196 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
3197 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
3198 
3199 
3200 // addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
3201 // base address: 0xa50
3202 #define mmCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
3203 #define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
3204 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
3205 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
3206 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
3207 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
3208 #define mmCURSOR0_3_CURSOR_SIZE                                                                        0x090f
3209 #define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
3210 #define mmCURSOR0_3_CURSOR_POSITION                                                                    0x0910
3211 #define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
3212 #define mmCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
3213 #define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
3214 #define mmCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
3215 #define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
3216 #define mmCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
3217 #define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
3218 #define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
3219 #define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
3220 #define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
3221 #define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
3222 #define mmCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
3223 #define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
3224 #define mmCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
3225 #define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
3226 #define mmCURSOR0_3_DMDATA_CNTL                                                                        0x0918
3227 #define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
3228 #define mmCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
3229 #define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
3230 #define mmCURSOR0_3_DMDATA_STATUS                                                                      0x091a
3231 #define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
3232 #define mmCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
3233 #define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
3234 #define mmCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
3235 #define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2
3236 
3237 
3238 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
3239 // base address: 0x24c4
3240 #define mmDC_PERFMON9_PERFCOUNTER_CNTL                                                                 0x0931
3241 #define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX                                                        2
3242 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2                                                                0x0932
3243 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
3244 #define mmDC_PERFMON9_PERFCOUNTER_STATE                                                                0x0933
3245 #define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX                                                       2
3246 #define mmDC_PERFMON9_PERFMON_CNTL                                                                     0x0934
3247 #define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX                                                            2
3248 #define mmDC_PERFMON9_PERFMON_CNTL2                                                                    0x0935
3249 #define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX                                                           2
3250 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                                          0x0936
3251 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
3252 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW                                                               0x0937
3253 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
3254 #define mmDC_PERFMON9_PERFMON_HI                                                                       0x0938
3255 #define mmDC_PERFMON9_PERFMON_HI_BASE_IDX                                                              2
3256 #define mmDC_PERFMON9_PERFMON_LOW                                                                      0x0939
3257 #define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX                                                             2
3258 
3259 
3260 // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
3261 // base address: 0x0
3262 #define mmDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
3263 #define mmDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
3264 #define mmDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
3265 #define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
3266 #define mmDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
3267 #define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
3268 #define mmDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
3269 #define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
3270 #define mmDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
3271 #define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
3272 #define mmDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
3273 #define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
3274 
3275 
3276 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
3277 // base address: 0x0
3278 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
3279 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
3280 #define mmCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
3281 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
3282 #define mmCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
3283 #define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
3284 #define mmCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
3285 #define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
3286 #define mmCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
3287 #define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
3288 #define mmCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
3289 #define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
3290 #define mmCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
3291 #define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
3292 #define mmCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
3293 #define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
3294 #define mmCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
3295 #define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
3296 #define mmCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
3297 #define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
3298 #define mmCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
3299 #define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
3300 #define mmCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
3301 #define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
3302 #define mmCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
3303 #define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
3304 #define mmCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
3305 #define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
3306 #define mmCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde
3307 #define mmCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2
3308 #define mmCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf
3309 #define mmCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2
3310 #define mmCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0
3311 #define mmCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2
3312 #define mmCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1
3313 #define mmCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2
3314 #define mmCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2
3315 #define mmCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2
3316 #define mmCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3
3317 #define mmCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2
3318 #define mmCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4
3319 #define mmCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2
3320 #define mmCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5
3321 #define mmCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2
3322 #define mmCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6
3323 #define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
3324 #define mmCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7
3325 #define mmCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
3326 #define mmCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8
3327 #define mmCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
3328 #define mmCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9
3329 #define mmCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
3330 #define mmCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea
3331 #define mmCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
3332 #define mmCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb
3333 #define mmCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
3334 #define mmCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec
3335 #define mmCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2
3336 #define mmCNVC_CFG0_PRE_DEGAM                                                                          0x0ced
3337 #define mmCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2
3338 #define mmCNVC_CFG0_PRE_REALPHA                                                                        0x0cee
3339 #define mmCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2
3340 
3341 
3342 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
3343 // base address: 0x0
3344 #define mmCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1
3345 #define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
3346 #define mmCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2
3347 #define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
3348 #define mmCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3
3349 #define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
3350 #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4
3351 #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
3352 
3353 
3354 // addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
3355 // base address: 0x0
3356 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9
3357 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
3358 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa
3359 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
3360 #define mmDSCL0_SCL_MODE                                                                               0x0cfb
3361 #define mmDSCL0_SCL_MODE_BASE_IDX                                                                      2
3362 #define mmDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc
3363 #define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
3364 #define mmDSCL0_DSCL_CONTROL                                                                           0x0cfd
3365 #define mmDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
3366 #define mmDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe
3367 #define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
3368 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff
3369 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
3370 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00
3371 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
3372 #define mmDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01
3373 #define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
3374 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02
3375 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
3376 #define mmDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03
3377 #define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
3378 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04
3379 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
3380 #define mmDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05
3381 #define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
3382 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06
3383 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
3384 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07
3385 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
3386 #define mmDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08
3387 #define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
3388 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09
3389 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
3390 #define mmDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a
3391 #define mmDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2
3392 #define mmDSCL0_DSCL_UPDATE                                                                            0x0d0b
3393 #define mmDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
3394 #define mmDSCL0_DSCL_AUTOCAL                                                                           0x0d0c
3395 #define mmDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
3396 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d
3397 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
3398 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e
3399 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
3400 #define mmDSCL0_OTG_H_BLANK                                                                            0x0d0f
3401 #define mmDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
3402 #define mmDSCL0_OTG_V_BLANK                                                                            0x0d10
3403 #define mmDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
3404 #define mmDSCL0_RECOUT_START                                                                           0x0d11
3405 #define mmDSCL0_RECOUT_START_BASE_IDX                                                                  2
3406 #define mmDSCL0_RECOUT_SIZE                                                                            0x0d12
3407 #define mmDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
3408 #define mmDSCL0_MPC_SIZE                                                                               0x0d13
3409 #define mmDSCL0_MPC_SIZE_BASE_IDX                                                                      2
3410 #define mmDSCL0_LB_DATA_FORMAT                                                                         0x0d14
3411 #define mmDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
3412 #define mmDSCL0_LB_MEMORY_CTRL                                                                         0x0d15
3413 #define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
3414 #define mmDSCL0_LB_V_COUNTER                                                                           0x0d16
3415 #define mmDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
3416 #define mmDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17
3417 #define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
3418 #define mmDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18
3419 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
3420 #define mmDSCL0_OBUF_CONTROL                                                                           0x0d19
3421 #define mmDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
3422 #define mmDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a
3423 #define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
3424 
3425 
3426 // addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
3427 // base address: 0x0
3428 #define mmCM0_CM_CONTROL                                                                               0x0d20
3429 #define mmCM0_CM_CONTROL_BASE_IDX                                                                      2
3430 #define mmCM0_CM_POST_CSC_CONTROL                                                                      0x0d21
3431 #define mmCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
3432 #define mmCM0_CM_POST_CSC_C11_C12                                                                      0x0d22
3433 #define mmCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
3434 #define mmCM0_CM_POST_CSC_C13_C14                                                                      0x0d23
3435 #define mmCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
3436 #define mmCM0_CM_POST_CSC_C21_C22                                                                      0x0d24
3437 #define mmCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
3438 #define mmCM0_CM_POST_CSC_C23_C24                                                                      0x0d25
3439 #define mmCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
3440 #define mmCM0_CM_POST_CSC_C31_C32                                                                      0x0d26
3441 #define mmCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
3442 #define mmCM0_CM_POST_CSC_C33_C34                                                                      0x0d27
3443 #define mmCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
3444 #define mmCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28
3445 #define mmCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
3446 #define mmCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29
3447 #define mmCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
3448 #define mmCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a
3449 #define mmCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
3450 #define mmCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b
3451 #define mmCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
3452 #define mmCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c
3453 #define mmCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
3454 #define mmCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d
3455 #define mmCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
3456 #define mmCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e
3457 #define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
3458 #define mmCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f
3459 #define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
3460 #define mmCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30
3461 #define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
3462 #define mmCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31
3463 #define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
3464 #define mmCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32
3465 #define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
3466 #define mmCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33
3467 #define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
3468 #define mmCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34
3469 #define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
3470 #define mmCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35
3471 #define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
3472 #define mmCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36
3473 #define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
3474 #define mmCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37
3475 #define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
3476 #define mmCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38
3477 #define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
3478 #define mmCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39
3479 #define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
3480 #define mmCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a
3481 #define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
3482 #define mmCM0_CM_BIAS_CR_R                                                                             0x0d3b
3483 #define mmCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
3484 #define mmCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c
3485 #define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
3486 #define mmCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d
3487 #define mmCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
3488 #define mmCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e
3489 #define mmCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
3490 #define mmCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f
3491 #define mmCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
3492 #define mmCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40
3493 #define mmCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
3494 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41
3495 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
3496 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42
3497 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
3498 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43
3499 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
3500 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44
3501 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
3502 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45
3503 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
3504 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46
3505 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
3506 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47
3507 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
3508 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48
3509 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
3510 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49
3511 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
3512 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a
3513 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
3514 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b
3515 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
3516 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c
3517 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
3518 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d
3519 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
3520 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e
3521 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
3522 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f
3523 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
3524 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50
3525 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
3526 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51
3527 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
3528 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52
3529 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
3530 #define mmCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53
3531 #define mmCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
3532 #define mmCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54
3533 #define mmCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
3534 #define mmCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55
3535 #define mmCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
3536 #define mmCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56
3537 #define mmCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
3538 #define mmCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57
3539 #define mmCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
3540 #define mmCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58
3541 #define mmCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
3542 #define mmCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59
3543 #define mmCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
3544 #define mmCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a
3545 #define mmCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
3546 #define mmCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b
3547 #define mmCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
3548 #define mmCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c
3549 #define mmCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
3550 #define mmCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d
3551 #define mmCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
3552 #define mmCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e
3553 #define mmCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
3554 #define mmCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f
3555 #define mmCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
3556 #define mmCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60
3557 #define mmCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
3558 #define mmCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61
3559 #define mmCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
3560 #define mmCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62
3561 #define mmCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
3562 #define mmCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63
3563 #define mmCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
3564 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64
3565 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
3566 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65
3567 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
3568 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66
3569 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
3570 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67
3571 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
3572 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68
3573 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
3574 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69
3575 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
3576 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a
3577 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
3578 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b
3579 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
3580 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c
3581 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
3582 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d
3583 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
3584 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e
3585 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
3586 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f
3587 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
3588 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70
3589 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
3590 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71
3591 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
3592 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72
3593 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
3594 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73
3595 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
3596 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74
3597 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
3598 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75
3599 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
3600 #define mmCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76
3601 #define mmCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
3602 #define mmCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77
3603 #define mmCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
3604 #define mmCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78
3605 #define mmCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
3606 #define mmCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79
3607 #define mmCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
3608 #define mmCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a
3609 #define mmCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
3610 #define mmCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b
3611 #define mmCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
3612 #define mmCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c
3613 #define mmCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
3614 #define mmCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d
3615 #define mmCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
3616 #define mmCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e
3617 #define mmCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
3618 #define mmCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f
3619 #define mmCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
3620 #define mmCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80
3621 #define mmCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
3622 #define mmCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81
3623 #define mmCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
3624 #define mmCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82
3625 #define mmCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
3626 #define mmCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83
3627 #define mmCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
3628 #define mmCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84
3629 #define mmCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
3630 #define mmCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85
3631 #define mmCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
3632 #define mmCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86
3633 #define mmCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
3634 #define mmCM0_CM_BLNDGAM_CONTROL                                                                       0x0d87
3635 #define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
3636 #define mmCM0_CM_BLNDGAM_LUT_INDEX                                                                     0x0d88
3637 #define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
3638 #define mmCM0_CM_BLNDGAM_LUT_DATA                                                                      0x0d89
3639 #define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
3640 #define mmCM0_CM_BLNDGAM_LUT_CONTROL                                                                   0x0d8a
3641 #define mmCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
3642 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0d8b
3643 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
3644 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0d8c
3645 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
3646 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0d8d
3647 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
3648 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x0d8e
3649 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
3650 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x0d8f
3651 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
3652 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x0d90
3653 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
3654 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x0d91
3655 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
3656 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x0d92
3657 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
3658 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x0d93
3659 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
3660 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0d94
3661 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
3662 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0d95
3663 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
3664 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0d96
3665 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
3666 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0d97
3667 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
3668 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0d98
3669 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
3670 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0d99
3671 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
3672 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x0d9a
3673 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
3674 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x0d9b
3675 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
3676 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x0d9c
3677 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
3678 #define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0d9d
3679 #define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
3680 #define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0d9e
3681 #define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
3682 #define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0d9f
3683 #define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
3684 #define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0da0
3685 #define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
3686 #define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0da1
3687 #define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
3688 #define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0da2
3689 #define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
3690 #define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0da3
3691 #define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
3692 #define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0da4
3693 #define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
3694 #define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0da5
3695 #define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
3696 #define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0da6
3697 #define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
3698 #define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0da7
3699 #define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
3700 #define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0da8
3701 #define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
3702 #define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0da9
3703 #define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
3704 #define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0daa
3705 #define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
3706 #define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0dab
3707 #define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
3708 #define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0dac
3709 #define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
3710 #define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0dad
3711 #define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
3712 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0dae
3713 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
3714 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0daf
3715 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
3716 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0db0
3717 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
3718 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x0db1
3719 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
3720 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x0db2
3721 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
3722 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x0db3
3723 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
3724 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x0db4
3725 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
3726 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x0db5
3727 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
3728 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x0db6
3729 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
3730 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0db7
3731 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
3732 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0db8
3733 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
3734 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0db9
3735 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
3736 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0dba
3737 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
3738 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0dbb
3739 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
3740 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0dbc
3741 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
3742 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x0dbd
3743 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
3744 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x0dbe
3745 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
3746 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x0dbf
3747 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
3748 #define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0dc0
3749 #define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
3750 #define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0dc1
3751 #define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
3752 #define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0dc2
3753 #define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
3754 #define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0dc3
3755 #define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
3756 #define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0dc4
3757 #define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
3758 #define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0dc5
3759 #define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
3760 #define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0dc6
3761 #define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
3762 #define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0dc7
3763 #define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
3764 #define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0dc8
3765 #define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
3766 #define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0dc9
3767 #define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
3768 #define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0dca
3769 #define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
3770 #define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0dcb
3771 #define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
3772 #define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0dcc
3773 #define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
3774 #define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0dcd
3775 #define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
3776 #define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0dce
3777 #define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
3778 #define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0dcf
3779 #define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
3780 #define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0dd0
3781 #define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
3782 #define mmCM0_CM_HDR_MULT_COEF                                                                         0x0dd1
3783 #define mmCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
3784 #define mmCM0_CM_MEM_PWR_CTRL                                                                          0x0dd2
3785 #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
3786 #define mmCM0_CM_MEM_PWR_STATUS                                                                        0x0dd3
3787 #define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
3788 #define mmCM0_CM_DEALPHA                                                                               0x0dd5
3789 #define mmCM0_CM_DEALPHA_BASE_IDX                                                                      2
3790 #define mmCM0_CM_COEF_FORMAT                                                                           0x0dd6
3791 #define mmCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
3792 #define mmCM0_CM_SHAPER_CONTROL                                                                        0x0dd7
3793 #define mmCM0_CM_SHAPER_CONTROL_BASE_IDX                                                               2
3794 #define mmCM0_CM_SHAPER_OFFSET_R                                                                       0x0dd8
3795 #define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
3796 #define mmCM0_CM_SHAPER_OFFSET_G                                                                       0x0dd9
3797 #define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
3798 #define mmCM0_CM_SHAPER_OFFSET_B                                                                       0x0dda
3799 #define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
3800 #define mmCM0_CM_SHAPER_SCALE_R                                                                        0x0ddb
3801 #define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
3802 #define mmCM0_CM_SHAPER_SCALE_G_B                                                                      0x0ddc
3803 #define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
3804 #define mmCM0_CM_SHAPER_LUT_INDEX                                                                      0x0ddd
3805 #define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
3806 #define mmCM0_CM_SHAPER_LUT_DATA                                                                       0x0dde
3807 #define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
3808 #define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0ddf
3809 #define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
3810 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0de0
3811 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
3812 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0de1
3813 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
3814 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0de2
3815 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
3816 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0de3
3817 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
3818 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0de4
3819 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
3820 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0de5
3821 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
3822 #define mmCM0_CM_SHAPER_RAMA_REGION_0_1                                                                0x0de6
3823 #define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
3824 #define mmCM0_CM_SHAPER_RAMA_REGION_2_3                                                                0x0de7
3825 #define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
3826 #define mmCM0_CM_SHAPER_RAMA_REGION_4_5                                                                0x0de8
3827 #define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
3828 #define mmCM0_CM_SHAPER_RAMA_REGION_6_7                                                                0x0de9
3829 #define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
3830 #define mmCM0_CM_SHAPER_RAMA_REGION_8_9                                                                0x0dea
3831 #define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
3832 #define mmCM0_CM_SHAPER_RAMA_REGION_10_11                                                              0x0deb
3833 #define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
3834 #define mmCM0_CM_SHAPER_RAMA_REGION_12_13                                                              0x0dec
3835 #define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
3836 #define mmCM0_CM_SHAPER_RAMA_REGION_14_15                                                              0x0ded
3837 #define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
3838 #define mmCM0_CM_SHAPER_RAMA_REGION_16_17                                                              0x0dee
3839 #define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
3840 #define mmCM0_CM_SHAPER_RAMA_REGION_18_19                                                              0x0def
3841 #define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
3842 #define mmCM0_CM_SHAPER_RAMA_REGION_20_21                                                              0x0df0
3843 #define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
3844 #define mmCM0_CM_SHAPER_RAMA_REGION_22_23                                                              0x0df1
3845 #define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
3846 #define mmCM0_CM_SHAPER_RAMA_REGION_24_25                                                              0x0df2
3847 #define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
3848 #define mmCM0_CM_SHAPER_RAMA_REGION_26_27                                                              0x0df3
3849 #define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
3850 #define mmCM0_CM_SHAPER_RAMA_REGION_28_29                                                              0x0df4
3851 #define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
3852 #define mmCM0_CM_SHAPER_RAMA_REGION_30_31                                                              0x0df5
3853 #define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
3854 #define mmCM0_CM_SHAPER_RAMA_REGION_32_33                                                              0x0df6
3855 #define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
3856 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0df7
3857 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
3858 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0df8
3859 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
3860 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0df9
3861 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
3862 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0dfa
3863 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
3864 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0dfb
3865 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
3866 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0dfc
3867 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
3868 #define mmCM0_CM_SHAPER_RAMB_REGION_0_1                                                                0x0dfd
3869 #define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
3870 #define mmCM0_CM_SHAPER_RAMB_REGION_2_3                                                                0x0dfe
3871 #define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
3872 #define mmCM0_CM_SHAPER_RAMB_REGION_4_5                                                                0x0dff
3873 #define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
3874 #define mmCM0_CM_SHAPER_RAMB_REGION_6_7                                                                0x0e00
3875 #define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
3876 #define mmCM0_CM_SHAPER_RAMB_REGION_8_9                                                                0x0e01
3877 #define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
3878 #define mmCM0_CM_SHAPER_RAMB_REGION_10_11                                                              0x0e02
3879 #define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
3880 #define mmCM0_CM_SHAPER_RAMB_REGION_12_13                                                              0x0e03
3881 #define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
3882 #define mmCM0_CM_SHAPER_RAMB_REGION_14_15                                                              0x0e04
3883 #define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
3884 #define mmCM0_CM_SHAPER_RAMB_REGION_16_17                                                              0x0e05
3885 #define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
3886 #define mmCM0_CM_SHAPER_RAMB_REGION_18_19                                                              0x0e06
3887 #define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
3888 #define mmCM0_CM_SHAPER_RAMB_REGION_20_21                                                              0x0e07
3889 #define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
3890 #define mmCM0_CM_SHAPER_RAMB_REGION_22_23                                                              0x0e08
3891 #define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
3892 #define mmCM0_CM_SHAPER_RAMB_REGION_24_25                                                              0x0e09
3893 #define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
3894 #define mmCM0_CM_SHAPER_RAMB_REGION_26_27                                                              0x0e0a
3895 #define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
3896 #define mmCM0_CM_SHAPER_RAMB_REGION_28_29                                                              0x0e0b
3897 #define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
3898 #define mmCM0_CM_SHAPER_RAMB_REGION_30_31                                                              0x0e0c
3899 #define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
3900 #define mmCM0_CM_SHAPER_RAMB_REGION_32_33                                                              0x0e0d
3901 #define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
3902 #define mmCM0_CM_MEM_PWR_CTRL2                                                                         0x0e0e
3903 #define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
3904 #define mmCM0_CM_MEM_PWR_STATUS2                                                                       0x0e0f
3905 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
3906 #define mmCM0_CM_3DLUT_MODE                                                                            0x0e10
3907 #define mmCM0_CM_3DLUT_MODE_BASE_IDX                                                                   2
3908 #define mmCM0_CM_3DLUT_INDEX                                                                           0x0e11
3909 #define mmCM0_CM_3DLUT_INDEX_BASE_IDX                                                                  2
3910 #define mmCM0_CM_3DLUT_DATA                                                                            0x0e12
3911 #define mmCM0_CM_3DLUT_DATA_BASE_IDX                                                                   2
3912 #define mmCM0_CM_3DLUT_DATA_30BIT                                                                      0x0e13
3913 #define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
3914 #define mmCM0_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0e14
3915 #define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
3916 #define mmCM0_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0e15
3917 #define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
3918 #define mmCM0_CM_3DLUT_OUT_OFFSET_R                                                                    0x0e16
3919 #define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
3920 #define mmCM0_CM_3DLUT_OUT_OFFSET_G                                                                    0x0e17
3921 #define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
3922 #define mmCM0_CM_3DLUT_OUT_OFFSET_B                                                                    0x0e18
3923 #define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
3924 #define mmCM0_CM_TEST_DEBUG_INDEX                                                                      0x0e19
3925 #define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
3926 #define mmCM0_CM_TEST_DEBUG_DATA                                                                       0x0e1a
3927 #define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
3928 
3929 
3930 // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
3931 // base address: 0x3890
3932 #define mmDC_PERFMON10_PERFCOUNTER_CNTL                                                                0x0e24
3933 #define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX                                                       2
3934 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2                                                               0x0e25
3935 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
3936 #define mmDC_PERFMON10_PERFCOUNTER_STATE                                                               0x0e26
3937 #define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX                                                      2
3938 #define mmDC_PERFMON10_PERFMON_CNTL                                                                    0x0e27
3939 #define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX                                                           2
3940 #define mmDC_PERFMON10_PERFMON_CNTL2                                                                   0x0e28
3941 #define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX                                                          2
3942 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                                         0x0e29
3943 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
3944 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW                                                              0x0e2a
3945 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
3946 #define mmDC_PERFMON10_PERFMON_HI                                                                      0x0e2b
3947 #define mmDC_PERFMON10_PERFMON_HI_BASE_IDX                                                             2
3948 #define mmDC_PERFMON10_PERFMON_LOW                                                                     0x0e2c
3949 #define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX                                                            2
3950 
3951 
3952 // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
3953 // base address: 0x5ac
3954 #define mmDPP_TOP1_DPP_CONTROL                                                                         0x0e30
3955 #define mmDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
3956 #define mmDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
3957 #define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
3958 #define mmDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
3959 #define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
3960 #define mmDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
3961 #define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
3962 #define mmDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
3963 #define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
3964 #define mmDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
3965 #define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
3966 
3967 
3968 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
3969 // base address: 0x5ac
3970 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
3971 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
3972 #define mmCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
3973 #define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
3974 #define mmCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
3975 #define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
3976 #define mmCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
3977 #define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
3978 #define mmCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
3979 #define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
3980 #define mmCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
3981 #define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
3982 #define mmCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
3983 #define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
3984 #define mmCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
3985 #define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
3986 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
3987 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
3988 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
3989 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
3990 #define mmCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
3991 #define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
3992 #define mmCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
3993 #define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
3994 #define mmCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
3995 #define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
3996 #define mmCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
3997 #define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
3998 #define mmCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49
3999 #define mmCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2
4000 #define mmCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a
4001 #define mmCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2
4002 #define mmCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b
4003 #define mmCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2
4004 #define mmCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c
4005 #define mmCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2
4006 #define mmCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d
4007 #define mmCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2
4008 #define mmCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e
4009 #define mmCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2
4010 #define mmCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f
4011 #define mmCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2
4012 #define mmCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50
4013 #define mmCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2
4014 #define mmCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51
4015 #define mmCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
4016 #define mmCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52
4017 #define mmCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
4018 #define mmCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53
4019 #define mmCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
4020 #define mmCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54
4021 #define mmCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
4022 #define mmCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55
4023 #define mmCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
4024 #define mmCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56
4025 #define mmCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
4026 #define mmCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57
4027 #define mmCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2
4028 #define mmCNVC_CFG1_PRE_DEGAM                                                                          0x0e58
4029 #define mmCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2
4030 #define mmCNVC_CFG1_PRE_REALPHA                                                                        0x0e59
4031 #define mmCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2
4032 
4033 
4034 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
4035 // base address: 0x5ac
4036 #define mmCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c
4037 #define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
4038 #define mmCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d
4039 #define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
4040 #define mmCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e
4041 #define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
4042 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f
4043 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
4044 
4045 
4046 // addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
4047 // base address: 0x5ac
4048 #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64
4049 #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
4050 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65
4051 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
4052 #define mmDSCL1_SCL_MODE                                                                               0x0e66
4053 #define mmDSCL1_SCL_MODE_BASE_IDX                                                                      2
4054 #define mmDSCL1_SCL_TAP_CONTROL                                                                        0x0e67
4055 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
4056 #define mmDSCL1_DSCL_CONTROL                                                                           0x0e68
4057 #define mmDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
4058 #define mmDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69
4059 #define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
4060 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a
4061 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
4062 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b
4063 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
4064 #define mmDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c
4065 #define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
4066 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d
4067 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
4068 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e
4069 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
4070 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f
4071 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
4072 #define mmDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70
4073 #define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
4074 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71
4075 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
4076 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72
4077 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
4078 #define mmDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73
4079 #define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
4080 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74
4081 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
4082 #define mmDSCL1_SCL_BLACK_COLOR                                                                        0x0e75
4083 #define mmDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2
4084 #define mmDSCL1_DSCL_UPDATE                                                                            0x0e76
4085 #define mmDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
4086 #define mmDSCL1_DSCL_AUTOCAL                                                                           0x0e77
4087 #define mmDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
4088 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78
4089 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
4090 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79
4091 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
4092 #define mmDSCL1_OTG_H_BLANK                                                                            0x0e7a
4093 #define mmDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
4094 #define mmDSCL1_OTG_V_BLANK                                                                            0x0e7b
4095 #define mmDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
4096 #define mmDSCL1_RECOUT_START                                                                           0x0e7c
4097 #define mmDSCL1_RECOUT_START_BASE_IDX                                                                  2
4098 #define mmDSCL1_RECOUT_SIZE                                                                            0x0e7d
4099 #define mmDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
4100 #define mmDSCL1_MPC_SIZE                                                                               0x0e7e
4101 #define mmDSCL1_MPC_SIZE_BASE_IDX                                                                      2
4102 #define mmDSCL1_LB_DATA_FORMAT                                                                         0x0e7f
4103 #define mmDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
4104 #define mmDSCL1_LB_MEMORY_CTRL                                                                         0x0e80
4105 #define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
4106 #define mmDSCL1_LB_V_COUNTER                                                                           0x0e81
4107 #define mmDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
4108 #define mmDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82
4109 #define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
4110 #define mmDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83
4111 #define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
4112 #define mmDSCL1_OBUF_CONTROL                                                                           0x0e84
4113 #define mmDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
4114 #define mmDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85
4115 #define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
4116 
4117 
4118 // addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
4119 // base address: 0x5ac
4120 #define mmCM1_CM_CONTROL                                                                               0x0e8b
4121 #define mmCM1_CM_CONTROL_BASE_IDX                                                                      2
4122 #define mmCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c
4123 #define mmCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
4124 #define mmCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d
4125 #define mmCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
4126 #define mmCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e
4127 #define mmCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
4128 #define mmCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f
4129 #define mmCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
4130 #define mmCM1_CM_POST_CSC_C23_C24                                                                      0x0e90
4131 #define mmCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
4132 #define mmCM1_CM_POST_CSC_C31_C32                                                                      0x0e91
4133 #define mmCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
4134 #define mmCM1_CM_POST_CSC_C33_C34                                                                      0x0e92
4135 #define mmCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
4136 #define mmCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93
4137 #define mmCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
4138 #define mmCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94
4139 #define mmCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
4140 #define mmCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95
4141 #define mmCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
4142 #define mmCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96
4143 #define mmCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
4144 #define mmCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97
4145 #define mmCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
4146 #define mmCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98
4147 #define mmCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
4148 #define mmCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99
4149 #define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
4150 #define mmCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a
4151 #define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
4152 #define mmCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b
4153 #define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
4154 #define mmCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c
4155 #define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
4156 #define mmCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d
4157 #define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
4158 #define mmCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e
4159 #define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
4160 #define mmCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f
4161 #define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
4162 #define mmCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0
4163 #define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
4164 #define mmCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1
4165 #define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
4166 #define mmCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2
4167 #define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
4168 #define mmCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3
4169 #define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
4170 #define mmCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4
4171 #define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
4172 #define mmCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5
4173 #define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
4174 #define mmCM1_CM_BIAS_CR_R                                                                             0x0ea6
4175 #define mmCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
4176 #define mmCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7
4177 #define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
4178 #define mmCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8
4179 #define mmCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
4180 #define mmCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9
4181 #define mmCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
4182 #define mmCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa
4183 #define mmCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
4184 #define mmCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab
4185 #define mmCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
4186 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac
4187 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
4188 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead
4189 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
4190 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae
4191 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
4192 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf
4193 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
4194 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0
4195 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
4196 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1
4197 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
4198 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2
4199 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
4200 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3
4201 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
4202 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4
4203 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
4204 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5
4205 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
4206 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6
4207 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
4208 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7
4209 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
4210 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8
4211 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
4212 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9
4213 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
4214 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba
4215 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
4216 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb
4217 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
4218 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc
4219 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
4220 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd
4221 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
4222 #define mmCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe
4223 #define mmCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
4224 #define mmCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf
4225 #define mmCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
4226 #define mmCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0
4227 #define mmCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
4228 #define mmCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1
4229 #define mmCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
4230 #define mmCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2
4231 #define mmCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
4232 #define mmCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3
4233 #define mmCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
4234 #define mmCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4
4235 #define mmCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
4236 #define mmCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5
4237 #define mmCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
4238 #define mmCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6
4239 #define mmCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
4240 #define mmCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7
4241 #define mmCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
4242 #define mmCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8
4243 #define mmCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
4244 #define mmCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9
4245 #define mmCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
4246 #define mmCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca
4247 #define mmCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
4248 #define mmCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb
4249 #define mmCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
4250 #define mmCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc
4251 #define mmCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
4252 #define mmCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd
4253 #define mmCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
4254 #define mmCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece
4255 #define mmCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
4256 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf
4257 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
4258 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0
4259 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
4260 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1
4261 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
4262 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2
4263 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
4264 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3
4265 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
4266 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4
4267 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
4268 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5
4269 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
4270 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6
4271 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
4272 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7
4273 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
4274 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8
4275 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
4276 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9
4277 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
4278 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda
4279 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
4280 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb
4281 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
4282 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc
4283 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
4284 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd
4285 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
4286 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede
4287 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
4288 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf
4289 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
4290 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0
4291 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
4292 #define mmCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1
4293 #define mmCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
4294 #define mmCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2
4295 #define mmCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
4296 #define mmCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3
4297 #define mmCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
4298 #define mmCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4
4299 #define mmCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
4300 #define mmCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5
4301 #define mmCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
4302 #define mmCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6
4303 #define mmCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
4304 #define mmCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7
4305 #define mmCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
4306 #define mmCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8
4307 #define mmCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
4308 #define mmCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9
4309 #define mmCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
4310 #define mmCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea
4311 #define mmCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
4312 #define mmCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb
4313 #define mmCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
4314 #define mmCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec
4315 #define mmCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
4316 #define mmCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed
4317 #define mmCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
4318 #define mmCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee
4319 #define mmCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
4320 #define mmCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef
4321 #define mmCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
4322 #define mmCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0
4323 #define mmCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
4324 #define mmCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1
4325 #define mmCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
4326 #define mmCM1_CM_BLNDGAM_CONTROL                                                                       0x0ef2
4327 #define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
4328 #define mmCM1_CM_BLNDGAM_LUT_INDEX                                                                     0x0ef3
4329 #define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
4330 #define mmCM1_CM_BLNDGAM_LUT_DATA                                                                      0x0ef4
4331 #define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
4332 #define mmCM1_CM_BLNDGAM_LUT_CONTROL                                                                   0x0ef5
4333 #define mmCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
4334 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0ef6
4335 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
4336 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0ef7
4337 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
4338 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0ef8
4339 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
4340 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x0ef9
4341 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
4342 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x0efa
4343 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
4344 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x0efb
4345 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
4346 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x0efc
4347 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
4348 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x0efd
4349 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
4350 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x0efe
4351 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
4352 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0eff
4353 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
4354 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0f00
4355 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
4356 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0f01
4357 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
4358 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0f02
4359 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
4360 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0f03
4361 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
4362 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0f04
4363 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
4364 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x0f05
4365 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
4366 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x0f06
4367 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
4368 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x0f07
4369 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
4370 #define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0f08
4371 #define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
4372 #define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0f09
4373 #define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
4374 #define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0f0a
4375 #define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
4376 #define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0f0b
4377 #define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
4378 #define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0f0c
4379 #define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
4380 #define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0f0d
4381 #define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
4382 #define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0f0e
4383 #define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
4384 #define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0f0f
4385 #define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
4386 #define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0f10
4387 #define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
4388 #define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0f11
4389 #define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
4390 #define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0f12
4391 #define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
4392 #define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0f13
4393 #define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
4394 #define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0f14
4395 #define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
4396 #define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0f15
4397 #define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
4398 #define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0f16
4399 #define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
4400 #define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0f17
4401 #define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
4402 #define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0f18
4403 #define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
4404 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0f19
4405 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
4406 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0f1a
4407 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
4408 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0f1b
4409 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
4410 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x0f1c
4411 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
4412 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x0f1d
4413 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
4414 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x0f1e
4415 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
4416 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x0f1f
4417 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
4418 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x0f20
4419 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
4420 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x0f21
4421 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
4422 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0f22
4423 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
4424 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0f23
4425 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
4426 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0f24
4427 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
4428 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0f25
4429 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
4430 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0f26
4431 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
4432 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0f27
4433 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
4434 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x0f28
4435 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
4436 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x0f29
4437 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
4438 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x0f2a
4439 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
4440 #define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0f2b
4441 #define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
4442 #define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0f2c
4443 #define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
4444 #define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0f2d
4445 #define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
4446 #define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0f2e
4447 #define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
4448 #define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0f2f
4449 #define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
4450 #define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0f30
4451 #define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
4452 #define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0f31
4453 #define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
4454 #define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0f32
4455 #define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
4456 #define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0f33
4457 #define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
4458 #define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0f34
4459 #define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
4460 #define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0f35
4461 #define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
4462 #define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0f36
4463 #define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
4464 #define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0f37
4465 #define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
4466 #define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0f38
4467 #define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
4468 #define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0f39
4469 #define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
4470 #define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0f3a
4471 #define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
4472 #define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0f3b
4473 #define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
4474 #define mmCM1_CM_HDR_MULT_COEF                                                                         0x0f3c
4475 #define mmCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
4476 #define mmCM1_CM_MEM_PWR_CTRL                                                                          0x0f3d
4477 #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
4478 #define mmCM1_CM_MEM_PWR_STATUS                                                                        0x0f3e
4479 #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
4480 #define mmCM1_CM_DEALPHA                                                                               0x0f40
4481 #define mmCM1_CM_DEALPHA_BASE_IDX                                                                      2
4482 #define mmCM1_CM_COEF_FORMAT                                                                           0x0f41
4483 #define mmCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
4484 #define mmCM1_CM_SHAPER_CONTROL                                                                        0x0f42
4485 #define mmCM1_CM_SHAPER_CONTROL_BASE_IDX                                                               2
4486 #define mmCM1_CM_SHAPER_OFFSET_R                                                                       0x0f43
4487 #define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
4488 #define mmCM1_CM_SHAPER_OFFSET_G                                                                       0x0f44
4489 #define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
4490 #define mmCM1_CM_SHAPER_OFFSET_B                                                                       0x0f45
4491 #define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
4492 #define mmCM1_CM_SHAPER_SCALE_R                                                                        0x0f46
4493 #define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
4494 #define mmCM1_CM_SHAPER_SCALE_G_B                                                                      0x0f47
4495 #define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
4496 #define mmCM1_CM_SHAPER_LUT_INDEX                                                                      0x0f48
4497 #define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
4498 #define mmCM1_CM_SHAPER_LUT_DATA                                                                       0x0f49
4499 #define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
4500 #define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0f4a
4501 #define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
4502 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0f4b
4503 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
4504 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0f4c
4505 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
4506 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0f4d
4507 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
4508 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0f4e
4509 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
4510 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0f4f
4511 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
4512 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0f50
4513 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
4514 #define mmCM1_CM_SHAPER_RAMA_REGION_0_1                                                                0x0f51
4515 #define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
4516 #define mmCM1_CM_SHAPER_RAMA_REGION_2_3                                                                0x0f52
4517 #define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
4518 #define mmCM1_CM_SHAPER_RAMA_REGION_4_5                                                                0x0f53
4519 #define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
4520 #define mmCM1_CM_SHAPER_RAMA_REGION_6_7                                                                0x0f54
4521 #define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
4522 #define mmCM1_CM_SHAPER_RAMA_REGION_8_9                                                                0x0f55
4523 #define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
4524 #define mmCM1_CM_SHAPER_RAMA_REGION_10_11                                                              0x0f56
4525 #define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
4526 #define mmCM1_CM_SHAPER_RAMA_REGION_12_13                                                              0x0f57
4527 #define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
4528 #define mmCM1_CM_SHAPER_RAMA_REGION_14_15                                                              0x0f58
4529 #define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
4530 #define mmCM1_CM_SHAPER_RAMA_REGION_16_17                                                              0x0f59
4531 #define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
4532 #define mmCM1_CM_SHAPER_RAMA_REGION_18_19                                                              0x0f5a
4533 #define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
4534 #define mmCM1_CM_SHAPER_RAMA_REGION_20_21                                                              0x0f5b
4535 #define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
4536 #define mmCM1_CM_SHAPER_RAMA_REGION_22_23                                                              0x0f5c
4537 #define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
4538 #define mmCM1_CM_SHAPER_RAMA_REGION_24_25                                                              0x0f5d
4539 #define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
4540 #define mmCM1_CM_SHAPER_RAMA_REGION_26_27                                                              0x0f5e
4541 #define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
4542 #define mmCM1_CM_SHAPER_RAMA_REGION_28_29                                                              0x0f5f
4543 #define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
4544 #define mmCM1_CM_SHAPER_RAMA_REGION_30_31                                                              0x0f60
4545 #define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
4546 #define mmCM1_CM_SHAPER_RAMA_REGION_32_33                                                              0x0f61
4547 #define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
4548 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0f62
4549 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
4550 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0f63
4551 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
4552 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0f64
4553 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
4554 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0f65
4555 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
4556 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0f66
4557 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
4558 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0f67
4559 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
4560 #define mmCM1_CM_SHAPER_RAMB_REGION_0_1                                                                0x0f68
4561 #define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
4562 #define mmCM1_CM_SHAPER_RAMB_REGION_2_3                                                                0x0f69
4563 #define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
4564 #define mmCM1_CM_SHAPER_RAMB_REGION_4_5                                                                0x0f6a
4565 #define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
4566 #define mmCM1_CM_SHAPER_RAMB_REGION_6_7                                                                0x0f6b
4567 #define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
4568 #define mmCM1_CM_SHAPER_RAMB_REGION_8_9                                                                0x0f6c
4569 #define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
4570 #define mmCM1_CM_SHAPER_RAMB_REGION_10_11                                                              0x0f6d
4571 #define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
4572 #define mmCM1_CM_SHAPER_RAMB_REGION_12_13                                                              0x0f6e
4573 #define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
4574 #define mmCM1_CM_SHAPER_RAMB_REGION_14_15                                                              0x0f6f
4575 #define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
4576 #define mmCM1_CM_SHAPER_RAMB_REGION_16_17                                                              0x0f70
4577 #define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
4578 #define mmCM1_CM_SHAPER_RAMB_REGION_18_19                                                              0x0f71
4579 #define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
4580 #define mmCM1_CM_SHAPER_RAMB_REGION_20_21                                                              0x0f72
4581 #define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
4582 #define mmCM1_CM_SHAPER_RAMB_REGION_22_23                                                              0x0f73
4583 #define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
4584 #define mmCM1_CM_SHAPER_RAMB_REGION_24_25                                                              0x0f74
4585 #define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
4586 #define mmCM1_CM_SHAPER_RAMB_REGION_26_27                                                              0x0f75
4587 #define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
4588 #define mmCM1_CM_SHAPER_RAMB_REGION_28_29                                                              0x0f76
4589 #define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
4590 #define mmCM1_CM_SHAPER_RAMB_REGION_30_31                                                              0x0f77
4591 #define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
4592 #define mmCM1_CM_SHAPER_RAMB_REGION_32_33                                                              0x0f78
4593 #define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
4594 #define mmCM1_CM_MEM_PWR_CTRL2                                                                         0x0f79
4595 #define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
4596 #define mmCM1_CM_MEM_PWR_STATUS2                                                                       0x0f7a
4597 #define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
4598 #define mmCM1_CM_3DLUT_MODE                                                                            0x0f7b
4599 #define mmCM1_CM_3DLUT_MODE_BASE_IDX                                                                   2
4600 #define mmCM1_CM_3DLUT_INDEX                                                                           0x0f7c
4601 #define mmCM1_CM_3DLUT_INDEX_BASE_IDX                                                                  2
4602 #define mmCM1_CM_3DLUT_DATA                                                                            0x0f7d
4603 #define mmCM1_CM_3DLUT_DATA_BASE_IDX                                                                   2
4604 #define mmCM1_CM_3DLUT_DATA_30BIT                                                                      0x0f7e
4605 #define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
4606 #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0f7f
4607 #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
4608 #define mmCM1_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0f80
4609 #define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
4610 #define mmCM1_CM_3DLUT_OUT_OFFSET_R                                                                    0x0f81
4611 #define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
4612 #define mmCM1_CM_3DLUT_OUT_OFFSET_G                                                                    0x0f82
4613 #define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
4614 #define mmCM1_CM_3DLUT_OUT_OFFSET_B                                                                    0x0f83
4615 #define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
4616 #define mmCM1_CM_TEST_DEBUG_INDEX                                                                      0x0f84
4617 #define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
4618 #define mmCM1_CM_TEST_DEBUG_DATA                                                                       0x0f85
4619 #define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
4620 
4621 
4622 // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
4623 // base address: 0x3e3c
4624 #define mmDC_PERFMON11_PERFCOUNTER_CNTL                                                                0x0f8f
4625 #define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX                                                       2
4626 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2                                                               0x0f90
4627 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
4628 #define mmDC_PERFMON11_PERFCOUNTER_STATE                                                               0x0f91
4629 #define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX                                                      2
4630 #define mmDC_PERFMON11_PERFMON_CNTL                                                                    0x0f92
4631 #define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX                                                           2
4632 #define mmDC_PERFMON11_PERFMON_CNTL2                                                                   0x0f93
4633 #define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX                                                          2
4634 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                                         0x0f94
4635 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
4636 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW                                                              0x0f95
4637 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
4638 #define mmDC_PERFMON11_PERFMON_HI                                                                      0x0f96
4639 #define mmDC_PERFMON11_PERFMON_HI_BASE_IDX                                                             2
4640 #define mmDC_PERFMON11_PERFMON_LOW                                                                     0x0f97
4641 #define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX                                                            2
4642 
4643 
4644 // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
4645 // base address: 0xb58
4646 #define mmDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
4647 #define mmDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
4648 #define mmDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
4649 #define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
4650 #define mmDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
4651 #define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
4652 #define mmDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
4653 #define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
4654 #define mmDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
4655 #define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
4656 #define mmDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
4657 #define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2
4658 
4659 
4660 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
4661 // base address: 0xb58
4662 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
4663 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
4664 #define mmCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
4665 #define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
4666 #define mmCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
4667 #define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
4668 #define mmCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
4669 #define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
4670 #define mmCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
4671 #define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
4672 #define mmCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
4673 #define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
4674 #define mmCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
4675 #define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
4676 #define mmCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
4677 #define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
4678 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
4679 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
4680 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
4681 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
4682 #define mmCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
4683 #define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
4684 #define mmCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
4685 #define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
4686 #define mmCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
4687 #define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
4688 #define mmCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
4689 #define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
4690 #define mmCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4
4691 #define mmCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2
4692 #define mmCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5
4693 #define mmCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2
4694 #define mmCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6
4695 #define mmCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2
4696 #define mmCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7
4697 #define mmCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2
4698 #define mmCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8
4699 #define mmCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2
4700 #define mmCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9
4701 #define mmCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2
4702 #define mmCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba
4703 #define mmCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2
4704 #define mmCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb
4705 #define mmCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2
4706 #define mmCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc
4707 #define mmCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
4708 #define mmCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd
4709 #define mmCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
4710 #define mmCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe
4711 #define mmCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
4712 #define mmCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf
4713 #define mmCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
4714 #define mmCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0
4715 #define mmCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
4716 #define mmCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1
4717 #define mmCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
4718 #define mmCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2
4719 #define mmCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2
4720 #define mmCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3
4721 #define mmCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2
4722 #define mmCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4
4723 #define mmCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2
4724 
4725 
4726 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
4727 // base address: 0xb58
4728 #define mmCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fc7
4729 #define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
4730 #define mmCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fc8
4731 #define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
4732 #define mmCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fc9
4733 #define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
4734 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fca
4735 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
4736 
4737 
4738 // addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
4739 // base address: 0xb58
4740 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fcf
4741 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
4742 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fd0
4743 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
4744 #define mmDSCL2_SCL_MODE                                                                               0x0fd1
4745 #define mmDSCL2_SCL_MODE_BASE_IDX                                                                      2
4746 #define mmDSCL2_SCL_TAP_CONTROL                                                                        0x0fd2
4747 #define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
4748 #define mmDSCL2_DSCL_CONTROL                                                                           0x0fd3
4749 #define mmDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
4750 #define mmDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fd4
4751 #define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
4752 #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fd5
4753 #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
4754 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fd6
4755 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
4756 #define mmDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fd7
4757 #define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
4758 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fd8
4759 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
4760 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fd9
4761 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
4762 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fda
4763 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
4764 #define mmDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fdb
4765 #define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
4766 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fdc
4767 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
4768 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fdd
4769 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
4770 #define mmDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fde
4771 #define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
4772 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fdf
4773 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
4774 #define mmDSCL2_SCL_BLACK_COLOR                                                                        0x0fe0
4775 #define mmDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2
4776 #define mmDSCL2_DSCL_UPDATE                                                                            0x0fe1
4777 #define mmDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
4778 #define mmDSCL2_DSCL_AUTOCAL                                                                           0x0fe2
4779 #define mmDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
4780 #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fe3
4781 #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
4782 #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fe4
4783 #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
4784 #define mmDSCL2_OTG_H_BLANK                                                                            0x0fe5
4785 #define mmDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
4786 #define mmDSCL2_OTG_V_BLANK                                                                            0x0fe6
4787 #define mmDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
4788 #define mmDSCL2_RECOUT_START                                                                           0x0fe7
4789 #define mmDSCL2_RECOUT_START_BASE_IDX                                                                  2
4790 #define mmDSCL2_RECOUT_SIZE                                                                            0x0fe8
4791 #define mmDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
4792 #define mmDSCL2_MPC_SIZE                                                                               0x0fe9
4793 #define mmDSCL2_MPC_SIZE_BASE_IDX                                                                      2
4794 #define mmDSCL2_LB_DATA_FORMAT                                                                         0x0fea
4795 #define mmDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
4796 #define mmDSCL2_LB_MEMORY_CTRL                                                                         0x0feb
4797 #define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
4798 #define mmDSCL2_LB_V_COUNTER                                                                           0x0fec
4799 #define mmDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
4800 #define mmDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fed
4801 #define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
4802 #define mmDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fee
4803 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
4804 #define mmDSCL2_OBUF_CONTROL                                                                           0x0fef
4805 #define mmDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
4806 #define mmDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ff0
4807 #define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
4808 
4809 
4810 // addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
4811 // base address: 0xb58
4812 #define mmCM2_CM_CONTROL                                                                               0x0ff6
4813 #define mmCM2_CM_CONTROL_BASE_IDX                                                                      2
4814 #define mmCM2_CM_POST_CSC_CONTROL                                                                      0x0ff7
4815 #define mmCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
4816 #define mmCM2_CM_POST_CSC_C11_C12                                                                      0x0ff8
4817 #define mmCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
4818 #define mmCM2_CM_POST_CSC_C13_C14                                                                      0x0ff9
4819 #define mmCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
4820 #define mmCM2_CM_POST_CSC_C21_C22                                                                      0x0ffa
4821 #define mmCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
4822 #define mmCM2_CM_POST_CSC_C23_C24                                                                      0x0ffb
4823 #define mmCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
4824 #define mmCM2_CM_POST_CSC_C31_C32                                                                      0x0ffc
4825 #define mmCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
4826 #define mmCM2_CM_POST_CSC_C33_C34                                                                      0x0ffd
4827 #define mmCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
4828 #define mmCM2_CM_POST_CSC_B_C11_C12                                                                    0x0ffe
4829 #define mmCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
4830 #define mmCM2_CM_POST_CSC_B_C13_C14                                                                    0x0fff
4831 #define mmCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
4832 #define mmCM2_CM_POST_CSC_B_C21_C22                                                                    0x1000
4833 #define mmCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
4834 #define mmCM2_CM_POST_CSC_B_C23_C24                                                                    0x1001
4835 #define mmCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
4836 #define mmCM2_CM_POST_CSC_B_C31_C32                                                                    0x1002
4837 #define mmCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
4838 #define mmCM2_CM_POST_CSC_B_C33_C34                                                                    0x1003
4839 #define mmCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
4840 #define mmCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x1004
4841 #define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
4842 #define mmCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x1005
4843 #define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
4844 #define mmCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1006
4845 #define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
4846 #define mmCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1007
4847 #define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
4848 #define mmCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1008
4849 #define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
4850 #define mmCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1009
4851 #define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
4852 #define mmCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x100a
4853 #define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
4854 #define mmCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x100b
4855 #define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
4856 #define mmCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x100c
4857 #define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
4858 #define mmCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x100d
4859 #define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
4860 #define mmCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x100e
4861 #define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
4862 #define mmCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x100f
4863 #define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
4864 #define mmCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1010
4865 #define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
4866 #define mmCM2_CM_BIAS_CR_R                                                                             0x1011
4867 #define mmCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
4868 #define mmCM2_CM_BIAS_Y_G_CB_B                                                                         0x1012
4869 #define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
4870 #define mmCM2_CM_GAMCOR_CONTROL                                                                        0x1013
4871 #define mmCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
4872 #define mmCM2_CM_GAMCOR_LUT_INDEX                                                                      0x1014
4873 #define mmCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
4874 #define mmCM2_CM_GAMCOR_LUT_DATA                                                                       0x1015
4875 #define mmCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
4876 #define mmCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1016
4877 #define mmCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
4878 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1017
4879 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
4880 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1018
4881 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
4882 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1019
4883 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
4884 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x101a
4885 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
4886 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x101b
4887 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
4888 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x101c
4889 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
4890 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x101d
4891 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
4892 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x101e
4893 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
4894 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x101f
4895 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
4896 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x1020
4897 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
4898 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x1021
4899 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
4900 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x1022
4901 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
4902 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x1023
4903 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
4904 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x1024
4905 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
4906 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1025
4907 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
4908 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1026
4909 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
4910 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1027
4911 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
4912 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1028
4913 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
4914 #define mmCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1029
4915 #define mmCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
4916 #define mmCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x102a
4917 #define mmCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
4918 #define mmCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x102b
4919 #define mmCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
4920 #define mmCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x102c
4921 #define mmCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
4922 #define mmCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x102d
4923 #define mmCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
4924 #define mmCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x102e
4925 #define mmCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
4926 #define mmCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x102f
4927 #define mmCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
4928 #define mmCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1030
4929 #define mmCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
4930 #define mmCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1031
4931 #define mmCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
4932 #define mmCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1032
4933 #define mmCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
4934 #define mmCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1033
4935 #define mmCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
4936 #define mmCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x1034
4937 #define mmCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
4938 #define mmCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x1035
4939 #define mmCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
4940 #define mmCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1036
4941 #define mmCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
4942 #define mmCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1037
4943 #define mmCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
4944 #define mmCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1038
4945 #define mmCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
4946 #define mmCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1039
4947 #define mmCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
4948 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x103a
4949 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
4950 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x103b
4951 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
4952 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x103c
4953 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
4954 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x103d
4955 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
4956 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x103e
4957 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
4958 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x103f
4959 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
4960 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1040
4961 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
4962 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1041
4963 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
4964 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1042
4965 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
4966 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1043
4967 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
4968 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x1044
4969 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
4970 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x1045
4971 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
4972 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1046
4973 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
4974 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1047
4975 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
4976 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1048
4977 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
4978 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1049
4979 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
4980 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x104a
4981 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
4982 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x104b
4983 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
4984 #define mmCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x104c
4985 #define mmCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
4986 #define mmCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x104d
4987 #define mmCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
4988 #define mmCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x104e
4989 #define mmCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
4990 #define mmCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x104f
4991 #define mmCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
4992 #define mmCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1050
4993 #define mmCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
4994 #define mmCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1051
4995 #define mmCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
4996 #define mmCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1052
4997 #define mmCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
4998 #define mmCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1053
4999 #define mmCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
5000 #define mmCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x1054
5001 #define mmCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
5002 #define mmCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x1055
5003 #define mmCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
5004 #define mmCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1056
5005 #define mmCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
5006 #define mmCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1057
5007 #define mmCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
5008 #define mmCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1058
5009 #define mmCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
5010 #define mmCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1059
5011 #define mmCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
5012 #define mmCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x105a
5013 #define mmCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
5014 #define mmCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x105b
5015 #define mmCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
5016 #define mmCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x105c
5017 #define mmCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
5018 #define mmCM2_CM_BLNDGAM_CONTROL                                                                       0x105d
5019 #define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
5020 #define mmCM2_CM_BLNDGAM_LUT_INDEX                                                                     0x105e
5021 #define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
5022 #define mmCM2_CM_BLNDGAM_LUT_DATA                                                                      0x105f
5023 #define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
5024 #define mmCM2_CM_BLNDGAM_LUT_CONTROL                                                                   0x1060
5025 #define mmCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
5026 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x1061
5027 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
5028 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x1062
5029 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
5030 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x1063
5031 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
5032 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x1064
5033 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
5034 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x1065
5035 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
5036 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x1066
5037 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
5038 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x1067
5039 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
5040 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x1068
5041 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
5042 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x1069
5043 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
5044 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x106a
5045 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
5046 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x106b
5047 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
5048 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x106c
5049 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
5050 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x106d
5051 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
5052 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x106e
5053 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
5054 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x106f
5055 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
5056 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x1070
5057 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
5058 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x1071
5059 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
5060 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x1072
5061 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
5062 #define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x1073
5063 #define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
5064 #define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x1074
5065 #define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
5066 #define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x1075
5067 #define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
5068 #define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x1076
5069 #define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
5070 #define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x1077
5071 #define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
5072 #define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x1078
5073 #define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
5074 #define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x1079
5075 #define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
5076 #define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x107a
5077 #define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
5078 #define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x107b
5079 #define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
5080 #define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x107c
5081 #define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
5082 #define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x107d
5083 #define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
5084 #define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x107e
5085 #define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
5086 #define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x107f
5087 #define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
5088 #define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x1080
5089 #define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
5090 #define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x1081
5091 #define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
5092 #define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x1082
5093 #define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
5094 #define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x1083
5095 #define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
5096 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x1084
5097 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
5098 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x1085
5099 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
5100 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x1086
5101 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
5102 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x1087
5103 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
5104 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x1088
5105 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
5106 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x1089
5107 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
5108 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x108a
5109 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
5110 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x108b
5111 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
5112 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x108c
5113 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
5114 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x108d
5115 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
5116 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x108e
5117 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
5118 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x108f
5119 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
5120 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x1090
5121 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
5122 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x1091
5123 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
5124 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x1092
5125 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
5126 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x1093
5127 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
5128 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x1094
5129 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
5130 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x1095
5131 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
5132 #define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x1096
5133 #define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
5134 #define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x1097
5135 #define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
5136 #define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x1098
5137 #define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
5138 #define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x1099
5139 #define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
5140 #define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x109a
5141 #define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
5142 #define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x109b
5143 #define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
5144 #define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x109c
5145 #define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
5146 #define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x109d
5147 #define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
5148 #define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x109e
5149 #define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
5150 #define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x109f
5151 #define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
5152 #define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x10a0
5153 #define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
5154 #define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x10a1
5155 #define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
5156 #define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x10a2
5157 #define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
5158 #define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x10a3
5159 #define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
5160 #define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x10a4
5161 #define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
5162 #define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x10a5
5163 #define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
5164 #define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x10a6
5165 #define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
5166 #define mmCM2_CM_HDR_MULT_COEF                                                                         0x10a7
5167 #define mmCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
5168 #define mmCM2_CM_MEM_PWR_CTRL                                                                          0x10a8
5169 #define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
5170 #define mmCM2_CM_MEM_PWR_STATUS                                                                        0x10a9
5171 #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
5172 #define mmCM2_CM_DEALPHA                                                                               0x10ab
5173 #define mmCM2_CM_DEALPHA_BASE_IDX                                                                      2
5174 #define mmCM2_CM_COEF_FORMAT                                                                           0x10ac
5175 #define mmCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
5176 #define mmCM2_CM_SHAPER_CONTROL                                                                        0x10ad
5177 #define mmCM2_CM_SHAPER_CONTROL_BASE_IDX                                                               2
5178 #define mmCM2_CM_SHAPER_OFFSET_R                                                                       0x10ae
5179 #define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
5180 #define mmCM2_CM_SHAPER_OFFSET_G                                                                       0x10af
5181 #define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
5182 #define mmCM2_CM_SHAPER_OFFSET_B                                                                       0x10b0
5183 #define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
5184 #define mmCM2_CM_SHAPER_SCALE_R                                                                        0x10b1
5185 #define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
5186 #define mmCM2_CM_SHAPER_SCALE_G_B                                                                      0x10b2
5187 #define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
5188 #define mmCM2_CM_SHAPER_LUT_INDEX                                                                      0x10b3
5189 #define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
5190 #define mmCM2_CM_SHAPER_LUT_DATA                                                                       0x10b4
5191 #define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
5192 #define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x10b5
5193 #define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
5194 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_B                                                              0x10b6
5195 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
5196 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_G                                                              0x10b7
5197 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
5198 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_R                                                              0x10b8
5199 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
5200 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_B                                                                0x10b9
5201 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
5202 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_G                                                                0x10ba
5203 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
5204 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_R                                                                0x10bb
5205 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
5206 #define mmCM2_CM_SHAPER_RAMA_REGION_0_1                                                                0x10bc
5207 #define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
5208 #define mmCM2_CM_SHAPER_RAMA_REGION_2_3                                                                0x10bd
5209 #define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
5210 #define mmCM2_CM_SHAPER_RAMA_REGION_4_5                                                                0x10be
5211 #define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
5212 #define mmCM2_CM_SHAPER_RAMA_REGION_6_7                                                                0x10bf
5213 #define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
5214 #define mmCM2_CM_SHAPER_RAMA_REGION_8_9                                                                0x10c0
5215 #define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
5216 #define mmCM2_CM_SHAPER_RAMA_REGION_10_11                                                              0x10c1
5217 #define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
5218 #define mmCM2_CM_SHAPER_RAMA_REGION_12_13                                                              0x10c2
5219 #define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
5220 #define mmCM2_CM_SHAPER_RAMA_REGION_14_15                                                              0x10c3
5221 #define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
5222 #define mmCM2_CM_SHAPER_RAMA_REGION_16_17                                                              0x10c4
5223 #define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
5224 #define mmCM2_CM_SHAPER_RAMA_REGION_18_19                                                              0x10c5
5225 #define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
5226 #define mmCM2_CM_SHAPER_RAMA_REGION_20_21                                                              0x10c6
5227 #define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
5228 #define mmCM2_CM_SHAPER_RAMA_REGION_22_23                                                              0x10c7
5229 #define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
5230 #define mmCM2_CM_SHAPER_RAMA_REGION_24_25                                                              0x10c8
5231 #define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
5232 #define mmCM2_CM_SHAPER_RAMA_REGION_26_27                                                              0x10c9
5233 #define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
5234 #define mmCM2_CM_SHAPER_RAMA_REGION_28_29                                                              0x10ca
5235 #define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
5236 #define mmCM2_CM_SHAPER_RAMA_REGION_30_31                                                              0x10cb
5237 #define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
5238 #define mmCM2_CM_SHAPER_RAMA_REGION_32_33                                                              0x10cc
5239 #define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
5240 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_B                                                              0x10cd
5241 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
5242 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_G                                                              0x10ce
5243 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
5244 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_R                                                              0x10cf
5245 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
5246 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_B                                                                0x10d0
5247 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
5248 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_G                                                                0x10d1
5249 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
5250 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_R                                                                0x10d2
5251 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
5252 #define mmCM2_CM_SHAPER_RAMB_REGION_0_1                                                                0x10d3
5253 #define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
5254 #define mmCM2_CM_SHAPER_RAMB_REGION_2_3                                                                0x10d4
5255 #define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
5256 #define mmCM2_CM_SHAPER_RAMB_REGION_4_5                                                                0x10d5
5257 #define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
5258 #define mmCM2_CM_SHAPER_RAMB_REGION_6_7                                                                0x10d6
5259 #define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
5260 #define mmCM2_CM_SHAPER_RAMB_REGION_8_9                                                                0x10d7
5261 #define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
5262 #define mmCM2_CM_SHAPER_RAMB_REGION_10_11                                                              0x10d8
5263 #define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
5264 #define mmCM2_CM_SHAPER_RAMB_REGION_12_13                                                              0x10d9
5265 #define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
5266 #define mmCM2_CM_SHAPER_RAMB_REGION_14_15                                                              0x10da
5267 #define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
5268 #define mmCM2_CM_SHAPER_RAMB_REGION_16_17                                                              0x10db
5269 #define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
5270 #define mmCM2_CM_SHAPER_RAMB_REGION_18_19                                                              0x10dc
5271 #define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
5272 #define mmCM2_CM_SHAPER_RAMB_REGION_20_21                                                              0x10dd
5273 #define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
5274 #define mmCM2_CM_SHAPER_RAMB_REGION_22_23                                                              0x10de
5275 #define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
5276 #define mmCM2_CM_SHAPER_RAMB_REGION_24_25                                                              0x10df
5277 #define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
5278 #define mmCM2_CM_SHAPER_RAMB_REGION_26_27                                                              0x10e0
5279 #define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
5280 #define mmCM2_CM_SHAPER_RAMB_REGION_28_29                                                              0x10e1
5281 #define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
5282 #define mmCM2_CM_SHAPER_RAMB_REGION_30_31                                                              0x10e2
5283 #define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
5284 #define mmCM2_CM_SHAPER_RAMB_REGION_32_33                                                              0x10e3
5285 #define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
5286 #define mmCM2_CM_MEM_PWR_CTRL2                                                                         0x10e4
5287 #define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
5288 #define mmCM2_CM_MEM_PWR_STATUS2                                                                       0x10e5
5289 #define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
5290 #define mmCM2_CM_3DLUT_MODE                                                                            0x10e6
5291 #define mmCM2_CM_3DLUT_MODE_BASE_IDX                                                                   2
5292 #define mmCM2_CM_3DLUT_INDEX                                                                           0x10e7
5293 #define mmCM2_CM_3DLUT_INDEX_BASE_IDX                                                                  2
5294 #define mmCM2_CM_3DLUT_DATA                                                                            0x10e8
5295 #define mmCM2_CM_3DLUT_DATA_BASE_IDX                                                                   2
5296 #define mmCM2_CM_3DLUT_DATA_30BIT                                                                      0x10e9
5297 #define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
5298 #define mmCM2_CM_3DLUT_READ_WRITE_CONTROL                                                              0x10ea
5299 #define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
5300 #define mmCM2_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x10eb
5301 #define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
5302 #define mmCM2_CM_3DLUT_OUT_OFFSET_R                                                                    0x10ec
5303 #define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
5304 #define mmCM2_CM_3DLUT_OUT_OFFSET_G                                                                    0x10ed
5305 #define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
5306 #define mmCM2_CM_3DLUT_OUT_OFFSET_B                                                                    0x10ee
5307 #define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
5308 #define mmCM2_CM_TEST_DEBUG_INDEX                                                                      0x10ef
5309 #define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
5310 #define mmCM2_CM_TEST_DEBUG_DATA                                                                       0x10f0
5311 #define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
5312 
5313 
5314 // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
5315 // base address: 0x43e8
5316 #define mmDC_PERFMON12_PERFCOUNTER_CNTL                                                                0x10fa
5317 #define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX                                                       2
5318 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2                                                               0x10fb
5319 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
5320 #define mmDC_PERFMON12_PERFCOUNTER_STATE                                                               0x10fc
5321 #define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX                                                      2
5322 #define mmDC_PERFMON12_PERFMON_CNTL                                                                    0x10fd
5323 #define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX                                                           2
5324 #define mmDC_PERFMON12_PERFMON_CNTL2                                                                   0x10fe
5325 #define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX                                                          2
5326 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                                         0x10ff
5327 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
5328 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW                                                              0x1100
5329 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
5330 #define mmDC_PERFMON12_PERFMON_HI                                                                      0x1101
5331 #define mmDC_PERFMON12_PERFMON_HI_BASE_IDX                                                             2
5332 #define mmDC_PERFMON12_PERFMON_LOW                                                                     0x1102
5333 #define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX                                                            2
5334 
5335 
5336 // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
5337 // base address: 0x1104
5338 #define mmDPP_TOP3_DPP_CONTROL                                                                         0x1106
5339 #define mmDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
5340 #define mmDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
5341 #define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
5342 #define mmDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
5343 #define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
5344 #define mmDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
5345 #define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
5346 #define mmDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
5347 #define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
5348 #define mmDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
5349 #define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2
5350 
5351 
5352 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
5353 // base address: 0x1104
5354 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
5355 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
5356 #define mmCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
5357 #define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
5358 #define mmCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
5359 #define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
5360 #define mmCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
5361 #define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
5362 #define mmCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
5363 #define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
5364 #define mmCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
5365 #define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
5366 #define mmCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
5367 #define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
5368 #define mmCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
5369 #define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
5370 #define mmCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
5371 #define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
5372 #define mmCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
5373 #define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
5374 #define mmCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
5375 #define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
5376 #define mmCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
5377 #define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
5378 #define mmCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
5379 #define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
5380 #define mmCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
5381 #define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
5382 #define mmCNVC_CFG3_PRE_DEALPHA                                                                        0x111f
5383 #define mmCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2
5384 #define mmCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120
5385 #define mmCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2
5386 #define mmCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121
5387 #define mmCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2
5388 #define mmCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122
5389 #define mmCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2
5390 #define mmCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123
5391 #define mmCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2
5392 #define mmCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124
5393 #define mmCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2
5394 #define mmCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125
5395 #define mmCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2
5396 #define mmCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126
5397 #define mmCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2
5398 #define mmCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127
5399 #define mmCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
5400 #define mmCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128
5401 #define mmCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
5402 #define mmCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129
5403 #define mmCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
5404 #define mmCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a
5405 #define mmCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
5406 #define mmCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b
5407 #define mmCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
5408 #define mmCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c
5409 #define mmCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
5410 #define mmCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d
5411 #define mmCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2
5412 #define mmCNVC_CFG3_PRE_DEGAM                                                                          0x112e
5413 #define mmCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2
5414 #define mmCNVC_CFG3_PRE_REALPHA                                                                        0x112f
5415 #define mmCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2
5416 
5417 
5418 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
5419 // base address: 0x1104
5420 #define mmCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1132
5421 #define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
5422 #define mmCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1133
5423 #define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
5424 #define mmCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1134
5425 #define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
5426 #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1135
5427 #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
5428 
5429 
5430 // addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
5431 // base address: 0x1104
5432 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x113a
5433 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
5434 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x113b
5435 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
5436 #define mmDSCL3_SCL_MODE                                                                               0x113c
5437 #define mmDSCL3_SCL_MODE_BASE_IDX                                                                      2
5438 #define mmDSCL3_SCL_TAP_CONTROL                                                                        0x113d
5439 #define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
5440 #define mmDSCL3_DSCL_CONTROL                                                                           0x113e
5441 #define mmDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
5442 #define mmDSCL3_DSCL_2TAP_CONTROL                                                                      0x113f
5443 #define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
5444 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1140
5445 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
5446 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1141
5447 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
5448 #define mmDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1142
5449 #define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
5450 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1143
5451 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
5452 #define mmDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1144
5453 #define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
5454 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1145
5455 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
5456 #define mmDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1146
5457 #define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
5458 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1147
5459 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
5460 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1148
5461 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
5462 #define mmDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1149
5463 #define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
5464 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x114a
5465 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
5466 #define mmDSCL3_SCL_BLACK_COLOR                                                                        0x114b
5467 #define mmDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2
5468 #define mmDSCL3_DSCL_UPDATE                                                                            0x114c
5469 #define mmDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
5470 #define mmDSCL3_DSCL_AUTOCAL                                                                           0x114d
5471 #define mmDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
5472 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x114e
5473 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
5474 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x114f
5475 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
5476 #define mmDSCL3_OTG_H_BLANK                                                                            0x1150
5477 #define mmDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
5478 #define mmDSCL3_OTG_V_BLANK                                                                            0x1151
5479 #define mmDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
5480 #define mmDSCL3_RECOUT_START                                                                           0x1152
5481 #define mmDSCL3_RECOUT_START_BASE_IDX                                                                  2
5482 #define mmDSCL3_RECOUT_SIZE                                                                            0x1153
5483 #define mmDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
5484 #define mmDSCL3_MPC_SIZE                                                                               0x1154
5485 #define mmDSCL3_MPC_SIZE_BASE_IDX                                                                      2
5486 #define mmDSCL3_LB_DATA_FORMAT                                                                         0x1155
5487 #define mmDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
5488 #define mmDSCL3_LB_MEMORY_CTRL                                                                         0x1156
5489 #define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
5490 #define mmDSCL3_LB_V_COUNTER                                                                           0x1157
5491 #define mmDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
5492 #define mmDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1158
5493 #define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
5494 #define mmDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1159
5495 #define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
5496 #define mmDSCL3_OBUF_CONTROL                                                                           0x115a
5497 #define mmDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
5498 #define mmDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x115b
5499 #define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
5500 
5501 
5502 // addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
5503 // base address: 0x1104
5504 #define mmCM3_CM_CONTROL                                                                               0x1161
5505 #define mmCM3_CM_CONTROL_BASE_IDX                                                                      2
5506 #define mmCM3_CM_POST_CSC_CONTROL                                                                      0x1162
5507 #define mmCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
5508 #define mmCM3_CM_POST_CSC_C11_C12                                                                      0x1163
5509 #define mmCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
5510 #define mmCM3_CM_POST_CSC_C13_C14                                                                      0x1164
5511 #define mmCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
5512 #define mmCM3_CM_POST_CSC_C21_C22                                                                      0x1165
5513 #define mmCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
5514 #define mmCM3_CM_POST_CSC_C23_C24                                                                      0x1166
5515 #define mmCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
5516 #define mmCM3_CM_POST_CSC_C31_C32                                                                      0x1167
5517 #define mmCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
5518 #define mmCM3_CM_POST_CSC_C33_C34                                                                      0x1168
5519 #define mmCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
5520 #define mmCM3_CM_POST_CSC_B_C11_C12                                                                    0x1169
5521 #define mmCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
5522 #define mmCM3_CM_POST_CSC_B_C13_C14                                                                    0x116a
5523 #define mmCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
5524 #define mmCM3_CM_POST_CSC_B_C21_C22                                                                    0x116b
5525 #define mmCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
5526 #define mmCM3_CM_POST_CSC_B_C23_C24                                                                    0x116c
5527 #define mmCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
5528 #define mmCM3_CM_POST_CSC_B_C31_C32                                                                    0x116d
5529 #define mmCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
5530 #define mmCM3_CM_POST_CSC_B_C33_C34                                                                    0x116e
5531 #define mmCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
5532 #define mmCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x116f
5533 #define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
5534 #define mmCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x1170
5535 #define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
5536 #define mmCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x1171
5537 #define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
5538 #define mmCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x1172
5539 #define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
5540 #define mmCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x1173
5541 #define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
5542 #define mmCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x1174
5543 #define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
5544 #define mmCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x1175
5545 #define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
5546 #define mmCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1176
5547 #define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
5548 #define mmCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1177
5549 #define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
5550 #define mmCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1178
5551 #define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
5552 #define mmCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1179
5553 #define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
5554 #define mmCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x117a
5555 #define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
5556 #define mmCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x117b
5557 #define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
5558 #define mmCM3_CM_BIAS_CR_R                                                                             0x117c
5559 #define mmCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
5560 #define mmCM3_CM_BIAS_Y_G_CB_B                                                                         0x117d
5561 #define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
5562 #define mmCM3_CM_GAMCOR_CONTROL                                                                        0x117e
5563 #define mmCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
5564 #define mmCM3_CM_GAMCOR_LUT_INDEX                                                                      0x117f
5565 #define mmCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
5566 #define mmCM3_CM_GAMCOR_LUT_DATA                                                                       0x1180
5567 #define mmCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
5568 #define mmCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x1181
5569 #define mmCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
5570 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1182
5571 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
5572 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1183
5573 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
5574 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1184
5575 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
5576 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1185
5577 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
5578 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1186
5579 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
5580 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1187
5581 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
5582 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1188
5583 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
5584 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1189
5585 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
5586 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x118a
5587 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
5588 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x118b
5589 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
5590 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x118c
5591 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
5592 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x118d
5593 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
5594 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x118e
5595 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
5596 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x118f
5597 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
5598 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1190
5599 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
5600 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1191
5601 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
5602 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1192
5603 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
5604 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1193
5605 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
5606 #define mmCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1194
5607 #define mmCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
5608 #define mmCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1195
5609 #define mmCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
5610 #define mmCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1196
5611 #define mmCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
5612 #define mmCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1197
5613 #define mmCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
5614 #define mmCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1198
5615 #define mmCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
5616 #define mmCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1199
5617 #define mmCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
5618 #define mmCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x119a
5619 #define mmCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
5620 #define mmCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x119b
5621 #define mmCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
5622 #define mmCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x119c
5623 #define mmCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
5624 #define mmCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x119d
5625 #define mmCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
5626 #define mmCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x119e
5627 #define mmCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
5628 #define mmCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x119f
5629 #define mmCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
5630 #define mmCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11a0
5631 #define mmCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
5632 #define mmCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11a1
5633 #define mmCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
5634 #define mmCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11a2
5635 #define mmCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
5636 #define mmCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11a3
5637 #define mmCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
5638 #define mmCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11a4
5639 #define mmCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
5640 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11a5
5641 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
5642 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11a6
5643 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
5644 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11a7
5645 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
5646 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11a8
5647 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
5648 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11a9
5649 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
5650 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11aa
5651 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
5652 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11ab
5653 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
5654 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11ac
5655 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
5656 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11ad
5657 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
5658 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11ae
5659 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
5660 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11af
5661 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
5662 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11b0
5663 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
5664 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11b1
5665 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
5666 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11b2
5667 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
5668 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11b3
5669 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
5670 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11b4
5671 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
5672 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11b5
5673 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
5674 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11b6
5675 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
5676 #define mmCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11b7
5677 #define mmCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
5678 #define mmCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11b8
5679 #define mmCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
5680 #define mmCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11b9
5681 #define mmCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
5682 #define mmCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11ba
5683 #define mmCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
5684 #define mmCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11bb
5685 #define mmCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
5686 #define mmCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11bc
5687 #define mmCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
5688 #define mmCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11bd
5689 #define mmCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
5690 #define mmCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11be
5691 #define mmCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
5692 #define mmCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11bf
5693 #define mmCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
5694 #define mmCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11c0
5695 #define mmCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
5696 #define mmCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11c1
5697 #define mmCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
5698 #define mmCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11c2
5699 #define mmCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
5700 #define mmCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11c3
5701 #define mmCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
5702 #define mmCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11c4
5703 #define mmCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
5704 #define mmCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11c5
5705 #define mmCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
5706 #define mmCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x11c6
5707 #define mmCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
5708 #define mmCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x11c7
5709 #define mmCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
5710 #define mmCM3_CM_BLNDGAM_CONTROL                                                                       0x11c8
5711 #define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
5712 #define mmCM3_CM_BLNDGAM_LUT_INDEX                                                                     0x11c9
5713 #define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
5714 #define mmCM3_CM_BLNDGAM_LUT_DATA                                                                      0x11ca
5715 #define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
5716 #define mmCM3_CM_BLNDGAM_LUT_CONTROL                                                                   0x11cb
5717 #define mmCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
5718 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x11cc
5719 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
5720 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x11cd
5721 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
5722 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x11ce
5723 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
5724 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x11cf
5725 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
5726 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x11d0
5727 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
5728 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x11d1
5729 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
5730 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x11d2
5731 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
5732 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x11d3
5733 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
5734 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x11d4
5735 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
5736 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x11d5
5737 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
5738 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x11d6
5739 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
5740 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x11d7
5741 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
5742 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x11d8
5743 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
5744 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x11d9
5745 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
5746 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x11da
5747 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
5748 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x11db
5749 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
5750 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x11dc
5751 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
5752 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x11dd
5753 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
5754 #define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x11de
5755 #define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
5756 #define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x11df
5757 #define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
5758 #define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x11e0
5759 #define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
5760 #define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x11e1
5761 #define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
5762 #define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x11e2
5763 #define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
5764 #define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x11e3
5765 #define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
5766 #define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x11e4
5767 #define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
5768 #define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x11e5
5769 #define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
5770 #define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x11e6
5771 #define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
5772 #define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x11e7
5773 #define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
5774 #define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x11e8
5775 #define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
5776 #define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x11e9
5777 #define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
5778 #define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x11ea
5779 #define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
5780 #define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x11eb
5781 #define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
5782 #define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x11ec
5783 #define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
5784 #define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x11ed
5785 #define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
5786 #define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x11ee
5787 #define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
5788 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x11ef
5789 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
5790 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x11f0
5791 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
5792 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x11f1
5793 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
5794 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x11f2
5795 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
5796 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x11f3
5797 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
5798 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x11f4
5799 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
5800 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x11f5
5801 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
5802 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x11f6
5803 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
5804 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x11f7
5805 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
5806 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x11f8
5807 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
5808 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x11f9
5809 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
5810 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x11fa
5811 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
5812 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x11fb
5813 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
5814 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x11fc
5815 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
5816 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x11fd
5817 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
5818 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x11fe
5819 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
5820 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x11ff
5821 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
5822 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x1200
5823 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
5824 #define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x1201
5825 #define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
5826 #define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x1202
5827 #define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
5828 #define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x1203
5829 #define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
5830 #define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x1204
5831 #define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
5832 #define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x1205
5833 #define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
5834 #define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x1206
5835 #define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
5836 #define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x1207
5837 #define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
5838 #define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x1208
5839 #define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
5840 #define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x1209
5841 #define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
5842 #define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x120a
5843 #define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
5844 #define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x120b
5845 #define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
5846 #define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x120c
5847 #define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
5848 #define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x120d
5849 #define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
5850 #define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x120e
5851 #define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
5852 #define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x120f
5853 #define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
5854 #define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x1210
5855 #define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
5856 #define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x1211
5857 #define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
5858 #define mmCM3_CM_HDR_MULT_COEF                                                                         0x1212
5859 #define mmCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
5860 #define mmCM3_CM_MEM_PWR_CTRL                                                                          0x1213
5861 #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
5862 #define mmCM3_CM_MEM_PWR_STATUS                                                                        0x1214
5863 #define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
5864 #define mmCM3_CM_DEALPHA                                                                               0x1216
5865 #define mmCM3_CM_DEALPHA_BASE_IDX                                                                      2
5866 #define mmCM3_CM_COEF_FORMAT                                                                           0x1217
5867 #define mmCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
5868 #define mmCM3_CM_SHAPER_CONTROL                                                                        0x1218
5869 #define mmCM3_CM_SHAPER_CONTROL_BASE_IDX                                                               2
5870 #define mmCM3_CM_SHAPER_OFFSET_R                                                                       0x1219
5871 #define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
5872 #define mmCM3_CM_SHAPER_OFFSET_G                                                                       0x121a
5873 #define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
5874 #define mmCM3_CM_SHAPER_OFFSET_B                                                                       0x121b
5875 #define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
5876 #define mmCM3_CM_SHAPER_SCALE_R                                                                        0x121c
5877 #define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
5878 #define mmCM3_CM_SHAPER_SCALE_G_B                                                                      0x121d
5879 #define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
5880 #define mmCM3_CM_SHAPER_LUT_INDEX                                                                      0x121e
5881 #define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
5882 #define mmCM3_CM_SHAPER_LUT_DATA                                                                       0x121f
5883 #define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
5884 #define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x1220
5885 #define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
5886 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_B                                                              0x1221
5887 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
5888 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_G                                                              0x1222
5889 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
5890 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_R                                                              0x1223
5891 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
5892 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_B                                                                0x1224
5893 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
5894 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_G                                                                0x1225
5895 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
5896 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_R                                                                0x1226
5897 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
5898 #define mmCM3_CM_SHAPER_RAMA_REGION_0_1                                                                0x1227
5899 #define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
5900 #define mmCM3_CM_SHAPER_RAMA_REGION_2_3                                                                0x1228
5901 #define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
5902 #define mmCM3_CM_SHAPER_RAMA_REGION_4_5                                                                0x1229
5903 #define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
5904 #define mmCM3_CM_SHAPER_RAMA_REGION_6_7                                                                0x122a
5905 #define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
5906 #define mmCM3_CM_SHAPER_RAMA_REGION_8_9                                                                0x122b
5907 #define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
5908 #define mmCM3_CM_SHAPER_RAMA_REGION_10_11                                                              0x122c
5909 #define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
5910 #define mmCM3_CM_SHAPER_RAMA_REGION_12_13                                                              0x122d
5911 #define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
5912 #define mmCM3_CM_SHAPER_RAMA_REGION_14_15                                                              0x122e
5913 #define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
5914 #define mmCM3_CM_SHAPER_RAMA_REGION_16_17                                                              0x122f
5915 #define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
5916 #define mmCM3_CM_SHAPER_RAMA_REGION_18_19                                                              0x1230
5917 #define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
5918 #define mmCM3_CM_SHAPER_RAMA_REGION_20_21                                                              0x1231
5919 #define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
5920 #define mmCM3_CM_SHAPER_RAMA_REGION_22_23                                                              0x1232
5921 #define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
5922 #define mmCM3_CM_SHAPER_RAMA_REGION_24_25                                                              0x1233
5923 #define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
5924 #define mmCM3_CM_SHAPER_RAMA_REGION_26_27                                                              0x1234
5925 #define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
5926 #define mmCM3_CM_SHAPER_RAMA_REGION_28_29                                                              0x1235
5927 #define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
5928 #define mmCM3_CM_SHAPER_RAMA_REGION_30_31                                                              0x1236
5929 #define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
5930 #define mmCM3_CM_SHAPER_RAMA_REGION_32_33                                                              0x1237
5931 #define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
5932 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_B                                                              0x1238
5933 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
5934 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_G                                                              0x1239
5935 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
5936 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_R                                                              0x123a
5937 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
5938 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_B                                                                0x123b
5939 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
5940 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_G                                                                0x123c
5941 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
5942 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_R                                                                0x123d
5943 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
5944 #define mmCM3_CM_SHAPER_RAMB_REGION_0_1                                                                0x123e
5945 #define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
5946 #define mmCM3_CM_SHAPER_RAMB_REGION_2_3                                                                0x123f
5947 #define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
5948 #define mmCM3_CM_SHAPER_RAMB_REGION_4_5                                                                0x1240
5949 #define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
5950 #define mmCM3_CM_SHAPER_RAMB_REGION_6_7                                                                0x1241
5951 #define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
5952 #define mmCM3_CM_SHAPER_RAMB_REGION_8_9                                                                0x1242
5953 #define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
5954 #define mmCM3_CM_SHAPER_RAMB_REGION_10_11                                                              0x1243
5955 #define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
5956 #define mmCM3_CM_SHAPER_RAMB_REGION_12_13                                                              0x1244
5957 #define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
5958 #define mmCM3_CM_SHAPER_RAMB_REGION_14_15                                                              0x1245
5959 #define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
5960 #define mmCM3_CM_SHAPER_RAMB_REGION_16_17                                                              0x1246
5961 #define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
5962 #define mmCM3_CM_SHAPER_RAMB_REGION_18_19                                                              0x1247
5963 #define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
5964 #define mmCM3_CM_SHAPER_RAMB_REGION_20_21                                                              0x1248
5965 #define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
5966 #define mmCM3_CM_SHAPER_RAMB_REGION_22_23                                                              0x1249
5967 #define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
5968 #define mmCM3_CM_SHAPER_RAMB_REGION_24_25                                                              0x124a
5969 #define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
5970 #define mmCM3_CM_SHAPER_RAMB_REGION_26_27                                                              0x124b
5971 #define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
5972 #define mmCM3_CM_SHAPER_RAMB_REGION_28_29                                                              0x124c
5973 #define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
5974 #define mmCM3_CM_SHAPER_RAMB_REGION_30_31                                                              0x124d
5975 #define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
5976 #define mmCM3_CM_SHAPER_RAMB_REGION_32_33                                                              0x124e
5977 #define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
5978 #define mmCM3_CM_MEM_PWR_CTRL2                                                                         0x124f
5979 #define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
5980 #define mmCM3_CM_MEM_PWR_STATUS2                                                                       0x1250
5981 #define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
5982 #define mmCM3_CM_3DLUT_MODE                                                                            0x1251
5983 #define mmCM3_CM_3DLUT_MODE_BASE_IDX                                                                   2
5984 #define mmCM3_CM_3DLUT_INDEX                                                                           0x1252
5985 #define mmCM3_CM_3DLUT_INDEX_BASE_IDX                                                                  2
5986 #define mmCM3_CM_3DLUT_DATA                                                                            0x1253
5987 #define mmCM3_CM_3DLUT_DATA_BASE_IDX                                                                   2
5988 #define mmCM3_CM_3DLUT_DATA_30BIT                                                                      0x1254
5989 #define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
5990 #define mmCM3_CM_3DLUT_READ_WRITE_CONTROL                                                              0x1255
5991 #define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
5992 #define mmCM3_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x1256
5993 #define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
5994 #define mmCM3_CM_3DLUT_OUT_OFFSET_R                                                                    0x1257
5995 #define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
5996 #define mmCM3_CM_3DLUT_OUT_OFFSET_G                                                                    0x1258
5997 #define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
5998 #define mmCM3_CM_3DLUT_OUT_OFFSET_B                                                                    0x1259
5999 #define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
6000 #define mmCM3_CM_TEST_DEBUG_INDEX                                                                      0x125a
6001 #define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
6002 #define mmCM3_CM_TEST_DEBUG_DATA                                                                       0x125b
6003 #define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
6004 
6005 
6006 // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
6007 // base address: 0x4994
6008 #define mmDC_PERFMON13_PERFCOUNTER_CNTL                                                                0x1265
6009 #define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX                                                       2
6010 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2                                                               0x1266
6011 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
6012 #define mmDC_PERFMON13_PERFCOUNTER_STATE                                                               0x1267
6013 #define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX                                                      2
6014 #define mmDC_PERFMON13_PERFMON_CNTL                                                                    0x1268
6015 #define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX                                                           2
6016 #define mmDC_PERFMON13_PERFMON_CNTL2                                                                   0x1269
6017 #define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX                                                          2
6018 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                                         0x126a
6019 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
6020 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW                                                              0x126b
6021 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
6022 #define mmDC_PERFMON13_PERFMON_HI                                                                      0x126c
6023 #define mmDC_PERFMON13_PERFMON_HI_BASE_IDX                                                             2
6024 #define mmDC_PERFMON13_PERFMON_LOW                                                                     0x126d
6025 #define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX                                                            2
6026 
6027 
6028 // addressBlock: dce_dc_opp_fmt0_dispdec
6029 // base address: 0x0
6030 #define mmFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
6031 #define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
6032 #define mmFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
6033 #define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
6034 #define mmFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
6035 #define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
6036 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
6037 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
6038 #define mmFMT0_FMT_CONTROL                                                                             0x1840
6039 #define mmFMT0_FMT_CONTROL_BASE_IDX                                                                    2
6040 #define mmFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
6041 #define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
6042 #define mmFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
6043 #define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
6044 #define mmFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
6045 #define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
6046 #define mmFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
6047 #define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
6048 #define mmFMT0_FMT_CLAMP_CNTL                                                                          0x1845
6049 #define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
6050 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
6051 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
6052 #define mmFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
6053 #define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
6054 #define mmFMT0_FMT_422_CONTROL                                                                         0x1849
6055 #define mmFMT0_FMT_422_CONTROL_BASE_IDX                                                                2
6056 
6057 
6058 // addressBlock: dce_dc_opp_dpg0_dispdec
6059 // base address: 0x0
6060 #define mmDPG0_DPG_CONTROL                                                                             0x1854
6061 #define mmDPG0_DPG_CONTROL_BASE_IDX                                                                    2
6062 #define mmDPG0_DPG_RAMP_CONTROL                                                                        0x1855
6063 #define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
6064 #define mmDPG0_DPG_DIMENSIONS                                                                          0x1856
6065 #define mmDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
6066 #define mmDPG0_DPG_COLOUR_R_CR                                                                         0x1857
6067 #define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
6068 #define mmDPG0_DPG_COLOUR_G_Y                                                                          0x1858
6069 #define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
6070 #define mmDPG0_DPG_COLOUR_B_CB                                                                         0x1859
6071 #define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
6072 #define mmDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
6073 #define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
6074 #define mmDPG0_DPG_STATUS                                                                              0x185b
6075 #define mmDPG0_DPG_STATUS_BASE_IDX                                                                     2
6076 
6077 
6078 // addressBlock: dce_dc_opp_oppbuf0_dispdec
6079 // base address: 0x0
6080 #define mmOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
6081 #define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
6082 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
6083 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
6084 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
6085 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
6086 #define mmOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
6087 #define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2
6088 
6089 
6090 // addressBlock: dce_dc_opp_opp_pipe0_dispdec
6091 // base address: 0x0
6092 #define mmOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
6093 #define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2
6094 
6095 
6096 // addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
6097 // base address: 0x0
6098 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
6099 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
6100 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
6101 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
6102 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
6103 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
6104 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
6105 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
6106 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
6107 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
6108 
6109 
6110 // addressBlock: dce_dc_opp_fmt1_dispdec
6111 // base address: 0x168
6112 #define mmFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
6113 #define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
6114 #define mmFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
6115 #define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
6116 #define mmFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
6117 #define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
6118 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
6119 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
6120 #define mmFMT1_FMT_CONTROL                                                                             0x189a
6121 #define mmFMT1_FMT_CONTROL_BASE_IDX                                                                    2
6122 #define mmFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
6123 #define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
6124 #define mmFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
6125 #define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
6126 #define mmFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
6127 #define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
6128 #define mmFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
6129 #define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
6130 #define mmFMT1_FMT_CLAMP_CNTL                                                                          0x189f
6131 #define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
6132 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
6133 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
6134 #define mmFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
6135 #define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
6136 #define mmFMT1_FMT_422_CONTROL                                                                         0x18a3
6137 #define mmFMT1_FMT_422_CONTROL_BASE_IDX                                                                2
6138 
6139 
6140 // addressBlock: dce_dc_opp_dpg1_dispdec
6141 // base address: 0x168
6142 #define mmDPG1_DPG_CONTROL                                                                             0x18ae
6143 #define mmDPG1_DPG_CONTROL_BASE_IDX                                                                    2
6144 #define mmDPG1_DPG_RAMP_CONTROL                                                                        0x18af
6145 #define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
6146 #define mmDPG1_DPG_DIMENSIONS                                                                          0x18b0
6147 #define mmDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
6148 #define mmDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
6149 #define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
6150 #define mmDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
6151 #define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
6152 #define mmDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
6153 #define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
6154 #define mmDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
6155 #define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
6156 #define mmDPG1_DPG_STATUS                                                                              0x18b5
6157 #define mmDPG1_DPG_STATUS_BASE_IDX                                                                     2
6158 
6159 
6160 // addressBlock: dce_dc_opp_oppbuf1_dispdec
6161 // base address: 0x168
6162 #define mmOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
6163 #define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
6164 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
6165 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
6166 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
6167 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
6168 #define mmOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
6169 #define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2
6170 
6171 
6172 // addressBlock: dce_dc_opp_opp_pipe1_dispdec
6173 // base address: 0x168
6174 #define mmOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
6175 #define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2
6176 
6177 
6178 // addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
6179 // base address: 0x168
6180 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
6181 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
6182 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
6183 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
6184 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
6185 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
6186 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
6187 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
6188 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
6189 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
6190 
6191 
6192 // addressBlock: dce_dc_opp_fmt2_dispdec
6193 // base address: 0x2d0
6194 #define mmFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0
6195 #define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
6196 #define mmFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1
6197 #define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
6198 #define mmFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2
6199 #define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
6200 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3
6201 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
6202 #define mmFMT2_FMT_CONTROL                                                                             0x18f4
6203 #define mmFMT2_FMT_CONTROL_BASE_IDX                                                                    2
6204 #define mmFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5
6205 #define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
6206 #define mmFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6
6207 #define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
6208 #define mmFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7
6209 #define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
6210 #define mmFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8
6211 #define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
6212 #define mmFMT2_FMT_CLAMP_CNTL                                                                          0x18f9
6213 #define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
6214 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa
6215 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
6216 #define mmFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb
6217 #define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
6218 #define mmFMT2_FMT_422_CONTROL                                                                         0x18fd
6219 #define mmFMT2_FMT_422_CONTROL_BASE_IDX                                                                2
6220 
6221 
6222 // addressBlock: dce_dc_opp_dpg2_dispdec
6223 // base address: 0x2d0
6224 #define mmDPG2_DPG_CONTROL                                                                             0x1908
6225 #define mmDPG2_DPG_CONTROL_BASE_IDX                                                                    2
6226 #define mmDPG2_DPG_RAMP_CONTROL                                                                        0x1909
6227 #define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2
6228 #define mmDPG2_DPG_DIMENSIONS                                                                          0x190a
6229 #define mmDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2
6230 #define mmDPG2_DPG_COLOUR_R_CR                                                                         0x190b
6231 #define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2
6232 #define mmDPG2_DPG_COLOUR_G_Y                                                                          0x190c
6233 #define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
6234 #define mmDPG2_DPG_COLOUR_B_CB                                                                         0x190d
6235 #define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2
6236 #define mmDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e
6237 #define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
6238 #define mmDPG2_DPG_STATUS                                                                              0x190f
6239 #define mmDPG2_DPG_STATUS_BASE_IDX                                                                     2
6240 
6241 
6242 // addressBlock: dce_dc_opp_oppbuf2_dispdec
6243 // base address: 0x2d0
6244 #define mmOPPBUF2_OPPBUF_CONTROL                                                                       0x1938
6245 #define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2
6246 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939
6247 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
6248 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a
6249 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
6250 #define mmOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d
6251 #define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2
6252 
6253 
6254 // addressBlock: dce_dc_opp_opp_pipe2_dispdec
6255 // base address: 0x2d0
6256 #define mmOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940
6257 #define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2
6258 
6259 
6260 // addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
6261 // base address: 0x2d0
6262 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945
6263 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
6264 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946
6265 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
6266 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947
6267 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
6268 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948
6269 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
6270 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949
6271 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
6272 
6273 
6274 // addressBlock: dce_dc_opp_fmt3_dispdec
6275 // base address: 0x438
6276 #define mmFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a
6277 #define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
6278 #define mmFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b
6279 #define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
6280 #define mmFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c
6281 #define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
6282 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d
6283 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
6284 #define mmFMT3_FMT_CONTROL                                                                             0x194e
6285 #define mmFMT3_FMT_CONTROL_BASE_IDX                                                                    2
6286 #define mmFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f
6287 #define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
6288 #define mmFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950
6289 #define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
6290 #define mmFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951
6291 #define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
6292 #define mmFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952
6293 #define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
6294 #define mmFMT3_FMT_CLAMP_CNTL                                                                          0x1953
6295 #define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
6296 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954
6297 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
6298 #define mmFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955
6299 #define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
6300 #define mmFMT3_FMT_422_CONTROL                                                                         0x1957
6301 #define mmFMT3_FMT_422_CONTROL_BASE_IDX                                                                2
6302 
6303 
6304 // addressBlock: dce_dc_opp_dpg3_dispdec
6305 // base address: 0x438
6306 #define mmDPG3_DPG_CONTROL                                                                             0x1962
6307 #define mmDPG3_DPG_CONTROL_BASE_IDX                                                                    2
6308 #define mmDPG3_DPG_RAMP_CONTROL                                                                        0x1963
6309 #define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2
6310 #define mmDPG3_DPG_DIMENSIONS                                                                          0x1964
6311 #define mmDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2
6312 #define mmDPG3_DPG_COLOUR_R_CR                                                                         0x1965
6313 #define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2
6314 #define mmDPG3_DPG_COLOUR_G_Y                                                                          0x1966
6315 #define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
6316 #define mmDPG3_DPG_COLOUR_B_CB                                                                         0x1967
6317 #define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2
6318 #define mmDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968
6319 #define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
6320 #define mmDPG3_DPG_STATUS                                                                              0x1969
6321 #define mmDPG3_DPG_STATUS_BASE_IDX                                                                     2
6322 
6323 
6324 // addressBlock: dce_dc_opp_oppbuf3_dispdec
6325 // base address: 0x438
6326 #define mmOPPBUF3_OPPBUF_CONTROL                                                                       0x1992
6327 #define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2
6328 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993
6329 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
6330 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994
6331 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
6332 #define mmOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997
6333 #define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2
6334 
6335 
6336 // addressBlock: dce_dc_opp_opp_pipe3_dispdec
6337 // base address: 0x438
6338 #define mmOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a
6339 #define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2
6340 
6341 
6342 // addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
6343 // base address: 0x438
6344 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f
6345 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
6346 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0
6347 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
6348 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1
6349 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
6350 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2
6351 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
6352 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3
6353 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
6354 
6355 
6356 // addressBlock: dce_dc_opp_opp_top_dispdec
6357 // base address: 0x0
6358 #define mmOPP_TOP_CLK_CONTROL                                                                          0x1a5e
6359 #define mmOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
6360 #define mmOPP_ABM_CONTROL                                                                              0x1a60
6361 #define mmOPP_ABM_CONTROL_BASE_IDX                                                                     2
6362 
6363 
6364 // addressBlock: dce_dc_opp_dscrm0_dispdec
6365 // base address: 0x0
6366 #define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
6367 #define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
6368 
6369 
6370 // addressBlock: dce_dc_opp_dscrm1_dispdec
6371 // base address: 0x4
6372 #define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
6373 #define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
6374 
6375 
6376 // addressBlock: dce_dc_opp_dscrm2_dispdec
6377 // base address: 0x8
6378 #define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66
6379 #define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
6380 
6381 
6382 // addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
6383 // base address: 0x6af8
6384 #define mmDC_PERFMON14_PERFCOUNTER_CNTL                                                                0x1abe
6385 #define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX                                                       2
6386 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2                                                               0x1abf
6387 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
6388 #define mmDC_PERFMON14_PERFCOUNTER_STATE                                                               0x1ac0
6389 #define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX                                                      2
6390 #define mmDC_PERFMON14_PERFMON_CNTL                                                                    0x1ac1
6391 #define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX                                                           2
6392 #define mmDC_PERFMON14_PERFMON_CNTL2                                                                   0x1ac2
6393 #define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX                                                          2
6394 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC                                                         0x1ac3
6395 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
6396 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW                                                              0x1ac4
6397 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
6398 #define mmDC_PERFMON14_PERFMON_HI                                                                      0x1ac5
6399 #define mmDC_PERFMON14_PERFMON_HI_BASE_IDX                                                             2
6400 #define mmDC_PERFMON14_PERFMON_LOW                                                                     0x1ac6
6401 #define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX                                                            2
6402 
6403 
6404 // addressBlock: dce_dc_optc_odm0_dispdec
6405 // base address: 0x0
6406 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
6407 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
6408 #define mmODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
6409 #define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
6410 #define mmODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
6411 #define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
6412 #define mmODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
6413 #define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
6414 #define mmODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
6415 #define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
6416 #define mmODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
6417 #define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
6418 #define mmODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
6419 #define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
6420 #define mmODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
6421 #define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
6422 
6423 
6424 // addressBlock: dce_dc_optc_odm1_dispdec
6425 // base address: 0x40
6426 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
6427 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
6428 #define mmODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
6429 #define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
6430 #define mmODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
6431 #define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
6432 #define mmODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
6433 #define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
6434 #define mmODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
6435 #define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
6436 #define mmODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
6437 #define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
6438 #define mmODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
6439 #define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
6440 #define mmODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
6441 #define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
6442 
6443 
6444 // addressBlock: dce_dc_optc_odm2_dispdec
6445 // base address: 0x80
6446 #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea
6447 #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
6448 #define mmODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb
6449 #define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
6450 #define mmODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec
6451 #define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
6452 #define mmODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed
6453 #define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
6454 #define mmODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee
6455 #define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
6456 #define mmODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef
6457 #define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
6458 #define mmODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0
6459 #define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
6460 #define mmODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1
6461 #define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
6462 
6463 
6464 // addressBlock: dce_dc_optc_odm3_dispdec
6465 // base address: 0xc0
6466 #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa
6467 #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
6468 #define mmODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb
6469 #define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
6470 #define mmODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc
6471 #define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
6472 #define mmODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd
6473 #define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
6474 #define mmODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe
6475 #define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
6476 #define mmODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff
6477 #define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
6478 #define mmODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00
6479 #define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
6480 #define mmODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01
6481 #define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
6482 
6483 
6484 // addressBlock: dce_dc_optc_otg0_dispdec
6485 // base address: 0x0
6486 #define mmOTG0_OTG_H_TOTAL                                                                             0x1b2a
6487 #define mmOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
6488 #define mmOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
6489 #define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
6490 #define mmOTG0_OTG_H_SYNC_A                                                                            0x1b2c
6491 #define mmOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
6492 #define mmOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
6493 #define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
6494 #define mmOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
6495 #define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
6496 #define mmOTG0_OTG_V_TOTAL                                                                             0x1b2f
6497 #define mmOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
6498 #define mmOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
6499 #define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
6500 #define mmOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
6501 #define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
6502 #define mmOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
6503 #define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
6504 #define mmOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
6505 #define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
6506 #define mmOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b34
6507 #define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
6508 #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b35
6509 #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
6510 #define mmOTG0_OTG_V_BLANK_START_END                                                                   0x1b36
6511 #define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
6512 #define mmOTG0_OTG_V_SYNC_A                                                                            0x1b37
6513 #define mmOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
6514 #define mmOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b38
6515 #define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
6516 #define mmOTG0_OTG_TRIGA_CNTL                                                                          0x1b39
6517 #define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
6518 #define mmOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3a
6519 #define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
6520 #define mmOTG0_OTG_TRIGB_CNTL                                                                          0x1b3b
6521 #define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
6522 #define mmOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3c
6523 #define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
6524 #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3d
6525 #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
6526 #define mmOTG0_OTG_FLOW_CONTROL                                                                        0x1b3e
6527 #define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2
6528 #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b3f
6529 #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
6530 #define mmOTG0_OTG_CONTROL                                                                             0x1b41
6531 #define mmOTG0_OTG_CONTROL_BASE_IDX                                                                    2
6532 #define mmOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b44
6533 #define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
6534 #define mmOTG0_OTG_INTERLACE_STATUS                                                                    0x1b45
6535 #define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
6536 #define mmOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
6537 #define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
6538 #define mmOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
6539 #define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
6540 #define mmOTG0_OTG_STATUS                                                                              0x1b49
6541 #define mmOTG0_OTG_STATUS_BASE_IDX                                                                     2
6542 #define mmOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
6543 #define mmOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
6544 #define mmOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4b
6545 #define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
6546 #define mmOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4c
6547 #define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
6548 #define mmOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4d
6549 #define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
6550 #define mmOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4e
6551 #define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
6552 #define mmOTG0_OTG_COUNT_CONTROL                                                                       0x1b4f
6553 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
6554 #define mmOTG0_OTG_COUNT_RESET                                                                         0x1b50
6555 #define mmOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
6556 #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b51
6557 #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
6558 #define mmOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b52
6559 #define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
6560 #define mmOTG0_OTG_STEREO_STATUS                                                                       0x1b53
6561 #define mmOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
6562 #define mmOTG0_OTG_STEREO_CONTROL                                                                      0x1b54
6563 #define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
6564 #define mmOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b55
6565 #define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
6566 #define mmOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b56
6567 #define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
6568 #define mmOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b57
6569 #define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
6570 #define mmOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b58
6571 #define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
6572 #define mmOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b59
6573 #define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
6574 #define mmOTG0_OTG_UPDATE_LOCK                                                                         0x1b5a
6575 #define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
6576 #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5b
6577 #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
6578 #define mmOTG0_OTG_MASTER_EN                                                                           0x1b5c
6579 #define mmOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
6580 #define mmOTG0_OTG_BLANK_DATA_COLOR                                                                    0x1b5e
6581 #define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
6582 #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT                                                                0x1b5f
6583 #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
6584 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b62
6585 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
6586 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b63
6587 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
6588 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b64
6589 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
6590 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b65
6591 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
6592 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b66
6593 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
6594 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b67
6595 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
6596 #define mmOTG0_OTG_CRC_CNTL                                                                            0x1b68
6597 #define mmOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
6598 #define mmOTG0_OTG_CRC_CNTL2                                                                           0x1b69
6599 #define mmOTG0_OTG_CRC_CNTL2_BASE_IDX                                                                  2
6600 #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b6a
6601 #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
6602 #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b6b
6603 #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
6604 #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b6c
6605 #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
6606 #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b6d
6607 #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
6608 #define mmOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6e
6609 #define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
6610 #define mmOTG0_OTG_CRC0_DATA_B                                                                         0x1b6f
6611 #define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
6612 #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b70
6613 #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
6614 #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b71
6615 #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
6616 #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b72
6617 #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
6618 #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b73
6619 #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
6620 #define mmOTG0_OTG_CRC1_DATA_RG                                                                        0x1b74
6621 #define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
6622 #define mmOTG0_OTG_CRC1_DATA_B                                                                         0x1b75
6623 #define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
6624 #define mmOTG0_OTG_CRC2_DATA_RG                                                                        0x1b76
6625 #define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
6626 #define mmOTG0_OTG_CRC2_DATA_B                                                                         0x1b77
6627 #define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
6628 #define mmOTG0_OTG_CRC3_DATA_RG                                                                        0x1b78
6629 #define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
6630 #define mmOTG0_OTG_CRC3_DATA_B                                                                         0x1b79
6631 #define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
6632 #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b7a
6633 #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
6634 #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b7b
6635 #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
6636 #define mmOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b82
6637 #define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
6638 #define mmOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b83
6639 #define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
6640 #define mmOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b84
6641 #define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
6642 #define mmOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b85
6643 #define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
6644 #define mmOTG0_OTG_CLOCK_CONTROL                                                                       0x1b86
6645 #define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
6646 #define mmOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b87
6647 #define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
6648 #define mmOTG0_OTG_VUPDATE_PARAM                                                                       0x1b88
6649 #define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
6650 #define mmOTG0_OTG_VREADY_PARAM                                                                        0x1b89
6651 #define mmOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
6652 #define mmOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b8a
6653 #define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
6654 #define mmOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b8b
6655 #define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
6656 #define mmOTG0_OTG_GSL_CONTROL                                                                         0x1b8c
6657 #define mmOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
6658 #define mmOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8d
6659 #define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
6660 #define mmOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8e
6661 #define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
6662 #define mmOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8f
6663 #define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
6664 #define mmOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b90
6665 #define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
6666 #define mmOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b91
6667 #define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
6668 #define mmOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b92
6669 #define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
6670 #define mmOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b93
6671 #define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
6672 #define mmOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b94
6673 #define mmOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
6674 #define mmOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b95
6675 #define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
6676 #define mmOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b96
6677 #define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
6678 #define mmOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b97
6679 #define mmOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
6680 #define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b98
6681 #define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
6682 #define mmOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b99
6683 #define mmOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
6684 #define mmOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b9a
6685 #define mmOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
6686 #define mmOTG0_OTG_DRR_CONTROL                                                                         0x1b9b
6687 #define mmOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
6688 #define mmOTG0_OTG_M_CONST_DTO0                                                                        0x1b9c
6689 #define mmOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2
6690 #define mmOTG0_OTG_M_CONST_DTO1                                                                        0x1b9d
6691 #define mmOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2
6692 #define mmOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9e
6693 #define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
6694 #define mmOTG0_OTG_DSC_START_POSITION                                                                  0x1b9f
6695 #define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
6696 #define mmOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1ba0
6697 #define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
6698 #define mmOTG0_OTG_SPARE_REGISTER                                                                      0x1ba2
6699 #define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2
6700 
6701 
6702 // addressBlock: dce_dc_optc_otg1_dispdec
6703 // base address: 0x200
6704 #define mmOTG1_OTG_H_TOTAL                                                                             0x1baa
6705 #define mmOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
6706 #define mmOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
6707 #define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
6708 #define mmOTG1_OTG_H_SYNC_A                                                                            0x1bac
6709 #define mmOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
6710 #define mmOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
6711 #define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
6712 #define mmOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
6713 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
6714 #define mmOTG1_OTG_V_TOTAL                                                                             0x1baf
6715 #define mmOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
6716 #define mmOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
6717 #define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
6718 #define mmOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
6719 #define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
6720 #define mmOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
6721 #define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
6722 #define mmOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
6723 #define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
6724 #define mmOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb4
6725 #define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
6726 #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb5
6727 #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
6728 #define mmOTG1_OTG_V_BLANK_START_END                                                                   0x1bb6
6729 #define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
6730 #define mmOTG1_OTG_V_SYNC_A                                                                            0x1bb7
6731 #define mmOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
6732 #define mmOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bb8
6733 #define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
6734 #define mmOTG1_OTG_TRIGA_CNTL                                                                          0x1bb9
6735 #define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
6736 #define mmOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bba
6737 #define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
6738 #define mmOTG1_OTG_TRIGB_CNTL                                                                          0x1bbb
6739 #define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
6740 #define mmOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbc
6741 #define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
6742 #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbd
6743 #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
6744 #define mmOTG1_OTG_FLOW_CONTROL                                                                        0x1bbe
6745 #define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2
6746 #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bbf
6747 #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
6748 #define mmOTG1_OTG_CONTROL                                                                             0x1bc1
6749 #define mmOTG1_OTG_CONTROL_BASE_IDX                                                                    2
6750 #define mmOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc4
6751 #define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
6752 #define mmOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc5
6753 #define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
6754 #define mmOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
6755 #define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
6756 #define mmOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
6757 #define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
6758 #define mmOTG1_OTG_STATUS                                                                              0x1bc9
6759 #define mmOTG1_OTG_STATUS_BASE_IDX                                                                     2
6760 #define mmOTG1_OTG_STATUS_POSITION                                                                     0x1bca
6761 #define mmOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
6762 #define mmOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcb
6763 #define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
6764 #define mmOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcc
6765 #define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
6766 #define mmOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bcd
6767 #define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
6768 #define mmOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bce
6769 #define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
6770 #define mmOTG1_OTG_COUNT_CONTROL                                                                       0x1bcf
6771 #define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
6772 #define mmOTG1_OTG_COUNT_RESET                                                                         0x1bd0
6773 #define mmOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
6774 #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd1
6775 #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
6776 #define mmOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd2
6777 #define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
6778 #define mmOTG1_OTG_STEREO_STATUS                                                                       0x1bd3
6779 #define mmOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
6780 #define mmOTG1_OTG_STEREO_CONTROL                                                                      0x1bd4
6781 #define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
6782 #define mmOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd5
6783 #define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
6784 #define mmOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd6
6785 #define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
6786 #define mmOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd7
6787 #define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
6788 #define mmOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd8
6789 #define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
6790 #define mmOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bd9
6791 #define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
6792 #define mmOTG1_OTG_UPDATE_LOCK                                                                         0x1bda
6793 #define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
6794 #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdb
6795 #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
6796 #define mmOTG1_OTG_MASTER_EN                                                                           0x1bdc
6797 #define mmOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
6798 #define mmOTG1_OTG_BLANK_DATA_COLOR                                                                    0x1bde
6799 #define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
6800 #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT                                                                0x1bdf
6801 #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
6802 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1be2
6803 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
6804 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be3
6805 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
6806 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be4
6807 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
6808 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be5
6809 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
6810 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be6
6811 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
6812 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be7
6813 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
6814 #define mmOTG1_OTG_CRC_CNTL                                                                            0x1be8
6815 #define mmOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
6816 #define mmOTG1_OTG_CRC_CNTL2                                                                           0x1be9
6817 #define mmOTG1_OTG_CRC_CNTL2_BASE_IDX                                                                  2
6818 #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1bea
6819 #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
6820 #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1beb
6821 #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
6822 #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1bec
6823 #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
6824 #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1bed
6825 #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
6826 #define mmOTG1_OTG_CRC0_DATA_RG                                                                        0x1bee
6827 #define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
6828 #define mmOTG1_OTG_CRC0_DATA_B                                                                         0x1bef
6829 #define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
6830 #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bf0
6831 #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
6832 #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bf1
6833 #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
6834 #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bf2
6835 #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
6836 #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bf3
6837 #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
6838 #define mmOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf4
6839 #define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
6840 #define mmOTG1_OTG_CRC1_DATA_B                                                                         0x1bf5
6841 #define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
6842 #define mmOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf6
6843 #define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
6844 #define mmOTG1_OTG_CRC2_DATA_B                                                                         0x1bf7
6845 #define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
6846 #define mmOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf8
6847 #define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
6848 #define mmOTG1_OTG_CRC3_DATA_B                                                                         0x1bf9
6849 #define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
6850 #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bfa
6851 #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
6852 #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bfb
6853 #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
6854 #define mmOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c02
6855 #define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
6856 #define mmOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c03
6857 #define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
6858 #define mmOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c04
6859 #define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
6860 #define mmOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c05
6861 #define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
6862 #define mmOTG1_OTG_CLOCK_CONTROL                                                                       0x1c06
6863 #define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
6864 #define mmOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c07
6865 #define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
6866 #define mmOTG1_OTG_VUPDATE_PARAM                                                                       0x1c08
6867 #define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
6868 #define mmOTG1_OTG_VREADY_PARAM                                                                        0x1c09
6869 #define mmOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
6870 #define mmOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c0a
6871 #define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
6872 #define mmOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c0b
6873 #define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
6874 #define mmOTG1_OTG_GSL_CONTROL                                                                         0x1c0c
6875 #define mmOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
6876 #define mmOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0d
6877 #define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
6878 #define mmOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0e
6879 #define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
6880 #define mmOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0f
6881 #define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
6882 #define mmOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c10
6883 #define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
6884 #define mmOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c11
6885 #define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
6886 #define mmOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c12
6887 #define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
6888 #define mmOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c13
6889 #define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
6890 #define mmOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c14
6891 #define mmOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
6892 #define mmOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c15
6893 #define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
6894 #define mmOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c16
6895 #define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
6896 #define mmOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c17
6897 #define mmOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
6898 #define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c18
6899 #define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
6900 #define mmOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c19
6901 #define mmOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
6902 #define mmOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c1a
6903 #define mmOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
6904 #define mmOTG1_OTG_DRR_CONTROL                                                                         0x1c1b
6905 #define mmOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
6906 #define mmOTG1_OTG_M_CONST_DTO0                                                                        0x1c1c
6907 #define mmOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2
6908 #define mmOTG1_OTG_M_CONST_DTO1                                                                        0x1c1d
6909 #define mmOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2
6910 #define mmOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1e
6911 #define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
6912 #define mmOTG1_OTG_DSC_START_POSITION                                                                  0x1c1f
6913 #define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
6914 #define mmOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c20
6915 #define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
6916 #define mmOTG1_OTG_SPARE_REGISTER                                                                      0x1c22
6917 #define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2
6918 
6919 
6920 // addressBlock: dce_dc_optc_otg2_dispdec
6921 // base address: 0x400
6922 #define mmOTG2_OTG_H_TOTAL                                                                             0x1c2a
6923 #define mmOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2
6924 #define mmOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b
6925 #define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2
6926 #define mmOTG2_OTG_H_SYNC_A                                                                            0x1c2c
6927 #define mmOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2
6928 #define mmOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d
6929 #define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
6930 #define mmOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e
6931 #define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
6932 #define mmOTG2_OTG_V_TOTAL                                                                             0x1c2f
6933 #define mmOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2
6934 #define mmOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30
6935 #define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
6936 #define mmOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31
6937 #define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
6938 #define mmOTG2_OTG_V_TOTAL_MID                                                                         0x1c32
6939 #define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2
6940 #define mmOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33
6941 #define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
6942 #define mmOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c34
6943 #define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
6944 #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c35
6945 #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
6946 #define mmOTG2_OTG_V_BLANK_START_END                                                                   0x1c36
6947 #define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2
6948 #define mmOTG2_OTG_V_SYNC_A                                                                            0x1c37
6949 #define mmOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2
6950 #define mmOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c38
6951 #define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
6952 #define mmOTG2_OTG_TRIGA_CNTL                                                                          0x1c39
6953 #define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
6954 #define mmOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3a
6955 #define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
6956 #define mmOTG2_OTG_TRIGB_CNTL                                                                          0x1c3b
6957 #define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
6958 #define mmOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3c
6959 #define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
6960 #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3d
6961 #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
6962 #define mmOTG2_OTG_FLOW_CONTROL                                                                        0x1c3e
6963 #define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX                                                               2
6964 #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c3f
6965 #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
6966 #define mmOTG2_OTG_CONTROL                                                                             0x1c41
6967 #define mmOTG2_OTG_CONTROL_BASE_IDX                                                                    2
6968 #define mmOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c44
6969 #define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
6970 #define mmOTG2_OTG_INTERLACE_STATUS                                                                    0x1c45
6971 #define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
6972 #define mmOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47
6973 #define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
6974 #define mmOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48
6975 #define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
6976 #define mmOTG2_OTG_STATUS                                                                              0x1c49
6977 #define mmOTG2_OTG_STATUS_BASE_IDX                                                                     2
6978 #define mmOTG2_OTG_STATUS_POSITION                                                                     0x1c4a
6979 #define mmOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2
6980 #define mmOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4b
6981 #define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
6982 #define mmOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4c
6983 #define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
6984 #define mmOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4d
6985 #define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
6986 #define mmOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4e
6987 #define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
6988 #define mmOTG2_OTG_COUNT_CONTROL                                                                       0x1c4f
6989 #define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2
6990 #define mmOTG2_OTG_COUNT_RESET                                                                         0x1c50
6991 #define mmOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2
6992 #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c51
6993 #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
6994 #define mmOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c52
6995 #define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
6996 #define mmOTG2_OTG_STEREO_STATUS                                                                       0x1c53
6997 #define mmOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2
6998 #define mmOTG2_OTG_STEREO_CONTROL                                                                      0x1c54
6999 #define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2
7000 #define mmOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c55
7001 #define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
7002 #define mmOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c56
7003 #define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
7004 #define mmOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c57
7005 #define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
7006 #define mmOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c58
7007 #define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
7008 #define mmOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c59
7009 #define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
7010 #define mmOTG2_OTG_UPDATE_LOCK                                                                         0x1c5a
7011 #define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2
7012 #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5b
7013 #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
7014 #define mmOTG2_OTG_MASTER_EN                                                                           0x1c5c
7015 #define mmOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2
7016 #define mmOTG2_OTG_BLANK_DATA_COLOR                                                                    0x1c5e
7017 #define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
7018 #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT                                                                0x1c5f
7019 #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
7020 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c62
7021 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
7022 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c63
7023 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
7024 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c64
7025 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
7026 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c65
7027 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
7028 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c66
7029 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
7030 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c67
7031 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
7032 #define mmOTG2_OTG_CRC_CNTL                                                                            0x1c68
7033 #define mmOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2
7034 #define mmOTG2_OTG_CRC_CNTL2                                                                           0x1c69
7035 #define mmOTG2_OTG_CRC_CNTL2_BASE_IDX                                                                  2
7036 #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c6a
7037 #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
7038 #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c6b
7039 #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
7040 #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c6c
7041 #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
7042 #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c6d
7043 #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
7044 #define mmOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6e
7045 #define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
7046 #define mmOTG2_OTG_CRC0_DATA_B                                                                         0x1c6f
7047 #define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2
7048 #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c70
7049 #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
7050 #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c71
7051 #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
7052 #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c72
7053 #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
7054 #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c73
7055 #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
7056 #define mmOTG2_OTG_CRC1_DATA_RG                                                                        0x1c74
7057 #define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
7058 #define mmOTG2_OTG_CRC1_DATA_B                                                                         0x1c75
7059 #define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2
7060 #define mmOTG2_OTG_CRC2_DATA_RG                                                                        0x1c76
7061 #define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
7062 #define mmOTG2_OTG_CRC2_DATA_B                                                                         0x1c77
7063 #define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2
7064 #define mmOTG2_OTG_CRC3_DATA_RG                                                                        0x1c78
7065 #define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
7066 #define mmOTG2_OTG_CRC3_DATA_B                                                                         0x1c79
7067 #define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2
7068 #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c7a
7069 #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
7070 #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c7b
7071 #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
7072 #define mmOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c82
7073 #define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
7074 #define mmOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c83
7075 #define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
7076 #define mmOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c84
7077 #define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
7078 #define mmOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c85
7079 #define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
7080 #define mmOTG2_OTG_CLOCK_CONTROL                                                                       0x1c86
7081 #define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
7082 #define mmOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c87
7083 #define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
7084 #define mmOTG2_OTG_VUPDATE_PARAM                                                                       0x1c88
7085 #define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
7086 #define mmOTG2_OTG_VREADY_PARAM                                                                        0x1c89
7087 #define mmOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2
7088 #define mmOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c8a
7089 #define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
7090 #define mmOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c8b
7091 #define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
7092 #define mmOTG2_OTG_GSL_CONTROL                                                                         0x1c8c
7093 #define mmOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2
7094 #define mmOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8d
7095 #define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
7096 #define mmOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8e
7097 #define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
7098 #define mmOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8f
7099 #define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
7100 #define mmOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c90
7101 #define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
7102 #define mmOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c91
7103 #define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
7104 #define mmOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c92
7105 #define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
7106 #define mmOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c93
7107 #define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
7108 #define mmOTG2_OTG_GLOBAL_CONTROL4                                                                     0x1c94
7109 #define mmOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
7110 #define mmOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c95
7111 #define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
7112 #define mmOTG2_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c96
7113 #define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
7114 #define mmOTG2_OTG_DRR_TIMING_INT_STATUS                                                               0x1c97
7115 #define mmOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
7116 #define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c98
7117 #define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
7118 #define mmOTG2_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c99
7119 #define mmOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
7120 #define mmOTG2_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c9a
7121 #define mmOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
7122 #define mmOTG2_OTG_DRR_CONTROL                                                                         0x1c9b
7123 #define mmOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2
7124 #define mmOTG2_OTG_M_CONST_DTO0                                                                        0x1c9c
7125 #define mmOTG2_OTG_M_CONST_DTO0_BASE_IDX                                                               2
7126 #define mmOTG2_OTG_M_CONST_DTO1                                                                        0x1c9d
7127 #define mmOTG2_OTG_M_CONST_DTO1_BASE_IDX                                                               2
7128 #define mmOTG2_OTG_REQUEST_CONTROL                                                                     0x1c9e
7129 #define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
7130 #define mmOTG2_OTG_DSC_START_POSITION                                                                  0x1c9f
7131 #define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2
7132 #define mmOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1ca0
7133 #define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
7134 #define mmOTG2_OTG_SPARE_REGISTER                                                                      0x1ca2
7135 #define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2
7136 
7137 
7138 // addressBlock: dce_dc_optc_otg3_dispdec
7139 // base address: 0x600
7140 #define mmOTG3_OTG_H_TOTAL                                                                             0x1caa
7141 #define mmOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2
7142 #define mmOTG3_OTG_H_BLANK_START_END                                                                   0x1cab
7143 #define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2
7144 #define mmOTG3_OTG_H_SYNC_A                                                                            0x1cac
7145 #define mmOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2
7146 #define mmOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad
7147 #define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
7148 #define mmOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae
7149 #define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
7150 #define mmOTG3_OTG_V_TOTAL                                                                             0x1caf
7151 #define mmOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2
7152 #define mmOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0
7153 #define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
7154 #define mmOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1
7155 #define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
7156 #define mmOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2
7157 #define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2
7158 #define mmOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3
7159 #define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
7160 #define mmOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb4
7161 #define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
7162 #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb5
7163 #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
7164 #define mmOTG3_OTG_V_BLANK_START_END                                                                   0x1cb6
7165 #define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2
7166 #define mmOTG3_OTG_V_SYNC_A                                                                            0x1cb7
7167 #define mmOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2
7168 #define mmOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cb8
7169 #define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
7170 #define mmOTG3_OTG_TRIGA_CNTL                                                                          0x1cb9
7171 #define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
7172 #define mmOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cba
7173 #define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
7174 #define mmOTG3_OTG_TRIGB_CNTL                                                                          0x1cbb
7175 #define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
7176 #define mmOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbc
7177 #define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
7178 #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbd
7179 #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
7180 #define mmOTG3_OTG_FLOW_CONTROL                                                                        0x1cbe
7181 #define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX                                                               2
7182 #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cbf
7183 #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
7184 #define mmOTG3_OTG_CONTROL                                                                             0x1cc1
7185 #define mmOTG3_OTG_CONTROL_BASE_IDX                                                                    2
7186 #define mmOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc4
7187 #define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
7188 #define mmOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc5
7189 #define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
7190 #define mmOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7
7191 #define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
7192 #define mmOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8
7193 #define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
7194 #define mmOTG3_OTG_STATUS                                                                              0x1cc9
7195 #define mmOTG3_OTG_STATUS_BASE_IDX                                                                     2
7196 #define mmOTG3_OTG_STATUS_POSITION                                                                     0x1cca
7197 #define mmOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2
7198 #define mmOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccb
7199 #define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
7200 #define mmOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccc
7201 #define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
7202 #define mmOTG3_OTG_STATUS_VF_COUNT                                                                     0x1ccd
7203 #define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
7204 #define mmOTG3_OTG_STATUS_HV_COUNT                                                                     0x1cce
7205 #define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
7206 #define mmOTG3_OTG_COUNT_CONTROL                                                                       0x1ccf
7207 #define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2
7208 #define mmOTG3_OTG_COUNT_RESET                                                                         0x1cd0
7209 #define mmOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
7210 #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd1
7211 #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
7212 #define mmOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd2
7213 #define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
7214 #define mmOTG3_OTG_STEREO_STATUS                                                                       0x1cd3
7215 #define mmOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2
7216 #define mmOTG3_OTG_STEREO_CONTROL                                                                      0x1cd4
7217 #define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2
7218 #define mmOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd5
7219 #define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
7220 #define mmOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd6
7221 #define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
7222 #define mmOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd7
7223 #define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
7224 #define mmOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd8
7225 #define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
7226 #define mmOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cd9
7227 #define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
7228 #define mmOTG3_OTG_UPDATE_LOCK                                                                         0x1cda
7229 #define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2
7230 #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdb
7231 #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
7232 #define mmOTG3_OTG_MASTER_EN                                                                           0x1cdc
7233 #define mmOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2
7234 #define mmOTG3_OTG_BLANK_DATA_COLOR                                                                    0x1cde
7235 #define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
7236 #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT                                                                0x1cdf
7237 #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
7238 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1ce2
7239 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
7240 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce3
7241 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
7242 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce4
7243 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
7244 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce5
7245 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
7246 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce6
7247 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
7248 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce7
7249 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
7250 #define mmOTG3_OTG_CRC_CNTL                                                                            0x1ce8
7251 #define mmOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2
7252 #define mmOTG3_OTG_CRC_CNTL2                                                                           0x1ce9
7253 #define mmOTG3_OTG_CRC_CNTL2_BASE_IDX                                                                  2
7254 #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1cea
7255 #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
7256 #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1ceb
7257 #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
7258 #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1cec
7259 #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
7260 #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ced
7261 #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
7262 #define mmOTG3_OTG_CRC0_DATA_RG                                                                        0x1cee
7263 #define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
7264 #define mmOTG3_OTG_CRC0_DATA_B                                                                         0x1cef
7265 #define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2
7266 #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cf0
7267 #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
7268 #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1cf1
7269 #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
7270 #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cf2
7271 #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
7272 #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cf3
7273 #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
7274 #define mmOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf4
7275 #define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
7276 #define mmOTG3_OTG_CRC1_DATA_B                                                                         0x1cf5
7277 #define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2
7278 #define mmOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf6
7279 #define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
7280 #define mmOTG3_OTG_CRC2_DATA_B                                                                         0x1cf7
7281 #define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2
7282 #define mmOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf8
7283 #define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
7284 #define mmOTG3_OTG_CRC3_DATA_B                                                                         0x1cf9
7285 #define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2
7286 #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cfa
7287 #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
7288 #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cfb
7289 #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
7290 #define mmOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d02
7291 #define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
7292 #define mmOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d03
7293 #define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
7294 #define mmOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d04
7295 #define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
7296 #define mmOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d05
7297 #define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
7298 #define mmOTG3_OTG_CLOCK_CONTROL                                                                       0x1d06
7299 #define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
7300 #define mmOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d07
7301 #define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
7302 #define mmOTG3_OTG_VUPDATE_PARAM                                                                       0x1d08
7303 #define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
7304 #define mmOTG3_OTG_VREADY_PARAM                                                                        0x1d09
7305 #define mmOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2
7306 #define mmOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d0a
7307 #define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
7308 #define mmOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d0b
7309 #define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
7310 #define mmOTG3_OTG_GSL_CONTROL                                                                         0x1d0c
7311 #define mmOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2
7312 #define mmOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0d
7313 #define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
7314 #define mmOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0e
7315 #define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
7316 #define mmOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0f
7317 #define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
7318 #define mmOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d10
7319 #define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
7320 #define mmOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d11
7321 #define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
7322 #define mmOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d12
7323 #define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
7324 #define mmOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d13
7325 #define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
7326 #define mmOTG3_OTG_GLOBAL_CONTROL4                                                                     0x1d14
7327 #define mmOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
7328 #define mmOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d15
7329 #define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
7330 #define mmOTG3_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d16
7331 #define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
7332 #define mmOTG3_OTG_DRR_TIMING_INT_STATUS                                                               0x1d17
7333 #define mmOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
7334 #define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d18
7335 #define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
7336 #define mmOTG3_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d19
7337 #define mmOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
7338 #define mmOTG3_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d1a
7339 #define mmOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
7340 #define mmOTG3_OTG_DRR_CONTROL                                                                         0x1d1b
7341 #define mmOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2
7342 #define mmOTG3_OTG_M_CONST_DTO0                                                                        0x1d1c
7343 #define mmOTG3_OTG_M_CONST_DTO0_BASE_IDX                                                               2
7344 #define mmOTG3_OTG_M_CONST_DTO1                                                                        0x1d1d
7345 #define mmOTG3_OTG_M_CONST_DTO1_BASE_IDX                                                               2
7346 #define mmOTG3_OTG_REQUEST_CONTROL                                                                     0x1d1e
7347 #define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
7348 #define mmOTG3_OTG_DSC_START_POSITION                                                                  0x1d1f
7349 #define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2
7350 #define mmOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d20
7351 #define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
7352 #define mmOTG3_OTG_SPARE_REGISTER                                                                      0x1d22
7353 #define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2
7354 
7355 
7356 // addressBlock: dce_dc_optc_optc_misc_dispdec
7357 // base address: 0x0
7358 #define mmDWB_SOURCE_SELECT                                                                            0x1e2a
7359 #define mmDWB_SOURCE_SELECT_BASE_IDX                                                                   2
7360 #define mmGSL_SOURCE_SELECT                                                                            0x1e2b
7361 #define mmGSL_SOURCE_SELECT_BASE_IDX                                                                   2
7362 #define mmOPTC_CLOCK_CONTROL                                                                           0x1e2c
7363 #define mmOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
7364 #define mmODM_MEM_PWR_CTRL                                                                             0x1e2d
7365 #define mmODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
7366 #define mmODM_MEM_PWR_CTRL2                                                                            0x1e2e
7367 #define mmODM_MEM_PWR_CTRL2_BASE_IDX                                                                   2
7368 #define mmODM_MEM_PWR_CTRL3                                                                            0x1e2f
7369 #define mmODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
7370 #define mmODM_MEM_PWR_STATUS                                                                           0x1e30
7371 #define mmODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
7372 #define mmOPTC_MISC_SPARE_REGISTER                                                                     0x1e31
7373 #define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2
7374 
7375 
7376 // addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
7377 // base address: 0x79a8
7378 #define mmDC_PERFMON15_PERFCOUNTER_CNTL                                                                0x1e6a
7379 #define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX                                                       2
7380 #define mmDC_PERFMON15_PERFCOUNTER_CNTL2                                                               0x1e6b
7381 #define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
7382 #define mmDC_PERFMON15_PERFCOUNTER_STATE                                                               0x1e6c
7383 #define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX                                                      2
7384 #define mmDC_PERFMON15_PERFMON_CNTL                                                                    0x1e6d
7385 #define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX                                                           2
7386 #define mmDC_PERFMON15_PERFMON_CNTL2                                                                   0x1e6e
7387 #define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX                                                          2
7388 #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC                                                         0x1e6f
7389 #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
7390 #define mmDC_PERFMON15_PERFMON_CVALUE_LOW                                                              0x1e70
7391 #define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
7392 #define mmDC_PERFMON15_PERFMON_HI                                                                      0x1e71
7393 #define mmDC_PERFMON15_PERFMON_HI_BASE_IDX                                                             2
7394 #define mmDC_PERFMON15_PERFMON_LOW                                                                     0x1e72
7395 #define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX                                                            2
7396 
7397 
7398 // addressBlock: dce_dc_dio_dout_i2c_dispdec
7399 // base address: 0x0
7400 #define mmDC_I2C_CONTROL                                                                               0x1e98
7401 #define mmDC_I2C_CONTROL_BASE_IDX                                                                      2
7402 #define mmDC_I2C_ARBITRATION                                                                           0x1e99
7403 #define mmDC_I2C_ARBITRATION_BASE_IDX                                                                  2
7404 #define mmDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
7405 #define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
7406 #define mmDC_I2C_SW_STATUS                                                                             0x1e9b
7407 #define mmDC_I2C_SW_STATUS_BASE_IDX                                                                    2
7408 #define mmDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
7409 #define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
7410 #define mmDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
7411 #define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
7412 #define mmDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e
7413 #define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
7414 #define mmDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f
7415 #define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
7416 #define mmDC_I2C_DDC1_SPEED                                                                            0x1ea2
7417 #define mmDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
7418 #define mmDC_I2C_DDC1_SETUP                                                                            0x1ea3
7419 #define mmDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
7420 #define mmDC_I2C_DDC2_SPEED                                                                            0x1ea4
7421 #define mmDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
7422 #define mmDC_I2C_DDC2_SETUP                                                                            0x1ea5
7423 #define mmDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
7424 #define mmDC_I2C_DDC3_SPEED                                                                            0x1ea6
7425 #define mmDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
7426 #define mmDC_I2C_DDC3_SETUP                                                                            0x1ea7
7427 #define mmDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
7428 #define mmDC_I2C_DDC4_SPEED                                                                            0x1ea8
7429 #define mmDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
7430 #define mmDC_I2C_DDC4_SETUP                                                                            0x1ea9
7431 #define mmDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
7432 #define mmDC_I2C_TRANSACTION0                                                                          0x1eae
7433 #define mmDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
7434 #define mmDC_I2C_TRANSACTION1                                                                          0x1eaf
7435 #define mmDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
7436 #define mmDC_I2C_TRANSACTION2                                                                          0x1eb0
7437 #define mmDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
7438 #define mmDC_I2C_TRANSACTION3                                                                          0x1eb1
7439 #define mmDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
7440 #define mmDC_I2C_DATA                                                                                  0x1eb2
7441 #define mmDC_I2C_DATA_BASE_IDX                                                                         2
7442 #define mmDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
7443 #define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
7444 #define mmDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
7445 #define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
7446 
7447 
7448 // addressBlock: dce_dc_dio_dio_misc_dispdec
7449 // base address: 0x0
7450 #define mmDIO_SCRATCH0                                                                                 0x1eca
7451 #define mmDIO_SCRATCH0_BASE_IDX                                                                        2
7452 #define mmDIO_SCRATCH1                                                                                 0x1ecb
7453 #define mmDIO_SCRATCH1_BASE_IDX                                                                        2
7454 #define mmDIO_SCRATCH2                                                                                 0x1ecc
7455 #define mmDIO_SCRATCH2_BASE_IDX                                                                        2
7456 #define mmDIO_SCRATCH3                                                                                 0x1ecd
7457 #define mmDIO_SCRATCH3_BASE_IDX                                                                        2
7458 #define mmDIO_SCRATCH4                                                                                 0x1ece
7459 #define mmDIO_SCRATCH4_BASE_IDX                                                                        2
7460 #define mmDIO_SCRATCH5                                                                                 0x1ecf
7461 #define mmDIO_SCRATCH5_BASE_IDX                                                                        2
7462 #define mmDIO_SCRATCH6                                                                                 0x1ed0
7463 #define mmDIO_SCRATCH6_BASE_IDX                                                                        2
7464 #define mmDIO_SCRATCH7                                                                                 0x1ed1
7465 #define mmDIO_SCRATCH7_BASE_IDX                                                                        2
7466 #define mmDIO_MEM_PWR_STATUS                                                                           0x1edd
7467 #define mmDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
7468 #define mmDIO_MEM_PWR_CTRL                                                                             0x1ede
7469 #define mmDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
7470 #define mmDIO_MEM_PWR_CTRL2                                                                            0x1edf
7471 #define mmDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
7472 #define mmDIO_CLK_CNTL                                                                                 0x1ee0
7473 #define mmDIO_CLK_CNTL_BASE_IDX                                                                        2
7474 #define mmDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
7475 #define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
7476 #define mmDIG_SOFT_RESET                                                                               0x1eee
7477 #define mmDIG_SOFT_RESET_BASE_IDX                                                                      2
7478 #define mmDIO_CLK_CNTL2                                                                                0x1ef2
7479 #define mmDIO_CLK_CNTL2_BASE_IDX                                                                       2
7480 #define mmDIO_CLK_CNTL3                                                                                0x1ef3
7481 #define mmDIO_CLK_CNTL3_BASE_IDX                                                                       2
7482 #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
7483 #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
7484 #define mmDIO_GENERIC_INTERRUPT_MESSAGE                                                                0x1f02
7485 #define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX                                                       2
7486 #define mmDIO_GENERIC_INTERRUPT_CLEAR                                                                  0x1f03
7487 #define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX                                                         2
7488 
7489 
7490 // addressBlock: dce_dc_dio_hpd0_dispdec
7491 // base address: 0x0
7492 #define mmHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
7493 #define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
7494 #define mmHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
7495 #define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
7496 #define mmHPD0_DC_HPD_CONTROL                                                                          0x1f16
7497 #define mmHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
7498 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
7499 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
7500 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
7501 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
7502 
7503 
7504 // addressBlock: dce_dc_dio_hpd1_dispdec
7505 // base address: 0x20
7506 #define mmHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
7507 #define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
7508 #define mmHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
7509 #define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
7510 #define mmHPD1_DC_HPD_CONTROL                                                                          0x1f1e
7511 #define mmHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
7512 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
7513 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
7514 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
7515 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
7516 
7517 
7518 // addressBlock: dce_dc_dio_hpd2_dispdec
7519 // base address: 0x40
7520 #define mmHPD2_DC_HPD_INT_STATUS                                                                       0x1f24
7521 #define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
7522 #define mmHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25
7523 #define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
7524 #define mmHPD2_DC_HPD_CONTROL                                                                          0x1f26
7525 #define mmHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
7526 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27
7527 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
7528 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28
7529 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
7530 
7531 
7532 // addressBlock: dce_dc_dio_hpd3_dispdec
7533 // base address: 0x60
7534 #define mmHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c
7535 #define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
7536 #define mmHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d
7537 #define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
7538 #define mmHPD3_DC_HPD_CONTROL                                                                          0x1f2e
7539 #define mmHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
7540 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f
7541 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
7542 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30
7543 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
7544 
7545 
7546 // addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
7547 // base address: 0x7d10
7548 #define mmDC_PERFMON16_PERFCOUNTER_CNTL                                                                0x1f44
7549 #define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX                                                       2
7550 #define mmDC_PERFMON16_PERFCOUNTER_CNTL2                                                               0x1f45
7551 #define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
7552 #define mmDC_PERFMON16_PERFCOUNTER_STATE                                                               0x1f46
7553 #define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX                                                      2
7554 #define mmDC_PERFMON16_PERFMON_CNTL                                                                    0x1f47
7555 #define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX                                                           2
7556 #define mmDC_PERFMON16_PERFMON_CNTL2                                                                   0x1f48
7557 #define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX                                                          2
7558 #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC                                                         0x1f49
7559 #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
7560 #define mmDC_PERFMON16_PERFMON_CVALUE_LOW                                                              0x1f4a
7561 #define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
7562 #define mmDC_PERFMON16_PERFMON_HI                                                                      0x1f4b
7563 #define mmDC_PERFMON16_PERFMON_HI_BASE_IDX                                                             2
7564 #define mmDC_PERFMON16_PERFMON_LOW                                                                     0x1f4c
7565 #define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX                                                            2
7566 
7567 
7568 // addressBlock: dce_dc_dio_dp_aux0_dispdec
7569 // base address: 0x0
7570 #define mmDP_AUX0_AUX_CONTROL                                                                          0x1f50
7571 #define mmDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
7572 #define mmDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
7573 #define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
7574 #define mmDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
7575 #define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
7576 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
7577 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
7578 #define mmDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
7579 #define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
7580 #define mmDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
7581 #define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
7582 #define mmDP_AUX0_AUX_SW_DATA                                                                          0x1f56
7583 #define mmDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
7584 #define mmDP_AUX0_AUX_LS_DATA                                                                          0x1f57
7585 #define mmDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
7586 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
7587 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
7588 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
7589 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
7590 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
7591 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
7592 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
7593 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
7594 #define mmDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
7595 #define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
7596 #define mmDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
7597 #define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
7598 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
7599 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
7600 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
7601 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
7602 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
7603 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
7604 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
7605 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
7606 #define mmDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
7607 #define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
7608 
7609 
7610 // addressBlock: dce_dc_dio_dp_aux1_dispdec
7611 // base address: 0x70
7612 #define mmDP_AUX1_AUX_CONTROL                                                                          0x1f6c
7613 #define mmDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
7614 #define mmDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
7615 #define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
7616 #define mmDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
7617 #define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
7618 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
7619 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
7620 #define mmDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
7621 #define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
7622 #define mmDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
7623 #define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
7624 #define mmDP_AUX1_AUX_SW_DATA                                                                          0x1f72
7625 #define mmDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
7626 #define mmDP_AUX1_AUX_LS_DATA                                                                          0x1f73
7627 #define mmDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
7628 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
7629 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
7630 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
7631 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
7632 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
7633 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
7634 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
7635 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
7636 #define mmDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
7637 #define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
7638 #define mmDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
7639 #define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
7640 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
7641 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
7642 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
7643 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
7644 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
7645 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
7646 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
7647 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
7648 #define mmDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
7649 #define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
7650 
7651 
7652 // addressBlock: dce_dc_dio_dp_aux2_dispdec
7653 // base address: 0xe0
7654 #define mmDP_AUX2_AUX_CONTROL                                                                          0x1f88
7655 #define mmDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
7656 #define mmDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89
7657 #define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
7658 #define mmDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a
7659 #define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
7660 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b
7661 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
7662 #define mmDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c
7663 #define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
7664 #define mmDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d
7665 #define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
7666 #define mmDP_AUX2_AUX_SW_DATA                                                                          0x1f8e
7667 #define mmDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
7668 #define mmDP_AUX2_AUX_LS_DATA                                                                          0x1f8f
7669 #define mmDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
7670 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90
7671 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
7672 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91
7673 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
7674 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92
7675 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
7676 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93
7677 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
7678 #define mmDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94
7679 #define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
7680 #define mmDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95
7681 #define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
7682 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96
7683 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
7684 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97
7685 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
7686 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98
7687 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
7688 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99
7689 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
7690 #define mmDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e
7691 #define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
7692 
7693 
7694 // addressBlock: dce_dc_dio_dp_aux3_dispdec
7695 // base address: 0x150
7696 #define mmDP_AUX3_AUX_CONTROL                                                                          0x1fa4
7697 #define mmDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
7698 #define mmDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5
7699 #define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
7700 #define mmDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6
7701 #define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
7702 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7
7703 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
7704 #define mmDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8
7705 #define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
7706 #define mmDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9
7707 #define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
7708 #define mmDP_AUX3_AUX_SW_DATA                                                                          0x1faa
7709 #define mmDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
7710 #define mmDP_AUX3_AUX_LS_DATA                                                                          0x1fab
7711 #define mmDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
7712 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac
7713 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
7714 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad
7715 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
7716 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae
7717 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
7718 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf
7719 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
7720 #define mmDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0
7721 #define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
7722 #define mmDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1
7723 #define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
7724 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2
7725 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
7726 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3
7727 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
7728 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4
7729 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
7730 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5
7731 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
7732 #define mmDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba
7733 #define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
7734 
7735 
7736 // addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
7737 // base address: 0x154a0
7738 #define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068
7739 #define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
7740 #define mmVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069
7741 #define mmVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
7742 #define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a
7743 #define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
7744 #define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b
7745 #define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
7746 #define mmVPG0_VPG_GENERIC_STATUS                                                                      0x206c
7747 #define mmVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2
7748 #define mmVPG0_VPG_MEM_PWR                                                                             0x206d
7749 #define mmVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2
7750 #define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e
7751 #define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
7752 #define mmVPG0_VPG_ISRC1_2_DATA                                                                        0x206f
7753 #define mmVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
7754 #define mmVPG0_VPG_MPEG_INFO0                                                                          0x2070
7755 #define mmVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2
7756 #define mmVPG0_VPG_MPEG_INFO1                                                                          0x2071
7757 #define mmVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2
7758 
7759 
7760 // addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
7761 // base address: 0x154cc
7762 #define mmAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074
7763 #define mmAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
7764 #define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075
7765 #define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
7766 #define mmAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076
7767 #define mmAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
7768 #define mmAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077
7769 #define mmAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
7770 #define mmAFMT0_AFMT_60958_0                                                                           0x2078
7771 #define mmAFMT0_AFMT_60958_0_BASE_IDX                                                                  2
7772 #define mmAFMT0_AFMT_60958_1                                                                           0x2079
7773 #define mmAFMT0_AFMT_60958_1_BASE_IDX                                                                  2
7774 #define mmAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a
7775 #define mmAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
7776 #define mmAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b
7777 #define mmAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
7778 #define mmAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c
7779 #define mmAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
7780 #define mmAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d
7781 #define mmAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
7782 #define mmAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e
7783 #define mmAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
7784 #define mmAFMT0_AFMT_60958_2                                                                           0x207f
7785 #define mmAFMT0_AFMT_60958_2_BASE_IDX                                                                  2
7786 #define mmAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080
7787 #define mmAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
7788 #define mmAFMT0_AFMT_STATUS                                                                            0x2081
7789 #define mmAFMT0_AFMT_STATUS_BASE_IDX                                                                   2
7790 #define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082
7791 #define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
7792 #define mmAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083
7793 #define mmAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
7794 #define mmAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084
7795 #define mmAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
7796 #define mmAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085
7797 #define mmAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
7798 #define mmAFMT0_AFMT_MEM_PWR                                                                           0x2087
7799 #define mmAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2
7800 
7801 
7802 // addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
7803 // base address: 0x15524
7804 #define mmDME0_DME_CONTROL                                                                             0x2089
7805 #define mmDME0_DME_CONTROL_BASE_IDX                                                                    2
7806 #define mmDME0_DME_MEMORY_CONTROL                                                                      0x208a
7807 #define mmDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2
7808 
7809 
7810 // addressBlock: dce_dc_dio_dig0_dispdec
7811 // base address: 0x0
7812 #define mmDIG0_DIG_FE_CNTL                                                                             0x208b
7813 #define mmDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
7814 #define mmDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x208c
7815 #define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
7816 #define mmDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x208d
7817 #define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
7818 #define mmDIG0_DIG_CLOCK_PATTERN                                                                       0x208e
7819 #define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
7820 #define mmDIG0_DIG_TEST_PATTERN                                                                        0x208f
7821 #define mmDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
7822 #define mmDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x2090
7823 #define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
7824 #define mmDIG0_DIG_FIFO_STATUS                                                                         0x2091
7825 #define mmDIG0_DIG_FIFO_STATUS_BASE_IDX                                                                2
7826 #define mmDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x2092
7827 #define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
7828 #define mmDIG0_HDMI_CONTROL                                                                            0x2093
7829 #define mmDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
7830 #define mmDIG0_HDMI_STATUS                                                                             0x2094
7831 #define mmDIG0_HDMI_STATUS_BASE_IDX                                                                    2
7832 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x2095
7833 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
7834 #define mmDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x2096
7835 #define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
7836 #define mmDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x2097
7837 #define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
7838 #define mmDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x2098
7839 #define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
7840 #define mmDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x2099
7841 #define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
7842 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x209a
7843 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
7844 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x209b
7845 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
7846 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x209c
7847 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
7848 #define mmDIG0_HDMI_GC                                                                                 0x209d
7849 #define mmDIG0_HDMI_GC_BASE_IDX                                                                        2
7850 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x209e
7851 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
7852 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x209f
7853 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
7854 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20a0
7855 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
7856 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20a1
7857 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
7858 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20a2
7859 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
7860 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20a3
7861 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
7862 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20a4
7863 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
7864 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20a5
7865 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
7866 #define mmDIG0_HDMI_DB_CONTROL                                                                         0x20a6
7867 #define mmDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
7868 #define mmDIG0_HDMI_ACR_32_0                                                                           0x20a7
7869 #define mmDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
7870 #define mmDIG0_HDMI_ACR_32_1                                                                           0x20a8
7871 #define mmDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
7872 #define mmDIG0_HDMI_ACR_44_0                                                                           0x20a9
7873 #define mmDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
7874 #define mmDIG0_HDMI_ACR_44_1                                                                           0x20aa
7875 #define mmDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
7876 #define mmDIG0_HDMI_ACR_48_0                                                                           0x20ab
7877 #define mmDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
7878 #define mmDIG0_HDMI_ACR_48_1                                                                           0x20ac
7879 #define mmDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
7880 #define mmDIG0_HDMI_ACR_STATUS_0                                                                       0x20ad
7881 #define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
7882 #define mmDIG0_HDMI_ACR_STATUS_1                                                                       0x20ae
7883 #define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
7884 #define mmDIG0_AFMT_CNTL                                                                               0x20af
7885 #define mmDIG0_AFMT_CNTL_BASE_IDX                                                                      2
7886 #define mmDIG0_DIG_BE_CNTL                                                                             0x20b0
7887 #define mmDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
7888 #define mmDIG0_DIG_BE_EN_CNTL                                                                          0x20b1
7889 #define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
7890 #define mmDIG0_TMDS_CNTL                                                                               0x20d7
7891 #define mmDIG0_TMDS_CNTL_BASE_IDX                                                                      2
7892 #define mmDIG0_TMDS_CONTROL_CHAR                                                                       0x20d8
7893 #define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
7894 #define mmDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20d9
7895 #define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
7896 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20da
7897 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
7898 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20db
7899 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
7900 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20dc
7901 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
7902 #define mmDIG0_TMDS_CTL_BITS                                                                           0x20de
7903 #define mmDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
7904 #define mmDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20df
7905 #define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
7906 #define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20e0
7907 #define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
7908 #define mmDIG0_DIG_VERSION                                                                             0x20e4
7909 #define mmDIG0_DIG_VERSION_BASE_IDX                                                                    2
7910 #define mmDIG0_DIG_LANE_ENABLE                                                                         0x20e5
7911 #define mmDIG0_DIG_LANE_ENABLE_BASE_IDX                                                                2
7912 #define mmDIG0_FORCE_DIG_DISABLE                                                                       0x20e6
7913 #define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX                                                              2
7914 
7915 
7916 // addressBlock: dce_dc_dio_dp0_dispdec
7917 // base address: 0x0
7918 #define mmDP0_DP_LINK_CNTL                                                                             0x2108
7919 #define mmDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
7920 #define mmDP0_DP_PIXEL_FORMAT                                                                          0x2109
7921 #define mmDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
7922 #define mmDP0_DP_MSA_COLORIMETRY                                                                       0x210a
7923 #define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
7924 #define mmDP0_DP_CONFIG                                                                                0x210b
7925 #define mmDP0_DP_CONFIG_BASE_IDX                                                                       2
7926 #define mmDP0_DP_VID_STREAM_CNTL                                                                       0x210c
7927 #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
7928 #define mmDP0_DP_STEER_FIFO                                                                            0x210d
7929 #define mmDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
7930 #define mmDP0_DP_MSA_MISC                                                                              0x210e
7931 #define mmDP0_DP_MSA_MISC_BASE_IDX                                                                     2
7932 #define mmDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x210f
7933 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
7934 #define mmDP0_DP_VID_TIMING                                                                            0x2110
7935 #define mmDP0_DP_VID_TIMING_BASE_IDX                                                                   2
7936 #define mmDP0_DP_VID_N                                                                                 0x2111
7937 #define mmDP0_DP_VID_N_BASE_IDX                                                                        2
7938 #define mmDP0_DP_VID_M                                                                                 0x2112
7939 #define mmDP0_DP_VID_M_BASE_IDX                                                                        2
7940 #define mmDP0_DP_LINK_FRAMING_CNTL                                                                     0x2113
7941 #define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
7942 #define mmDP0_DP_HBR2_EYE_PATTERN                                                                      0x2114
7943 #define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
7944 #define mmDP0_DP_VID_MSA_VBID                                                                          0x2115
7945 #define mmDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
7946 #define mmDP0_DP_VID_INTERRUPT_CNTL                                                                    0x2116
7947 #define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
7948 #define mmDP0_DP_DPHY_CNTL                                                                             0x2117
7949 #define mmDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
7950 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2118
7951 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
7952 #define mmDP0_DP_DPHY_SYM0                                                                             0x2119
7953 #define mmDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
7954 #define mmDP0_DP_DPHY_SYM1                                                                             0x211a
7955 #define mmDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
7956 #define mmDP0_DP_DPHY_SYM2                                                                             0x211b
7957 #define mmDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
7958 #define mmDP0_DP_DPHY_8B10B_CNTL                                                                       0x211c
7959 #define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
7960 #define mmDP0_DP_DPHY_PRBS_CNTL                                                                        0x211d
7961 #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
7962 #define mmDP0_DP_DPHY_SCRAM_CNTL                                                                       0x211e
7963 #define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
7964 #define mmDP0_DP_DPHY_CRC_EN                                                                           0x211f
7965 #define mmDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
7966 #define mmDP0_DP_DPHY_CRC_CNTL                                                                         0x2120
7967 #define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
7968 #define mmDP0_DP_DPHY_CRC_RESULT                                                                       0x2121
7969 #define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
7970 #define mmDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2122
7971 #define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
7972 #define mmDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2123
7973 #define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
7974 #define mmDP0_DP_DPHY_FAST_TRAINING                                                                    0x2124
7975 #define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
7976 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2125
7977 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
7978 #define mmDP0_DP_SEC_CNTL                                                                              0x212b
7979 #define mmDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
7980 #define mmDP0_DP_SEC_CNTL1                                                                             0x212c
7981 #define mmDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
7982 #define mmDP0_DP_SEC_FRAMING1                                                                          0x212d
7983 #define mmDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
7984 #define mmDP0_DP_SEC_FRAMING2                                                                          0x212e
7985 #define mmDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
7986 #define mmDP0_DP_SEC_FRAMING3                                                                          0x212f
7987 #define mmDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
7988 #define mmDP0_DP_SEC_FRAMING4                                                                          0x2130
7989 #define mmDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
7990 #define mmDP0_DP_SEC_AUD_N                                                                             0x2131
7991 #define mmDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
7992 #define mmDP0_DP_SEC_AUD_N_READBACK                                                                    0x2132
7993 #define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
7994 #define mmDP0_DP_SEC_AUD_M                                                                             0x2133
7995 #define mmDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
7996 #define mmDP0_DP_SEC_AUD_M_READBACK                                                                    0x2134
7997 #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
7998 #define mmDP0_DP_SEC_TIMESTAMP                                                                         0x2135
7999 #define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
8000 #define mmDP0_DP_SEC_PACKET_CNTL                                                                       0x2136
8001 #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
8002 #define mmDP0_DP_MSE_RATE_CNTL                                                                         0x2137
8003 #define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
8004 #define mmDP0_DP_MSE_RATE_UPDATE                                                                       0x2139
8005 #define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
8006 #define mmDP0_DP_MSE_SAT0                                                                              0x213a
8007 #define mmDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
8008 #define mmDP0_DP_MSE_SAT1                                                                              0x213b
8009 #define mmDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
8010 #define mmDP0_DP_MSE_SAT2                                                                              0x213c
8011 #define mmDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
8012 #define mmDP0_DP_MSE_SAT_UPDATE                                                                        0x213d
8013 #define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
8014 #define mmDP0_DP_MSE_LINK_TIMING                                                                       0x213e
8015 #define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
8016 #define mmDP0_DP_MSE_MISC_CNTL                                                                         0x213f
8017 #define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
8018 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2144
8019 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
8020 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
8021 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
8022 #define mmDP0_DP_MSE_SAT0_STATUS                                                                       0x2147
8023 #define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
8024 #define mmDP0_DP_MSE_SAT1_STATUS                                                                       0x2148
8025 #define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
8026 #define mmDP0_DP_MSE_SAT2_STATUS                                                                       0x2149
8027 #define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
8028 #define mmDP0_DP_MSA_TIMING_PARAM1                                                                     0x214c
8029 #define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
8030 #define mmDP0_DP_MSA_TIMING_PARAM2                                                                     0x214d
8031 #define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
8032 #define mmDP0_DP_MSA_TIMING_PARAM3                                                                     0x214e
8033 #define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
8034 #define mmDP0_DP_MSA_TIMING_PARAM4                                                                     0x214f
8035 #define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
8036 #define mmDP0_DP_MSO_CNTL                                                                              0x2150
8037 #define mmDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
8038 #define mmDP0_DP_MSO_CNTL1                                                                             0x2151
8039 #define mmDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
8040 #define mmDP0_DP_DSC_CNTL                                                                              0x2152
8041 #define mmDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
8042 #define mmDP0_DP_SEC_CNTL2                                                                             0x2153
8043 #define mmDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
8044 #define mmDP0_DP_SEC_CNTL3                                                                             0x2154
8045 #define mmDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
8046 #define mmDP0_DP_SEC_CNTL4                                                                             0x2155
8047 #define mmDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
8048 #define mmDP0_DP_SEC_CNTL5                                                                             0x2156
8049 #define mmDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
8050 #define mmDP0_DP_SEC_CNTL6                                                                             0x2157
8051 #define mmDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
8052 #define mmDP0_DP_SEC_CNTL7                                                                             0x2158
8053 #define mmDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
8054 #define mmDP0_DP_DB_CNTL                                                                               0x2159
8055 #define mmDP0_DP_DB_CNTL_BASE_IDX                                                                      2
8056 #define mmDP0_DP_MSA_VBID_MISC                                                                         0x215a
8057 #define mmDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
8058 #define mmDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x215b
8059 #define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
8060 #define mmDP0_DP_DSC_BYTES_PER_PIXEL                                                                   0x215c
8061 #define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
8062 #define mmDP0_DP_ALPM_CNTL                                                                             0x215d
8063 #define mmDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
8064 #define mmDP0_DP_GSP8_CNTL                                                                             0x215e
8065 #define mmDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2
8066 #define mmDP0_DP_GSP9_CNTL                                                                             0x215f
8067 #define mmDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2
8068 #define mmDP0_DP_GSP10_CNTL                                                                            0x2160
8069 #define mmDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2
8070 #define mmDP0_DP_GSP11_CNTL                                                                            0x2161
8071 #define mmDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2
8072 #define mmDP0_DP_GSP_EN_DB_STATUS                                                                      0x2162
8073 #define mmDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
8074 
8075 
8076 // addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
8077 // base address: 0x158a0
8078 #define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2168
8079 #define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
8080 #define mmVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x2169
8081 #define mmVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
8082 #define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x216a
8083 #define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
8084 #define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x216b
8085 #define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
8086 #define mmVPG1_VPG_GENERIC_STATUS                                                                      0x216c
8087 #define mmVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2
8088 #define mmVPG1_VPG_MEM_PWR                                                                             0x216d
8089 #define mmVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2
8090 #define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x216e
8091 #define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
8092 #define mmVPG1_VPG_ISRC1_2_DATA                                                                        0x216f
8093 #define mmVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
8094 #define mmVPG1_VPG_MPEG_INFO0                                                                          0x2170
8095 #define mmVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2
8096 #define mmVPG1_VPG_MPEG_INFO1                                                                          0x2171
8097 #define mmVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2
8098 
8099 
8100 // addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
8101 // base address: 0x158cc
8102 #define mmAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2174
8103 #define mmAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
8104 #define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2175
8105 #define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
8106 #define mmAFMT1_AFMT_AUDIO_INFO0                                                                       0x2176
8107 #define mmAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
8108 #define mmAFMT1_AFMT_AUDIO_INFO1                                                                       0x2177
8109 #define mmAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
8110 #define mmAFMT1_AFMT_60958_0                                                                           0x2178
8111 #define mmAFMT1_AFMT_60958_0_BASE_IDX                                                                  2
8112 #define mmAFMT1_AFMT_60958_1                                                                           0x2179
8113 #define mmAFMT1_AFMT_60958_1_BASE_IDX                                                                  2
8114 #define mmAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x217a
8115 #define mmAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
8116 #define mmAFMT1_AFMT_RAMP_CONTROL0                                                                     0x217b
8117 #define mmAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
8118 #define mmAFMT1_AFMT_RAMP_CONTROL1                                                                     0x217c
8119 #define mmAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
8120 #define mmAFMT1_AFMT_RAMP_CONTROL2                                                                     0x217d
8121 #define mmAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
8122 #define mmAFMT1_AFMT_RAMP_CONTROL3                                                                     0x217e
8123 #define mmAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
8124 #define mmAFMT1_AFMT_60958_2                                                                           0x217f
8125 #define mmAFMT1_AFMT_60958_2_BASE_IDX                                                                  2
8126 #define mmAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x2180
8127 #define mmAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
8128 #define mmAFMT1_AFMT_STATUS                                                                            0x2181
8129 #define mmAFMT1_AFMT_STATUS_BASE_IDX                                                                   2
8130 #define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x2182
8131 #define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
8132 #define mmAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x2183
8133 #define mmAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
8134 #define mmAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x2184
8135 #define mmAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
8136 #define mmAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x2185
8137 #define mmAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
8138 #define mmAFMT1_AFMT_MEM_PWR                                                                           0x2187
8139 #define mmAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2
8140 
8141 
8142 // addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
8143 // base address: 0x15924
8144 #define mmDME1_DME_CONTROL                                                                             0x2189
8145 #define mmDME1_DME_CONTROL_BASE_IDX                                                                    2
8146 #define mmDME1_DME_MEMORY_CONTROL                                                                      0x218a
8147 #define mmDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2
8148 
8149 
8150 // addressBlock: dce_dc_dio_dig1_dispdec
8151 // base address: 0x400
8152 #define mmDIG1_DIG_FE_CNTL                                                                             0x218b
8153 #define mmDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
8154 #define mmDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x218c
8155 #define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
8156 #define mmDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x218d
8157 #define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
8158 #define mmDIG1_DIG_CLOCK_PATTERN                                                                       0x218e
8159 #define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
8160 #define mmDIG1_DIG_TEST_PATTERN                                                                        0x218f
8161 #define mmDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
8162 #define mmDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x2190
8163 #define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
8164 #define mmDIG1_DIG_FIFO_STATUS                                                                         0x2191
8165 #define mmDIG1_DIG_FIFO_STATUS_BASE_IDX                                                                2
8166 #define mmDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x2192
8167 #define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
8168 #define mmDIG1_HDMI_CONTROL                                                                            0x2193
8169 #define mmDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
8170 #define mmDIG1_HDMI_STATUS                                                                             0x2194
8171 #define mmDIG1_HDMI_STATUS_BASE_IDX                                                                    2
8172 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x2195
8173 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
8174 #define mmDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x2196
8175 #define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
8176 #define mmDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x2197
8177 #define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
8178 #define mmDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x2198
8179 #define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
8180 #define mmDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x2199
8181 #define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
8182 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x219a
8183 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
8184 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x219b
8185 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
8186 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x219c
8187 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
8188 #define mmDIG1_HDMI_GC                                                                                 0x219d
8189 #define mmDIG1_HDMI_GC_BASE_IDX                                                                        2
8190 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x219e
8191 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
8192 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x219f
8193 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
8194 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21a0
8195 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
8196 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21a1
8197 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
8198 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21a2
8199 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
8200 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21a3
8201 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
8202 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21a4
8203 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
8204 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21a5
8205 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
8206 #define mmDIG1_HDMI_DB_CONTROL                                                                         0x21a6
8207 #define mmDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
8208 #define mmDIG1_HDMI_ACR_32_0                                                                           0x21a7
8209 #define mmDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
8210 #define mmDIG1_HDMI_ACR_32_1                                                                           0x21a8
8211 #define mmDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
8212 #define mmDIG1_HDMI_ACR_44_0                                                                           0x21a9
8213 #define mmDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
8214 #define mmDIG1_HDMI_ACR_44_1                                                                           0x21aa
8215 #define mmDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
8216 #define mmDIG1_HDMI_ACR_48_0                                                                           0x21ab
8217 #define mmDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
8218 #define mmDIG1_HDMI_ACR_48_1                                                                           0x21ac
8219 #define mmDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
8220 #define mmDIG1_HDMI_ACR_STATUS_0                                                                       0x21ad
8221 #define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
8222 #define mmDIG1_HDMI_ACR_STATUS_1                                                                       0x21ae
8223 #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
8224 #define mmDIG1_AFMT_CNTL                                                                               0x21af
8225 #define mmDIG1_AFMT_CNTL_BASE_IDX                                                                      2
8226 #define mmDIG1_DIG_BE_CNTL                                                                             0x21b0
8227 #define mmDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
8228 #define mmDIG1_DIG_BE_EN_CNTL                                                                          0x21b1
8229 #define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
8230 #define mmDIG1_TMDS_CNTL                                                                               0x21d7
8231 #define mmDIG1_TMDS_CNTL_BASE_IDX                                                                      2
8232 #define mmDIG1_TMDS_CONTROL_CHAR                                                                       0x21d8
8233 #define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
8234 #define mmDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x21d9
8235 #define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
8236 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x21da
8237 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
8238 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x21db
8239 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
8240 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x21dc
8241 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
8242 #define mmDIG1_TMDS_CTL_BITS                                                                           0x21de
8243 #define mmDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
8244 #define mmDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x21df
8245 #define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
8246 #define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x21e0
8247 #define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
8248 #define mmDIG1_DIG_VERSION                                                                             0x21e4
8249 #define mmDIG1_DIG_VERSION_BASE_IDX                                                                    2
8250 #define mmDIG1_DIG_LANE_ENABLE                                                                         0x21e5
8251 #define mmDIG1_DIG_LANE_ENABLE_BASE_IDX                                                                2
8252 #define mmDIG1_FORCE_DIG_DISABLE                                                                       0x21e6
8253 #define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX                                                              2
8254 
8255 
8256 // addressBlock: dce_dc_dio_dp1_dispdec
8257 // base address: 0x400
8258 #define mmDP1_DP_LINK_CNTL                                                                             0x2208
8259 #define mmDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
8260 #define mmDP1_DP_PIXEL_FORMAT                                                                          0x2209
8261 #define mmDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
8262 #define mmDP1_DP_MSA_COLORIMETRY                                                                       0x220a
8263 #define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
8264 #define mmDP1_DP_CONFIG                                                                                0x220b
8265 #define mmDP1_DP_CONFIG_BASE_IDX                                                                       2
8266 #define mmDP1_DP_VID_STREAM_CNTL                                                                       0x220c
8267 #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
8268 #define mmDP1_DP_STEER_FIFO                                                                            0x220d
8269 #define mmDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
8270 #define mmDP1_DP_MSA_MISC                                                                              0x220e
8271 #define mmDP1_DP_MSA_MISC_BASE_IDX                                                                     2
8272 #define mmDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x220f
8273 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
8274 #define mmDP1_DP_VID_TIMING                                                                            0x2210
8275 #define mmDP1_DP_VID_TIMING_BASE_IDX                                                                   2
8276 #define mmDP1_DP_VID_N                                                                                 0x2211
8277 #define mmDP1_DP_VID_N_BASE_IDX                                                                        2
8278 #define mmDP1_DP_VID_M                                                                                 0x2212
8279 #define mmDP1_DP_VID_M_BASE_IDX                                                                        2
8280 #define mmDP1_DP_LINK_FRAMING_CNTL                                                                     0x2213
8281 #define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
8282 #define mmDP1_DP_HBR2_EYE_PATTERN                                                                      0x2214
8283 #define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
8284 #define mmDP1_DP_VID_MSA_VBID                                                                          0x2215
8285 #define mmDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
8286 #define mmDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2216
8287 #define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
8288 #define mmDP1_DP_DPHY_CNTL                                                                             0x2217
8289 #define mmDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
8290 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2218
8291 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
8292 #define mmDP1_DP_DPHY_SYM0                                                                             0x2219
8293 #define mmDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
8294 #define mmDP1_DP_DPHY_SYM1                                                                             0x221a
8295 #define mmDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
8296 #define mmDP1_DP_DPHY_SYM2                                                                             0x221b
8297 #define mmDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
8298 #define mmDP1_DP_DPHY_8B10B_CNTL                                                                       0x221c
8299 #define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
8300 #define mmDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
8301 #define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
8302 #define mmDP1_DP_DPHY_SCRAM_CNTL                                                                       0x221e
8303 #define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
8304 #define mmDP1_DP_DPHY_CRC_EN                                                                           0x221f
8305 #define mmDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
8306 #define mmDP1_DP_DPHY_CRC_CNTL                                                                         0x2220
8307 #define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
8308 #define mmDP1_DP_DPHY_CRC_RESULT                                                                       0x2221
8309 #define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
8310 #define mmDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x2222
8311 #define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
8312 #define mmDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x2223
8313 #define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
8314 #define mmDP1_DP_DPHY_FAST_TRAINING                                                                    0x2224
8315 #define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
8316 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2225
8317 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
8318 #define mmDP1_DP_SEC_CNTL                                                                              0x222b
8319 #define mmDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
8320 #define mmDP1_DP_SEC_CNTL1                                                                             0x222c
8321 #define mmDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
8322 #define mmDP1_DP_SEC_FRAMING1                                                                          0x222d
8323 #define mmDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
8324 #define mmDP1_DP_SEC_FRAMING2                                                                          0x222e
8325 #define mmDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
8326 #define mmDP1_DP_SEC_FRAMING3                                                                          0x222f
8327 #define mmDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
8328 #define mmDP1_DP_SEC_FRAMING4                                                                          0x2230
8329 #define mmDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
8330 #define mmDP1_DP_SEC_AUD_N                                                                             0x2231
8331 #define mmDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
8332 #define mmDP1_DP_SEC_AUD_N_READBACK                                                                    0x2232
8333 #define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
8334 #define mmDP1_DP_SEC_AUD_M                                                                             0x2233
8335 #define mmDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
8336 #define mmDP1_DP_SEC_AUD_M_READBACK                                                                    0x2234
8337 #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
8338 #define mmDP1_DP_SEC_TIMESTAMP                                                                         0x2235
8339 #define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
8340 #define mmDP1_DP_SEC_PACKET_CNTL                                                                       0x2236
8341 #define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
8342 #define mmDP1_DP_MSE_RATE_CNTL                                                                         0x2237
8343 #define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
8344 #define mmDP1_DP_MSE_RATE_UPDATE                                                                       0x2239
8345 #define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
8346 #define mmDP1_DP_MSE_SAT0                                                                              0x223a
8347 #define mmDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
8348 #define mmDP1_DP_MSE_SAT1                                                                              0x223b
8349 #define mmDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
8350 #define mmDP1_DP_MSE_SAT2                                                                              0x223c
8351 #define mmDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
8352 #define mmDP1_DP_MSE_SAT_UPDATE                                                                        0x223d
8353 #define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
8354 #define mmDP1_DP_MSE_LINK_TIMING                                                                       0x223e
8355 #define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
8356 #define mmDP1_DP_MSE_MISC_CNTL                                                                         0x223f
8357 #define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
8358 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2244
8359 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
8360 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
8361 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
8362 #define mmDP1_DP_MSE_SAT0_STATUS                                                                       0x2247
8363 #define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
8364 #define mmDP1_DP_MSE_SAT1_STATUS                                                                       0x2248
8365 #define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
8366 #define mmDP1_DP_MSE_SAT2_STATUS                                                                       0x2249
8367 #define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
8368 #define mmDP1_DP_MSA_TIMING_PARAM1                                                                     0x224c
8369 #define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
8370 #define mmDP1_DP_MSA_TIMING_PARAM2                                                                     0x224d
8371 #define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
8372 #define mmDP1_DP_MSA_TIMING_PARAM3                                                                     0x224e
8373 #define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
8374 #define mmDP1_DP_MSA_TIMING_PARAM4                                                                     0x224f
8375 #define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
8376 #define mmDP1_DP_MSO_CNTL                                                                              0x2250
8377 #define mmDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
8378 #define mmDP1_DP_MSO_CNTL1                                                                             0x2251
8379 #define mmDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
8380 #define mmDP1_DP_DSC_CNTL                                                                              0x2252
8381 #define mmDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
8382 #define mmDP1_DP_SEC_CNTL2                                                                             0x2253
8383 #define mmDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
8384 #define mmDP1_DP_SEC_CNTL3                                                                             0x2254
8385 #define mmDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
8386 #define mmDP1_DP_SEC_CNTL4                                                                             0x2255
8387 #define mmDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
8388 #define mmDP1_DP_SEC_CNTL5                                                                             0x2256
8389 #define mmDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
8390 #define mmDP1_DP_SEC_CNTL6                                                                             0x2257
8391 #define mmDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
8392 #define mmDP1_DP_SEC_CNTL7                                                                             0x2258
8393 #define mmDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
8394 #define mmDP1_DP_DB_CNTL                                                                               0x2259
8395 #define mmDP1_DP_DB_CNTL_BASE_IDX                                                                      2
8396 #define mmDP1_DP_MSA_VBID_MISC                                                                         0x225a
8397 #define mmDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
8398 #define mmDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x225b
8399 #define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
8400 #define mmDP1_DP_DSC_BYTES_PER_PIXEL                                                                   0x225c
8401 #define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
8402 #define mmDP1_DP_ALPM_CNTL                                                                             0x225d
8403 #define mmDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
8404 #define mmDP1_DP_GSP8_CNTL                                                                             0x225e
8405 #define mmDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2
8406 #define mmDP1_DP_GSP9_CNTL                                                                             0x225f
8407 #define mmDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2
8408 #define mmDP1_DP_GSP10_CNTL                                                                            0x2260
8409 #define mmDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2
8410 #define mmDP1_DP_GSP11_CNTL                                                                            0x2261
8411 #define mmDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2
8412 #define mmDP1_DP_GSP_EN_DB_STATUS                                                                      0x2262
8413 #define mmDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
8414 
8415 
8416 // addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
8417 // base address: 0x15ca0
8418 #define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2268
8419 #define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
8420 #define mmVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x2269
8421 #define mmVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
8422 #define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x226a
8423 #define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
8424 #define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x226b
8425 #define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
8426 #define mmVPG2_VPG_GENERIC_STATUS                                                                      0x226c
8427 #define mmVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             2
8428 #define mmVPG2_VPG_MEM_PWR                                                                             0x226d
8429 #define mmVPG2_VPG_MEM_PWR_BASE_IDX                                                                    2
8430 #define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x226e
8431 #define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
8432 #define mmVPG2_VPG_ISRC1_2_DATA                                                                        0x226f
8433 #define mmVPG2_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
8434 #define mmVPG2_VPG_MPEG_INFO0                                                                          0x2270
8435 #define mmVPG2_VPG_MPEG_INFO0_BASE_IDX                                                                 2
8436 #define mmVPG2_VPG_MPEG_INFO1                                                                          0x2271
8437 #define mmVPG2_VPG_MPEG_INFO1_BASE_IDX                                                                 2
8438 
8439 
8440 // addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
8441 // base address: 0x15ccc
8442 #define mmAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x2274
8443 #define mmAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
8444 #define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2275
8445 #define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
8446 #define mmAFMT2_AFMT_AUDIO_INFO0                                                                       0x2276
8447 #define mmAFMT2_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
8448 #define mmAFMT2_AFMT_AUDIO_INFO1                                                                       0x2277
8449 #define mmAFMT2_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
8450 #define mmAFMT2_AFMT_60958_0                                                                           0x2278
8451 #define mmAFMT2_AFMT_60958_0_BASE_IDX                                                                  2
8452 #define mmAFMT2_AFMT_60958_1                                                                           0x2279
8453 #define mmAFMT2_AFMT_60958_1_BASE_IDX                                                                  2
8454 #define mmAFMT2_AFMT_AUDIO_CRC_CONTROL                                                                 0x227a
8455 #define mmAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
8456 #define mmAFMT2_AFMT_RAMP_CONTROL0                                                                     0x227b
8457 #define mmAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
8458 #define mmAFMT2_AFMT_RAMP_CONTROL1                                                                     0x227c
8459 #define mmAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
8460 #define mmAFMT2_AFMT_RAMP_CONTROL2                                                                     0x227d
8461 #define mmAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
8462 #define mmAFMT2_AFMT_RAMP_CONTROL3                                                                     0x227e
8463 #define mmAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
8464 #define mmAFMT2_AFMT_60958_2                                                                           0x227f
8465 #define mmAFMT2_AFMT_60958_2_BASE_IDX                                                                  2
8466 #define mmAFMT2_AFMT_AUDIO_CRC_RESULT                                                                  0x2280
8467 #define mmAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
8468 #define mmAFMT2_AFMT_STATUS                                                                            0x2281
8469 #define mmAFMT2_AFMT_STATUS_BASE_IDX                                                                   2
8470 #define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x2282
8471 #define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
8472 #define mmAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x2283
8473 #define mmAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
8474 #define mmAFMT2_AFMT_INTERRUPT_STATUS                                                                  0x2284
8475 #define mmAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
8476 #define mmAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x2285
8477 #define mmAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
8478 #define mmAFMT2_AFMT_MEM_PWR                                                                           0x2287
8479 #define mmAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  2
8480 
8481 
8482 // addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
8483 // base address: 0x15d24
8484 #define mmDME2_DME_CONTROL                                                                             0x2289
8485 #define mmDME2_DME_CONTROL_BASE_IDX                                                                    2
8486 #define mmDME2_DME_MEMORY_CONTROL                                                                      0x228a
8487 #define mmDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             2
8488 
8489 
8490 // addressBlock: dce_dc_dio_dig2_dispdec
8491 // base address: 0x800
8492 #define mmDIG2_DIG_FE_CNTL                                                                             0x228b
8493 #define mmDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
8494 #define mmDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x228c
8495 #define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
8496 #define mmDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x228d
8497 #define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
8498 #define mmDIG2_DIG_CLOCK_PATTERN                                                                       0x228e
8499 #define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
8500 #define mmDIG2_DIG_TEST_PATTERN                                                                        0x228f
8501 #define mmDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
8502 #define mmDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x2290
8503 #define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
8504 #define mmDIG2_DIG_FIFO_STATUS                                                                         0x2291
8505 #define mmDIG2_DIG_FIFO_STATUS_BASE_IDX                                                                2
8506 #define mmDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x2292
8507 #define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
8508 #define mmDIG2_HDMI_CONTROL                                                                            0x2293
8509 #define mmDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
8510 #define mmDIG2_HDMI_STATUS                                                                             0x2294
8511 #define mmDIG2_HDMI_STATUS_BASE_IDX                                                                    2
8512 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x2295
8513 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
8514 #define mmDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x2296
8515 #define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
8516 #define mmDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x2297
8517 #define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
8518 #define mmDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x2298
8519 #define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
8520 #define mmDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x2299
8521 #define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
8522 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x229a
8523 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
8524 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6                                                            0x229b
8525 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
8526 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x229c
8527 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
8528 #define mmDIG2_HDMI_GC                                                                                 0x229d
8529 #define mmDIG2_HDMI_GC_BASE_IDX                                                                        2
8530 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x229e
8531 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
8532 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x229f
8533 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
8534 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x22a0
8535 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
8536 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x22a1
8537 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
8538 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7                                                            0x22a2
8539 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
8540 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8                                                            0x22a3
8541 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
8542 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9                                                            0x22a4
8543 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
8544 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10                                                           0x22a5
8545 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
8546 #define mmDIG2_HDMI_DB_CONTROL                                                                         0x22a6
8547 #define mmDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2
8548 #define mmDIG2_HDMI_ACR_32_0                                                                           0x22a7
8549 #define mmDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
8550 #define mmDIG2_HDMI_ACR_32_1                                                                           0x22a8
8551 #define mmDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
8552 #define mmDIG2_HDMI_ACR_44_0                                                                           0x22a9
8553 #define mmDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
8554 #define mmDIG2_HDMI_ACR_44_1                                                                           0x22aa
8555 #define mmDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
8556 #define mmDIG2_HDMI_ACR_48_0                                                                           0x22ab
8557 #define mmDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
8558 #define mmDIG2_HDMI_ACR_48_1                                                                           0x22ac
8559 #define mmDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
8560 #define mmDIG2_HDMI_ACR_STATUS_0                                                                       0x22ad
8561 #define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
8562 #define mmDIG2_HDMI_ACR_STATUS_1                                                                       0x22ae
8563 #define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
8564 #define mmDIG2_AFMT_CNTL                                                                               0x22af
8565 #define mmDIG2_AFMT_CNTL_BASE_IDX                                                                      2
8566 #define mmDIG2_DIG_BE_CNTL                                                                             0x22b0
8567 #define mmDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
8568 #define mmDIG2_DIG_BE_EN_CNTL                                                                          0x22b1
8569 #define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
8570 #define mmDIG2_TMDS_CNTL                                                                               0x22d7
8571 #define mmDIG2_TMDS_CNTL_BASE_IDX                                                                      2
8572 #define mmDIG2_TMDS_CONTROL_CHAR                                                                       0x22d8
8573 #define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
8574 #define mmDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x22d9
8575 #define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
8576 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x22da
8577 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
8578 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x22db
8579 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
8580 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x22dc
8581 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
8582 #define mmDIG2_TMDS_CTL_BITS                                                                           0x22de
8583 #define mmDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
8584 #define mmDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x22df
8585 #define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
8586 #define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x22e0
8587 #define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
8588 #define mmDIG2_DIG_VERSION                                                                             0x22e4
8589 #define mmDIG2_DIG_VERSION_BASE_IDX                                                                    2
8590 #define mmDIG2_DIG_LANE_ENABLE                                                                         0x22e5
8591 #define mmDIG2_DIG_LANE_ENABLE_BASE_IDX                                                                2
8592 #define mmDIG2_FORCE_DIG_DISABLE                                                                       0x22e6
8593 #define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX                                                              2
8594 
8595 
8596 // addressBlock: dce_dc_dio_dp2_dispdec
8597 // base address: 0x800
8598 #define mmDP2_DP_LINK_CNTL                                                                             0x2308
8599 #define mmDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
8600 #define mmDP2_DP_PIXEL_FORMAT                                                                          0x2309
8601 #define mmDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
8602 #define mmDP2_DP_MSA_COLORIMETRY                                                                       0x230a
8603 #define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
8604 #define mmDP2_DP_CONFIG                                                                                0x230b
8605 #define mmDP2_DP_CONFIG_BASE_IDX                                                                       2
8606 #define mmDP2_DP_VID_STREAM_CNTL                                                                       0x230c
8607 #define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
8608 #define mmDP2_DP_STEER_FIFO                                                                            0x230d
8609 #define mmDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
8610 #define mmDP2_DP_MSA_MISC                                                                              0x230e
8611 #define mmDP2_DP_MSA_MISC_BASE_IDX                                                                     2
8612 #define mmDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x230f
8613 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
8614 #define mmDP2_DP_VID_TIMING                                                                            0x2310
8615 #define mmDP2_DP_VID_TIMING_BASE_IDX                                                                   2
8616 #define mmDP2_DP_VID_N                                                                                 0x2311
8617 #define mmDP2_DP_VID_N_BASE_IDX                                                                        2
8618 #define mmDP2_DP_VID_M                                                                                 0x2312
8619 #define mmDP2_DP_VID_M_BASE_IDX                                                                        2
8620 #define mmDP2_DP_LINK_FRAMING_CNTL                                                                     0x2313
8621 #define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
8622 #define mmDP2_DP_HBR2_EYE_PATTERN                                                                      0x2314
8623 #define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
8624 #define mmDP2_DP_VID_MSA_VBID                                                                          0x2315
8625 #define mmDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
8626 #define mmDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2316
8627 #define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
8628 #define mmDP2_DP_DPHY_CNTL                                                                             0x2317
8629 #define mmDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
8630 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2318
8631 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
8632 #define mmDP2_DP_DPHY_SYM0                                                                             0x2319
8633 #define mmDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
8634 #define mmDP2_DP_DPHY_SYM1                                                                             0x231a
8635 #define mmDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
8636 #define mmDP2_DP_DPHY_SYM2                                                                             0x231b
8637 #define mmDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
8638 #define mmDP2_DP_DPHY_8B10B_CNTL                                                                       0x231c
8639 #define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
8640 #define mmDP2_DP_DPHY_PRBS_CNTL                                                                        0x231d
8641 #define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
8642 #define mmDP2_DP_DPHY_SCRAM_CNTL                                                                       0x231e
8643 #define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
8644 #define mmDP2_DP_DPHY_CRC_EN                                                                           0x231f
8645 #define mmDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
8646 #define mmDP2_DP_DPHY_CRC_CNTL                                                                         0x2320
8647 #define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
8648 #define mmDP2_DP_DPHY_CRC_RESULT                                                                       0x2321
8649 #define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
8650 #define mmDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2322
8651 #define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
8652 #define mmDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2323
8653 #define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
8654 #define mmDP2_DP_DPHY_FAST_TRAINING                                                                    0x2324
8655 #define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
8656 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2325
8657 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
8658 #define mmDP2_DP_SEC_CNTL                                                                              0x232b
8659 #define mmDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
8660 #define mmDP2_DP_SEC_CNTL1                                                                             0x232c
8661 #define mmDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
8662 #define mmDP2_DP_SEC_FRAMING1                                                                          0x232d
8663 #define mmDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
8664 #define mmDP2_DP_SEC_FRAMING2                                                                          0x232e
8665 #define mmDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
8666 #define mmDP2_DP_SEC_FRAMING3                                                                          0x232f
8667 #define mmDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
8668 #define mmDP2_DP_SEC_FRAMING4                                                                          0x2330
8669 #define mmDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
8670 #define mmDP2_DP_SEC_AUD_N                                                                             0x2331
8671 #define mmDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
8672 #define mmDP2_DP_SEC_AUD_N_READBACK                                                                    0x2332
8673 #define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
8674 #define mmDP2_DP_SEC_AUD_M                                                                             0x2333
8675 #define mmDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
8676 #define mmDP2_DP_SEC_AUD_M_READBACK                                                                    0x2334
8677 #define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
8678 #define mmDP2_DP_SEC_TIMESTAMP                                                                         0x2335
8679 #define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
8680 #define mmDP2_DP_SEC_PACKET_CNTL                                                                       0x2336
8681 #define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
8682 #define mmDP2_DP_MSE_RATE_CNTL                                                                         0x2337
8683 #define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
8684 #define mmDP2_DP_MSE_RATE_UPDATE                                                                       0x2339
8685 #define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
8686 #define mmDP2_DP_MSE_SAT0                                                                              0x233a
8687 #define mmDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
8688 #define mmDP2_DP_MSE_SAT1                                                                              0x233b
8689 #define mmDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
8690 #define mmDP2_DP_MSE_SAT2                                                                              0x233c
8691 #define mmDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
8692 #define mmDP2_DP_MSE_SAT_UPDATE                                                                        0x233d
8693 #define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
8694 #define mmDP2_DP_MSE_LINK_TIMING                                                                       0x233e
8695 #define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
8696 #define mmDP2_DP_MSE_MISC_CNTL                                                                         0x233f
8697 #define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
8698 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2344
8699 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
8700 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2345
8701 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
8702 #define mmDP2_DP_MSE_SAT0_STATUS                                                                       0x2347
8703 #define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
8704 #define mmDP2_DP_MSE_SAT1_STATUS                                                                       0x2348
8705 #define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
8706 #define mmDP2_DP_MSE_SAT2_STATUS                                                                       0x2349
8707 #define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
8708 #define mmDP2_DP_MSA_TIMING_PARAM1                                                                     0x234c
8709 #define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
8710 #define mmDP2_DP_MSA_TIMING_PARAM2                                                                     0x234d
8711 #define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
8712 #define mmDP2_DP_MSA_TIMING_PARAM3                                                                     0x234e
8713 #define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
8714 #define mmDP2_DP_MSA_TIMING_PARAM4                                                                     0x234f
8715 #define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
8716 #define mmDP2_DP_MSO_CNTL                                                                              0x2350
8717 #define mmDP2_DP_MSO_CNTL_BASE_IDX                                                                     2
8718 #define mmDP2_DP_MSO_CNTL1                                                                             0x2351
8719 #define mmDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2
8720 #define mmDP2_DP_DSC_CNTL                                                                              0x2352
8721 #define mmDP2_DP_DSC_CNTL_BASE_IDX                                                                     2
8722 #define mmDP2_DP_SEC_CNTL2                                                                             0x2353
8723 #define mmDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2
8724 #define mmDP2_DP_SEC_CNTL3                                                                             0x2354
8725 #define mmDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2
8726 #define mmDP2_DP_SEC_CNTL4                                                                             0x2355
8727 #define mmDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2
8728 #define mmDP2_DP_SEC_CNTL5                                                                             0x2356
8729 #define mmDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2
8730 #define mmDP2_DP_SEC_CNTL6                                                                             0x2357
8731 #define mmDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2
8732 #define mmDP2_DP_SEC_CNTL7                                                                             0x2358
8733 #define mmDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2
8734 #define mmDP2_DP_DB_CNTL                                                                               0x2359
8735 #define mmDP2_DP_DB_CNTL_BASE_IDX                                                                      2
8736 #define mmDP2_DP_MSA_VBID_MISC                                                                         0x235a
8737 #define mmDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2
8738 #define mmDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x235b
8739 #define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
8740 #define mmDP2_DP_DSC_BYTES_PER_PIXEL                                                                   0x235c
8741 #define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
8742 #define mmDP2_DP_ALPM_CNTL                                                                             0x235d
8743 #define mmDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2
8744 #define mmDP2_DP_GSP8_CNTL                                                                             0x235e
8745 #define mmDP2_DP_GSP8_CNTL_BASE_IDX                                                                    2
8746 #define mmDP2_DP_GSP9_CNTL                                                                             0x235f
8747 #define mmDP2_DP_GSP9_CNTL_BASE_IDX                                                                    2
8748 #define mmDP2_DP_GSP10_CNTL                                                                            0x2360
8749 #define mmDP2_DP_GSP10_CNTL_BASE_IDX                                                                   2
8750 #define mmDP2_DP_GSP11_CNTL                                                                            0x2361
8751 #define mmDP2_DP_GSP11_CNTL_BASE_IDX                                                                   2
8752 #define mmDP2_DP_GSP_EN_DB_STATUS                                                                      0x2362
8753 #define mmDP2_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
8754 
8755 
8756 // addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
8757 // base address: 0x160a0
8758 #define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2368
8759 #define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
8760 #define mmVPG3_VPG_GENERIC_PACKET_DATA                                                                 0x2369
8761 #define mmVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
8762 #define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x236a
8763 #define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
8764 #define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x236b
8765 #define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
8766 #define mmVPG3_VPG_GENERIC_STATUS                                                                      0x236c
8767 #define mmVPG3_VPG_GENERIC_STATUS_BASE_IDX                                                             2
8768 #define mmVPG3_VPG_MEM_PWR                                                                             0x236d
8769 #define mmVPG3_VPG_MEM_PWR_BASE_IDX                                                                    2
8770 #define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x236e
8771 #define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
8772 #define mmVPG3_VPG_ISRC1_2_DATA                                                                        0x236f
8773 #define mmVPG3_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
8774 #define mmVPG3_VPG_MPEG_INFO0                                                                          0x2370
8775 #define mmVPG3_VPG_MPEG_INFO0_BASE_IDX                                                                 2
8776 #define mmVPG3_VPG_MPEG_INFO1                                                                          0x2371
8777 #define mmVPG3_VPG_MPEG_INFO1_BASE_IDX                                                                 2
8778 
8779 
8780 // addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
8781 // base address: 0x160cc
8782 #define mmAFMT3_AFMT_VBI_PACKET_CONTROL                                                                0x2374
8783 #define mmAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
8784 #define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2375
8785 #define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
8786 #define mmAFMT3_AFMT_AUDIO_INFO0                                                                       0x2376
8787 #define mmAFMT3_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
8788 #define mmAFMT3_AFMT_AUDIO_INFO1                                                                       0x2377
8789 #define mmAFMT3_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
8790 #define mmAFMT3_AFMT_60958_0                                                                           0x2378
8791 #define mmAFMT3_AFMT_60958_0_BASE_IDX                                                                  2
8792 #define mmAFMT3_AFMT_60958_1                                                                           0x2379
8793 #define mmAFMT3_AFMT_60958_1_BASE_IDX                                                                  2
8794 #define mmAFMT3_AFMT_AUDIO_CRC_CONTROL                                                                 0x237a
8795 #define mmAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
8796 #define mmAFMT3_AFMT_RAMP_CONTROL0                                                                     0x237b
8797 #define mmAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
8798 #define mmAFMT3_AFMT_RAMP_CONTROL1                                                                     0x237c
8799 #define mmAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
8800 #define mmAFMT3_AFMT_RAMP_CONTROL2                                                                     0x237d
8801 #define mmAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
8802 #define mmAFMT3_AFMT_RAMP_CONTROL3                                                                     0x237e
8803 #define mmAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
8804 #define mmAFMT3_AFMT_60958_2                                                                           0x237f
8805 #define mmAFMT3_AFMT_60958_2_BASE_IDX                                                                  2
8806 #define mmAFMT3_AFMT_AUDIO_CRC_RESULT                                                                  0x2380
8807 #define mmAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
8808 #define mmAFMT3_AFMT_STATUS                                                                            0x2381
8809 #define mmAFMT3_AFMT_STATUS_BASE_IDX                                                                   2
8810 #define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL                                                              0x2382
8811 #define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
8812 #define mmAFMT3_AFMT_INFOFRAME_CONTROL0                                                                0x2383
8813 #define mmAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
8814 #define mmAFMT3_AFMT_INTERRUPT_STATUS                                                                  0x2384
8815 #define mmAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
8816 #define mmAFMT3_AFMT_AUDIO_SRC_CONTROL                                                                 0x2385
8817 #define mmAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
8818 #define mmAFMT3_AFMT_MEM_PWR                                                                           0x2387
8819 #define mmAFMT3_AFMT_MEM_PWR_BASE_IDX                                                                  2
8820 
8821 
8822 // addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
8823 // base address: 0x16124
8824 #define mmDME3_DME_CONTROL                                                                             0x2389
8825 #define mmDME3_DME_CONTROL_BASE_IDX                                                                    2
8826 #define mmDME3_DME_MEMORY_CONTROL                                                                      0x238a
8827 #define mmDME3_DME_MEMORY_CONTROL_BASE_IDX                                                             2
8828 
8829 
8830 // addressBlock: dce_dc_dio_dig3_dispdec
8831 // base address: 0xc00
8832 #define mmDIG3_DIG_FE_CNTL                                                                             0x238b
8833 #define mmDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
8834 #define mmDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x238c
8835 #define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
8836 #define mmDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x238d
8837 #define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
8838 #define mmDIG3_DIG_CLOCK_PATTERN                                                                       0x238e
8839 #define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
8840 #define mmDIG3_DIG_TEST_PATTERN                                                                        0x238f
8841 #define mmDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
8842 #define mmDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x2390
8843 #define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
8844 #define mmDIG3_DIG_FIFO_STATUS                                                                         0x2391
8845 #define mmDIG3_DIG_FIFO_STATUS_BASE_IDX                                                                2
8846 #define mmDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x2392
8847 #define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
8848 #define mmDIG3_HDMI_CONTROL                                                                            0x2393
8849 #define mmDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
8850 #define mmDIG3_HDMI_STATUS                                                                             0x2394
8851 #define mmDIG3_HDMI_STATUS_BASE_IDX                                                                    2
8852 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x2395
8853 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
8854 #define mmDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x2396
8855 #define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
8856 #define mmDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x2397
8857 #define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
8858 #define mmDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x2398
8859 #define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
8860 #define mmDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x2399
8861 #define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
8862 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x239a
8863 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
8864 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6                                                            0x239b
8865 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
8866 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x239c
8867 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
8868 #define mmDIG3_HDMI_GC                                                                                 0x239d
8869 #define mmDIG3_HDMI_GC_BASE_IDX                                                                        2
8870 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x239e
8871 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
8872 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x239f
8873 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
8874 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x23a0
8875 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
8876 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x23a1
8877 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
8878 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7                                                            0x23a2
8879 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
8880 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8                                                            0x23a3
8881 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
8882 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9                                                            0x23a4
8883 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
8884 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10                                                           0x23a5
8885 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
8886 #define mmDIG3_HDMI_DB_CONTROL                                                                         0x23a6
8887 #define mmDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2
8888 #define mmDIG3_HDMI_ACR_32_0                                                                           0x23a7
8889 #define mmDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
8890 #define mmDIG3_HDMI_ACR_32_1                                                                           0x23a8
8891 #define mmDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
8892 #define mmDIG3_HDMI_ACR_44_0                                                                           0x23a9
8893 #define mmDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
8894 #define mmDIG3_HDMI_ACR_44_1                                                                           0x23aa
8895 #define mmDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
8896 #define mmDIG3_HDMI_ACR_48_0                                                                           0x23ab
8897 #define mmDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
8898 #define mmDIG3_HDMI_ACR_48_1                                                                           0x23ac
8899 #define mmDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
8900 #define mmDIG3_HDMI_ACR_STATUS_0                                                                       0x23ad
8901 #define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
8902 #define mmDIG3_HDMI_ACR_STATUS_1                                                                       0x23ae
8903 #define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
8904 #define mmDIG3_AFMT_CNTL                                                                               0x23af
8905 #define mmDIG3_AFMT_CNTL_BASE_IDX                                                                      2
8906 #define mmDIG3_DIG_BE_CNTL                                                                             0x23b0
8907 #define mmDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
8908 #define mmDIG3_DIG_BE_EN_CNTL                                                                          0x23b1
8909 #define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
8910 #define mmDIG3_TMDS_CNTL                                                                               0x23d7
8911 #define mmDIG3_TMDS_CNTL_BASE_IDX                                                                      2
8912 #define mmDIG3_TMDS_CONTROL_CHAR                                                                       0x23d8
8913 #define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
8914 #define mmDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x23d9
8915 #define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
8916 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x23da
8917 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
8918 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x23db
8919 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
8920 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x23dc
8921 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
8922 #define mmDIG3_TMDS_CTL_BITS                                                                           0x23de
8923 #define mmDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
8924 #define mmDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x23df
8925 #define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
8926 #define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x23e0
8927 #define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
8928 #define mmDIG3_DIG_VERSION                                                                             0x23e4
8929 #define mmDIG3_DIG_VERSION_BASE_IDX                                                                    2
8930 #define mmDIG3_DIG_LANE_ENABLE                                                                         0x23e5
8931 #define mmDIG3_DIG_LANE_ENABLE_BASE_IDX                                                                2
8932 #define mmDIG3_FORCE_DIG_DISABLE                                                                       0x23e6
8933 #define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX                                                              2
8934 
8935 
8936 // addressBlock: dce_dc_dio_dp3_dispdec
8937 // base address: 0xc00
8938 #define mmDP3_DP_LINK_CNTL                                                                             0x2408
8939 #define mmDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
8940 #define mmDP3_DP_PIXEL_FORMAT                                                                          0x2409
8941 #define mmDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
8942 #define mmDP3_DP_MSA_COLORIMETRY                                                                       0x240a
8943 #define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
8944 #define mmDP3_DP_CONFIG                                                                                0x240b
8945 #define mmDP3_DP_CONFIG_BASE_IDX                                                                       2
8946 #define mmDP3_DP_VID_STREAM_CNTL                                                                       0x240c
8947 #define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
8948 #define mmDP3_DP_STEER_FIFO                                                                            0x240d
8949 #define mmDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
8950 #define mmDP3_DP_MSA_MISC                                                                              0x240e
8951 #define mmDP3_DP_MSA_MISC_BASE_IDX                                                                     2
8952 #define mmDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x240f
8953 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
8954 #define mmDP3_DP_VID_TIMING                                                                            0x2410
8955 #define mmDP3_DP_VID_TIMING_BASE_IDX                                                                   2
8956 #define mmDP3_DP_VID_N                                                                                 0x2411
8957 #define mmDP3_DP_VID_N_BASE_IDX                                                                        2
8958 #define mmDP3_DP_VID_M                                                                                 0x2412
8959 #define mmDP3_DP_VID_M_BASE_IDX                                                                        2
8960 #define mmDP3_DP_LINK_FRAMING_CNTL                                                                     0x2413
8961 #define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
8962 #define mmDP3_DP_HBR2_EYE_PATTERN                                                                      0x2414
8963 #define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
8964 #define mmDP3_DP_VID_MSA_VBID                                                                          0x2415
8965 #define mmDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
8966 #define mmDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2416
8967 #define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
8968 #define mmDP3_DP_DPHY_CNTL                                                                             0x2417
8969 #define mmDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
8970 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2418
8971 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
8972 #define mmDP3_DP_DPHY_SYM0                                                                             0x2419
8973 #define mmDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
8974 #define mmDP3_DP_DPHY_SYM1                                                                             0x241a
8975 #define mmDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
8976 #define mmDP3_DP_DPHY_SYM2                                                                             0x241b
8977 #define mmDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
8978 #define mmDP3_DP_DPHY_8B10B_CNTL                                                                       0x241c
8979 #define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
8980 #define mmDP3_DP_DPHY_PRBS_CNTL                                                                        0x241d
8981 #define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
8982 #define mmDP3_DP_DPHY_SCRAM_CNTL                                                                       0x241e
8983 #define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
8984 #define mmDP3_DP_DPHY_CRC_EN                                                                           0x241f
8985 #define mmDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
8986 #define mmDP3_DP_DPHY_CRC_CNTL                                                                         0x2420
8987 #define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
8988 #define mmDP3_DP_DPHY_CRC_RESULT                                                                       0x2421
8989 #define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
8990 #define mmDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x2422
8991 #define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
8992 #define mmDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x2423
8993 #define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
8994 #define mmDP3_DP_DPHY_FAST_TRAINING                                                                    0x2424
8995 #define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
8996 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2425
8997 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
8998 #define mmDP3_DP_SEC_CNTL                                                                              0x242b
8999 #define mmDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
9000 #define mmDP3_DP_SEC_CNTL1                                                                             0x242c
9001 #define mmDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
9002 #define mmDP3_DP_SEC_FRAMING1                                                                          0x242d
9003 #define mmDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
9004 #define mmDP3_DP_SEC_FRAMING2                                                                          0x242e
9005 #define mmDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
9006 #define mmDP3_DP_SEC_FRAMING3                                                                          0x242f
9007 #define mmDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
9008 #define mmDP3_DP_SEC_FRAMING4                                                                          0x2430
9009 #define mmDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
9010 #define mmDP3_DP_SEC_AUD_N                                                                             0x2431
9011 #define mmDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
9012 #define mmDP3_DP_SEC_AUD_N_READBACK                                                                    0x2432
9013 #define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
9014 #define mmDP3_DP_SEC_AUD_M                                                                             0x2433
9015 #define mmDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
9016 #define mmDP3_DP_SEC_AUD_M_READBACK                                                                    0x2434
9017 #define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
9018 #define mmDP3_DP_SEC_TIMESTAMP                                                                         0x2435
9019 #define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
9020 #define mmDP3_DP_SEC_PACKET_CNTL                                                                       0x2436
9021 #define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
9022 #define mmDP3_DP_MSE_RATE_CNTL                                                                         0x2437
9023 #define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
9024 #define mmDP3_DP_MSE_RATE_UPDATE                                                                       0x2439
9025 #define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
9026 #define mmDP3_DP_MSE_SAT0                                                                              0x243a
9027 #define mmDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
9028 #define mmDP3_DP_MSE_SAT1                                                                              0x243b
9029 #define mmDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
9030 #define mmDP3_DP_MSE_SAT2                                                                              0x243c
9031 #define mmDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
9032 #define mmDP3_DP_MSE_SAT_UPDATE                                                                        0x243d
9033 #define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
9034 #define mmDP3_DP_MSE_LINK_TIMING                                                                       0x243e
9035 #define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
9036 #define mmDP3_DP_MSE_MISC_CNTL                                                                         0x243f
9037 #define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
9038 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2444
9039 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
9040 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2445
9041 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
9042 #define mmDP3_DP_MSE_SAT0_STATUS                                                                       0x2447
9043 #define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
9044 #define mmDP3_DP_MSE_SAT1_STATUS                                                                       0x2448
9045 #define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
9046 #define mmDP3_DP_MSE_SAT2_STATUS                                                                       0x2449
9047 #define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
9048 #define mmDP3_DP_MSA_TIMING_PARAM1                                                                     0x244c
9049 #define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
9050 #define mmDP3_DP_MSA_TIMING_PARAM2                                                                     0x244d
9051 #define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
9052 #define mmDP3_DP_MSA_TIMING_PARAM3                                                                     0x244e
9053 #define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
9054 #define mmDP3_DP_MSA_TIMING_PARAM4                                                                     0x244f
9055 #define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
9056 #define mmDP3_DP_MSO_CNTL                                                                              0x2450
9057 #define mmDP3_DP_MSO_CNTL_BASE_IDX                                                                     2
9058 #define mmDP3_DP_MSO_CNTL1                                                                             0x2451
9059 #define mmDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2
9060 #define mmDP3_DP_DSC_CNTL                                                                              0x2452
9061 #define mmDP3_DP_DSC_CNTL_BASE_IDX                                                                     2
9062 #define mmDP3_DP_SEC_CNTL2                                                                             0x2453
9063 #define mmDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2
9064 #define mmDP3_DP_SEC_CNTL3                                                                             0x2454
9065 #define mmDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2
9066 #define mmDP3_DP_SEC_CNTL4                                                                             0x2455
9067 #define mmDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2
9068 #define mmDP3_DP_SEC_CNTL5                                                                             0x2456
9069 #define mmDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
9070 #define mmDP3_DP_SEC_CNTL6                                                                             0x2457
9071 #define mmDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2
9072 #define mmDP3_DP_SEC_CNTL7                                                                             0x2458
9073 #define mmDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2
9074 #define mmDP3_DP_DB_CNTL                                                                               0x2459
9075 #define mmDP3_DP_DB_CNTL_BASE_IDX                                                                      2
9076 #define mmDP3_DP_MSA_VBID_MISC                                                                         0x245a
9077 #define mmDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2
9078 #define mmDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x245b
9079 #define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
9080 #define mmDP3_DP_DSC_BYTES_PER_PIXEL                                                                   0x245c
9081 #define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
9082 #define mmDP3_DP_ALPM_CNTL                                                                             0x245d
9083 #define mmDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2
9084 #define mmDP3_DP_GSP8_CNTL                                                                             0x245e
9085 #define mmDP3_DP_GSP8_CNTL_BASE_IDX                                                                    2
9086 #define mmDP3_DP_GSP9_CNTL                                                                             0x245f
9087 #define mmDP3_DP_GSP9_CNTL_BASE_IDX                                                                    2
9088 #define mmDP3_DP_GSP10_CNTL                                                                            0x2460
9089 #define mmDP3_DP_GSP10_CNTL_BASE_IDX                                                                   2
9090 #define mmDP3_DP_GSP11_CNTL                                                                            0x2461
9091 #define mmDP3_DP_GSP11_CNTL_BASE_IDX                                                                   2
9092 #define mmDP3_DP_GSP_EN_DB_STATUS                                                                      0x2462
9093 #define mmDP3_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
9094 
9095 
9096 // addressBlock: dce_dc_dcio_dcio_dispdec
9097 // base address: 0x0
9098 #define mmDC_GENERICA                                                                                  0x2868
9099 #define mmDC_GENERICA_BASE_IDX                                                                         2
9100 #define mmDC_GENERICB                                                                                  0x2869
9101 #define mmDC_GENERICB_BASE_IDX                                                                         2
9102 #define mmDCIO_CLOCK_CNTL                                                                              0x286a
9103 #define mmDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
9104 #define mmDC_REF_CLK_CNTL                                                                              0x286b
9105 #define mmDC_REF_CLK_CNTL_BASE_IDX                                                                     2
9106 #define mmUNIPHYA_LINK_CNTL                                                                            0x286d
9107 #define mmUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
9108 #define mmUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
9109 #define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
9110 #define mmUNIPHYB_LINK_CNTL                                                                            0x286f
9111 #define mmUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
9112 #define mmUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
9113 #define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
9114 #define mmUNIPHYC_LINK_CNTL                                                                            0x2871
9115 #define mmUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
9116 #define mmUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
9117 #define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
9118 #define mmUNIPHYD_LINK_CNTL                                                                            0x2873
9119 #define mmUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
9120 #define mmUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
9121 #define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
9122 #define mmDCIO_WRCMD_DELAY                                                                             0x287e
9123 #define mmDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
9124 #define mmDC_PINSTRAPS                                                                                 0x2880
9125 #define mmDC_PINSTRAPS_BASE_IDX                                                                        2
9126 #define mmPANEL_PWRSEQ0_CNTL                                                                           0x2883
9127 #define mmPANEL_PWRSEQ0_CNTL_BASE_IDX                                                                  2
9128 #define mmPANEL_PWRSEQ0_STATE                                                                          0x2884
9129 #define mmPANEL_PWRSEQ0_STATE_BASE_IDX                                                                 2
9130 #define mmPANEL_PWRSEQ0_REF_DIV                                                                        0x2885
9131 #define mmPANEL_PWRSEQ0_REF_DIV_BASE_IDX                                                               2
9132 #define mmPANEL_PWRSEQ0_DELAY1                                                                         0x2886
9133 #define mmPANEL_PWRSEQ0_DELAY1_BASE_IDX                                                                2
9134 #define mmPANEL_PWRSEQ0_DELAY2                                                                         0x2887
9135 #define mmPANEL_PWRSEQ0_DELAY2_BASE_IDX                                                                2
9136 #define mmBL_PWM0_CNTL                                                                                 0x2888
9137 #define mmBL_PWM0_CNTL_BASE_IDX                                                                        2
9138 #define mmBL_PWM0_CNTL2                                                                                0x2889
9139 #define mmBL_PWM0_CNTL2_BASE_IDX                                                                       2
9140 #define mmBL_PWM0_PERIOD_CNTL                                                                          0x288a
9141 #define mmBL_PWM0_PERIOD_CNTL_BASE_IDX                                                                 2
9142 #define mmBL_PWM0_GRP1_REG_LOCK                                                                        0x288b
9143 #define mmBL_PWM0_GRP1_REG_LOCK_BASE_IDX                                                               2
9144 #define mmDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
9145 #define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
9146 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
9147 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
9148 #define mmDCIO_SOFT_RESET                                                                              0x289e
9149 #define mmDCIO_SOFT_RESET_BASE_IDX                                                                     2
9150 #define mmPANEL_PWRSEQ1_CNTL                                                                           0x28a6
9151 #define mmPANEL_PWRSEQ1_CNTL_BASE_IDX                                                                  2
9152 #define mmPANEL_PWRSEQ1_STATE                                                                          0x28a7
9153 #define mmPANEL_PWRSEQ1_STATE_BASE_IDX                                                                 2
9154 #define mmPANEL_PWRSEQ1_REF_DIV                                                                        0x28a8
9155 #define mmPANEL_PWRSEQ1_REF_DIV_BASE_IDX                                                               2
9156 #define mmPANEL_PWRSEQ1_DELAY1                                                                         0x28a9
9157 #define mmPANEL_PWRSEQ1_DELAY1_BASE_IDX                                                                2
9158 #define mmPANEL_PWRSEQ1_DELAY2                                                                         0x28aa
9159 #define mmPANEL_PWRSEQ1_DELAY2_BASE_IDX                                                                2
9160 #define mmBL_PWM1_CNTL                                                                                 0x28ab
9161 #define mmBL_PWM1_CNTL_BASE_IDX                                                                        2
9162 #define mmBL_PWM1_CNTL2                                                                                0x28ac
9163 #define mmBL_PWM1_CNTL2_BASE_IDX                                                                       2
9164 #define mmBL_PWM1_PERIOD_CNTL                                                                          0x28ad
9165 #define mmBL_PWM1_PERIOD_CNTL_BASE_IDX                                                                 2
9166 #define mmBL_PWM1_GRP1_REG_LOCK                                                                        0x28ae
9167 #define mmBL_PWM1_GRP1_REG_LOCK_BASE_IDX                                                               2
9168 
9169 
9170 // addressBlock: dce_dc_dcio_dcio_chip_dispdec
9171 // base address: 0x0
9172 #define mmDC_GPIO_GENERIC_MASK                                                                         0x28c8
9173 #define mmDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
9174 #define mmDC_GPIO_GENERIC_A                                                                            0x28c9
9175 #define mmDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
9176 #define mmDC_GPIO_GENERIC_EN                                                                           0x28ca
9177 #define mmDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
9178 #define mmDC_GPIO_GENERIC_Y                                                                            0x28cb
9179 #define mmDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
9180 #define mmDC_GPIO_DDC1_MASK                                                                            0x28d0
9181 #define mmDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
9182 #define mmDC_GPIO_DDC1_A                                                                               0x28d1
9183 #define mmDC_GPIO_DDC1_A_BASE_IDX                                                                      2
9184 #define mmDC_GPIO_DDC1_EN                                                                              0x28d2
9185 #define mmDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
9186 #define mmDC_GPIO_DDC1_Y                                                                               0x28d3
9187 #define mmDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
9188 #define mmDC_GPIO_DDC2_MASK                                                                            0x28d4
9189 #define mmDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
9190 #define mmDC_GPIO_DDC2_A                                                                               0x28d5
9191 #define mmDC_GPIO_DDC2_A_BASE_IDX                                                                      2
9192 #define mmDC_GPIO_DDC2_EN                                                                              0x28d6
9193 #define mmDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
9194 #define mmDC_GPIO_DDC2_Y                                                                               0x28d7
9195 #define mmDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
9196 #define mmDC_GPIO_DDC3_MASK                                                                            0x28d8
9197 #define mmDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
9198 #define mmDC_GPIO_DDC3_A                                                                               0x28d9
9199 #define mmDC_GPIO_DDC3_A_BASE_IDX                                                                      2
9200 #define mmDC_GPIO_DDC3_EN                                                                              0x28da
9201 #define mmDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
9202 #define mmDC_GPIO_DDC3_Y                                                                               0x28db
9203 #define mmDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
9204 #define mmDC_GPIO_DDC4_MASK                                                                            0x28dc
9205 #define mmDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
9206 #define mmDC_GPIO_DDC4_A                                                                               0x28dd
9207 #define mmDC_GPIO_DDC4_A_BASE_IDX                                                                      2
9208 #define mmDC_GPIO_DDC4_EN                                                                              0x28de
9209 #define mmDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
9210 #define mmDC_GPIO_DDC4_Y                                                                               0x28df
9211 #define mmDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
9212 #define mmDC_GPIO_DDCVGA_MASK                                                                          0x28e8
9213 #define mmDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
9214 #define mmDC_GPIO_DDCVGA_A                                                                             0x28e9
9215 #define mmDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
9216 #define mmDC_GPIO_DDCVGA_EN                                                                            0x28ea
9217 #define mmDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
9218 #define mmDC_GPIO_DDCVGA_Y                                                                             0x28eb
9219 #define mmDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
9220 #define mmDC_GPIO_GENLK_MASK                                                                           0x28f0
9221 #define mmDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
9222 #define mmDC_GPIO_GENLK_A                                                                              0x28f1
9223 #define mmDC_GPIO_GENLK_A_BASE_IDX                                                                     2
9224 #define mmDC_GPIO_GENLK_EN                                                                             0x28f2
9225 #define mmDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
9226 #define mmDC_GPIO_GENLK_Y                                                                              0x28f3
9227 #define mmDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
9228 #define mmDC_GPIO_HPD_MASK                                                                             0x28f4
9229 #define mmDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
9230 #define mmDC_GPIO_HPD_A                                                                                0x28f5
9231 #define mmDC_GPIO_HPD_A_BASE_IDX                                                                       2
9232 #define mmDC_GPIO_HPD_EN                                                                               0x28f6
9233 #define mmDC_GPIO_HPD_EN_BASE_IDX                                                                      2
9234 #define mmDC_GPIO_HPD_Y                                                                                0x28f7
9235 #define mmDC_GPIO_HPD_Y_BASE_IDX                                                                       2
9236 #define mmDC_GPIO_PWRSEQ0_MASK                                                                         0x28f8
9237 #define mmDC_GPIO_PWRSEQ0_MASK_BASE_IDX                                                                2
9238 #define mmDC_GPIO_PWRSEQ0_A                                                                            0x28f9
9239 #define mmDC_GPIO_PWRSEQ0_A_BASE_IDX                                                                   2
9240 #define mmDC_GPIO_PWRSEQ0_EN                                                                           0x28fa
9241 #define mmDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2
9242 #define mmDC_GPIO_PWRSEQ0_Y                                                                            0x28fb
9243 #define mmDC_GPIO_PWRSEQ0_Y_BASE_IDX                                                                   2
9244 #define mmDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
9245 #define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
9246 #define mmDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
9247 #define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
9248 #define mmPHY_AUX_CNTL                                                                                 0x28ff
9249 #define mmPHY_AUX_CNTL_BASE_IDX                                                                        2
9250 #define mmDC_GPIO_PWRSEQ1_MASK                                                                         0x2900
9251 #define mmDC_GPIO_PWRSEQ1_MASK_BASE_IDX                                                                2
9252 #define mmDC_GPIO_PWRSEQ1_A                                                                            0x2901
9253 #define mmDC_GPIO_PWRSEQ1_A_BASE_IDX                                                                   2
9254 #define mmDC_GPIO_PWRSEQ1_EN                                                                           0x2902
9255 #define mmDC_GPIO_PWRSEQ1_EN_BASE_IDX                                                                  2
9256 #define mmDC_GPIO_PWRSEQ1_Y                                                                            0x2903
9257 #define mmDC_GPIO_PWRSEQ1_Y_BASE_IDX                                                                   2
9258 #define mmDC_GPIO_TX12_EN                                                                              0x2915
9259 #define mmDC_GPIO_TX12_EN_BASE_IDX                                                                     2
9260 #define mmDC_GPIO_AUX_CTRL_0                                                                           0x2916
9261 #define mmDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
9262 #define mmDC_GPIO_AUX_CTRL_1                                                                           0x2917
9263 #define mmDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
9264 #define mmDC_GPIO_AUX_CTRL_2                                                                           0x2918
9265 #define mmDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
9266 #define mmDC_GPIO_RXEN                                                                                 0x2919
9267 #define mmDC_GPIO_RXEN_BASE_IDX                                                                        2
9268 #define mmDC_GPIO_PULLUPEN                                                                             0x291a
9269 #define mmDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
9270 #define mmDC_GPIO_AUX_CTRL_3                                                                           0x291b
9271 #define mmDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
9272 #define mmDC_GPIO_AUX_CTRL_4                                                                           0x291c
9273 #define mmDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
9274 #define mmDC_GPIO_AUX_CTRL_5                                                                           0x291d
9275 #define mmDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
9276 #define mmAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
9277 #define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
9278 
9279 
9280 // addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
9281 // base address: 0x360
9282 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00
9283 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
9284 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01
9285 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
9286 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02
9287 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
9288 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03
9289 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
9290 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04
9291 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
9292 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05
9293 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
9294 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06
9295 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
9296 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07
9297 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
9298 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08
9299 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
9300 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09
9301 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
9302 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a
9303 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
9304 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b
9305 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
9306 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c
9307 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
9308 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d
9309 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
9310 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e
9311 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
9312 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f
9313 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
9314 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10
9315 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
9316 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11
9317 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
9318 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12
9319 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
9320 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13
9321 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
9322 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14
9323 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
9324 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15
9325 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
9326 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16
9327 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
9328 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17
9329 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
9330 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18
9331 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
9332 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19
9333 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
9334 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a
9335 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
9336 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b
9337 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
9338 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c
9339 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
9340 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d
9341 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
9342 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e
9343 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
9344 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f
9345 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
9346 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20
9347 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
9348 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21
9349 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
9350 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22
9351 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
9352 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23
9353 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
9354 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24
9355 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
9356 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25
9357 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
9358 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26
9359 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
9360 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27
9361 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
9362 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28
9363 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
9364 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29
9365 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
9366 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a
9367 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
9368 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b
9369 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
9370 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c
9371 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
9372 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d
9373 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
9374 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e
9375 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
9376 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f
9377 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
9378 
9379 
9380 // addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
9381 // base address: 0x6c0
9382 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8
9383 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
9384 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9
9385 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
9386 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada
9387 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
9388 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb
9389 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
9390 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc
9391 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
9392 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add
9393 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
9394 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade
9395 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
9396 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf
9397 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
9398 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0
9399 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
9400 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1
9401 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
9402 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2
9403 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
9404 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3
9405 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
9406 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4
9407 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
9408 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5
9409 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
9410 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6
9411 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
9412 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7
9413 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
9414 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8
9415 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
9416 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9
9417 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
9418 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea
9419 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
9420 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb
9421 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
9422 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec
9423 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
9424 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed
9425 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
9426 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee
9427 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
9428 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef
9429 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
9430 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0
9431 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
9432 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1
9433 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
9434 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2
9435 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
9436 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3
9437 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
9438 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4
9439 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
9440 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5
9441 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
9442 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6
9443 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
9444 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7
9445 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
9446 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8
9447 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
9448 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9
9449 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
9450 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa
9451 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
9452 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb
9453 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
9454 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc
9455 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
9456 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd
9457 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
9458 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe
9459 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
9460 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff
9461 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
9462 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00
9463 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
9464 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01
9465 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
9466 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02
9467 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
9468 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03
9469 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
9470 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04
9471 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
9472 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05
9473 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
9474 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06
9475 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
9476 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07
9477 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
9478 
9479 
9480 // addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
9481 // base address: 0xa20
9482 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0
9483 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
9484 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1
9485 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
9486 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2
9487 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
9488 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3
9489 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
9490 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4
9491 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
9492 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5
9493 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
9494 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6
9495 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
9496 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7
9497 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
9498 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8
9499 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
9500 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9
9501 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
9502 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba
9503 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
9504 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb
9505 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
9506 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc
9507 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
9508 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd
9509 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
9510 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe
9511 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
9512 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf
9513 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
9514 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0
9515 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
9516 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1
9517 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
9518 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2
9519 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
9520 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3
9521 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
9522 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4
9523 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
9524 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5
9525 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
9526 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6
9527 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
9528 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7
9529 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
9530 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8
9531 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
9532 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9
9533 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
9534 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca
9535 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
9536 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb
9537 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
9538 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc
9539 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
9540 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd
9541 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
9542 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce
9543 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
9544 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf
9545 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
9546 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0
9547 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
9548 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1
9549 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
9550 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2
9551 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
9552 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3
9553 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
9554 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4
9555 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
9556 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5
9557 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
9558 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6
9559 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
9560 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7
9561 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
9562 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8
9563 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
9564 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9
9565 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
9566 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda
9567 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
9568 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb
9569 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
9570 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc
9571 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
9572 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd
9573 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
9574 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde
9575 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
9576 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf
9577 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
9578 
9579 
9580 // addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
9581 // base address: 0x0
9582 #define mmDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
9583 #define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
9584 #define mmDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
9585 #define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
9586 
9587 
9588 // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
9589 // base address: 0x0
9590 #define mmDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
9591 #define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
9592 #define mmDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
9593 #define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2
9594 
9595 
9596 // addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
9597 // base address: 0x0
9598 #define mmDSCC0_DSCC_CONFIG0                                                                           0x300a
9599 #define mmDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
9600 #define mmDSCC0_DSCC_CONFIG1                                                                           0x300b
9601 #define mmDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
9602 #define mmDSCC0_DSCC_STATUS                                                                            0x300c
9603 #define mmDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
9604 #define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
9605 #define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
9606 #define mmDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
9607 #define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
9608 #define mmDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
9609 #define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
9610 #define mmDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
9611 #define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
9612 #define mmDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
9613 #define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
9614 #define mmDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
9615 #define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
9616 #define mmDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
9617 #define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
9618 #define mmDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
9619 #define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
9620 #define mmDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
9621 #define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
9622 #define mmDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
9623 #define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
9624 #define mmDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
9625 #define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
9626 #define mmDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
9627 #define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
9628 #define mmDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
9629 #define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
9630 #define mmDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
9631 #define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
9632 #define mmDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
9633 #define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
9634 #define mmDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
9635 #define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
9636 #define mmDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
9637 #define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
9638 #define mmDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
9639 #define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
9640 #define mmDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
9641 #define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
9642 #define mmDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
9643 #define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
9644 #define mmDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
9645 #define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
9646 #define mmDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
9647 #define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
9648 #define mmDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
9649 #define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
9650 #define mmDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
9651 #define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
9652 #define mmDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
9653 #define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
9654 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
9655 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
9656 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
9657 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
9658 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
9659 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
9660 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
9661 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
9662 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
9663 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
9664 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
9665 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
9666 #define mmDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
9667 #define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
9668 #define mmDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
9669 #define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
9670 #define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
9671 #define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
9672 #define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
9673 #define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
9674 #define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
9675 #define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
9676 #define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
9677 #define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
9678 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
9679 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
9680 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
9681 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
9682 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
9683 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
9684 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
9685 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
9686 #define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a
9687 #define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
9688 
9689 
9690 // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
9691 // base address: 0xc140
9692 #define mmDC_PERFMON17_PERFCOUNTER_CNTL                                                                0x3050
9693 #define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX                                                       2
9694 #define mmDC_PERFMON17_PERFCOUNTER_CNTL2                                                               0x3051
9695 #define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
9696 #define mmDC_PERFMON17_PERFCOUNTER_STATE                                                               0x3052
9697 #define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX                                                      2
9698 #define mmDC_PERFMON17_PERFMON_CNTL                                                                    0x3053
9699 #define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX                                                           2
9700 #define mmDC_PERFMON17_PERFMON_CNTL2                                                                   0x3054
9701 #define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX                                                          2
9702 #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC                                                         0x3055
9703 #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
9704 #define mmDC_PERFMON17_PERFMON_CVALUE_LOW                                                              0x3056
9705 #define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
9706 #define mmDC_PERFMON17_PERFMON_HI                                                                      0x3057
9707 #define mmDC_PERFMON17_PERFMON_HI_BASE_IDX                                                             2
9708 #define mmDC_PERFMON17_PERFMON_LOW                                                                     0x3058
9709 #define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX                                                            2
9710 
9711 
9712 // addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
9713 // base address: 0x170
9714 #define mmDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
9715 #define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
9716 #define mmDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
9717 #define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
9718 
9719 
9720 // addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
9721 // base address: 0x170
9722 #define mmDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
9723 #define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
9724 #define mmDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
9725 #define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2
9726 
9727 
9728 // addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
9729 // base address: 0x170
9730 #define mmDSCC1_DSCC_CONFIG0                                                                           0x3066
9731 #define mmDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
9732 #define mmDSCC1_DSCC_CONFIG1                                                                           0x3067
9733 #define mmDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
9734 #define mmDSCC1_DSCC_STATUS                                                                            0x3068
9735 #define mmDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
9736 #define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
9737 #define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
9738 #define mmDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
9739 #define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
9740 #define mmDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
9741 #define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
9742 #define mmDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
9743 #define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
9744 #define mmDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
9745 #define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
9746 #define mmDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
9747 #define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
9748 #define mmDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
9749 #define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
9750 #define mmDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
9751 #define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
9752 #define mmDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
9753 #define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
9754 #define mmDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
9755 #define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
9756 #define mmDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
9757 #define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
9758 #define mmDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
9759 #define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
9760 #define mmDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
9761 #define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
9762 #define mmDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
9763 #define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
9764 #define mmDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
9765 #define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
9766 #define mmDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
9767 #define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
9768 #define mmDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
9769 #define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
9770 #define mmDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
9771 #define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
9772 #define mmDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
9773 #define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
9774 #define mmDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
9775 #define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
9776 #define mmDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
9777 #define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
9778 #define mmDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
9779 #define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
9780 #define mmDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
9781 #define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
9782 #define mmDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
9783 #define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
9784 #define mmDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
9785 #define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
9786 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
9787 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
9788 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
9789 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
9790 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
9791 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
9792 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
9793 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
9794 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
9795 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
9796 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
9797 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
9798 #define mmDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
9799 #define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
9800 #define mmDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
9801 #define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
9802 #define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
9803 #define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
9804 #define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
9805 #define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
9806 #define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
9807 #define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
9808 #define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
9809 #define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
9810 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
9811 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
9812 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
9813 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
9814 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
9815 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
9816 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
9817 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
9818 #define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096
9819 #define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
9820 
9821 
9822 // addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
9823 // base address: 0xc2b0
9824 #define mmDC_PERFMON18_PERFCOUNTER_CNTL                                                                0x30ac
9825 #define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX                                                       2
9826 #define mmDC_PERFMON18_PERFCOUNTER_CNTL2                                                               0x30ad
9827 #define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
9828 #define mmDC_PERFMON18_PERFCOUNTER_STATE                                                               0x30ae
9829 #define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX                                                      2
9830 #define mmDC_PERFMON18_PERFMON_CNTL                                                                    0x30af
9831 #define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX                                                           2
9832 #define mmDC_PERFMON18_PERFMON_CNTL2                                                                   0x30b0
9833 #define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX                                                          2
9834 #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC                                                         0x30b1
9835 #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
9836 #define mmDC_PERFMON18_PERFMON_CVALUE_LOW                                                              0x30b2
9837 #define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
9838 #define mmDC_PERFMON18_PERFMON_HI                                                                      0x30b3
9839 #define mmDC_PERFMON18_PERFMON_HI_BASE_IDX                                                             2
9840 #define mmDC_PERFMON18_PERFMON_LOW                                                                     0x30b4
9841 #define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX                                                            2
9842 
9843 
9844 // addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
9845 // base address: 0x2e0
9846 #define mmDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8
9847 #define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2
9848 #define mmDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9
9849 #define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
9850 
9851 
9852 // addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
9853 // base address: 0x2e0
9854 #define mmDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd
9855 #define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2
9856 #define mmDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be
9857 #define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2
9858 
9859 
9860 // addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
9861 // base address: 0x2e0
9862 #define mmDSCC2_DSCC_CONFIG0                                                                           0x30c2
9863 #define mmDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2
9864 #define mmDSCC2_DSCC_CONFIG1                                                                           0x30c3
9865 #define mmDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2
9866 #define mmDSCC2_DSCC_STATUS                                                                            0x30c4
9867 #define mmDSCC2_DSCC_STATUS_BASE_IDX                                                                   2
9868 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5
9869 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
9870 #define mmDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6
9871 #define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
9872 #define mmDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7
9873 #define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
9874 #define mmDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8
9875 #define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
9876 #define mmDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9
9877 #define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
9878 #define mmDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca
9879 #define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
9880 #define mmDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb
9881 #define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
9882 #define mmDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc
9883 #define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
9884 #define mmDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd
9885 #define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
9886 #define mmDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce
9887 #define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
9888 #define mmDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf
9889 #define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
9890 #define mmDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0
9891 #define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
9892 #define mmDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1
9893 #define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
9894 #define mmDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2
9895 #define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
9896 #define mmDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3
9897 #define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
9898 #define mmDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4
9899 #define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
9900 #define mmDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5
9901 #define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
9902 #define mmDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6
9903 #define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
9904 #define mmDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7
9905 #define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
9906 #define mmDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8
9907 #define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
9908 #define mmDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9
9909 #define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
9910 #define mmDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da
9911 #define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
9912 #define mmDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db
9913 #define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
9914 #define mmDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc
9915 #define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
9916 #define mmDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd
9917 #define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
9918 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de
9919 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
9920 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df
9921 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
9922 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0
9923 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
9924 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1
9925 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
9926 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2
9927 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
9928 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3
9929 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
9930 #define mmDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4
9931 #define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
9932 #define mmDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5
9933 #define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
9934 #define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6
9935 #define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
9936 #define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7
9937 #define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
9938 #define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8
9939 #define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
9940 #define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9
9941 #define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
9942 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea
9943 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
9944 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb
9945 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
9946 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec
9947 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
9948 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
9949 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
9950 #define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2
9951 #define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
9952 
9953 
9954 // addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
9955 // base address: 0xc420
9956 #define mmDC_PERFMON19_PERFCOUNTER_CNTL                                                                0x3108
9957 #define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX                                                       2
9958 #define mmDC_PERFMON19_PERFCOUNTER_CNTL2                                                               0x3109
9959 #define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
9960 #define mmDC_PERFMON19_PERFCOUNTER_STATE                                                               0x310a
9961 #define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX                                                      2
9962 #define mmDC_PERFMON19_PERFMON_CNTL                                                                    0x310b
9963 #define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX                                                           2
9964 #define mmDC_PERFMON19_PERFMON_CNTL2                                                                   0x310c
9965 #define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX                                                          2
9966 #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC                                                         0x310d
9967 #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
9968 #define mmDC_PERFMON19_PERFMON_CVALUE_LOW                                                              0x310e
9969 #define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
9970 #define mmDC_PERFMON19_PERFMON_HI                                                                      0x310f
9971 #define mmDC_PERFMON19_PERFMON_HI_BASE_IDX                                                             2
9972 #define mmDC_PERFMON19_PERFMON_LOW                                                                     0x3110
9973 #define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX                                                            2
9974 
9975 
9976 // addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
9977 // base address: 0x0
9978 #define mmDWB_ENABLE_CLK_CTRL                                                                          0x3228
9979 #define mmDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2
9980 #define mmDWB_MEM_PWR_CTRL                                                                             0x3229
9981 #define mmDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2
9982 #define mmFC_MODE_CTRL                                                                                 0x322a
9983 #define mmFC_MODE_CTRL_BASE_IDX                                                                        2
9984 #define mmFC_FLOW_CTRL                                                                                 0x322b
9985 #define mmFC_FLOW_CTRL_BASE_IDX                                                                        2
9986 #define mmFC_WINDOW_START                                                                              0x322c
9987 #define mmFC_WINDOW_START_BASE_IDX                                                                     2
9988 #define mmFC_WINDOW_SIZE                                                                               0x322d
9989 #define mmFC_WINDOW_SIZE_BASE_IDX                                                                      2
9990 #define mmFC_SOURCE_SIZE                                                                               0x322e
9991 #define mmFC_SOURCE_SIZE_BASE_IDX                                                                      2
9992 #define mmDWB_UPDATE_CTRL                                                                              0x322f
9993 #define mmDWB_UPDATE_CTRL_BASE_IDX                                                                     2
9994 #define mmDWB_CRC_CTRL                                                                                 0x3230
9995 #define mmDWB_CRC_CTRL_BASE_IDX                                                                        2
9996 #define mmDWB_CRC_MASK_R_G                                                                             0x3231
9997 #define mmDWB_CRC_MASK_R_G_BASE_IDX                                                                    2
9998 #define mmDWB_CRC_MASK_B_A                                                                             0x3232
9999 #define mmDWB_CRC_MASK_B_A_BASE_IDX                                                                    2
10000 #define mmDWB_CRC_VAL_R_G                                                                              0x3233
10001 #define mmDWB_CRC_VAL_R_G_BASE_IDX                                                                     2
10002 #define mmDWB_CRC_VAL_B_A                                                                              0x3234
10003 #define mmDWB_CRC_VAL_B_A_BASE_IDX                                                                     2
10004 #define mmDWB_OUT_CTRL                                                                                 0x3235
10005 #define mmDWB_OUT_CTRL_BASE_IDX                                                                        2
10006 #define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236
10007 #define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2
10008 #define mmDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237
10009 #define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2
10010 #define mmDWB_HOST_READ_CONTROL                                                                        0x3238
10011 #define mmDWB_HOST_READ_CONTROL_BASE_IDX                                                               2
10012 #define mmDWB_OVERFLOW_STATUS                                                                          0x3239
10013 #define mmDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2
10014 #define mmDWB_OVERFLOW_COUNTER                                                                         0x323a
10015 #define mmDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2
10016 #define mmDWB_SOFT_RESET                                                                               0x323b
10017 #define mmDWB_SOFT_RESET_BASE_IDX                                                                      2
10018 #define mmDWB_DEBUG_CTRL                                                                               0x323c
10019 #define mmDWB_DEBUG_CTRL_BASE_IDX                                                                      2
10020 
10021 
10022 // addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
10023 // base address: 0xca20
10024 #define mmDC_PERFMON20_PERFCOUNTER_CNTL                                                                0x3288
10025 #define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX                                                       2
10026 #define mmDC_PERFMON20_PERFCOUNTER_CNTL2                                                               0x3289
10027 #define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
10028 #define mmDC_PERFMON20_PERFCOUNTER_STATE                                                               0x328a
10029 #define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX                                                      2
10030 #define mmDC_PERFMON20_PERFMON_CNTL                                                                    0x328b
10031 #define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX                                                           2
10032 #define mmDC_PERFMON20_PERFMON_CNTL2                                                                   0x328c
10033 #define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX                                                          2
10034 #define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC                                                         0x328d
10035 #define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
10036 #define mmDC_PERFMON20_PERFMON_CVALUE_LOW                                                              0x328e
10037 #define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
10038 #define mmDC_PERFMON20_PERFMON_HI                                                                      0x328f
10039 #define mmDC_PERFMON20_PERFMON_HI_BASE_IDX                                                             2
10040 #define mmDC_PERFMON20_PERFMON_LOW                                                                     0x3290
10041 #define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX                                                            2
10042 
10043 
10044 // addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
10045 // base address: 0x0
10046 #define mmDWB_HDR_MULT_COEF                                                                            0x3294
10047 #define mmDWB_HDR_MULT_COEF_BASE_IDX                                                                   2
10048 #define mmDWB_GAMUT_REMAP_MODE                                                                         0x3295
10049 #define mmDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2
10050 #define mmDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296
10051 #define mmDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2
10052 #define mmDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297
10053 #define mmDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2
10054 #define mmDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298
10055 #define mmDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2
10056 #define mmDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299
10057 #define mmDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2
10058 #define mmDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a
10059 #define mmDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2
10060 #define mmDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b
10061 #define mmDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2
10062 #define mmDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c
10063 #define mmDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2
10064 #define mmDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d
10065 #define mmDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2
10066 #define mmDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e
10067 #define mmDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2
10068 #define mmDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f
10069 #define mmDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2
10070 #define mmDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0
10071 #define mmDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2
10072 #define mmDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1
10073 #define mmDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2
10074 #define mmDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2
10075 #define mmDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2
10076 #define mmDWB_OGAM_CONTROL                                                                             0x32a3
10077 #define mmDWB_OGAM_CONTROL_BASE_IDX                                                                    2
10078 #define mmDWB_OGAM_LUT_INDEX                                                                           0x32a4
10079 #define mmDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2
10080 #define mmDWB_OGAM_LUT_DATA                                                                            0x32a5
10081 #define mmDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2
10082 #define mmDWB_OGAM_LUT_CONTROL                                                                         0x32a6
10083 #define mmDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2
10084 #define mmDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7
10085 #define mmDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2
10086 #define mmDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8
10087 #define mmDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2
10088 #define mmDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9
10089 #define mmDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2
10090 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa
10091 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2
10092 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab
10093 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2
10094 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac
10095 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2
10096 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad
10097 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2
10098 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae
10099 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2
10100 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af
10101 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2
10102 #define mmDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0
10103 #define mmDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2
10104 #define mmDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1
10105 #define mmDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2
10106 #define mmDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2
10107 #define mmDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2
10108 #define mmDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3
10109 #define mmDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2
10110 #define mmDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4
10111 #define mmDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2
10112 #define mmDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5
10113 #define mmDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2
10114 #define mmDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6
10115 #define mmDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2
10116 #define mmDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7
10117 #define mmDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2
10118 #define mmDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8
10119 #define mmDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2
10120 #define mmDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9
10121 #define mmDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2
10122 #define mmDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba
10123 #define mmDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2
10124 #define mmDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb
10125 #define mmDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2
10126 #define mmDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc
10127 #define mmDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2
10128 #define mmDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd
10129 #define mmDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2
10130 #define mmDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be
10131 #define mmDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2
10132 #define mmDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf
10133 #define mmDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2
10134 #define mmDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0
10135 #define mmDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2
10136 #define mmDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1
10137 #define mmDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2
10138 #define mmDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2
10139 #define mmDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2
10140 #define mmDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3
10141 #define mmDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2
10142 #define mmDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4
10143 #define mmDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2
10144 #define mmDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5
10145 #define mmDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2
10146 #define mmDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6
10147 #define mmDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2
10148 #define mmDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7
10149 #define mmDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2
10150 #define mmDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8
10151 #define mmDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2
10152 #define mmDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9
10153 #define mmDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2
10154 #define mmDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca
10155 #define mmDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2
10156 #define mmDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb
10157 #define mmDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2
10158 #define mmDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc
10159 #define mmDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2
10160 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd
10161 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2
10162 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce
10163 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2
10164 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf
10165 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2
10166 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0
10167 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2
10168 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1
10169 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2
10170 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2
10171 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2
10172 #define mmDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3
10173 #define mmDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2
10174 #define mmDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4
10175 #define mmDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2
10176 #define mmDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5
10177 #define mmDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2
10178 #define mmDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6
10179 #define mmDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2
10180 #define mmDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7
10181 #define mmDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2
10182 #define mmDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8
10183 #define mmDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2
10184 #define mmDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9
10185 #define mmDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2
10186 #define mmDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da
10187 #define mmDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2
10188 #define mmDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db
10189 #define mmDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2
10190 #define mmDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc
10191 #define mmDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2
10192 #define mmDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd
10193 #define mmDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2
10194 #define mmDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de
10195 #define mmDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2
10196 #define mmDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df
10197 #define mmDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2
10198 #define mmDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0
10199 #define mmDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2
10200 #define mmDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1
10201 #define mmDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2
10202 #define mmDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2
10203 #define mmDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2
10204 #define mmDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3
10205 #define mmDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2
10206 #define mmDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4
10207 #define mmDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2
10208 #define mmDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5
10209 #define mmDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2
10210 #define mmDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6
10211 #define mmDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2
10212 #define mmDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7
10213 #define mmDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2
10214 #define mmDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8
10215 #define mmDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2
10216 #define mmDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9
10217 #define mmDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2
10218 #define mmDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea
10219 #define mmDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2
10220 #define mmDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb
10221 #define mmDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2
10222 #define mmDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec
10223 #define mmDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2
10224 
10225 
10226 // addressBlock: dce_dc_dchvm_hvm_dispdec
10227 // base address: 0x0
10228 #define mmDCHVM_CTRL0                                                                                  0x3603
10229 #define mmDCHVM_CTRL0_BASE_IDX                                                                         2
10230 #define mmDCHVM_CTRL1                                                                                  0x3604
10231 #define mmDCHVM_CTRL1_BASE_IDX                                                                         2
10232 #define mmDCHVM_CLK_CTRL                                                                               0x3605
10233 #define mmDCHVM_CLK_CTRL_BASE_IDX                                                                      2
10234 #define mmDCHVM_MEM_CTRL                                                                               0x3606
10235 #define mmDCHVM_MEM_CTRL_BASE_IDX                                                                      2
10236 #define mmDCHVM_RIOMMU_CTRL0                                                                           0x3607
10237 #define mmDCHVM_RIOMMU_CTRL0_BASE_IDX                                                                  2
10238 #define mmDCHVM_RIOMMU_STAT0                                                                           0x3608
10239 #define mmDCHVM_RIOMMU_STAT0_BASE_IDX                                                                  2
10240 
10241 
10242 // addressBlock: dce_dc_mpc_mpcc0_dispdec
10243 // base address: 0x0
10244 #define mmMPCC0_MPCC_TOP_SEL                                                                           0x0000
10245 #define mmMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3
10246 #define mmMPCC0_MPCC_BOT_SEL                                                                           0x0001
10247 #define mmMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3
10248 #define mmMPCC0_MPCC_OPP_ID                                                                            0x0002
10249 #define mmMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3
10250 #define mmMPCC0_MPCC_CONTROL                                                                           0x0003
10251 #define mmMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3
10252 #define mmMPCC0_MPCC_SM_CONTROL                                                                        0x0004
10253 #define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3
10254 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005
10255 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
10256 #define mmMPCC0_MPCC_TOP_GAIN                                                                          0x0006
10257 #define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3
10258 #define mmMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007
10259 #define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
10260 #define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008
10261 #define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
10262 #define mmMPCC0_MPCC_BG_R_CR                                                                           0x0009
10263 #define mmMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3
10264 #define mmMPCC0_MPCC_BG_G_Y                                                                            0x000a
10265 #define mmMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3
10266 #define mmMPCC0_MPCC_BG_B_CB                                                                           0x000b
10267 #define mmMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3
10268 #define mmMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000c
10269 #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
10270 #define mmMPCC0_MPCC_STATUS                                                                            0x000d
10271 #define mmMPCC0_MPCC_STATUS_BASE_IDX                                                                   3
10272 
10273 
10274 // addressBlock: dce_dc_mpc_mpcc1_dispdec
10275 // base address: 0x80
10276 #define mmMPCC1_MPCC_TOP_SEL                                                                           0x0020
10277 #define mmMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3
10278 #define mmMPCC1_MPCC_BOT_SEL                                                                           0x0021
10279 #define mmMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3
10280 #define mmMPCC1_MPCC_OPP_ID                                                                            0x0022
10281 #define mmMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3
10282 #define mmMPCC1_MPCC_CONTROL                                                                           0x0023
10283 #define mmMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3
10284 #define mmMPCC1_MPCC_SM_CONTROL                                                                        0x0024
10285 #define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3
10286 #define mmMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x0025
10287 #define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
10288 #define mmMPCC1_MPCC_TOP_GAIN                                                                          0x0026
10289 #define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3
10290 #define mmMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x0027
10291 #define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
10292 #define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0028
10293 #define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
10294 #define mmMPCC1_MPCC_BG_R_CR                                                                           0x0029
10295 #define mmMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3
10296 #define mmMPCC1_MPCC_BG_G_Y                                                                            0x002a
10297 #define mmMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3
10298 #define mmMPCC1_MPCC_BG_B_CB                                                                           0x002b
10299 #define mmMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3
10300 #define mmMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x002c
10301 #define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
10302 #define mmMPCC1_MPCC_STATUS                                                                            0x002d
10303 #define mmMPCC1_MPCC_STATUS_BASE_IDX                                                                   3
10304 
10305 
10306 // addressBlock: dce_dc_mpc_mpcc2_dispdec
10307 // base address: 0x100
10308 #define mmMPCC2_MPCC_TOP_SEL                                                                           0x0040
10309 #define mmMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3
10310 #define mmMPCC2_MPCC_BOT_SEL                                                                           0x0041
10311 #define mmMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3
10312 #define mmMPCC2_MPCC_OPP_ID                                                                            0x0042
10313 #define mmMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3
10314 #define mmMPCC2_MPCC_CONTROL                                                                           0x0043
10315 #define mmMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3
10316 #define mmMPCC2_MPCC_SM_CONTROL                                                                        0x0044
10317 #define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3
10318 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x0045
10319 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
10320 #define mmMPCC2_MPCC_TOP_GAIN                                                                          0x0046
10321 #define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3
10322 #define mmMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0047
10323 #define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
10324 #define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0048
10325 #define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
10326 #define mmMPCC2_MPCC_BG_R_CR                                                                           0x0049
10327 #define mmMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3
10328 #define mmMPCC2_MPCC_BG_G_Y                                                                            0x004a
10329 #define mmMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3
10330 #define mmMPCC2_MPCC_BG_B_CB                                                                           0x004b
10331 #define mmMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3
10332 #define mmMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x004c
10333 #define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
10334 #define mmMPCC2_MPCC_STATUS                                                                            0x004d
10335 #define mmMPCC2_MPCC_STATUS_BASE_IDX                                                                   3
10336 
10337 
10338 // addressBlock: dce_dc_mpc_mpcc3_dispdec
10339 // base address: 0x180
10340 #define mmMPCC3_MPCC_TOP_SEL                                                                           0x0060
10341 #define mmMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3
10342 #define mmMPCC3_MPCC_BOT_SEL                                                                           0x0061
10343 #define mmMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3
10344 #define mmMPCC3_MPCC_OPP_ID                                                                            0x0062
10345 #define mmMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3
10346 #define mmMPCC3_MPCC_CONTROL                                                                           0x0063
10347 #define mmMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3
10348 #define mmMPCC3_MPCC_SM_CONTROL                                                                        0x0064
10349 #define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3
10350 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0065
10351 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
10352 #define mmMPCC3_MPCC_TOP_GAIN                                                                          0x0066
10353 #define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3
10354 #define mmMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0067
10355 #define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
10356 #define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0068
10357 #define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
10358 #define mmMPCC3_MPCC_BG_R_CR                                                                           0x0069
10359 #define mmMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3
10360 #define mmMPCC3_MPCC_BG_G_Y                                                                            0x006a
10361 #define mmMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3
10362 #define mmMPCC3_MPCC_BG_B_CB                                                                           0x006b
10363 #define mmMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3
10364 #define mmMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x006c
10365 #define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
10366 #define mmMPCC3_MPCC_STATUS                                                                            0x006d
10367 #define mmMPCC3_MPCC_STATUS_BASE_IDX                                                                   3
10368 
10369 
10370 // addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
10371 // base address: 0x0
10372 #define mmMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x0100
10373 #define mmMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
10374 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x0101
10375 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
10376 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x0102
10377 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
10378 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x0103
10379 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
10380 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0104
10381 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
10382 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0105
10383 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
10384 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0106
10385 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
10386 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0107
10387 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
10388 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0108
10389 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
10390 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0109
10391 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
10392 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x010a
10393 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
10394 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x010b
10395 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
10396 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x010c
10397 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
10398 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x010d
10399 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
10400 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x010e
10401 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
10402 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x010f
10403 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
10404 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0110
10405 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
10406 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0111
10407 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
10408 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0112
10409 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
10410 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0113
10411 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
10412 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0114
10413 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
10414 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0115
10415 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
10416 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0116
10417 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
10418 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0117
10419 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
10420 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0118
10421 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
10422 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0119
10423 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
10424 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x011a
10425 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
10426 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x011b
10427 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
10428 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x011c
10429 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
10430 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x011d
10431 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
10432 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x011e
10433 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
10434 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x011f
10435 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
10436 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0120
10437 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
10438 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0121
10439 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
10440 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0122
10441 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
10442 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0123
10443 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
10444 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0124
10445 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
10446 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0125
10447 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
10448 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0126
10449 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
10450 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0127
10451 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
10452 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0128
10453 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
10454 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0129
10455 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
10456 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x012a
10457 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
10458 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x012b
10459 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
10460 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x012c
10461 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
10462 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x012d
10463 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
10464 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x012e
10465 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
10466 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x012f
10467 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
10468 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0130
10469 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
10470 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0131
10471 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
10472 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0132
10473 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
10474 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0133
10475 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
10476 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0134
10477 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
10478 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0135
10479 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
10480 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0136
10481 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
10482 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0137
10483 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
10484 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0138
10485 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
10486 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0139
10487 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
10488 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x013a
10489 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
10490 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x013b
10491 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
10492 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x013c
10493 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
10494 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x013d
10495 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
10496 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x013e
10497 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
10498 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x013f
10499 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
10500 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0140
10501 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
10502 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0141
10503 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
10504 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0142
10505 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
10506 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0143
10507 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
10508 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0144
10509 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
10510 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0145
10511 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
10512 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0146
10513 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
10514 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0147
10515 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
10516 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0148
10517 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
10518 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0149
10519 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
10520 #define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x014a
10521 #define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
10522 #define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x014b
10523 #define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
10524 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x014c
10525 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
10526 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x014d
10527 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
10528 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x014e
10529 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
10530 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x014f
10531 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
10532 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0150
10533 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
10534 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0151
10535 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
10536 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0152
10537 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
10538 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0153
10539 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
10540 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0154
10541 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
10542 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0155
10543 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
10544 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0156
10545 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
10546 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0157
10547 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
10548 
10549 
10550 // addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
10551 // base address: 0x200
10552 #define mmMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0180
10553 #define mmMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
10554 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0181
10555 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
10556 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0182
10557 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
10558 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0183
10559 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
10560 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0184
10561 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
10562 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0185
10563 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
10564 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0186
10565 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
10566 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0187
10567 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
10568 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0188
10569 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
10570 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0189
10571 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
10572 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x018a
10573 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
10574 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x018b
10575 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
10576 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x018c
10577 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
10578 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x018d
10579 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
10580 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x018e
10581 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
10582 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x018f
10583 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
10584 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0190
10585 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
10586 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0191
10587 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
10588 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0192
10589 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
10590 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0193
10591 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
10592 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0194
10593 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
10594 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0195
10595 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
10596 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0196
10597 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
10598 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0197
10599 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
10600 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0198
10601 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
10602 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0199
10603 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
10604 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x019a
10605 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
10606 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x019b
10607 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
10608 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x019c
10609 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
10610 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x019d
10611 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
10612 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x019e
10613 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
10614 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x019f
10615 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
10616 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01a0
10617 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
10618 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01a1
10619 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
10620 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01a2
10621 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
10622 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01a3
10623 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
10624 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01a4
10625 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
10626 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01a5
10627 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
10628 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01a6
10629 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
10630 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01a7
10631 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
10632 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01a8
10633 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
10634 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01a9
10635 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
10636 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01aa
10637 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
10638 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ab
10639 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
10640 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ac
10641 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
10642 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ad
10643 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
10644 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01ae
10645 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
10646 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01af
10647 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
10648 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01b0
10649 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
10650 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01b1
10651 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
10652 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01b2
10653 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
10654 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01b3
10655 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
10656 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01b4
10657 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
10658 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01b5
10659 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
10660 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01b6
10661 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
10662 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01b7
10663 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
10664 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01b8
10665 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
10666 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01b9
10667 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
10668 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01ba
10669 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
10670 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01bb
10671 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
10672 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01bc
10673 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
10674 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01bd
10675 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
10676 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01be
10677 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
10678 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01bf
10679 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
10680 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01c0
10681 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
10682 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01c1
10683 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
10684 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01c2
10685 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
10686 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01c3
10687 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
10688 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01c4
10689 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
10690 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01c5
10691 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
10692 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01c6
10693 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
10694 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01c7
10695 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
10696 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01c8
10697 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
10698 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01c9
10699 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
10700 #define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ca
10701 #define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
10702 #define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x01cb
10703 #define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
10704 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01cc
10705 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
10706 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01cd
10707 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
10708 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01ce
10709 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
10710 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01cf
10711 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
10712 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01d0
10713 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
10714 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01d1
10715 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
10716 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01d2
10717 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
10718 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01d3
10719 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
10720 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01d4
10721 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
10722 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01d5
10723 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
10724 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01d6
10725 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
10726 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01d7
10727 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
10728 
10729 
10730 // addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
10731 // base address: 0x400
10732 #define mmMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x0200
10733 #define mmMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
10734 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x0201
10735 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
10736 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x0202
10737 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
10738 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x0203
10739 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
10740 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0204
10741 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
10742 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0205
10743 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
10744 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0206
10745 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
10746 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0207
10747 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
10748 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0208
10749 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
10750 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0209
10751 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
10752 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x020a
10753 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
10754 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x020b
10755 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
10756 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x020c
10757 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
10758 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x020d
10759 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
10760 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x020e
10761 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
10762 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x020f
10763 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
10764 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0210
10765 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
10766 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0211
10767 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
10768 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0212
10769 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
10770 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0213
10771 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
10772 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0214
10773 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
10774 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0215
10775 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
10776 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0216
10777 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
10778 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0217
10779 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
10780 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0218
10781 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
10782 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0219
10783 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
10784 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x021a
10785 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
10786 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x021b
10787 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
10788 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x021c
10789 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
10790 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x021d
10791 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
10792 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x021e
10793 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
10794 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x021f
10795 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
10796 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0220
10797 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
10798 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0221
10799 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
10800 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0222
10801 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
10802 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0223
10803 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
10804 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0224
10805 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
10806 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0225
10807 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
10808 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0226
10809 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
10810 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0227
10811 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
10812 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0228
10813 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
10814 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0229
10815 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
10816 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x022a
10817 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
10818 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x022b
10819 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
10820 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x022c
10821 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
10822 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x022d
10823 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
10824 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x022e
10825 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
10826 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x022f
10827 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
10828 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0230
10829 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
10830 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0231
10831 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
10832 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0232
10833 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
10834 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0233
10835 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
10836 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0234
10837 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
10838 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0235
10839 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
10840 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0236
10841 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
10842 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0237
10843 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
10844 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0238
10845 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
10846 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0239
10847 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
10848 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x023a
10849 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
10850 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x023b
10851 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
10852 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x023c
10853 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
10854 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x023d
10855 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
10856 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x023e
10857 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
10858 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x023f
10859 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
10860 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0240
10861 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
10862 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0241
10863 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
10864 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0242
10865 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
10866 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0243
10867 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
10868 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0244
10869 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
10870 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0245
10871 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
10872 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0246
10873 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
10874 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0247
10875 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
10876 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0248
10877 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
10878 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0249
10879 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
10880 #define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x024a
10881 #define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
10882 #define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x024b
10883 #define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
10884 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x024c
10885 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
10886 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x024d
10887 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
10888 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x024e
10889 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
10890 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x024f
10891 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
10892 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0250
10893 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
10894 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0251
10895 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
10896 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0252
10897 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
10898 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0253
10899 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
10900 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0254
10901 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
10902 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0255
10903 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
10904 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0256
10905 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
10906 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0257
10907 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
10908 
10909 
10910 // addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
10911 // base address: 0x600
10912 #define mmMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x0280
10913 #define mmMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
10914 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x0281
10915 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
10916 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x0282
10917 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
10918 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x0283
10919 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
10920 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0284
10921 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
10922 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0285
10923 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
10924 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0286
10925 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
10926 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0287
10927 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
10928 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0288
10929 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
10930 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0289
10931 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
10932 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x028a
10933 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
10934 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x028b
10935 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
10936 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x028c
10937 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
10938 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x028d
10939 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
10940 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x028e
10941 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
10942 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x028f
10943 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
10944 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0290
10945 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
10946 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0291
10947 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
10948 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0292
10949 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
10950 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0293
10951 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
10952 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0294
10953 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
10954 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0295
10955 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
10956 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0296
10957 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
10958 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0297
10959 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
10960 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0298
10961 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
10962 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0299
10963 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
10964 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x029a
10965 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
10966 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x029b
10967 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
10968 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x029c
10969 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
10970 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x029d
10971 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
10972 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x029e
10973 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
10974 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x029f
10975 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
10976 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x02a0
10977 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
10978 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x02a1
10979 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
10980 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x02a2
10981 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
10982 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x02a3
10983 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
10984 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x02a4
10985 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
10986 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x02a5
10987 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
10988 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x02a6
10989 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
10990 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x02a7
10991 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
10992 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x02a8
10993 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
10994 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x02a9
10995 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
10996 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x02aa
10997 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
10998 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x02ab
10999 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
11000 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x02ac
11001 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
11002 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x02ad
11003 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
11004 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x02ae
11005 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
11006 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x02af
11007 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
11008 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x02b0
11009 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
11010 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x02b1
11011 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
11012 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x02b2
11013 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
11014 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x02b3
11015 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
11016 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x02b4
11017 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
11018 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x02b5
11019 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
11020 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x02b6
11021 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
11022 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x02b7
11023 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
11024 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x02b8
11025 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
11026 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x02b9
11027 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
11028 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x02ba
11029 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
11030 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x02bb
11031 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
11032 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x02bc
11033 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
11034 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x02bd
11035 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
11036 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x02be
11037 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
11038 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x02bf
11039 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
11040 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x02c0
11041 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
11042 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x02c1
11043 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
11044 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x02c2
11045 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
11046 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x02c3
11047 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
11048 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x02c4
11049 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
11050 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x02c5
11051 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
11052 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x02c6
11053 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
11054 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x02c7
11055 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
11056 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x02c8
11057 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
11058 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x02c9
11059 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
11060 #define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x02ca
11061 #define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
11062 #define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE                                                             0x02cb
11063 #define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
11064 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A                                                         0x02cc
11065 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
11066 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A                                                         0x02cd
11067 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
11068 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A                                                         0x02ce
11069 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
11070 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A                                                         0x02cf
11071 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
11072 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A                                                         0x02d0
11073 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
11074 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A                                                         0x02d1
11075 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
11076 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B                                                         0x02d2
11077 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
11078 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B                                                         0x02d3
11079 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
11080 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B                                                         0x02d4
11081 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
11082 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B                                                         0x02d5
11083 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
11084 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B                                                         0x02d6
11085 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
11086 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B                                                         0x02d7
11087 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
11088 
11089 
11090 // addressBlock: dce_dc_mpc_mpc_cfg_dispdec
11091 // base address: 0x0
11092 #define mmMPC_CLOCK_CONTROL                                                                            0x0500
11093 #define mmMPC_CLOCK_CONTROL_BASE_IDX                                                                   3
11094 #define mmMPC_SOFT_RESET                                                                               0x0501
11095 #define mmMPC_SOFT_RESET_BASE_IDX                                                                      3
11096 #define mmMPC_CRC_CTRL                                                                                 0x0502
11097 #define mmMPC_CRC_CTRL_BASE_IDX                                                                        3
11098 #define mmMPC_CRC_SEL_CONTROL                                                                          0x0503
11099 #define mmMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3
11100 #define mmMPC_CRC_RESULT_AR                                                                            0x0504
11101 #define mmMPC_CRC_RESULT_AR_BASE_IDX                                                                   3
11102 #define mmMPC_CRC_RESULT_GB                                                                            0x0505
11103 #define mmMPC_CRC_RESULT_GB_BASE_IDX                                                                   3
11104 #define mmMPC_CRC_RESULT_C                                                                             0x0506
11105 #define mmMPC_CRC_RESULT_C_BASE_IDX                                                                    3
11106 #define mmMPC_PERFMON_EVENT_CTRL                                                                       0x0509
11107 #define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX                                                              3
11108 #define mmMPC_BYPASS_BG_AR                                                                             0x050a
11109 #define mmMPC_BYPASS_BG_AR_BASE_IDX                                                                    3
11110 #define mmMPC_BYPASS_BG_GB                                                                             0x050b
11111 #define mmMPC_BYPASS_BG_GB_BASE_IDX                                                                    3
11112 #define mmMPC_HOST_READ_CONTROL                                                                        0x050c
11113 #define mmMPC_HOST_READ_CONTROL_BASE_IDX                                                               3
11114 #define mmMPC_DPP_PENDING_STATUS                                                                       0x050d
11115 #define mmMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3
11116 #define mmMPC_PENDING_STATUS_MISC                                                                      0x050e
11117 #define mmMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3
11118 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x050f
11119 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3
11120 #define mmADR_CFG_VUPDATE_LOCK_SET0                                                                    0x0510
11121 #define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3
11122 #define mmADR_VUPDATE_LOCK_SET0                                                                        0x0511
11123 #define mmADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
11124 #define mmCFG_VUPDATE_LOCK_SET0                                                                        0x0512
11125 #define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
11126 #define mmCUR_VUPDATE_LOCK_SET0                                                                        0x0513
11127 #define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
11128 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x0514
11129 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3
11130 #define mmADR_CFG_VUPDATE_LOCK_SET1                                                                    0x0515
11131 #define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3
11132 #define mmADR_VUPDATE_LOCK_SET1                                                                        0x0516
11133 #define mmADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
11134 #define mmCFG_VUPDATE_LOCK_SET1                                                                        0x0517
11135 #define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
11136 #define mmCUR_VUPDATE_LOCK_SET1                                                                        0x0518
11137 #define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
11138 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x0519
11139 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3
11140 #define mmADR_CFG_VUPDATE_LOCK_SET2                                                                    0x051a
11141 #define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3
11142 #define mmADR_VUPDATE_LOCK_SET2                                                                        0x051b
11143 #define mmADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
11144 #define mmCFG_VUPDATE_LOCK_SET2                                                                        0x051c
11145 #define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
11146 #define mmCUR_VUPDATE_LOCK_SET2                                                                        0x051d
11147 #define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
11148 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x051e
11149 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3
11150 #define mmADR_CFG_VUPDATE_LOCK_SET3                                                                    0x051f
11151 #define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3
11152 #define mmADR_VUPDATE_LOCK_SET3                                                                        0x0520
11153 #define mmADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
11154 #define mmCFG_VUPDATE_LOCK_SET3                                                                        0x0521
11155 #define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
11156 #define mmCUR_VUPDATE_LOCK_SET3                                                                        0x0522
11157 #define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
11158 #define mmMPC_DWB0_MUX                                                                                 0x055c
11159 #define mmMPC_DWB0_MUX_BASE_IDX                                                                        3
11160 
11161 
11162 // addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
11163 // base address: 0x0
11164 #define mmMPC_OUT0_MUX                                                                                 0x0580
11165 #define mmMPC_OUT0_MUX_BASE_IDX                                                                        3
11166 #define mmMPC_OUT0_DENORM_CONTROL                                                                      0x0581
11167 #define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3
11168 #define mmMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x0582
11169 #define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
11170 #define mmMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x0583
11171 #define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
11172 #define mmMPC_OUT1_MUX                                                                                 0x0584
11173 #define mmMPC_OUT1_MUX_BASE_IDX                                                                        3
11174 #define mmMPC_OUT1_DENORM_CONTROL                                                                      0x0585
11175 #define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3
11176 #define mmMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x0586
11177 #define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
11178 #define mmMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x0587
11179 #define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
11180 #define mmMPC_OUT2_MUX                                                                                 0x0588
11181 #define mmMPC_OUT2_MUX_BASE_IDX                                                                        3
11182 #define mmMPC_OUT2_DENORM_CONTROL                                                                      0x0589
11183 #define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             3
11184 #define mmMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x058a
11185 #define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
11186 #define mmMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x058b
11187 #define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
11188 #define mmMPC_OUT3_MUX                                                                                 0x058c
11189 #define mmMPC_OUT3_MUX_BASE_IDX                                                                        3
11190 #define mmMPC_OUT3_DENORM_CONTROL                                                                      0x058d
11191 #define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             3
11192 #define mmMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x058e
11193 #define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
11194 #define mmMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x058f
11195 #define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
11196 #define mmMPC_OUT_CSC_COEF_FORMAT                                                                      0x0590
11197 #define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3
11198 #define mmMPC_OUT0_CSC_MODE                                                                            0x0591
11199 #define mmMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3
11200 #define mmMPC_OUT0_CSC_C11_C12_A                                                                       0x0592
11201 #define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3
11202 #define mmMPC_OUT0_CSC_C13_C14_A                                                                       0x0593
11203 #define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3
11204 #define mmMPC_OUT0_CSC_C21_C22_A                                                                       0x0594
11205 #define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3
11206 #define mmMPC_OUT0_CSC_C23_C24_A                                                                       0x0595
11207 #define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3
11208 #define mmMPC_OUT0_CSC_C31_C32_A                                                                       0x0596
11209 #define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3
11210 #define mmMPC_OUT0_CSC_C33_C34_A                                                                       0x0597
11211 #define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3
11212 #define mmMPC_OUT0_CSC_C11_C12_B                                                                       0x0598
11213 #define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3
11214 #define mmMPC_OUT0_CSC_C13_C14_B                                                                       0x0599
11215 #define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3
11216 #define mmMPC_OUT0_CSC_C21_C22_B                                                                       0x059a
11217 #define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3
11218 #define mmMPC_OUT0_CSC_C23_C24_B                                                                       0x059b
11219 #define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3
11220 #define mmMPC_OUT0_CSC_C31_C32_B                                                                       0x059c
11221 #define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3
11222 #define mmMPC_OUT0_CSC_C33_C34_B                                                                       0x059d
11223 #define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3
11224 #define mmMPC_OUT1_CSC_MODE                                                                            0x059e
11225 #define mmMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3
11226 #define mmMPC_OUT1_CSC_C11_C12_A                                                                       0x059f
11227 #define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3
11228 #define mmMPC_OUT1_CSC_C13_C14_A                                                                       0x05a0
11229 #define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3
11230 #define mmMPC_OUT1_CSC_C21_C22_A                                                                       0x05a1
11231 #define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3
11232 #define mmMPC_OUT1_CSC_C23_C24_A                                                                       0x05a2
11233 #define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3
11234 #define mmMPC_OUT1_CSC_C31_C32_A                                                                       0x05a3
11235 #define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3
11236 #define mmMPC_OUT1_CSC_C33_C34_A                                                                       0x05a4
11237 #define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3
11238 #define mmMPC_OUT1_CSC_C11_C12_B                                                                       0x05a5
11239 #define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3
11240 #define mmMPC_OUT1_CSC_C13_C14_B                                                                       0x05a6
11241 #define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3
11242 #define mmMPC_OUT1_CSC_C21_C22_B                                                                       0x05a7
11243 #define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3
11244 #define mmMPC_OUT1_CSC_C23_C24_B                                                                       0x05a8
11245 #define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3
11246 #define mmMPC_OUT1_CSC_C31_C32_B                                                                       0x05a9
11247 #define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3
11248 #define mmMPC_OUT1_CSC_C33_C34_B                                                                       0x05aa
11249 #define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3
11250 #define mmMPC_OUT2_CSC_MODE                                                                            0x05ab
11251 #define mmMPC_OUT2_CSC_MODE_BASE_IDX                                                                   3
11252 #define mmMPC_OUT2_CSC_C11_C12_A                                                                       0x05ac
11253 #define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              3
11254 #define mmMPC_OUT2_CSC_C13_C14_A                                                                       0x05ad
11255 #define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              3
11256 #define mmMPC_OUT2_CSC_C21_C22_A                                                                       0x05ae
11257 #define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              3
11258 #define mmMPC_OUT2_CSC_C23_C24_A                                                                       0x05af
11259 #define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              3
11260 #define mmMPC_OUT2_CSC_C31_C32_A                                                                       0x05b0
11261 #define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              3
11262 #define mmMPC_OUT2_CSC_C33_C34_A                                                                       0x05b1
11263 #define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              3
11264 #define mmMPC_OUT2_CSC_C11_C12_B                                                                       0x05b2
11265 #define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              3
11266 #define mmMPC_OUT2_CSC_C13_C14_B                                                                       0x05b3
11267 #define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              3
11268 #define mmMPC_OUT2_CSC_C21_C22_B                                                                       0x05b4
11269 #define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              3
11270 #define mmMPC_OUT2_CSC_C23_C24_B                                                                       0x05b5
11271 #define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              3
11272 #define mmMPC_OUT2_CSC_C31_C32_B                                                                       0x05b6
11273 #define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              3
11274 #define mmMPC_OUT2_CSC_C33_C34_B                                                                       0x05b7
11275 #define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              3
11276 #define mmMPC_OUT3_CSC_MODE                                                                            0x05b8
11277 #define mmMPC_OUT3_CSC_MODE_BASE_IDX                                                                   3
11278 #define mmMPC_OUT3_CSC_C11_C12_A                                                                       0x05b9
11279 #define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              3
11280 #define mmMPC_OUT3_CSC_C13_C14_A                                                                       0x05ba
11281 #define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              3
11282 #define mmMPC_OUT3_CSC_C21_C22_A                                                                       0x05bb
11283 #define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              3
11284 #define mmMPC_OUT3_CSC_C23_C24_A                                                                       0x05bc
11285 #define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              3
11286 #define mmMPC_OUT3_CSC_C31_C32_A                                                                       0x05bd
11287 #define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              3
11288 #define mmMPC_OUT3_CSC_C33_C34_A                                                                       0x05be
11289 #define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              3
11290 #define mmMPC_OUT3_CSC_C11_C12_B                                                                       0x05bf
11291 #define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              3
11292 #define mmMPC_OUT3_CSC_C13_C14_B                                                                       0x05c0
11293 #define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              3
11294 #define mmMPC_OUT3_CSC_C21_C22_B                                                                       0x05c1
11295 #define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              3
11296 #define mmMPC_OUT3_CSC_C23_C24_B                                                                       0x05c2
11297 #define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              3
11298 #define mmMPC_OUT3_CSC_C31_C32_B                                                                       0x05c3
11299 #define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              3
11300 #define mmMPC_OUT3_CSC_C33_C34_B                                                                       0x05c4
11301 #define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              3
11302 
11303 
11304 // addressBlock: dce_dc_mpc_mpc_rmu_dispdec
11305 // base address: 0x0
11306 #define mmMPC_RMU_CONTROL                                                                              0x0680
11307 #define mmMPC_RMU_CONTROL_BASE_IDX                                                                     3
11308 #define mmMPC_RMU_MEM_PWR_CTRL                                                                         0x0681
11309 #define mmMPC_RMU_MEM_PWR_CTRL_BASE_IDX                                                                3
11310 #define mmMPC_RMU0_SHAPER_CONTROL                                                                      0x0682
11311 #define mmMPC_RMU0_SHAPER_CONTROL_BASE_IDX                                                             3
11312 #define mmMPC_RMU0_SHAPER_OFFSET_R                                                                     0x0683
11313 #define mmMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX                                                            3
11314 #define mmMPC_RMU0_SHAPER_OFFSET_G                                                                     0x0684
11315 #define mmMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX                                                            3
11316 #define mmMPC_RMU0_SHAPER_OFFSET_B                                                                     0x0685
11317 #define mmMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX                                                            3
11318 #define mmMPC_RMU0_SHAPER_SCALE_R                                                                      0x0686
11319 #define mmMPC_RMU0_SHAPER_SCALE_R_BASE_IDX                                                             3
11320 #define mmMPC_RMU0_SHAPER_SCALE_G_B                                                                    0x0687
11321 #define mmMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX                                                           3
11322 #define mmMPC_RMU0_SHAPER_LUT_INDEX                                                                    0x0688
11323 #define mmMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX                                                           3
11324 #define mmMPC_RMU0_SHAPER_LUT_DATA                                                                     0x0689
11325 #define mmMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX                                                            3
11326 #define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK                                                            0x068a
11327 #define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                   3
11328 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B                                                            0x068b
11329 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                   3
11330 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G                                                            0x068c
11331 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                   3
11332 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R                                                            0x068d
11333 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                   3
11334 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B                                                              0x068e
11335 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                     3
11336 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G                                                              0x068f
11337 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                     3
11338 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R                                                              0x0690
11339 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                     3
11340 #define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1                                                              0x0691
11341 #define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                     3
11342 #define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3                                                              0x0692
11343 #define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                     3
11344 #define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5                                                              0x0693
11345 #define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                     3
11346 #define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7                                                              0x0694
11347 #define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                     3
11348 #define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9                                                              0x0695
11349 #define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                     3
11350 #define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11                                                            0x0696
11351 #define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                   3
11352 #define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13                                                            0x0697
11353 #define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                   3
11354 #define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15                                                            0x0698
11355 #define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                   3
11356 #define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17                                                            0x0699
11357 #define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                   3
11358 #define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19                                                            0x069a
11359 #define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                   3
11360 #define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21                                                            0x069b
11361 #define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                   3
11362 #define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23                                                            0x069c
11363 #define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                   3
11364 #define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25                                                            0x069d
11365 #define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                   3
11366 #define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27                                                            0x069e
11367 #define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                   3
11368 #define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29                                                            0x069f
11369 #define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                   3
11370 #define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31                                                            0x06a0
11371 #define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                   3
11372 #define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33                                                            0x06a1
11373 #define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                   3
11374 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B                                                            0x06a2
11375 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                   3
11376 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G                                                            0x06a3
11377 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                   3
11378 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R                                                            0x06a4
11379 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                   3
11380 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B                                                              0x06a5
11381 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                     3
11382 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G                                                              0x06a6
11383 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                     3
11384 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R                                                              0x06a7
11385 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                     3
11386 #define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1                                                              0x06a8
11387 #define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                     3
11388 #define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3                                                              0x06a9
11389 #define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                     3
11390 #define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5                                                              0x06aa
11391 #define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                     3
11392 #define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7                                                              0x06ab
11393 #define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                     3
11394 #define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9                                                              0x06ac
11395 #define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                     3
11396 #define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11                                                            0x06ad
11397 #define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                   3
11398 #define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13                                                            0x06ae
11399 #define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                   3
11400 #define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15                                                            0x06af
11401 #define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                   3
11402 #define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17                                                            0x06b0
11403 #define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                   3
11404 #define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19                                                            0x06b1
11405 #define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                   3
11406 #define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21                                                            0x06b2
11407 #define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                   3
11408 #define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23                                                            0x06b3
11409 #define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                   3
11410 #define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25                                                            0x06b4
11411 #define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                   3
11412 #define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27                                                            0x06b5
11413 #define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                   3
11414 #define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29                                                            0x06b6
11415 #define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                   3
11416 #define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31                                                            0x06b7
11417 #define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                   3
11418 #define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33                                                            0x06b8
11419 #define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                   3
11420 #define mmMPC_RMU0_3DLUT_MODE                                                                          0x06b9
11421 #define mmMPC_RMU0_3DLUT_MODE_BASE_IDX                                                                 3
11422 #define mmMPC_RMU0_3DLUT_INDEX                                                                         0x06ba
11423 #define mmMPC_RMU0_3DLUT_INDEX_BASE_IDX                                                                3
11424 #define mmMPC_RMU0_3DLUT_DATA                                                                          0x06bb
11425 #define mmMPC_RMU0_3DLUT_DATA_BASE_IDX                                                                 3
11426 #define mmMPC_RMU0_3DLUT_DATA_30BIT                                                                    0x06bc
11427 #define mmMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX                                                           3
11428 #define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL                                                            0x06bd
11429 #define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                   3
11430 #define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR                                                               0x06be
11431 #define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                      3
11432 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_R                                                                  0x06bf
11433 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX                                                         3
11434 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_G                                                                  0x06c0
11435 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX                                                         3
11436 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_B                                                                  0x06c1
11437 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX                                                         3
11438 #define mmMPC_RMU1_SHAPER_CONTROL                                                                      0x06c2
11439 #define mmMPC_RMU1_SHAPER_CONTROL_BASE_IDX                                                             3
11440 #define mmMPC_RMU1_SHAPER_OFFSET_R                                                                     0x06c3
11441 #define mmMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX                                                            3
11442 #define mmMPC_RMU1_SHAPER_OFFSET_G                                                                     0x06c4
11443 #define mmMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX                                                            3
11444 #define mmMPC_RMU1_SHAPER_OFFSET_B                                                                     0x06c5
11445 #define mmMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX                                                            3
11446 #define mmMPC_RMU1_SHAPER_SCALE_R                                                                      0x06c6
11447 #define mmMPC_RMU1_SHAPER_SCALE_R_BASE_IDX                                                             3
11448 #define mmMPC_RMU1_SHAPER_SCALE_G_B                                                                    0x06c7
11449 #define mmMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX                                                           3
11450 #define mmMPC_RMU1_SHAPER_LUT_INDEX                                                                    0x06c8
11451 #define mmMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX                                                           3
11452 #define mmMPC_RMU1_SHAPER_LUT_DATA                                                                     0x06c9
11453 #define mmMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX                                                            3
11454 #define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK                                                            0x06ca
11455 #define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                   3
11456 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B                                                            0x06cb
11457 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                   3
11458 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G                                                            0x06cc
11459 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                   3
11460 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R                                                            0x06cd
11461 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                   3
11462 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B                                                              0x06ce
11463 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                     3
11464 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G                                                              0x06cf
11465 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                     3
11466 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R                                                              0x06d0
11467 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                     3
11468 #define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1                                                              0x06d1
11469 #define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                     3
11470 #define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3                                                              0x06d2
11471 #define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                     3
11472 #define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5                                                              0x06d3
11473 #define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                     3
11474 #define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7                                                              0x06d4
11475 #define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                     3
11476 #define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9                                                              0x06d5
11477 #define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                     3
11478 #define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11                                                            0x06d6
11479 #define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                   3
11480 #define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13                                                            0x06d7
11481 #define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                   3
11482 #define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15                                                            0x06d8
11483 #define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                   3
11484 #define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17                                                            0x06d9
11485 #define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                   3
11486 #define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19                                                            0x06da
11487 #define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                   3
11488 #define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21                                                            0x06db
11489 #define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                   3
11490 #define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23                                                            0x06dc
11491 #define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                   3
11492 #define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25                                                            0x06dd
11493 #define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                   3
11494 #define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27                                                            0x06de
11495 #define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                   3
11496 #define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29                                                            0x06df
11497 #define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                   3
11498 #define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31                                                            0x06e0
11499 #define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                   3
11500 #define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33                                                            0x06e1
11501 #define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                   3
11502 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B                                                            0x06e2
11503 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                   3
11504 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G                                                            0x06e3
11505 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                   3
11506 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R                                                            0x06e4
11507 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                   3
11508 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B                                                              0x06e5
11509 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                     3
11510 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G                                                              0x06e6
11511 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                     3
11512 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R                                                              0x06e7
11513 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                     3
11514 #define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1                                                              0x06e8
11515 #define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                     3
11516 #define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3                                                              0x06e9
11517 #define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                     3
11518 #define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5                                                              0x06ea
11519 #define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                     3
11520 #define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7                                                              0x06eb
11521 #define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                     3
11522 #define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9                                                              0x06ec
11523 #define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                     3
11524 #define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11                                                            0x06ed
11525 #define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                   3
11526 #define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13                                                            0x06ee
11527 #define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                   3
11528 #define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15                                                            0x06ef
11529 #define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                   3
11530 #define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17                                                            0x06f0
11531 #define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                   3
11532 #define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19                                                            0x06f1
11533 #define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                   3
11534 #define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21                                                            0x06f2
11535 #define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                   3
11536 #define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23                                                            0x06f3
11537 #define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                   3
11538 #define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25                                                            0x06f4
11539 #define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                   3
11540 #define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27                                                            0x06f5
11541 #define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                   3
11542 #define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29                                                            0x06f6
11543 #define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                   3
11544 #define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31                                                            0x06f7
11545 #define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                   3
11546 #define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33                                                            0x06f8
11547 #define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                   3
11548 #define mmMPC_RMU1_3DLUT_MODE                                                                          0x06f9
11549 #define mmMPC_RMU1_3DLUT_MODE_BASE_IDX                                                                 3
11550 #define mmMPC_RMU1_3DLUT_INDEX                                                                         0x06fa
11551 #define mmMPC_RMU1_3DLUT_INDEX_BASE_IDX                                                                3
11552 #define mmMPC_RMU1_3DLUT_DATA                                                                          0x06fb
11553 #define mmMPC_RMU1_3DLUT_DATA_BASE_IDX                                                                 3
11554 #define mmMPC_RMU1_3DLUT_DATA_30BIT                                                                    0x06fc
11555 #define mmMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX                                                           3
11556 #define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL                                                            0x06fd
11557 #define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                   3
11558 #define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR                                                               0x06fe
11559 #define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                      3
11560 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_R                                                                  0x06ff
11561 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX                                                         3
11562 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_G                                                                  0x0700
11563 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX                                                         3
11564 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_B                                                                  0x0701
11565 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX                                                         3
11566 
11567 
11568 // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
11569 // base address: 0x1901c
11570 #define mmDC_PERFMON21_PERFCOUNTER_CNTL                                                                0x08c7
11571 #define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX                                                       3
11572 #define mmDC_PERFMON21_PERFCOUNTER_CNTL2                                                               0x08c8
11573 #define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX                                                      3
11574 #define mmDC_PERFMON21_PERFCOUNTER_STATE                                                               0x08c9
11575 #define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX                                                      3
11576 #define mmDC_PERFMON21_PERFMON_CNTL                                                                    0x08ca
11577 #define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX                                                           3
11578 #define mmDC_PERFMON21_PERFMON_CNTL2                                                                   0x08cb
11579 #define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX                                                          3
11580 #define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC                                                         0x08cc
11581 #define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3
11582 #define mmDC_PERFMON21_PERFMON_CVALUE_LOW                                                              0x08cd
11583 #define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX                                                     3
11584 #define mmDC_PERFMON21_PERFMON_HI                                                                      0x08ce
11585 #define mmDC_PERFMON21_PERFMON_HI_BASE_IDX                                                             3
11586 #define mmDC_PERFMON21_PERFMON_LOW                                                                     0x08cf
11587 #define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX                                                            3
11588 
11589 
11590 // addressBlock: dce_dc_opp_abm0_dispdec
11591 // base address: 0x0
11592 #define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a
11593 #define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
11594 #define mmABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b
11595 #define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
11596 #define mmABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c
11597 #define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
11598 #define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d
11599 #define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
11600 #define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e
11601 #define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
11602 #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f
11603 #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
11604 #define mmABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80
11605 #define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
11606 #define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81
11607 #define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
11608 #define mmABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82
11609 #define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
11610 #define mmABM0_DC_ABM1_CNTL                                                                            0x0e83
11611 #define mmABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3
11612 #define mmABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84
11613 #define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
11614 #define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8e
11615 #define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
11616 #define mmABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8f
11617 #define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
11618 #define mmABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e90
11619 #define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
11620 #define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e91
11621 #define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
11622 #define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e92
11623 #define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
11624 #define mmABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e93
11625 #define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
11626 #define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e94
11627 #define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
11628 #define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e95
11629 #define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
11630 #define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e96
11631 #define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
11632 #define mmABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e97
11633 #define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
11634 #define mmABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e98
11635 #define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
11636 #define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e99
11637 #define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
11638 #define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e9a
11639 #define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
11640 #define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e9b
11641 #define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
11642 #define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e9c
11643 #define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
11644 #define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9d
11645 #define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
11646 #define mmABM0_DC_ABM1_HG_RESULT_1                                                                     0x0e9e
11647 #define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
11648 #define mmABM0_DC_ABM1_HG_RESULT_2                                                                     0x0e9f
11649 #define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
11650 #define mmABM0_DC_ABM1_HG_RESULT_3                                                                     0x0ea0
11651 #define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
11652 #define mmABM0_DC_ABM1_HG_RESULT_4                                                                     0x0ea1
11653 #define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
11654 #define mmABM0_DC_ABM1_HG_RESULT_5                                                                     0x0ea2
11655 #define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
11656 #define mmABM0_DC_ABM1_HG_RESULT_6                                                                     0x0ea3
11657 #define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
11658 #define mmABM0_DC_ABM1_HG_RESULT_7                                                                     0x0ea4
11659 #define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
11660 #define mmABM0_DC_ABM1_HG_RESULT_8                                                                     0x0ea5
11661 #define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
11662 #define mmABM0_DC_ABM1_HG_RESULT_9                                                                     0x0ea6
11663 #define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
11664 #define mmABM0_DC_ABM1_HG_RESULT_10                                                                    0x0ea7
11665 #define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
11666 #define mmABM0_DC_ABM1_HG_RESULT_11                                                                    0x0ea8
11667 #define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
11668 #define mmABM0_DC_ABM1_HG_RESULT_12                                                                    0x0ea9
11669 #define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
11670 #define mmABM0_DC_ABM1_HG_RESULT_13                                                                    0x0eaa
11671 #define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
11672 #define mmABM0_DC_ABM1_HG_RESULT_14                                                                    0x0eab
11673 #define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
11674 #define mmABM0_DC_ABM1_HG_RESULT_15                                                                    0x0eac
11675 #define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
11676 #define mmABM0_DC_ABM1_HG_RESULT_16                                                                    0x0ead
11677 #define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
11678 #define mmABM0_DC_ABM1_HG_RESULT_17                                                                    0x0eae
11679 #define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
11680 #define mmABM0_DC_ABM1_HG_RESULT_18                                                                    0x0eaf
11681 #define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
11682 #define mmABM0_DC_ABM1_HG_RESULT_19                                                                    0x0eb0
11683 #define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
11684 #define mmABM0_DC_ABM1_HG_RESULT_20                                                                    0x0eb1
11685 #define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
11686 #define mmABM0_DC_ABM1_HG_RESULT_21                                                                    0x0eb2
11687 #define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
11688 #define mmABM0_DC_ABM1_HG_RESULT_22                                                                    0x0eb3
11689 #define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
11690 #define mmABM0_DC_ABM1_HG_RESULT_23                                                                    0x0eb4
11691 #define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
11692 #define mmABM0_DC_ABM1_HG_RESULT_24                                                                    0x0eb5
11693 #define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
11694 #define mmABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0eb6
11695 #define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
11696 
11697 
11698 // addressBlock: dce_dc_opp_abm1_dispdec
11699 // base address: 0x104
11700 #define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb
11701 #define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
11702 #define mmABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc
11703 #define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
11704 #define mmABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd
11705 #define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
11706 #define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe
11707 #define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
11708 #define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf
11709 #define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
11710 #define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0
11711 #define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
11712 #define mmABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1
11713 #define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
11714 #define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2
11715 #define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
11716 #define mmABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3
11717 #define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
11718 #define mmABM1_DC_ABM1_CNTL                                                                            0x0ec4
11719 #define mmABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3
11720 #define mmABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5
11721 #define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
11722 #define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecf
11723 #define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
11724 #define mmABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ed0
11725 #define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
11726 #define mmABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ed1
11727 #define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
11728 #define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ed2
11729 #define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
11730 #define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ed3
11731 #define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
11732 #define mmABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed4
11733 #define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
11734 #define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed5
11735 #define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
11736 #define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed6
11737 #define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
11738 #define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed7
11739 #define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
11740 #define mmABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed8
11741 #define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
11742 #define mmABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed9
11743 #define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
11744 #define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0eda
11745 #define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
11746 #define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0edb
11747 #define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
11748 #define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0edc
11749 #define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
11750 #define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0edd
11751 #define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
11752 #define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0ede
11753 #define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
11754 #define mmABM1_DC_ABM1_HG_RESULT_1                                                                     0x0edf
11755 #define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
11756 #define mmABM1_DC_ABM1_HG_RESULT_2                                                                     0x0ee0
11757 #define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
11758 #define mmABM1_DC_ABM1_HG_RESULT_3                                                                     0x0ee1
11759 #define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
11760 #define mmABM1_DC_ABM1_HG_RESULT_4                                                                     0x0ee2
11761 #define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
11762 #define mmABM1_DC_ABM1_HG_RESULT_5                                                                     0x0ee3
11763 #define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
11764 #define mmABM1_DC_ABM1_HG_RESULT_6                                                                     0x0ee4
11765 #define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
11766 #define mmABM1_DC_ABM1_HG_RESULT_7                                                                     0x0ee5
11767 #define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
11768 #define mmABM1_DC_ABM1_HG_RESULT_8                                                                     0x0ee6
11769 #define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
11770 #define mmABM1_DC_ABM1_HG_RESULT_9                                                                     0x0ee7
11771 #define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
11772 #define mmABM1_DC_ABM1_HG_RESULT_10                                                                    0x0ee8
11773 #define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
11774 #define mmABM1_DC_ABM1_HG_RESULT_11                                                                    0x0ee9
11775 #define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
11776 #define mmABM1_DC_ABM1_HG_RESULT_12                                                                    0x0eea
11777 #define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
11778 #define mmABM1_DC_ABM1_HG_RESULT_13                                                                    0x0eeb
11779 #define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
11780 #define mmABM1_DC_ABM1_HG_RESULT_14                                                                    0x0eec
11781 #define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
11782 #define mmABM1_DC_ABM1_HG_RESULT_15                                                                    0x0eed
11783 #define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
11784 #define mmABM1_DC_ABM1_HG_RESULT_16                                                                    0x0eee
11785 #define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
11786 #define mmABM1_DC_ABM1_HG_RESULT_17                                                                    0x0eef
11787 #define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
11788 #define mmABM1_DC_ABM1_HG_RESULT_18                                                                    0x0ef0
11789 #define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
11790 #define mmABM1_DC_ABM1_HG_RESULT_19                                                                    0x0ef1
11791 #define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
11792 #define mmABM1_DC_ABM1_HG_RESULT_20                                                                    0x0ef2
11793 #define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
11794 #define mmABM1_DC_ABM1_HG_RESULT_21                                                                    0x0ef3
11795 #define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
11796 #define mmABM1_DC_ABM1_HG_RESULT_22                                                                    0x0ef4
11797 #define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
11798 #define mmABM1_DC_ABM1_HG_RESULT_23                                                                    0x0ef5
11799 #define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
11800 #define mmABM1_DC_ABM1_HG_RESULT_24                                                                    0x0ef6
11801 #define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
11802 #define mmABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ef7
11803 #define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
11804 
11805 
11806 // addressBlock: dce_dc_opp_abm2_dispdec
11807 // base address: 0x208
11808 #define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0efc
11809 #define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
11810 #define mmABM2_BL1_PWM_USER_LEVEL                                                                      0x0efd
11811 #define mmABM2_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
11812 #define mmABM2_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0efe
11813 #define mmABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
11814 #define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0eff
11815 #define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
11816 #define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f00
11817 #define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
11818 #define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f01
11819 #define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
11820 #define mmABM2_BL1_PWM_ABM_CNTL                                                                        0x0f02
11821 #define mmABM2_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
11822 #define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f03
11823 #define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
11824 #define mmABM2_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f04
11825 #define mmABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
11826 #define mmABM2_DC_ABM1_CNTL                                                                            0x0f05
11827 #define mmABM2_DC_ABM1_CNTL_BASE_IDX                                                                   3
11828 #define mmABM2_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f06
11829 #define mmABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
11830 #define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f10
11831 #define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
11832 #define mmABM2_DC_ABM1_HG_MISC_CTRL                                                                    0x0f11
11833 #define mmABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
11834 #define mmABM2_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f12
11835 #define mmABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
11836 #define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f13
11837 #define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
11838 #define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f14
11839 #define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
11840 #define mmABM2_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f15
11841 #define mmABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
11842 #define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f16
11843 #define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
11844 #define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f17
11845 #define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
11846 #define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f18
11847 #define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
11848 #define mmABM2_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f19
11849 #define mmABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
11850 #define mmABM2_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f1a
11851 #define mmABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
11852 #define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f1b
11853 #define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
11854 #define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f1c
11855 #define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
11856 #define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f1d
11857 #define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
11858 #define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f1e
11859 #define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
11860 #define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f1f
11861 #define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
11862 #define mmABM2_DC_ABM1_HG_RESULT_1                                                                     0x0f20
11863 #define mmABM2_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
11864 #define mmABM2_DC_ABM1_HG_RESULT_2                                                                     0x0f21
11865 #define mmABM2_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
11866 #define mmABM2_DC_ABM1_HG_RESULT_3                                                                     0x0f22
11867 #define mmABM2_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
11868 #define mmABM2_DC_ABM1_HG_RESULT_4                                                                     0x0f23
11869 #define mmABM2_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
11870 #define mmABM2_DC_ABM1_HG_RESULT_5                                                                     0x0f24
11871 #define mmABM2_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
11872 #define mmABM2_DC_ABM1_HG_RESULT_6                                                                     0x0f25
11873 #define mmABM2_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
11874 #define mmABM2_DC_ABM1_HG_RESULT_7                                                                     0x0f26
11875 #define mmABM2_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
11876 #define mmABM2_DC_ABM1_HG_RESULT_8                                                                     0x0f27
11877 #define mmABM2_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
11878 #define mmABM2_DC_ABM1_HG_RESULT_9                                                                     0x0f28
11879 #define mmABM2_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
11880 #define mmABM2_DC_ABM1_HG_RESULT_10                                                                    0x0f29
11881 #define mmABM2_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
11882 #define mmABM2_DC_ABM1_HG_RESULT_11                                                                    0x0f2a
11883 #define mmABM2_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
11884 #define mmABM2_DC_ABM1_HG_RESULT_12                                                                    0x0f2b
11885 #define mmABM2_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
11886 #define mmABM2_DC_ABM1_HG_RESULT_13                                                                    0x0f2c
11887 #define mmABM2_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
11888 #define mmABM2_DC_ABM1_HG_RESULT_14                                                                    0x0f2d
11889 #define mmABM2_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
11890 #define mmABM2_DC_ABM1_HG_RESULT_15                                                                    0x0f2e
11891 #define mmABM2_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
11892 #define mmABM2_DC_ABM1_HG_RESULT_16                                                                    0x0f2f
11893 #define mmABM2_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
11894 #define mmABM2_DC_ABM1_HG_RESULT_17                                                                    0x0f30
11895 #define mmABM2_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
11896 #define mmABM2_DC_ABM1_HG_RESULT_18                                                                    0x0f31
11897 #define mmABM2_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
11898 #define mmABM2_DC_ABM1_HG_RESULT_19                                                                    0x0f32
11899 #define mmABM2_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
11900 #define mmABM2_DC_ABM1_HG_RESULT_20                                                                    0x0f33
11901 #define mmABM2_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
11902 #define mmABM2_DC_ABM1_HG_RESULT_21                                                                    0x0f34
11903 #define mmABM2_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
11904 #define mmABM2_DC_ABM1_HG_RESULT_22                                                                    0x0f35
11905 #define mmABM2_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
11906 #define mmABM2_DC_ABM1_HG_RESULT_23                                                                    0x0f36
11907 #define mmABM2_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
11908 #define mmABM2_DC_ABM1_HG_RESULT_24                                                                    0x0f37
11909 #define mmABM2_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
11910 #define mmABM2_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f38
11911 #define mmABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
11912 
11913 
11914 // addressBlock: dce_dc_opp_abm3_dispdec
11915 // base address: 0x30c
11916 #define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f3d
11917 #define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
11918 #define mmABM3_BL1_PWM_USER_LEVEL                                                                      0x0f3e
11919 #define mmABM3_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
11920 #define mmABM3_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f3f
11921 #define mmABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
11922 #define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f40
11923 #define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
11924 #define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f41
11925 #define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
11926 #define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f42
11927 #define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
11928 #define mmABM3_BL1_PWM_ABM_CNTL                                                                        0x0f43
11929 #define mmABM3_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
11930 #define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f44
11931 #define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
11932 #define mmABM3_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f45
11933 #define mmABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
11934 #define mmABM3_DC_ABM1_CNTL                                                                            0x0f46
11935 #define mmABM3_DC_ABM1_CNTL_BASE_IDX                                                                   3
11936 #define mmABM3_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f47
11937 #define mmABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
11938 #define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f51
11939 #define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
11940 #define mmABM3_DC_ABM1_HG_MISC_CTRL                                                                    0x0f52
11941 #define mmABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
11942 #define mmABM3_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f53
11943 #define mmABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
11944 #define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f54
11945 #define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
11946 #define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f55
11947 #define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
11948 #define mmABM3_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f56
11949 #define mmABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
11950 #define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f57
11951 #define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
11952 #define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f58
11953 #define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
11954 #define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f59
11955 #define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
11956 #define mmABM3_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f5a
11957 #define mmABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
11958 #define mmABM3_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f5b
11959 #define mmABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
11960 #define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f5c
11961 #define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
11962 #define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f5d
11963 #define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
11964 #define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f5e
11965 #define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
11966 #define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f5f
11967 #define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
11968 #define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f60
11969 #define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
11970 #define mmABM3_DC_ABM1_HG_RESULT_1                                                                     0x0f61
11971 #define mmABM3_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
11972 #define mmABM3_DC_ABM1_HG_RESULT_2                                                                     0x0f62
11973 #define mmABM3_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
11974 #define mmABM3_DC_ABM1_HG_RESULT_3                                                                     0x0f63
11975 #define mmABM3_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
11976 #define mmABM3_DC_ABM1_HG_RESULT_4                                                                     0x0f64
11977 #define mmABM3_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
11978 #define mmABM3_DC_ABM1_HG_RESULT_5                                                                     0x0f65
11979 #define mmABM3_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
11980 #define mmABM3_DC_ABM1_HG_RESULT_6                                                                     0x0f66
11981 #define mmABM3_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
11982 #define mmABM3_DC_ABM1_HG_RESULT_7                                                                     0x0f67
11983 #define mmABM3_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
11984 #define mmABM3_DC_ABM1_HG_RESULT_8                                                                     0x0f68
11985 #define mmABM3_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
11986 #define mmABM3_DC_ABM1_HG_RESULT_9                                                                     0x0f69
11987 #define mmABM3_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
11988 #define mmABM3_DC_ABM1_HG_RESULT_10                                                                    0x0f6a
11989 #define mmABM3_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
11990 #define mmABM3_DC_ABM1_HG_RESULT_11                                                                    0x0f6b
11991 #define mmABM3_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
11992 #define mmABM3_DC_ABM1_HG_RESULT_12                                                                    0x0f6c
11993 #define mmABM3_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
11994 #define mmABM3_DC_ABM1_HG_RESULT_13                                                                    0x0f6d
11995 #define mmABM3_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
11996 #define mmABM3_DC_ABM1_HG_RESULT_14                                                                    0x0f6e
11997 #define mmABM3_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
11998 #define mmABM3_DC_ABM1_HG_RESULT_15                                                                    0x0f6f
11999 #define mmABM3_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
12000 #define mmABM3_DC_ABM1_HG_RESULT_16                                                                    0x0f70
12001 #define mmABM3_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
12002 #define mmABM3_DC_ABM1_HG_RESULT_17                                                                    0x0f71
12003 #define mmABM3_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
12004 #define mmABM3_DC_ABM1_HG_RESULT_18                                                                    0x0f72
12005 #define mmABM3_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
12006 #define mmABM3_DC_ABM1_HG_RESULT_19                                                                    0x0f73
12007 #define mmABM3_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
12008 #define mmABM3_DC_ABM1_HG_RESULT_20                                                                    0x0f74
12009 #define mmABM3_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
12010 #define mmABM3_DC_ABM1_HG_RESULT_21                                                                    0x0f75
12011 #define mmABM3_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
12012 #define mmABM3_DC_ABM1_HG_RESULT_22                                                                    0x0f76
12013 #define mmABM3_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
12014 #define mmABM3_DC_ABM1_HG_RESULT_23                                                                    0x0f77
12015 #define mmABM3_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
12016 #define mmABM3_DC_ABM1_HG_RESULT_24                                                                    0x0f78
12017 #define mmABM3_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
12018 #define mmABM3_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f79
12019 #define mmABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
12020 
12021 
12022 // addressBlock: vga_vgaseqind
12023 // base address: 0x0
12024 #define ixSEQ00                                                                                        0x0000
12025 #define ixSEQ01                                                                                        0x0001
12026 #define ixSEQ02                                                                                        0x0002
12027 #define ixSEQ03                                                                                        0x0003
12028 #define ixSEQ04                                                                                        0x0004
12029 
12030 
12031 // addressBlock: vga_vgacrtind
12032 // base address: 0x0
12033 #define ixCRT00                                                                                        0x0000
12034 #define ixCRT01                                                                                        0x0001
12035 #define ixCRT02                                                                                        0x0002
12036 #define ixCRT03                                                                                        0x0003
12037 #define ixCRT04                                                                                        0x0004
12038 #define ixCRT05                                                                                        0x0005
12039 #define ixCRT06                                                                                        0x0006
12040 #define ixCRT07                                                                                        0x0007
12041 #define ixCRT08                                                                                        0x0008
12042 #define ixCRT09                                                                                        0x0009
12043 #define ixCRT0A                                                                                        0x000a
12044 #define ixCRT0B                                                                                        0x000b
12045 #define ixCRT0C                                                                                        0x000c
12046 #define ixCRT0D                                                                                        0x000d
12047 #define ixCRT0E                                                                                        0x000e
12048 #define ixCRT0F                                                                                        0x000f
12049 #define ixCRT10                                                                                        0x0010
12050 #define ixCRT11                                                                                        0x0011
12051 #define ixCRT12                                                                                        0x0012
12052 #define ixCRT13                                                                                        0x0013
12053 #define ixCRT14                                                                                        0x0014
12054 #define ixCRT15                                                                                        0x0015
12055 #define ixCRT16                                                                                        0x0016
12056 #define ixCRT17                                                                                        0x0017
12057 #define ixCRT18                                                                                        0x0018
12058 #define ixCRT1E                                                                                        0x001e
12059 #define ixCRT1F                                                                                        0x001f
12060 #define ixCRT22                                                                                        0x0022
12061 
12062 
12063 // addressBlock: vga_vgagrphind
12064 // base address: 0x0
12065 #define ixGRA00                                                                                        0x0000
12066 #define ixGRA01                                                                                        0x0001
12067 #define ixGRA02                                                                                        0x0002
12068 #define ixGRA03                                                                                        0x0003
12069 #define ixGRA04                                                                                        0x0004
12070 #define ixGRA05                                                                                        0x0005
12071 #define ixGRA06                                                                                        0x0006
12072 #define ixGRA07                                                                                        0x0007
12073 #define ixGRA08                                                                                        0x0008
12074 
12075 
12076 // addressBlock: vga_vgaattrind
12077 // base address: 0x0
12078 #define ixATTR00                                                                                       0x0000
12079 #define ixATTR01                                                                                       0x0001
12080 #define ixATTR02                                                                                       0x0002
12081 #define ixATTR03                                                                                       0x0003
12082 #define ixATTR04                                                                                       0x0004
12083 #define ixATTR05                                                                                       0x0005
12084 #define ixATTR06                                                                                       0x0006
12085 #define ixATTR07                                                                                       0x0007
12086 #define ixATTR08                                                                                       0x0008
12087 #define ixATTR09                                                                                       0x0009
12088 #define ixATTR0A                                                                                       0x000a
12089 #define ixATTR0B                                                                                       0x000b
12090 #define ixATTR0C                                                                                       0x000c
12091 #define ixATTR0D                                                                                       0x000d
12092 #define ixATTR0E                                                                                       0x000e
12093 #define ixATTR0F                                                                                       0x000f
12094 #define ixATTR10                                                                                       0x0010
12095 #define ixATTR11                                                                                       0x0011
12096 #define ixATTR12                                                                                       0x0012
12097 #define ixATTR13                                                                                       0x0013
12098 #define ixATTR14                                                                                       0x0014
12099 
12100 
12101 // addressBlock: azendpoint_f2codecind
12102 // base address: 0x0
12103 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
12104 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
12105 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
12106 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
12107 #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
12108 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
12109 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
12110 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
12111 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
12112 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
12113 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
12114 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
12115 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
12116 #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
12117 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
12118 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
12119 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
12120 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
12121 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
12122 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
12123 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
12124 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
12125 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
12126 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
12127 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
12128 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
12129 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
12130 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
12131 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
12132 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
12133 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
12134 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
12135 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
12136 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
12137 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
12138 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
12139 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
12140 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
12141 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
12142 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
12143 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
12144 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
12145 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
12146 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
12147 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
12148 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
12149 #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
12150 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
12151 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
12152 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
12153 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
12154 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
12155 #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
12156 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
12157 #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
12158 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
12159 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
12160 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
12161 
12162 
12163 // addressBlock: azendpoint_descriptorind
12164 // base address: 0x0
12165 #define ixAUDIO_DESCRIPTOR0                                                                            0x0001
12166 #define ixAUDIO_DESCRIPTOR1                                                                            0x0002
12167 #define ixAUDIO_DESCRIPTOR2                                                                            0x0003
12168 #define ixAUDIO_DESCRIPTOR3                                                                            0x0004
12169 #define ixAUDIO_DESCRIPTOR4                                                                            0x0005
12170 #define ixAUDIO_DESCRIPTOR5                                                                            0x0006
12171 #define ixAUDIO_DESCRIPTOR6                                                                            0x0007
12172 #define ixAUDIO_DESCRIPTOR7                                                                            0x0008
12173 #define ixAUDIO_DESCRIPTOR8                                                                            0x0009
12174 #define ixAUDIO_DESCRIPTOR9                                                                            0x000a
12175 #define ixAUDIO_DESCRIPTOR10                                                                           0x000b
12176 #define ixAUDIO_DESCRIPTOR11                                                                           0x000c
12177 #define ixAUDIO_DESCRIPTOR12                                                                           0x000d
12178 #define ixAUDIO_DESCRIPTOR13                                                                           0x000e
12179 
12180 
12181 // addressBlock: azendpoint_sinkinfoind
12182 // base address: 0x0
12183 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
12184 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
12185 #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
12186 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
12187 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
12188 #define ixSINK_DESCRIPTION0                                                                            0x0005
12189 #define ixSINK_DESCRIPTION1                                                                            0x0006
12190 #define ixSINK_DESCRIPTION2                                                                            0x0007
12191 #define ixSINK_DESCRIPTION3                                                                            0x0008
12192 #define ixSINK_DESCRIPTION4                                                                            0x0009
12193 #define ixSINK_DESCRIPTION5                                                                            0x000a
12194 #define ixSINK_DESCRIPTION6                                                                            0x000b
12195 #define ixSINK_DESCRIPTION7                                                                            0x000c
12196 #define ixSINK_DESCRIPTION8                                                                            0x000d
12197 #define ixSINK_DESCRIPTION9                                                                            0x000e
12198 #define ixSINK_DESCRIPTION10                                                                           0x000f
12199 #define ixSINK_DESCRIPTION11                                                                           0x0010
12200 #define ixSINK_DESCRIPTION12                                                                           0x0011
12201 #define ixSINK_DESCRIPTION13                                                                           0x0012
12202 #define ixSINK_DESCRIPTION14                                                                           0x0013
12203 #define ixSINK_DESCRIPTION15                                                                           0x0014
12204 #define ixSINK_DESCRIPTION16                                                                           0x0015
12205 #define ixSINK_DESCRIPTION17                                                                           0x0016
12206 
12207 
12208 // addressBlock: azf0controller_azinputcrc0resultind
12209 // base address: 0x0
12210 #define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
12211 #define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
12212 #define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
12213 #define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
12214 #define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
12215 #define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
12216 #define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
12217 #define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
12218 
12219 
12220 // addressBlock: azf0controller_azinputcrc1resultind
12221 // base address: 0x0
12222 #define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
12223 #define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
12224 #define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
12225 #define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
12226 #define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
12227 #define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
12228 #define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
12229 #define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
12230 
12231 
12232 // addressBlock: azf0controller_azcrc0resultind
12233 // base address: 0x0
12234 #define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
12235 #define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
12236 #define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
12237 #define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
12238 #define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
12239 #define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
12240 #define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
12241 #define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
12242 
12243 
12244 // addressBlock: azf0controller_azcrc1resultind
12245 // base address: 0x0
12246 #define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
12247 #define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
12248 #define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
12249 #define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
12250 #define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
12251 #define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
12252 #define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
12253 #define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
12254 
12255 
12256 // addressBlock: azinputendpoint_f2codecind
12257 // base address: 0x0
12258 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
12259 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
12260 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
12261 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
12262 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
12263 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
12264 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
12265 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
12266 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
12267 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
12268 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
12269 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
12270 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
12271 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
12272 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
12273 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
12274 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
12275 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
12276 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
12277 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
12278 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
12279 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
12280 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
12281 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
12282 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
12283 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
12284 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
12285 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
12286 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
12287 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
12288 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
12289 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
12290 
12291 
12292 // addressBlock: azroot_f2codecind
12293 // base address: 0x0
12294 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
12295 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
12296 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
12297 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
12298 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
12299 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
12300 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
12301 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
12302 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
12303 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
12304 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
12305 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
12306 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
12307 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
12308 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
12309 
12310 
12311 // addressBlock: azf0stream0_streamind
12312 // base address: 0x0
12313 #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12314 #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12315 #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12316 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12317 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12318 
12319 
12320 // addressBlock: azf0stream1_streamind
12321 // base address: 0x0
12322 #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12323 #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12324 #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12325 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12326 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12327 
12328 
12329 // addressBlock: azf0stream2_streamind
12330 // base address: 0x0
12331 #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12332 #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12333 #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12334 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12335 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12336 
12337 
12338 // addressBlock: azf0stream3_streamind
12339 // base address: 0x0
12340 #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12341 #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12342 #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12343 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12344 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12345 
12346 
12347 // addressBlock: azf0stream4_streamind
12348 // base address: 0x0
12349 #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12350 #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12351 #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12352 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12353 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12354 
12355 
12356 // addressBlock: azf0stream5_streamind
12357 // base address: 0x0
12358 #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12359 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12360 #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12361 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12362 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12363 
12364 
12365 // addressBlock: azf0stream6_streamind
12366 // base address: 0x0
12367 #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12368 #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12369 #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12370 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12371 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12372 
12373 
12374 // addressBlock: azf0stream7_streamind
12375 // base address: 0x0
12376 #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12377 #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12378 #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12379 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12380 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12381 
12382 
12383 // addressBlock: azf0stream8_streamind
12384 // base address: 0x0
12385 #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12386 #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12387 #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12388 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12389 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12390 
12391 
12392 // addressBlock: azf0stream9_streamind
12393 // base address: 0x0
12394 #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12395 #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12396 #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12397 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12398 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12399 
12400 
12401 // addressBlock: azf0stream10_streamind
12402 // base address: 0x0
12403 #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
12404 #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
12405 #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
12406 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
12407 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
12408 
12409 
12410 // addressBlock: azf0stream11_streamind
12411 // base address: 0x0
12412 #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
12413 #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
12414 #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
12415 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
12416 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
12417 
12418 
12419 // addressBlock: azf0stream12_streamind
12420 // base address: 0x0
12421 #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
12422 #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
12423 #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
12424 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
12425 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
12426 
12427 
12428 // addressBlock: azf0stream13_streamind
12429 // base address: 0x0
12430 #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
12431 #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
12432 #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
12433 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
12434 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
12435 
12436 
12437 // addressBlock: azf0stream14_streamind
12438 // base address: 0x0
12439 #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
12440 #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
12441 #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
12442 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
12443 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
12444 
12445 
12446 // addressBlock: azf0stream15_streamind
12447 // base address: 0x0
12448 #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
12449 #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
12450 #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
12451 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
12452 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
12453 
12454 
12455 // addressBlock: azf0endpoint0_endpointind
12456 // base address: 0x0
12457 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
12458 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
12459 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
12460 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
12461 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
12462 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
12463 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
12464 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
12465 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
12466 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
12467 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
12468 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
12469 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
12470 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
12471 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
12472 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
12473 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
12474 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
12475 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
12476 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
12477 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
12478 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
12479 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
12480 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
12481 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
12482 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
12483 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
12484 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
12485 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
12486 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
12487 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
12488 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
12489 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
12490 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
12491 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
12492 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
12493 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
12494 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
12495 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
12496 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
12497 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
12498 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
12499 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
12500 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
12501 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
12502 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
12503 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
12504 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
12505 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
12506 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
12507 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
12508 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
12509 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
12510 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
12511 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
12512 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
12513 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
12514 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
12515 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
12516 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
12517 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
12518 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
12519 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
12520 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
12521 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
12522 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
12523 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
12524 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
12525 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
12526 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
12527 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
12528 
12529 
12530 // addressBlock: azf0endpoint1_endpointind
12531 // base address: 0x0
12532 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
12533 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
12534 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
12535 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
12536 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
12537 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
12538 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
12539 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
12540 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
12541 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
12542 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
12543 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
12544 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
12545 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
12546 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
12547 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
12548 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
12549 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
12550 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
12551 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
12552 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
12553 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
12554 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
12555 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
12556 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
12557 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
12558 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
12559 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
12560 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
12561 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
12562 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
12563 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
12564 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
12565 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
12566 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
12567 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
12568 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
12569 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
12570 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
12571 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
12572 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
12573 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
12574 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
12575 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
12576 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
12577 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
12578 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
12579 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
12580 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
12581 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
12582 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
12583 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
12584 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
12585 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
12586 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
12587 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
12588 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
12589 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
12590 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
12591 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
12592 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
12593 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
12594 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
12595 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
12596 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
12597 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
12598 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
12599 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
12600 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
12601 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
12602 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
12603 
12604 
12605 // addressBlock: azf0endpoint2_endpointind
12606 // base address: 0x0
12607 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
12608 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
12609 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
12610 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
12611 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
12612 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
12613 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
12614 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
12615 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
12616 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
12617 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
12618 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
12619 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
12620 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
12621 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
12622 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
12623 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
12624 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
12625 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
12626 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
12627 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
12628 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
12629 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
12630 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
12631 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
12632 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
12633 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
12634 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
12635 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
12636 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
12637 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
12638 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
12639 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
12640 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
12641 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
12642 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
12643 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
12644 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
12645 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
12646 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
12647 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
12648 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
12649 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
12650 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
12651 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
12652 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
12653 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
12654 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
12655 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
12656 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
12657 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
12658 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
12659 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
12660 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
12661 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
12662 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
12663 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
12664 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
12665 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
12666 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
12667 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
12668 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
12669 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
12670 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
12671 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
12672 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
12673 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
12674 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
12675 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
12676 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
12677 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
12678 
12679 
12680 // addressBlock: azf0endpoint3_endpointind
12681 // base address: 0x0
12682 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
12683 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
12684 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
12685 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
12686 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
12687 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
12688 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
12689 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
12690 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
12691 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
12692 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
12693 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
12694 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
12695 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
12696 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
12697 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
12698 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
12699 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
12700 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
12701 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
12702 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
12703 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
12704 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
12705 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
12706 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
12707 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
12708 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
12709 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
12710 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
12711 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
12712 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
12713 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
12714 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
12715 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
12716 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
12717 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
12718 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
12719 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
12720 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
12721 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
12722 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
12723 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
12724 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
12725 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
12726 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
12727 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
12728 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
12729 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
12730 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
12731 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
12732 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
12733 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
12734 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
12735 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
12736 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
12737 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
12738 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
12739 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
12740 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
12741 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
12742 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
12743 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
12744 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
12745 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
12746 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
12747 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
12748 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
12749 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
12750 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
12751 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
12752 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
12753 
12754 
12755 // addressBlock: azf0endpoint4_endpointind
12756 // base address: 0x0
12757 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
12758 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
12759 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
12760 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
12761 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
12762 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
12763 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
12764 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
12765 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
12766 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
12767 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
12768 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
12769 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
12770 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
12771 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
12772 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
12773 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
12774 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
12775 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
12776 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
12777 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
12778 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
12779 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
12780 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
12781 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
12782 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
12783 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
12784 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
12785 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
12786 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
12787 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
12788 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
12789 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
12790 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
12791 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
12792 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
12793 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
12794 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
12795 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
12796 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
12797 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
12798 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
12799 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
12800 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
12801 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
12802 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
12803 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
12804 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
12805 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
12806 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
12807 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
12808 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
12809 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
12810 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
12811 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
12812 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
12813 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
12814 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
12815 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
12816 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
12817 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
12818 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
12819 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
12820 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
12821 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
12822 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
12823 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
12824 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
12825 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
12826 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
12827 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
12828 
12829 
12830 // addressBlock: azf0endpoint5_endpointind
12831 // base address: 0x0
12832 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
12833 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
12834 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
12835 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
12836 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
12837 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
12838 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
12839 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
12840 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
12841 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
12842 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
12843 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
12844 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
12845 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
12846 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
12847 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
12848 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
12849 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
12850 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
12851 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
12852 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
12853 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
12854 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
12855 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
12856 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
12857 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
12858 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
12859 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
12860 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
12861 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
12862 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
12863 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
12864 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
12865 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
12866 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
12867 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
12868 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
12869 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
12870 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
12871 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
12872 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
12873 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
12874 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
12875 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
12876 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
12877 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
12878 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
12879 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
12880 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
12881 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
12882 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
12883 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
12884 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
12885 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
12886 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
12887 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
12888 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
12889 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
12890 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
12891 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
12892 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
12893 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
12894 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
12895 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
12896 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
12897 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
12898 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
12899 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
12900 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
12901 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
12902 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
12903 
12904 
12905 // addressBlock: azf0endpoint6_endpointind
12906 // base address: 0x0
12907 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
12908 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
12909 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
12910 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
12911 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
12912 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
12913 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
12914 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
12915 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
12916 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
12917 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
12918 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
12919 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
12920 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
12921 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
12922 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
12923 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
12924 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
12925 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
12926 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
12927 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
12928 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
12929 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
12930 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
12931 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
12932 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
12933 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
12934 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
12935 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
12936 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
12937 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
12938 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
12939 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
12940 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
12941 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
12942 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
12943 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
12944 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
12945 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
12946 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
12947 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
12948 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
12949 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
12950 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
12951 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
12952 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
12953 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
12954 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
12955 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
12956 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
12957 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
12958 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
12959 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
12960 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
12961 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
12962 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
12963 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
12964 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
12965 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
12966 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
12967 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
12968 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
12969 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
12970 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
12971 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
12972 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
12973 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
12974 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
12975 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
12976 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
12977 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
12978 
12979 
12980 // addressBlock: azf0endpoint7_endpointind
12981 // base address: 0x0
12982 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
12983 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
12984 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
12985 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
12986 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
12987 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
12988 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
12989 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
12990 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
12991 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
12992 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
12993 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
12994 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
12995 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
12996 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
12997 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
12998 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
12999 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
13000 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
13001 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
13002 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
13003 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
13004 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
13005 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
13006 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
13007 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
13008 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
13009 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
13010 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
13011 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
13012 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
13013 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
13014 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
13015 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
13016 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
13017 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
13018 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
13019 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
13020 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
13021 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
13022 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
13023 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
13024 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
13025 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
13026 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
13027 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
13028 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
13029 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
13030 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
13031 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
13032 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
13033 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
13034 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
13035 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
13036 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
13037 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
13038 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
13039 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
13040 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
13041 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
13042 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
13043 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
13044 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
13045 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
13046 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
13047 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
13048 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
13049 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
13050 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
13051 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
13052 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
13053 
13054 
13055 // addressBlock: azf0inputendpoint0_inputendpointind
13056 // base address: 0x0
13057 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13058 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13059 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13060 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13061 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13062 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13063 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13064 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13065 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13066 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13067 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13068 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13069 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13070 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13071 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13072 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13073 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13074 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13075 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13076 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13077 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13078 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13079 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13080 
13081 
13082 // addressBlock: azf0inputendpoint1_inputendpointind
13083 // base address: 0x0
13084 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13085 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13086 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13087 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13088 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13089 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13090 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13091 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13092 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13093 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13094 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13095 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13096 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13097 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13098 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13099 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13100 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13101 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13102 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13103 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13104 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13105 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13106 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13107 
13108 
13109 // addressBlock: azf0inputendpoint2_inputendpointind
13110 // base address: 0x0
13111 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13112 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13113 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13114 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13115 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13116 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13117 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13118 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13119 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13120 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13121 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13122 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13123 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13124 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13125 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13126 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13127 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13128 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13129 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13130 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13131 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13132 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13133 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13134 
13135 
13136 // addressBlock: azf0inputendpoint3_inputendpointind
13137 // base address: 0x0
13138 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13139 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13140 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13141 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13142 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13143 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13144 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13145 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13146 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13147 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13148 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13149 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13150 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13151 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13152 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13153 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13154 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13155 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13156 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13157 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13158 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13159 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13160 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13161 
13162 
13163 // addressBlock: azf0inputendpoint4_inputendpointind
13164 // base address: 0x0
13165 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13166 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13167 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13168 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13169 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13170 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13171 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13172 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13173 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13174 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13175 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13176 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13177 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13178 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13179 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13180 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13181 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13182 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13183 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13184 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13185 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13186 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13187 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13188 
13189 
13190 // addressBlock: azf0inputendpoint5_inputendpointind
13191 // base address: 0x0
13192 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13193 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13194 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13195 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13196 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13197 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13198 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13199 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13200 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13201 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13202 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13203 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13204 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13205 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13206 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13207 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13208 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13209 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13210 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13211 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13212 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13213 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13214 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13215 
13216 
13217 // addressBlock: azf0inputendpoint6_inputendpointind
13218 // base address: 0x0
13219 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13220 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13221 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13222 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13223 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13224 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13225 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13226 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13227 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13228 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13229 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13230 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13231 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13232 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13233 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13234 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13235 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13236 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13237 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13238 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13239 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13240 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13241 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13242 
13243 
13244 // addressBlock: azf0inputendpoint7_inputendpointind
13245 // base address: 0x0
13246 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13247 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13248 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13249 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13250 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13251 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13252 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13253 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13254 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13255 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13256 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13257 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13258 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13259 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13260 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13261 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13262 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13263 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13264 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13265 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13266 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13267 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13268 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13269 
13270 
13271 #endif
13272