1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
4 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
5 *
6 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
7 * but this keeps the ISA-Bridge and slots alive.
8 *
9 */
10
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/ide.h>
16 #include <linux/init.h>
17
18 #define DRV_NAME "slc90e66"
19
20 static DEFINE_SPINLOCK(slc90e66_lock);
21
slc90e66_set_pio_mode(ide_hwif_t * hwif,ide_drive_t * drive)22 static void slc90e66_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
23 {
24 struct pci_dev *dev = to_pci_dev(hwif->dev);
25 int is_slave = drive->dn & 1;
26 int master_port = hwif->channel ? 0x42 : 0x40;
27 int slave_port = 0x44;
28 unsigned long flags;
29 u16 master_data;
30 u8 slave_data;
31 int control = 0;
32 const u8 pio = drive->pio_mode - XFER_PIO_0;
33
34 /* ISP RTC */
35 static const u8 timings[][2] = {
36 { 0, 0 },
37 { 0, 0 },
38 { 1, 0 },
39 { 2, 1 },
40 { 2, 3 }, };
41
42 spin_lock_irqsave(&slc90e66_lock, flags);
43 pci_read_config_word(dev, master_port, &master_data);
44
45 if (pio > 1)
46 control |= 1; /* Programmable timing on */
47 if (drive->media == ide_disk)
48 control |= 4; /* Prefetch, post write */
49 if (ide_pio_need_iordy(drive, pio))
50 control |= 2; /* IORDY */
51 if (is_slave) {
52 master_data |= 0x4000;
53 master_data &= ~0x0070;
54 if (pio > 1) {
55 /* Set PPE, IE and TIME */
56 master_data |= control << 4;
57 }
58 pci_read_config_byte(dev, slave_port, &slave_data);
59 slave_data &= hwif->channel ? 0x0f : 0xf0;
60 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
61 (hwif->channel ? 4 : 0);
62 } else {
63 master_data &= ~0x3307;
64 if (pio > 1) {
65 /* enable PPE, IE and TIME */
66 master_data |= control;
67 }
68 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
69 }
70 pci_write_config_word(dev, master_port, master_data);
71 if (is_slave)
72 pci_write_config_byte(dev, slave_port, slave_data);
73 spin_unlock_irqrestore(&slc90e66_lock, flags);
74 }
75
slc90e66_set_dma_mode(ide_hwif_t * hwif,ide_drive_t * drive)76 static void slc90e66_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
77 {
78 struct pci_dev *dev = to_pci_dev(hwif->dev);
79 u8 maslave = hwif->channel ? 0x42 : 0x40;
80 int sitre = 0, a_speed = 7 << (drive->dn * 4);
81 int u_speed = 0, u_flag = 1 << drive->dn;
82 u16 reg4042, reg44, reg48, reg4a;
83 const u8 speed = drive->dma_mode;
84
85 pci_read_config_word(dev, maslave, ®4042);
86 sitre = (reg4042 & 0x4000) ? 1 : 0;
87 pci_read_config_word(dev, 0x44, ®44);
88 pci_read_config_word(dev, 0x48, ®48);
89 pci_read_config_word(dev, 0x4a, ®4a);
90
91 if (speed >= XFER_UDMA_0) {
92 u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4);
93
94 if (!(reg48 & u_flag))
95 pci_write_config_word(dev, 0x48, reg48|u_flag);
96 if ((reg4a & a_speed) != u_speed) {
97 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
98 pci_read_config_word(dev, 0x4a, ®4a);
99 pci_write_config_word(dev, 0x4a, reg4a|u_speed);
100 }
101 } else {
102 const u8 mwdma_to_pio[] = { 0, 3, 4 };
103
104 if (reg48 & u_flag)
105 pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
106 if (reg4a & a_speed)
107 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
108
109 if (speed >= XFER_MW_DMA_0)
110 drive->pio_mode =
111 mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
112 else
113 drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
114
115 slc90e66_set_pio_mode(hwif, drive);
116 }
117 }
118
slc90e66_cable_detect(ide_hwif_t * hwif)119 static u8 slc90e66_cable_detect(ide_hwif_t *hwif)
120 {
121 struct pci_dev *dev = to_pci_dev(hwif->dev);
122 u8 reg47 = 0, mask = hwif->channel ? 0x01 : 0x02;
123
124 pci_read_config_byte(dev, 0x47, ®47);
125
126 /* bit[0(1)]: 0:80, 1:40 */
127 return (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
128 }
129
130 static const struct ide_port_ops slc90e66_port_ops = {
131 .set_pio_mode = slc90e66_set_pio_mode,
132 .set_dma_mode = slc90e66_set_dma_mode,
133 .cable_detect = slc90e66_cable_detect,
134 };
135
136 static const struct ide_port_info slc90e66_chipset = {
137 .name = DRV_NAME,
138 .enablebits = { {0x41, 0x80, 0x80}, {0x43, 0x80, 0x80} },
139 .port_ops = &slc90e66_port_ops,
140 .pio_mask = ATA_PIO4,
141 .swdma_mask = ATA_SWDMA2_ONLY,
142 .mwdma_mask = ATA_MWDMA12_ONLY,
143 .udma_mask = ATA_UDMA4,
144 };
145
slc90e66_init_one(struct pci_dev * dev,const struct pci_device_id * id)146 static int slc90e66_init_one(struct pci_dev *dev,
147 const struct pci_device_id *id)
148 {
149 return ide_pci_init_one(dev, &slc90e66_chipset, NULL);
150 }
151
152 static const struct pci_device_id slc90e66_pci_tbl[] = {
153 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 },
154 { 0, },
155 };
156 MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
157
158 static struct pci_driver slc90e66_pci_driver = {
159 .name = "SLC90e66_IDE",
160 .id_table = slc90e66_pci_tbl,
161 .probe = slc90e66_init_one,
162 .remove = ide_pci_remove,
163 .suspend = ide_pci_suspend,
164 .resume = ide_pci_resume,
165 };
166
slc90e66_ide_init(void)167 static int __init slc90e66_ide_init(void)
168 {
169 return ide_pci_register_driver(&slc90e66_pci_driver);
170 }
171
slc90e66_ide_exit(void)172 static void __exit slc90e66_ide_exit(void)
173 {
174 pci_unregister_driver(&slc90e66_pci_driver);
175 }
176
177 module_init(slc90e66_ide_init);
178 module_exit(slc90e66_ide_exit);
179
180 MODULE_AUTHOR("Andre Hedrick");
181 MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
182 MODULE_LICENSE("GPL");
183