1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef GAUDI_MASKS_H_ 9 #define GAUDI_MASKS_H_ 10 11 #include "asic_reg/gaudi_regs.h" 12 13 /* Useful masks for bits in various registers */ 14 #define PCI_DMA_QMAN_ENABLE (\ 15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ 16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \ 17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF))) 18 19 #define QMAN_EXTERNAL_MAKE_TRUSTED (\ 20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \ 21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \ 22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \ 23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1))) 24 25 #define QMAN_INTERNAL_MAKE_TRUSTED (\ 26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \ 27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1))) 28 29 #define HBM_DMA_QMAN_ENABLE (\ 30 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ 31 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \ 32 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F))) 33 34 #define QMAN_MME_ENABLE (\ 35 (FIELD_PREP(MME0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ 36 (FIELD_PREP(MME0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \ 37 (FIELD_PREP(MME0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F))) 38 39 #define QMAN_TPC_ENABLE (\ 40 (FIELD_PREP(TPC0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ 41 (FIELD_PREP(TPC0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \ 42 (FIELD_PREP(TPC0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F))) 43 44 #define NIC_QMAN_ENABLE (\ 45 (FIELD_PREP(NIC0_QM0_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ 46 (FIELD_PREP(NIC0_QM0_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \ 47 (FIELD_PREP(NIC0_QM0_GLBL_CFG0_CP_EN_MASK, 0xF))) 48 49 #define QMAN_UPPER_CP_CGM_PWR_GATE_EN (\ 50 (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \ 51 (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \ 52 (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0x10)) | \ 53 (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1))) 54 55 #define QMAN_COMMON_CP_CGM_PWR_GATE_EN (\ 56 (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \ 57 (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \ 58 (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0xF)) | \ 59 (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1))) 60 61 #define PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ 62 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ 63 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \ 64 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF))) 65 66 #define PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ 67 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ 68 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \ 69 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF))) 70 71 #define HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ 72 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ 73 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \ 74 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F))) 75 76 #define HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ 77 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ 78 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \ 79 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F))) 80 81 #define TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ 82 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ 83 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \ 84 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F))) 85 86 #define TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ 87 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ 88 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \ 89 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F))) 90 91 #define MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ 92 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ 93 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \ 94 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F))) 95 96 #define MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ 97 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ 98 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \ 99 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F))) 100 101 #define NIC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ 102 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ 103 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \ 104 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF))) 105 106 #define NIC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ 107 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ 108 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \ 109 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF))) 110 111 #define QMAN_CGM1_PWR_GATE_EN (FIELD_PREP(DMA0_QM_CGM_CFG1_MASK_TH_MASK, 0xA)) 112 113 /* RESET registers configuration */ 114 #define CFG_RST_L_PSOC_MASK BIT_MASK(0) 115 #define CFG_RST_L_PCIE_MASK BIT_MASK(1) 116 #define CFG_RST_L_PCIE_IF_MASK BIT_MASK(2) 117 #define CFG_RST_L_HBM_S_PLL_MASK BIT_MASK(3) 118 #define CFG_RST_L_TPC_S_PLL_MASK BIT_MASK(4) 119 #define CFG_RST_L_MME_S_PLL_MASK BIT_MASK(5) 120 #define CFG_RST_L_CPU_PLL_MASK BIT_MASK(6) 121 #define CFG_RST_L_PCIE_PLL_MASK BIT_MASK(7) 122 #define CFG_RST_L_NIC_S_PLL_MASK BIT_MASK(8) 123 #define CFG_RST_L_HBM_N_PLL_MASK BIT_MASK(9) 124 #define CFG_RST_L_TPC_N_PLL_MASK BIT_MASK(10) 125 #define CFG_RST_L_MME_N_PLL_MASK BIT_MASK(11) 126 #define CFG_RST_L_NIC_N_PLL_MASK BIT_MASK(12) 127 #define CFG_RST_L_DMA_W_PLL_MASK BIT_MASK(13) 128 #define CFG_RST_L_SIF_W_PLL_MASK BIT_MASK(14) 129 #define CFG_RST_L_MESH_W_PLL_MASK BIT_MASK(15) 130 #define CFG_RST_L_SRAM_W_PLL_MASK BIT_MASK(16) 131 #define CFG_RST_L_DMA_E_PLL_MASK BIT_MASK(17) 132 #define CFG_RST_L_SIF_E_PLL_MASK BIT_MASK(18) 133 #define CFG_RST_L_MESH_E_PLL_MASK BIT_MASK(19) 134 #define CFG_RST_L_SRAM_E_PLL_MASK BIT_MASK(20) 135 136 #define CFG_RST_L_IF_1_MASK BIT_MASK(21) 137 #define CFG_RST_L_IF_0_MASK BIT_MASK(22) 138 #define CFG_RST_L_IF_2_MASK BIT_MASK(23) 139 #define CFG_RST_L_IF_3_MASK BIT_MASK(24) 140 #define CFG_RST_L_IF_MASK GENMASK(24, 21) 141 142 #define CFG_RST_L_TPC_0_MASK BIT_MASK(25) 143 #define CFG_RST_L_TPC_1_MASK BIT_MASK(26) 144 #define CFG_RST_L_TPC_2_MASK BIT_MASK(27) 145 #define CFG_RST_L_TPC_3_MASK BIT_MASK(28) 146 #define CFG_RST_L_TPC_4_MASK BIT_MASK(29) 147 #define CFG_RST_L_TPC_5_MASK BIT_MASK(30) 148 #define CFG_RST_L_TPC_6_MASK BIT_MASK(31) 149 #define CFG_RST_L_TPC_MASK GENMASK(31, 25) 150 151 #define CFG_RST_H_TPC_7_MASK BIT_MASK(0) 152 153 #define CFG_RST_H_MME_0_MASK BIT_MASK(1) 154 #define CFG_RST_H_MME_1_MASK BIT_MASK(2) 155 #define CFG_RST_H_MME_2_MASK BIT_MASK(3) 156 #define CFG_RST_H_MME_3_MASK BIT_MASK(4) 157 #define CFG_RST_H_MME_MASK GENMASK(4, 1) 158 159 #define CFG_RST_H_HBM_0_MASK BIT_MASK(5) 160 #define CFG_RST_H_HBM_1_MASK BIT_MASK(6) 161 #define CFG_RST_H_HBM_2_MASK BIT_MASK(7) 162 #define CFG_RST_H_HBM_3_MASK BIT_MASK(8) 163 #define CFG_RST_H_HBM_MASK GENMASK(8, 5) 164 165 #define CFG_RST_H_NIC_0_MASK BIT_MASK(9) 166 #define CFG_RST_H_NIC_1_MASK BIT_MASK(10) 167 #define CFG_RST_H_NIC_2_MASK BIT_MASK(11) 168 #define CFG_RST_H_NIC_3_MASK BIT_MASK(12) 169 #define CFG_RST_H_NIC_4_MASK BIT_MASK(13) 170 #define CFG_RST_H_NIC_MASK GENMASK(13, 9) 171 172 #define CFG_RST_H_SM_0_MASK BIT_MASK(14) 173 #define CFG_RST_H_SM_1_MASK BIT_MASK(15) 174 #define CFG_RST_H_SM_2_MASK BIT_MASK(16) 175 #define CFG_RST_H_SM_3_MASK BIT_MASK(17) 176 #define CFG_RST_H_SM_MASK GENMASK(17, 14) 177 178 #define CFG_RST_H_DMA_0_MASK BIT_MASK(18) 179 #define CFG_RST_H_DMA_1_MASK BIT_MASK(19) 180 #define CFG_RST_H_DMA_MASK GENMASK(19, 18) 181 182 #define CFG_RST_H_CPU_MASK BIT_MASK(20) 183 #define CFG_RST_H_MMU_MASK BIT_MASK(21) 184 185 #define UNIT_RST_L_PSOC_SHIFT 0 186 #define UNIT_RST_L_PCIE_SHIFT 1 187 #define UNIT_RST_L_PCIE_IF_SHIFT 2 188 #define UNIT_RST_L_HBM_S_PLL_SHIFT 3 189 #define UNIT_RST_L_TPC_S_PLL_SHIFT 4 190 #define UNIT_RST_L_MME_S_PLL_SHIFT 5 191 #define UNIT_RST_L_CPU_PLL_SHIFT 6 192 #define UNIT_RST_L_PCIE_PLL_SHIFT 7 193 #define UNIT_RST_L_NIC_S_PLL_SHIFT 8 194 #define UNIT_RST_L_HBM_N_PLL_SHIFT 9 195 #define UNIT_RST_L_TPC_N_PLL_SHIFT 10 196 #define UNIT_RST_L_MME_N_PLL_SHIFT 11 197 #define UNIT_RST_L_NIC_N_PLL_SHIFT 12 198 #define UNIT_RST_L_DMA_W_PLL_SHIFT 13 199 #define UNIT_RST_L_SIF_W_PLL_SHIFT 14 200 #define UNIT_RST_L_MESH_W_PLL_SHIFT 15 201 #define UNIT_RST_L_SRAM_W_PLL_SHIFT 16 202 #define UNIT_RST_L_DMA_E_PLL_SHIFT 17 203 #define UNIT_RST_L_SIF_E_PLL_SHIFT 18 204 #define UNIT_RST_L_MESH_E_PLL_SHIFT 19 205 #define UNIT_RST_L_SRAM_E_PLL_SHIFT 20 206 #define UNIT_RST_L_TPC_0_SHIFT 21 207 #define UNIT_RST_L_TPC_1_SHIFT 22 208 #define UNIT_RST_L_TPC_2_SHIFT 23 209 #define UNIT_RST_L_TPC_3_SHIFT 24 210 #define UNIT_RST_L_TPC_4_SHIFT 25 211 #define UNIT_RST_L_TPC_5_SHIFT 26 212 #define UNIT_RST_L_TPC_6_SHIFT 27 213 #define UNIT_RST_L_TPC_7_SHIFT 28 214 #define UNIT_RST_L_MME_0_SHIFT 29 215 #define UNIT_RST_L_MME_1_SHIFT 30 216 #define UNIT_RST_L_MME_2_SHIFT 31 217 218 #define UNIT_RST_H_MME_3_SHIFT 0 219 #define UNIT_RST_H_HBM_0_SHIFT 1 220 #define UNIT_RST_H_HBM_1_SHIFT 2 221 #define UNIT_RST_H_HBM_2_SHIFT 3 222 #define UNIT_RST_H_HBM_3_SHIFT 4 223 #define UNIT_RST_H_NIC_0_SHIFT 5 224 #define UNIT_RST_H_NIC_1_SHIFT 6 225 #define UNIT_RST_H_NIC_2_SHIFT 7 226 #define UNIT_RST_H_NIC_3_SHIFT 8 227 #define UNIT_RST_H_NIC_4_SHIFT 9 228 #define UNIT_RST_H_SM_0_SHIFT 10 229 #define UNIT_RST_H_SM_1_SHIFT 11 230 #define UNIT_RST_H_SM_2_SHIFT 12 231 #define UNIT_RST_H_SM_3_SHIFT 13 232 #define UNIT_RST_H_IF_0_SHIFT 14 233 #define UNIT_RST_H_IF_1_SHIFT 15 234 #define UNIT_RST_H_IF_2_SHIFT 16 235 #define UNIT_RST_H_IF_3_SHIFT 17 236 #define UNIT_RST_H_DMA_0_SHIFT 18 237 #define UNIT_RST_H_DMA_1_SHIFT 19 238 #define UNIT_RST_H_CPU_SHIFT 20 239 #define UNIT_RST_H_MMU_SHIFT 21 240 241 #define UNIT_RST_H_HBM_MASK ((1 << UNIT_RST_H_HBM_0_SHIFT) | \ 242 (1 << UNIT_RST_H_HBM_1_SHIFT) | \ 243 (1 << UNIT_RST_H_HBM_2_SHIFT) | \ 244 (1 << UNIT_RST_H_HBM_3_SHIFT)) 245 246 #define UNIT_RST_H_NIC_MASK ((1 << UNIT_RST_H_NIC_0_SHIFT) | \ 247 (1 << UNIT_RST_H_NIC_1_SHIFT) | \ 248 (1 << UNIT_RST_H_NIC_2_SHIFT) | \ 249 (1 << UNIT_RST_H_NIC_3_SHIFT) | \ 250 (1 << UNIT_RST_H_NIC_4_SHIFT)) 251 252 #define UNIT_RST_H_SM_MASK ((1 << UNIT_RST_H_SM_0_SHIFT) | \ 253 (1 << UNIT_RST_H_SM_1_SHIFT) | \ 254 (1 << UNIT_RST_H_SM_2_SHIFT) | \ 255 (1 << UNIT_RST_H_SM_3_SHIFT)) 256 257 #define UNIT_RST_H_MME_MASK ((1 << UNIT_RST_H_MME_0_SHIFT) | \ 258 (1 << UNIT_RST_H_MME_1_SHIFT) | \ 259 (1 << UNIT_RST_H_MME_2_SHIFT)) 260 261 #define UNIT_RST_L_MME_MASK (1 << UNIT_RST_L_MME_3_SHIFT) 262 263 #define UNIT_RST_L_IF_MASK ((1 << UNIT_RST_L_IF_0_SHIFT) | \ 264 (1 << UNIT_RST_L_IF_1_SHIFT) | \ 265 (1 << UNIT_RST_L_IF_2_SHIFT) | \ 266 (1 << UNIT_RST_L_IF_3_SHIFT)) 267 268 #define UNIT_RST_L_TPC_MASK ((1 << UNIT_RST_L_TPC_0_SHIFT) | \ 269 (1 << UNIT_RST_L_TPC_1_SHIFT) | \ 270 (1 << UNIT_RST_L_TPC_2_SHIFT) | \ 271 (1 << UNIT_RST_L_TPC_3_SHIFT) | \ 272 (1 << UNIT_RST_L_TPC_4_SHIFT) | \ 273 (1 << UNIT_RST_L_TPC_5_SHIFT) | \ 274 (1 << UNIT_RST_L_TPC_6_SHIFT) | \ 275 (1 << UNIT_RST_L_TPC_7_SHIFT)) 276 277 /* CPU_CA53_CFG_ARM_RST_CONTROL */ 278 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0 279 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3 280 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4 281 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30 282 #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8 283 #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100 284 #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12 285 #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000 286 #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16 287 #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000 288 #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20 289 #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000 290 291 #define CPU_RESET_ASSERT (\ 292 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) 293 294 #define CPU_RESET_CORE0_DEASSERT (\ 295 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\ 296 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\ 297 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\ 298 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) 299 300 /* QM_IDLE_MASK is valid for all engines QM idle check */ 301 #define QM_IDLE_MASK (DMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \ 302 DMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \ 303 DMA0_QM_GLBL_STS0_CP_IDLE_MASK) 304 305 /* CGM_IDLE_MASK is valid for all engines CGM idle check */ 306 #define CGM_IDLE_MASK DMA0_QM_CGM_STS_AGENT_IDLE_MASK 307 308 #define TPC_IDLE_MASK ((1 << TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT) | \ 309 (1 << TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT) | \ 310 (1 << TPC0_CFG_STATUS_IQ_EMPTY_SHIFT) | \ 311 (1 << TPC0_CFG_STATUS_SB_EMPTY_SHIFT) | \ 312 (1 << TPC0_CFG_STATUS_QM_IDLE_SHIFT) | \ 313 (1 << TPC0_CFG_STATUS_QM_RDY_SHIFT)) 314 315 #define MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK 0x80 316 #define MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK 0x100 317 #define MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x1000 318 319 #define MME_ARCH_IDLE_MASK (MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK | \ 320 MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK | \ 321 MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK) 322 323 #define IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) \ 324 ((((qm_glbl_sts0) & QM_IDLE_MASK) == QM_IDLE_MASK) && \ 325 (((qm_cgm_sts) & CGM_IDLE_MASK) == CGM_IDLE_MASK)) 326 327 #define IS_DMA_IDLE(dma_core_sts0) \ 328 !(dma_core_sts0 & DMA0_CORE_STS0_BUSY_MASK) 329 330 #define IS_TPC_IDLE(tpc_cfg_sts) \ 331 (((tpc_cfg_sts) & TPC_IDLE_MASK) == TPC_IDLE_MASK) 332 333 #define IS_MME_IDLE(mme_arch_sts) \ 334 (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK) 335 336 enum axi_id { 337 AXI_ID_MME, 338 AXI_ID_TPC, 339 AXI_ID_DMA, 340 AXI_ID_NIC, /* Local NIC */ 341 AXI_ID_PCI, 342 AXI_ID_CPU, 343 AXI_ID_PSOC, 344 AXI_ID_MMU, 345 AXI_ID_NIC_FT /* Feed-Through NIC */ 346 }; 347 348 /* RAZWI initiator ID is built from the location in the chip and the AXI ID */ 349 350 #define RAZWI_INITIATOR_AXI_ID_SHIFT 20 351 #define RAZWI_INITIATOR_AXI_ID_MASK 0xF 352 #define RAZWI_INITIATOR_X_SHIFT 24 353 #define RAZWI_INITIATOR_X_MASK 0xF 354 #define RAZWI_INITIATOR_Y_SHIFT 28 355 #define RAZWI_INITIATOR_Y_MASK 0x7 356 357 #define RAZWI_INITIATOR_ID_AXI_ID(axi_id) \ 358 (((axi_id) & RAZWI_INITIATOR_AXI_ID_MASK) << \ 359 RAZWI_INITIATOR_AXI_ID_SHIFT) 360 361 #define RAZWI_INITIATOR_ID_X_Y(x, y) \ 362 ((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \ 363 (((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT)) 364 365 #define RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0 RAZWI_INITIATOR_ID_X_Y(1, 1) 366 #define RAZWI_INITIATOR_ID_X_Y_TPC1 RAZWI_INITIATOR_ID_X_Y(2, 1) 367 #define RAZWI_INITIATOR_ID_X_Y_MME0_0 RAZWI_INITIATOR_ID_X_Y(3, 1) 368 #define RAZWI_INITIATOR_ID_X_Y_MME0_1 RAZWI_INITIATOR_ID_X_Y(4, 1) 369 #define RAZWI_INITIATOR_ID_X_Y_MME1_0 RAZWI_INITIATOR_ID_X_Y(5, 1) 370 #define RAZWI_INITIATOR_ID_X_Y_MME1_1 RAZWI_INITIATOR_ID_X_Y(6, 1) 371 #define RAZWI_INITIATOR_ID_X_Y_TPC2 RAZWI_INITIATOR_ID_X_Y(7, 1) 372 #define RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC \ 373 RAZWI_INITIATOR_ID_X_Y(8, 1) 374 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0 RAZWI_INITIATOR_ID_X_Y(0, 1) 375 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0 RAZWI_INITIATOR_ID_X_Y(9, 1) 376 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1 RAZWI_INITIATOR_ID_X_Y(0, 2) 377 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1 RAZWI_INITIATOR_ID_X_Y(9, 2) 378 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0 RAZWI_INITIATOR_ID_X_Y(0, 3) 379 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0 RAZWI_INITIATOR_ID_X_Y(9, 3) 380 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1 RAZWI_INITIATOR_ID_X_Y(0, 4) 381 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1 RAZWI_INITIATOR_ID_X_Y(9, 4) 382 #define RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2 RAZWI_INITIATOR_ID_X_Y(1, 6) 383 #define RAZWI_INITIATOR_ID_X_Y_TPC5 RAZWI_INITIATOR_ID_X_Y(2, 6) 384 #define RAZWI_INITIATOR_ID_X_Y_MME2_0 RAZWI_INITIATOR_ID_X_Y(3, 6) 385 #define RAZWI_INITIATOR_ID_X_Y_MME2_1 RAZWI_INITIATOR_ID_X_Y(4, 6) 386 #define RAZWI_INITIATOR_ID_X_Y_MME3_0 RAZWI_INITIATOR_ID_X_Y(5, 6) 387 #define RAZWI_INITIATOR_ID_X_Y_MME3_1 RAZWI_INITIATOR_ID_X_Y(6, 6) 388 #define RAZWI_INITIATOR_ID_X_Y_TPC6 RAZWI_INITIATOR_ID_X_Y(7, 6) 389 #define RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5 RAZWI_INITIATOR_ID_X_Y(8, 6) 390 391 #define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1 392 #define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1 393 #define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2 394 #define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00 395 396 /* STLB_CACHE_INV */ 397 #define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 398 #define STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF 399 #define STLB_CACHE_INV_INDEX_MASK_SHIFT 8 400 #define STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 401 402 #define MME_ACC_ACC_STALL_R_SHIFT 0 403 #define MME_SBAB_SB_STALL_R_SHIFT 0 404 405 #define PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK 0x700 406 #define PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK 0x7000 407 408 #define PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT 0 409 #define PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT 0 410 411 /* DMA_IF_HBM_CRED_EN */ 412 #define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT 0 413 #define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_MASK 0x1 414 #define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT 1 415 #define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_MASK 0x2 416 417 #define DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT 0 418 #define DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT 0 419 #define DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT 0 420 #define DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT 0 421 422 #define IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT 0 423 #define IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT 0 424 425 #define IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT 0 426 #define IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT 0 427 428 /* MMU_UP_PAGE_ERROR_CAPTURE */ 429 #define MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF 430 #define MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 431 432 /* MMU_UP_ACCESS_ERROR_CAPTURE */ 433 #define MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF 434 #define MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 435 436 #define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 437 #define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 438 #define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 439 440 #define QM_ARB_ERR_MSG_EN_MASK (\ 441 QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\ 442 QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK) 443 444 #define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1 445 #define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2 446 447 #endif /* GAUDI_MASKS_H_ */ 448