1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4 */
5
6 #ifndef __MT7530_H
7 #define __MT7530_H
8
9 #define MT7530_NUM_PORTS 7
10 #define MT7530_CPU_PORT 6
11 #define MT7530_NUM_FDB_RECORDS 2048
12 #define MT7530_ALL_MEMBERS 0xff
13
14 #define MTK_HDR_LEN 4
15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
16
17 enum mt753x_id {
18 ID_MT7530 = 0,
19 ID_MT7621 = 1,
20 ID_MT7531 = 2,
21 };
22
23 #define NUM_TRGMII_CTRL 5
24
25 #define TRGMII_BASE(x) (0x10000 + (x))
26
27 /* Registers to ethsys access */
28 #define ETHSYS_CLKCFG0 0x2c
29 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
30
31 #define SYSC_REG_RSTCTRL 0x34
32 #define RESET_MCM BIT(2)
33
34 /* Registers to mac forward control for unknown frames */
35 #define MT7530_MFC 0x10
36 #define BC_FFP(x) (((x) & 0xff) << 24)
37 #define BC_FFP_MASK BC_FFP(~0)
38 #define UNM_FFP(x) (((x) & 0xff) << 16)
39 #define UNM_FFP_MASK UNM_FFP(~0)
40 #define UNU_FFP(x) (((x) & 0xff) << 8)
41 #define UNU_FFP_MASK UNU_FFP(~0)
42 #define CPU_EN BIT(7)
43 #define CPU_PORT(x) ((x) << 4)
44 #define CPU_MASK (0xf << 4)
45 #define MIRROR_EN BIT(3)
46 #define MIRROR_PORT(x) ((x) & 0x7)
47 #define MIRROR_MASK 0x7
48
49 /* Registers for CPU forward control */
50 #define MT7531_CFC 0x4
51 #define MT7531_MIRROR_EN BIT(19)
52 #define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
53 #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
54 #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
55 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
56
57 #define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \
58 MT7531_CFC : MT7530_MFC)
59 #define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \
60 MT7531_MIRROR_EN : MIRROR_EN)
61 #define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \
62 MT7531_MIRROR_MASK : MIRROR_MASK)
63
64 /* Registers for BPDU and PAE frame control*/
65 #define MT753X_BPC 0x24
66 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
67
68 enum mt753x_bpdu_port_fw {
69 MT753X_BPDU_FOLLOW_MFC,
70 MT753X_BPDU_CPU_EXCLUDE = 4,
71 MT753X_BPDU_CPU_INCLUDE = 5,
72 MT753X_BPDU_CPU_ONLY = 6,
73 MT753X_BPDU_DROP = 7,
74 };
75
76 /* Registers for address table access */
77 #define MT7530_ATA1 0x74
78 #define STATIC_EMP 0
79 #define STATIC_ENT 3
80 #define MT7530_ATA2 0x78
81
82 /* Register for address table write data */
83 #define MT7530_ATWD 0x7c
84
85 /* Register for address table control */
86 #define MT7530_ATC 0x80
87 #define ATC_HASH (((x) & 0xfff) << 16)
88 #define ATC_BUSY BIT(15)
89 #define ATC_SRCH_END BIT(14)
90 #define ATC_SRCH_HIT BIT(13)
91 #define ATC_INVALID BIT(12)
92 #define ATC_MAT(x) (((x) & 0xf) << 8)
93 #define ATC_MAT_MACTAB ATC_MAT(0)
94
95 enum mt7530_fdb_cmd {
96 MT7530_FDB_READ = 0,
97 MT7530_FDB_WRITE = 1,
98 MT7530_FDB_FLUSH = 2,
99 MT7530_FDB_START = 4,
100 MT7530_FDB_NEXT = 5,
101 };
102
103 /* Registers for table search read address */
104 #define MT7530_TSRA1 0x84
105 #define MAC_BYTE_0 24
106 #define MAC_BYTE_1 16
107 #define MAC_BYTE_2 8
108 #define MAC_BYTE_3 0
109 #define MAC_BYTE_MASK 0xff
110
111 #define MT7530_TSRA2 0x88
112 #define MAC_BYTE_4 24
113 #define MAC_BYTE_5 16
114 #define CVID 0
115 #define CVID_MASK 0xfff
116
117 #define MT7530_ATRD 0x8C
118 #define AGE_TIMER 24
119 #define AGE_TIMER_MASK 0xff
120 #define PORT_MAP 4
121 #define PORT_MAP_MASK 0xff
122 #define ENT_STATUS 2
123 #define ENT_STATUS_MASK 0x3
124
125 /* Register for vlan table control */
126 #define MT7530_VTCR 0x90
127 #define VTCR_BUSY BIT(31)
128 #define VTCR_INVALID BIT(16)
129 #define VTCR_FUNC(x) (((x) & 0xf) << 12)
130 #define VTCR_VID ((x) & 0xfff)
131
132 enum mt7530_vlan_cmd {
133 /* Read/Write the specified VID entry from VAWD register based
134 * on VID.
135 */
136 MT7530_VTCR_RD_VID = 0,
137 MT7530_VTCR_WR_VID = 1,
138 };
139
140 /* Register for setup vlan and acl write data */
141 #define MT7530_VAWD1 0x94
142 #define PORT_STAG BIT(31)
143 /* Independent VLAN Learning */
144 #define IVL_MAC BIT(30)
145 /* Per VLAN Egress Tag Control */
146 #define VTAG_EN BIT(28)
147 /* VLAN Member Control */
148 #define PORT_MEM(x) (((x) & 0xff) << 16)
149 /* VLAN Entry Valid */
150 #define VLAN_VALID BIT(0)
151 #define PORT_MEM_SHFT 16
152 #define PORT_MEM_MASK 0xff
153
154 #define MT7530_VAWD2 0x98
155 /* Egress Tag Control */
156 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
157 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
158
159 enum mt7530_vlan_egress_attr {
160 MT7530_VLAN_EGRESS_UNTAG = 0,
161 MT7530_VLAN_EGRESS_TAG = 2,
162 MT7530_VLAN_EGRESS_STACK = 3,
163 };
164
165 /* Register for address age control */
166 #define MT7530_AAC 0xa0
167 /* Disable ageing */
168 #define AGE_DIS BIT(20)
169 /* Age count */
170 #define AGE_CNT_MASK GENMASK(19, 12)
171 #define AGE_CNT_MAX 0xff
172 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12))
173 /* Age unit */
174 #define AGE_UNIT_MASK GENMASK(11, 0)
175 #define AGE_UNIT_MAX 0xfff
176 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x))
177
178 /* Register for port STP state control */
179 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
180 #define FID_PST(x) ((x) & 0x3)
181 #define FID_PST_MASK FID_PST(0x3)
182
183 enum mt7530_stp_state {
184 MT7530_STP_DISABLED = 0,
185 MT7530_STP_BLOCKING = 1,
186 MT7530_STP_LISTENING = 1,
187 MT7530_STP_LEARNING = 2,
188 MT7530_STP_FORWARDING = 3
189 };
190
191 /* Register for port control */
192 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
193 #define PORT_TX_MIR BIT(9)
194 #define PORT_RX_MIR BIT(8)
195 #define PORT_VLAN(x) ((x) & 0x3)
196
197 enum mt7530_port_mode {
198 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
199 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
200
201 /* Fallback Mode: Forward received frames with ingress ports that do
202 * not belong to the VLAN member. Frames whose VID is not listed on
203 * the VLAN table are forwarded by the PCR_MATRIX members.
204 */
205 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
206
207 /* Security Mode: Discard any frame due to ingress membership
208 * violation or VID missed on the VLAN table.
209 */
210 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
211 };
212
213 #define PCR_MATRIX(x) (((x) & 0xff) << 16)
214 #define PORT_PRI(x) (((x) & 0x7) << 24)
215 #define EG_TAG(x) (((x) & 0x3) << 28)
216 #define PCR_MATRIX_MASK PCR_MATRIX(0xff)
217 #define PCR_MATRIX_CLR PCR_MATRIX(0)
218 #define PCR_PORT_VLAN_MASK PORT_VLAN(3)
219
220 /* Register for port security control */
221 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
222 #define SA_DIS BIT(4)
223
224 /* Register for port vlan control */
225 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
226 #define PORT_SPEC_TAG BIT(5)
227 #define PVC_EG_TAG(x) (((x) & 0x7) << 8)
228 #define PVC_EG_TAG_MASK PVC_EG_TAG(7)
229 #define VLAN_ATTR(x) (((x) & 0x3) << 6)
230 #define VLAN_ATTR_MASK VLAN_ATTR(3)
231
232 enum mt7530_vlan_port_eg_tag {
233 MT7530_VLAN_EG_DISABLED = 0,
234 MT7530_VLAN_EG_CONSISTENT = 1,
235 };
236
237 enum mt7530_vlan_port_attr {
238 MT7530_VLAN_USER = 0,
239 MT7530_VLAN_TRANSPARENT = 3,
240 };
241
242 #define STAG_VPID (((x) & 0xffff) << 16)
243
244 /* Register for port port-and-protocol based vlan 1 control */
245 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
246 #define G0_PORT_VID(x) (((x) & 0xfff) << 0)
247 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
248 #define G0_PORT_VID_DEF G0_PORT_VID(1)
249
250 /* Register for port MAC control register */
251 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
252 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
253 #define PMCR_EXT_PHY BIT(17)
254 #define PMCR_MAC_MODE BIT(16)
255 #define PMCR_FORCE_MODE BIT(15)
256 #define PMCR_TX_EN BIT(14)
257 #define PMCR_RX_EN BIT(13)
258 #define PMCR_BACKOFF_EN BIT(9)
259 #define PMCR_BACKPR_EN BIT(8)
260 #define PMCR_FORCE_EEE1G BIT(7)
261 #define PMCR_FORCE_EEE100 BIT(6)
262 #define PMCR_TX_FC_EN BIT(5)
263 #define PMCR_RX_FC_EN BIT(4)
264 #define PMCR_FORCE_SPEED_1000 BIT(3)
265 #define PMCR_FORCE_SPEED_100 BIT(2)
266 #define PMCR_FORCE_FDX BIT(1)
267 #define PMCR_FORCE_LNK BIT(0)
268 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
269 PMCR_FORCE_SPEED_1000)
270 #define MT7531_FORCE_LNK BIT(31)
271 #define MT7531_FORCE_SPD BIT(30)
272 #define MT7531_FORCE_DPX BIT(29)
273 #define MT7531_FORCE_RX_FC BIT(28)
274 #define MT7531_FORCE_TX_FC BIT(27)
275 #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
276 MT7531_FORCE_SPD | \
277 MT7531_FORCE_DPX | \
278 MT7531_FORCE_RX_FC | \
279 MT7531_FORCE_TX_FC)
280 #define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \
281 MT7531_FORCE_MODE : \
282 PMCR_FORCE_MODE)
283 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
284 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
285 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
286 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
287 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
288 #define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \
289 PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
290 PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
291 PMCR_TX_EN | PMCR_RX_EN | \
292 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
293 PMCR_FORCE_SPEED_1000 | \
294 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
295
296 #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
297 #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
298 #define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16)
299 #define LPI_THRESH_MASK GENMASK(15, 4)
300 #define LPI_THRESH_SHT 4
301 #define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK)
302 #define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT)
303 #define LPI_MODE_EN BIT(0)
304
305 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
306 #define PMSR_EEE1G BIT(7)
307 #define PMSR_EEE100M BIT(6)
308 #define PMSR_RX_FC BIT(5)
309 #define PMSR_TX_FC BIT(4)
310 #define PMSR_SPEED_1000 BIT(3)
311 #define PMSR_SPEED_100 BIT(2)
312 #define PMSR_SPEED_10 0x00
313 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000)
314 #define PMSR_DPX BIT(1)
315 #define PMSR_LINK BIT(0)
316
317 /* Register for port debug count */
318 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
319 #define MT7531_DIS_CLR BIT(31)
320
321 #define MT7530_GMACCR 0x30e0
322 #define MAX_RX_JUMBO(x) ((x) << 2)
323 #define MAX_RX_JUMBO_MASK GENMASK(5, 2)
324 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
325 #define MAX_RX_PKT_LEN_1522 0x0
326 #define MAX_RX_PKT_LEN_1536 0x1
327 #define MAX_RX_PKT_LEN_1552 0x2
328 #define MAX_RX_PKT_LEN_JUMBO 0x3
329
330 /* Register for MIB */
331 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
332 #define MT7530_MIB_CCR 0x4fe0
333 #define CCR_MIB_ENABLE BIT(31)
334 #define CCR_RX_OCT_CNT_GOOD BIT(7)
335 #define CCR_RX_OCT_CNT_BAD BIT(6)
336 #define CCR_TX_OCT_CNT_GOOD BIT(5)
337 #define CCR_TX_OCT_CNT_BAD BIT(4)
338 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \
339 CCR_RX_OCT_CNT_BAD | \
340 CCR_TX_OCT_CNT_GOOD | \
341 CCR_TX_OCT_CNT_BAD)
342 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \
343 CCR_RX_OCT_CNT_GOOD | \
344 CCR_RX_OCT_CNT_BAD | \
345 CCR_TX_OCT_CNT_GOOD | \
346 CCR_TX_OCT_CNT_BAD)
347
348 /* MT7531 SGMII register group */
349 #define MT7531_SGMII_REG_BASE 0x5000
350 #define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
351 ((p) - 5) * 0x1000 + (r))
352
353 /* Register forSGMII PCS_CONTROL_1 */
354 #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00)
355 #define MT7531_SGMII_LINK_STATUS BIT(18)
356 #define MT7531_SGMII_AN_ENABLE BIT(12)
357 #define MT7531_SGMII_AN_RESTART BIT(9)
358
359 /* Register for SGMII PCS_SPPED_ABILITY */
360 #define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08)
361 #define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0)
362 #define MT7531_SGMII_TX_CONFIG BIT(0)
363
364 /* Register for SGMII_MODE */
365 #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20)
366 #define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
367 #define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1)
368 #define MT7531_SGMII_FORCE_DUPLEX BIT(4)
369 #define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2)
370 #define MT7531_SGMII_FORCE_SPEED_1000 BIT(3)
371 #define MT7531_SGMII_FORCE_SPEED_100 BIT(2)
372 #define MT7531_SGMII_FORCE_SPEED_10 0
373 #define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1)
374
375 enum mt7531_sgmii_force_duplex {
376 MT7531_SGMII_FORCE_FULL_DUPLEX = 0,
377 MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10,
378 };
379
380 /* Fields of QPHY_PWR_STATE_CTRL */
381 #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8)
382 #define MT7531_SGMII_PHYA_PWD BIT(4)
383
384 /* Values of SGMII SPEED */
385 #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128)
386 #define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3))
387 #define MT7531_RG_TPHY_SPEED_1_25G 0x0
388 #define MT7531_RG_TPHY_SPEED_3_125G BIT(2)
389
390 /* Register for system reset */
391 #define MT7530_SYS_CTRL 0x7000
392 #define SYS_CTRL_PHY_RST BIT(2)
393 #define SYS_CTRL_SW_RST BIT(1)
394 #define SYS_CTRL_REG_RST BIT(0)
395
396 /* Register for PHY Indirect Access Control */
397 #define MT7531_PHY_IAC 0x701C
398 #define MT7531_PHY_ACS_ST BIT(31)
399 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
400 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
401 #define MT7531_MDIO_CMD_MASK (0x3 << 18)
402 #define MT7531_MDIO_ST_MASK (0x3 << 16)
403 #define MT7531_MDIO_RW_DATA_MASK (0xffff)
404 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
405 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
406 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
407 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
408 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
409
410 enum mt7531_phy_iac_cmd {
411 MT7531_MDIO_ADDR = 0,
412 MT7531_MDIO_WRITE = 1,
413 MT7531_MDIO_READ = 2,
414 MT7531_MDIO_READ_CL45 = 3,
415 };
416
417 /* MDIO_ST: MDIO start field */
418 enum mt7531_mdio_st {
419 MT7531_MDIO_ST_CL45 = 0,
420 MT7531_MDIO_ST_CL22 = 1,
421 };
422
423 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
424 MT7531_MDIO_CMD(MT7531_MDIO_READ))
425 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
426 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
427 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
428 MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
429 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
430 MT7531_MDIO_CMD(MT7531_MDIO_READ))
431 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
432 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
433
434 /* Register for RGMII clock phase */
435 #define MT7531_CLKGEN_CTRL 0x7500
436 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
437 #define CLK_SKEW_OUT_MASK GENMASK(9, 8)
438 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
439 #define CLK_SKEW_IN_MASK GENMASK(7, 6)
440 #define RXCLK_NO_DELAY BIT(5)
441 #define TXCLK_NO_REVERSE BIT(4)
442 #define GP_MODE(x) (((x) & 0x3) << 1)
443 #define GP_MODE_MASK GENMASK(2, 1)
444 #define GP_CLK_EN BIT(0)
445
446 enum mt7531_gp_mode {
447 MT7531_GP_MODE_RGMII = 0,
448 MT7531_GP_MODE_MII = 1,
449 MT7531_GP_MODE_REV_MII = 2
450 };
451
452 enum mt7531_clk_skew {
453 MT7531_CLK_SKEW_NO_CHG = 0,
454 MT7531_CLK_SKEW_DLY_100PPS = 1,
455 MT7531_CLK_SKEW_DLY_200PPS = 2,
456 MT7531_CLK_SKEW_REVERSE = 3,
457 };
458
459 /* Register for hw trap status */
460 #define MT7530_HWTRAP 0x7800
461 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
462 #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
463 #define HWTRAP_XTAL_40MHZ (BIT(10))
464 #define HWTRAP_XTAL_20MHZ (BIT(9))
465
466 #define MT7531_HWTRAP 0x7800
467 #define HWTRAP_XTAL_FSEL_MASK BIT(7)
468 #define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
469 #define HWTRAP_XTAL_FSEL_40MHZ 0
470 /* Unique fields of (M)HWSTRAP for MT7531 */
471 #define XTAL_FSEL_S 7
472 #define XTAL_FSEL_M BIT(7)
473 #define PHY_EN BIT(6)
474 #define CHG_STRAP BIT(8)
475
476 /* Register for hw trap modification */
477 #define MT7530_MHWTRAP 0x7804
478 #define MHWTRAP_PHY0_SEL BIT(20)
479 #define MHWTRAP_MANUAL BIT(16)
480 #define MHWTRAP_P5_MAC_SEL BIT(13)
481 #define MHWTRAP_P6_DIS BIT(8)
482 #define MHWTRAP_P5_RGMII_MODE BIT(7)
483 #define MHWTRAP_P5_DIS BIT(6)
484 #define MHWTRAP_PHY_ACCESS BIT(5)
485
486 /* Register for TOP signal control */
487 #define MT7530_TOP_SIG_CTRL 0x7808
488 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
489
490 #define MT7531_TOP_SIG_SR 0x780c
491 #define PAD_DUAL_SGMII_EN BIT(1)
492 #define PAD_MCM_SMI_EN BIT(0)
493
494 #define MT7530_IO_DRV_CR 0x7810
495 #define P5_IO_CLK_DRV(x) ((x) & 0x3)
496 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
497
498 #define MT7531_CHIP_REV 0x781C
499
500 #define MT7531_PLLGP_EN 0x7820
501 #define EN_COREPLL BIT(2)
502 #define SW_CLKSW BIT(1)
503 #define SW_PLLGP BIT(0)
504
505 #define MT7530_P6ECR 0x7830
506 #define P6_INTF_MODE_MASK 0x3
507 #define P6_INTF_MODE(x) ((x) & 0x3)
508
509 #define MT7531_PLLGP_CR0 0x78a8
510 #define RG_COREPLL_EN BIT(22)
511 #define RG_COREPLL_POSDIV_S 23
512 #define RG_COREPLL_POSDIV_M 0x3800000
513 #define RG_COREPLL_SDM_PCW_S 1
514 #define RG_COREPLL_SDM_PCW_M 0x3ffffe
515 #define RG_COREPLL_SDM_PCW_CHG BIT(0)
516
517 /* Registers for RGMII and SGMII PLL clock */
518 #define MT7531_ANA_PLLGP_CR2 0x78b0
519 #define MT7531_ANA_PLLGP_CR5 0x78bc
520
521 /* Registers for TRGMII on the both side */
522 #define MT7530_TRGMII_RCK_CTRL 0x7a00
523 #define RX_RST BIT(31)
524 #define RXC_DQSISEL BIT(30)
525 #define DQSI1_TAP_MASK (0x7f << 8)
526 #define DQSI0_TAP_MASK 0x7f
527 #define DQSI1_TAP(x) (((x) & 0x7f) << 8)
528 #define DQSI0_TAP(x) ((x) & 0x7f)
529
530 #define MT7530_TRGMII_RCK_RTT 0x7a04
531 #define DQS1_GATE BIT(31)
532 #define DQS0_GATE BIT(30)
533
534 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
535 #define BSLIP_EN BIT(31)
536 #define EDGE_CHK BIT(30)
537 #define RD_TAP_MASK 0x7f
538 #define RD_TAP(x) ((x) & 0x7f)
539
540 #define MT7530_TRGMII_TXCTRL 0x7a40
541 #define TRAIN_TXEN BIT(31)
542 #define TXC_INV BIT(30)
543 #define TX_RST BIT(28)
544
545 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
546 #define TD_DM_DRVP(x) ((x) & 0xf)
547 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
548
549 #define MT7530_TRGMII_TCK_CTRL 0x7a78
550 #define TCK_TAP(x) (((x) & 0xf) << 8)
551
552 #define MT7530_P5RGMIIRXCR 0x7b00
553 #define CSR_RGMII_EDGE_ALIGN BIT(8)
554 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
555
556 #define MT7530_P5RGMIITXCR 0x7b04
557 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
558
559 /* Registers for GPIO mode */
560 #define MT7531_GPIO_MODE0 0x7c0c
561 #define MT7531_GPIO0_MASK GENMASK(3, 0)
562 #define MT7531_GPIO0_INTERRUPT 1
563
564 #define MT7531_GPIO_MODE1 0x7c10
565 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
566 #define MT7531_EXT_P_MDC_11 (2 << 12)
567 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
568 #define MT7531_EXT_P_MDIO_12 (2 << 16)
569
570 /* Registers for LED GPIO control (MT7530 only)
571 * All registers follow this pattern:
572 * [ 2: 0] port 0
573 * [ 6: 4] port 1
574 * [10: 8] port 2
575 * [14:12] port 3
576 * [18:16] port 4
577 */
578
579 /* LED enable, 0: Disable, 1: Enable (Default) */
580 #define MT7530_LED_EN 0x7d00
581 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */
582 #define MT7530_LED_IO_MODE 0x7d04
583 /* GPIO direction, 0: Input, 1: Output */
584 #define MT7530_LED_GPIO_DIR 0x7d10
585 /* GPIO output enable, 0: Disable, 1: Enable */
586 #define MT7530_LED_GPIO_OE 0x7d14
587 /* GPIO value, 0: Low, 1: High */
588 #define MT7530_LED_GPIO_DATA 0x7d18
589
590 #define MT7530_CREV 0x7ffc
591 #define CHIP_NAME_SHIFT 16
592 #define MT7530_ID 0x7530
593
594 #define MT7531_CREV 0x781C
595 #define CHIP_REV_M 0x0f
596 #define MT7531_ID 0x7531
597
598 /* Registers for core PLL access through mmd indirect */
599 #define CORE_PLL_GROUP2 0x401
600 #define RG_SYSPLL_EN_NORMAL BIT(15)
601 #define RG_SYSPLL_VODEN BIT(14)
602 #define RG_SYSPLL_LF BIT(13)
603 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
604 #define RG_SYSPLL_LVROD_EN BIT(10)
605 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
606 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
607 #define RG_SYSPLL_FBKSEL BIT(4)
608 #define RT_SYSPLL_EN_AFE_OLT BIT(0)
609
610 #define CORE_PLL_GROUP4 0x403
611 #define RG_SYSPLL_DDSFBK_EN BIT(12)
612 #define RG_SYSPLL_BIAS_EN BIT(11)
613 #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
614 #define MT7531_PHY_PLL_OFF BIT(5)
615 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
616
617 #define MT753X_CTRL_PHY_ADDR 0
618
619 #define CORE_PLL_GROUP5 0x404
620 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
621
622 #define CORE_PLL_GROUP6 0x405
623 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
624
625 #define CORE_PLL_GROUP7 0x406
626 #define RG_LCDDS_PWDB BIT(15)
627 #define RG_LCDDS_ISO_EN BIT(13)
628 #define RG_LCCDS_C(x) (((x) & 0x7) << 4)
629 #define RG_LCDDS_PCW_NCPO_CHG BIT(3)
630
631 #define CORE_PLL_GROUP10 0x409
632 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
633
634 #define CORE_PLL_GROUP11 0x40a
635 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
636
637 #define CORE_GSWPLL_GRP1 0x40d
638 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
639 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
640 #define RG_GSWPLL_EN_PRE BIT(11)
641 #define RG_GSWPLL_FBKSEL BIT(10)
642 #define RG_GSWPLL_BP BIT(9)
643 #define RG_GSWPLL_BR BIT(8)
644 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
645
646 #define CORE_GSWPLL_GRP2 0x40e
647 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
648 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
649
650 #define CORE_TRGMII_GSW_CLK_CG 0x410
651 #define REG_GSWCK_EN BIT(0)
652 #define REG_TRGMIICK_EN BIT(1)
653
654 #define MIB_DESC(_s, _o, _n) \
655 { \
656 .size = (_s), \
657 .offset = (_o), \
658 .name = (_n), \
659 }
660
661 struct mt7530_mib_desc {
662 unsigned int size;
663 unsigned int offset;
664 const char *name;
665 };
666
667 struct mt7530_fdb {
668 u16 vid;
669 u8 port_mask;
670 u8 aging;
671 u8 mac[6];
672 bool noarp;
673 };
674
675 /* struct mt7530_port - This is the main data structure for holding the state
676 * of the port.
677 * @enable: The status used for show port is enabled or not.
678 * @pm: The matrix used to show all connections with the port.
679 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
680 * untagged frames will be assigned to the related VLAN.
681 * @vlan_filtering: The flags indicating whether the port that can recognize
682 * VLAN-tagged frames.
683 */
684 struct mt7530_port {
685 bool enable;
686 u32 pm;
687 u16 pvid;
688 };
689
690 /* Port 5 interface select definitions */
691 enum p5_interface_select {
692 P5_DISABLED = 0,
693 P5_INTF_SEL_PHY_P0,
694 P5_INTF_SEL_PHY_P4,
695 P5_INTF_SEL_GMAC5,
696 P5_INTF_SEL_GMAC5_SGMII,
697 };
698
p5_intf_modes(unsigned int p5_interface)699 static const char *p5_intf_modes(unsigned int p5_interface)
700 {
701 switch (p5_interface) {
702 case P5_DISABLED:
703 return "DISABLED";
704 case P5_INTF_SEL_PHY_P0:
705 return "PHY P0";
706 case P5_INTF_SEL_PHY_P4:
707 return "PHY P4";
708 case P5_INTF_SEL_GMAC5:
709 return "GMAC5";
710 case P5_INTF_SEL_GMAC5_SGMII:
711 return "GMAC5_SGMII";
712 default:
713 return "unknown";
714 }
715 }
716
717 /* struct mt753x_info - This is the main data structure for holding the specific
718 * part for each supported device
719 * @sw_setup: Holding the handler to a device initialization
720 * @phy_read: Holding the way reading PHY port
721 * @phy_write: Holding the way writing PHY port
722 * @pad_setup: Holding the way setting up the bus pad for a certain
723 * MAC port
724 * @phy_mode_supported: Check if the PHY type is being supported on a certain
725 * port
726 * @mac_port_validate: Holding the way to set addition validate type for a
727 * certan MAC port
728 * @mac_port_get_state: Holding the way getting the MAC/PCS state for a certain
729 * MAC port
730 * @mac_port_config: Holding the way setting up the PHY attribute to a
731 * certain MAC port
732 * @mac_pcs_an_restart Holding the way restarting PCS autonegotiation for a
733 * certain MAC port
734 * @mac_pcs_link_up: Holding the way setting up the PHY attribute to the pcs
735 * of the certain MAC port
736 */
737 struct mt753x_info {
738 enum mt753x_id id;
739
740 int (*sw_setup)(struct dsa_switch *ds);
741 int (*phy_read)(struct dsa_switch *ds, int port, int regnum);
742 int (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val);
743 int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
744 int (*cpu_port_config)(struct dsa_switch *ds, int port);
745 bool (*phy_mode_supported)(struct dsa_switch *ds, int port,
746 const struct phylink_link_state *state);
747 void (*mac_port_validate)(struct dsa_switch *ds, int port,
748 unsigned long *supported);
749 int (*mac_port_get_state)(struct dsa_switch *ds, int port,
750 struct phylink_link_state *state);
751 int (*mac_port_config)(struct dsa_switch *ds, int port,
752 unsigned int mode,
753 phy_interface_t interface);
754 void (*mac_pcs_an_restart)(struct dsa_switch *ds, int port);
755 void (*mac_pcs_link_up)(struct dsa_switch *ds, int port,
756 unsigned int mode, phy_interface_t interface,
757 int speed, int duplex);
758 };
759
760 /* struct mt7530_priv - This is the main data structure for holding the state
761 * of the driver
762 * @dev: The device pointer
763 * @ds: The pointer to the dsa core structure
764 * @bus: The bus used for the device and built-in PHY
765 * @rstc: The pointer to reset control used by MCM
766 * @core_pwr: The power supplied into the core
767 * @io_pwr: The power supplied into the I/O
768 * @reset: The descriptor for GPIO line tied to its reset pin
769 * @mcm: Flag for distinguishing if standalone IC or module
770 * coupling
771 * @ports: Holding the state among ports
772 * @reg_mutex: The lock for protecting among process accessing
773 * registers
774 * @p6_interface Holding the current port 6 interface
775 * @p5_intf_sel: Holding the current port 5 interface select
776 */
777 struct mt7530_priv {
778 struct device *dev;
779 struct dsa_switch *ds;
780 struct mii_bus *bus;
781 struct reset_control *rstc;
782 struct regulator *core_pwr;
783 struct regulator *io_pwr;
784 struct gpio_desc *reset;
785 const struct mt753x_info *info;
786 unsigned int id;
787 bool mcm;
788 phy_interface_t p6_interface;
789 phy_interface_t p5_interface;
790 unsigned int p5_intf_sel;
791 u8 mirror_rx;
792 u8 mirror_tx;
793
794 struct mt7530_port ports[MT7530_NUM_PORTS];
795 /* protect among processes for registers access*/
796 struct mutex reg_mutex;
797 };
798
799 struct mt7530_hw_vlan_entry {
800 int port;
801 u8 old_members;
802 bool untagged;
803 };
804
mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry * e,int port,bool untagged)805 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
806 int port, bool untagged)
807 {
808 e->port = port;
809 e->untagged = untagged;
810 }
811
812 typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
813 struct mt7530_hw_vlan_entry *);
814
815 struct mt7530_hw_stats {
816 const char *string;
817 u16 reg;
818 u8 sizeof_stat;
819 };
820
821 struct mt7530_dummy_poll {
822 struct mt7530_priv *priv;
823 u32 reg;
824 };
825
INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll * p,struct mt7530_priv * priv,u32 reg)826 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
827 struct mt7530_priv *priv, u32 reg)
828 {
829 p->priv = priv;
830 p->reg = reg;
831 }
832
833 #endif /* __MT7530_H */
834