1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/etherdevice.h>
5
6 #include "hclge_cmd.h"
7 #include "hclge_main.h"
8 #include "hclge_tm.h"
9
10 enum hclge_shaper_level {
11 HCLGE_SHAPER_LVL_PRI = 0,
12 HCLGE_SHAPER_LVL_PG = 1,
13 HCLGE_SHAPER_LVL_PORT = 2,
14 HCLGE_SHAPER_LVL_QSET = 3,
15 HCLGE_SHAPER_LVL_CNT = 4,
16 HCLGE_SHAPER_LVL_VF = 0,
17 HCLGE_SHAPER_LVL_PF = 1,
18 };
19
20 #define HCLGE_TM_PFC_PKT_GET_CMD_NUM 3
21 #define HCLGE_TM_PFC_NUM_GET_PER_CMD 3
22
23 #define HCLGE_SHAPER_BS_U_DEF 5
24 #define HCLGE_SHAPER_BS_S_DEF 20
25
26 /* hclge_shaper_para_calc: calculate ir parameter for the shaper
27 * @ir: Rate to be config, its unit is Mbps
28 * @shaper_level: the shaper level. eg: port, pg, priority, queueset
29 * @ir_para: parameters of IR shaper
30 * @max_tm_rate: max tm rate is available to config
31 *
32 * the formula:
33 *
34 * IR_b * (2 ^ IR_u) * 8
35 * IR(Mbps) = ------------------------- * CLOCK(1000Mbps)
36 * Tick * (2 ^ IR_s)
37 *
38 * @return: 0: calculate sucessful, negative: fail
39 */
hclge_shaper_para_calc(u32 ir,u8 shaper_level,struct hclge_shaper_ir_para * ir_para,u32 max_tm_rate)40 static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
41 struct hclge_shaper_ir_para *ir_para,
42 u32 max_tm_rate)
43 {
44 #define DEFAULT_SHAPER_IR_B 126
45 #define DIVISOR_CLK (1000 * 8)
46 #define DEFAULT_DIVISOR_IR_B (DEFAULT_SHAPER_IR_B * DIVISOR_CLK)
47
48 static const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = {
49 6 * 256, /* Prioriy level */
50 6 * 32, /* Prioriy group level */
51 6 * 8, /* Port level */
52 6 * 256 /* Qset level */
53 };
54 u8 ir_u_calc = 0;
55 u8 ir_s_calc = 0;
56 u32 ir_calc;
57 u32 tick;
58
59 /* Calc tick */
60 if (shaper_level >= HCLGE_SHAPER_LVL_CNT ||
61 ir > max_tm_rate)
62 return -EINVAL;
63
64 tick = tick_array[shaper_level];
65
66 /**
67 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0
68 * the formula is changed to:
69 * 126 * 1 * 8
70 * ir_calc = ---------------- * 1000
71 * tick * 1
72 */
73 ir_calc = (DEFAULT_DIVISOR_IR_B + (tick >> 1) - 1) / tick;
74
75 if (ir_calc == ir) {
76 ir_para->ir_b = DEFAULT_SHAPER_IR_B;
77 ir_para->ir_u = 0;
78 ir_para->ir_s = 0;
79
80 return 0;
81 } else if (ir_calc > ir) {
82 /* Increasing the denominator to select ir_s value */
83 while (ir_calc >= ir && ir) {
84 ir_s_calc++;
85 ir_calc = DEFAULT_DIVISOR_IR_B /
86 (tick * (1 << ir_s_calc));
87 }
88
89 ir_para->ir_b = (ir * tick * (1 << ir_s_calc) +
90 (DIVISOR_CLK >> 1)) / DIVISOR_CLK;
91 } else {
92 /* Increasing the numerator to select ir_u value */
93 u32 numerator;
94
95 while (ir_calc < ir) {
96 ir_u_calc++;
97 numerator = DEFAULT_DIVISOR_IR_B * (1 << ir_u_calc);
98 ir_calc = (numerator + (tick >> 1)) / tick;
99 }
100
101 if (ir_calc == ir) {
102 ir_para->ir_b = DEFAULT_SHAPER_IR_B;
103 } else {
104 u32 denominator = DIVISOR_CLK * (1 << --ir_u_calc);
105 ir_para->ir_b = (ir * tick + (denominator >> 1)) /
106 denominator;
107 }
108 }
109
110 ir_para->ir_u = ir_u_calc;
111 ir_para->ir_s = ir_s_calc;
112
113 return 0;
114 }
115
hclge_pfc_stats_get(struct hclge_dev * hdev,enum hclge_opcode_type opcode,u64 * stats)116 static int hclge_pfc_stats_get(struct hclge_dev *hdev,
117 enum hclge_opcode_type opcode, u64 *stats)
118 {
119 struct hclge_desc desc[HCLGE_TM_PFC_PKT_GET_CMD_NUM];
120 int ret, i, j;
121
122 if (!(opcode == HCLGE_OPC_QUERY_PFC_RX_PKT_CNT ||
123 opcode == HCLGE_OPC_QUERY_PFC_TX_PKT_CNT))
124 return -EINVAL;
125
126 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1; i++) {
127 hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
128 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
129 }
130
131 hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
132
133 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_TM_PFC_PKT_GET_CMD_NUM);
134 if (ret)
135 return ret;
136
137 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) {
138 struct hclge_pfc_stats_cmd *pfc_stats =
139 (struct hclge_pfc_stats_cmd *)desc[i].data;
140
141 for (j = 0; j < HCLGE_TM_PFC_NUM_GET_PER_CMD; j++) {
142 u32 index = i * HCLGE_TM_PFC_PKT_GET_CMD_NUM + j;
143
144 if (index < HCLGE_MAX_TC_NUM)
145 stats[index] =
146 le64_to_cpu(pfc_stats->pkt_num[j]);
147 }
148 }
149 return 0;
150 }
151
hclge_pfc_rx_stats_get(struct hclge_dev * hdev,u64 * stats)152 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats)
153 {
154 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_RX_PKT_CNT, stats);
155 }
156
hclge_pfc_tx_stats_get(struct hclge_dev * hdev,u64 * stats)157 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats)
158 {
159 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_TX_PKT_CNT, stats);
160 }
161
hclge_mac_pause_en_cfg(struct hclge_dev * hdev,bool tx,bool rx)162 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx)
163 {
164 struct hclge_desc desc;
165
166 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PAUSE_EN, false);
167
168 desc.data[0] = cpu_to_le32((tx ? HCLGE_TX_MAC_PAUSE_EN_MSK : 0) |
169 (rx ? HCLGE_RX_MAC_PAUSE_EN_MSK : 0));
170
171 return hclge_cmd_send(&hdev->hw, &desc, 1);
172 }
173
hclge_pfc_pause_en_cfg(struct hclge_dev * hdev,u8 tx_rx_bitmap,u8 pfc_bitmap)174 static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
175 u8 pfc_bitmap)
176 {
177 struct hclge_desc desc;
178 struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data;
179
180 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PFC_PAUSE_EN, false);
181
182 pfc->tx_rx_en_bitmap = tx_rx_bitmap;
183 pfc->pri_en_bitmap = pfc_bitmap;
184
185 return hclge_cmd_send(&hdev->hw, &desc, 1);
186 }
187
hclge_pause_param_cfg(struct hclge_dev * hdev,const u8 * addr,u8 pause_trans_gap,u16 pause_trans_time)188 static int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr,
189 u8 pause_trans_gap, u16 pause_trans_time)
190 {
191 struct hclge_cfg_pause_param_cmd *pause_param;
192 struct hclge_desc desc;
193
194 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
195
196 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, false);
197
198 ether_addr_copy(pause_param->mac_addr, addr);
199 ether_addr_copy(pause_param->mac_addr_extra, addr);
200 pause_param->pause_trans_gap = pause_trans_gap;
201 pause_param->pause_trans_time = cpu_to_le16(pause_trans_time);
202
203 return hclge_cmd_send(&hdev->hw, &desc, 1);
204 }
205
hclge_pause_addr_cfg(struct hclge_dev * hdev,const u8 * mac_addr)206 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr)
207 {
208 struct hclge_cfg_pause_param_cmd *pause_param;
209 struct hclge_desc desc;
210 u16 trans_time;
211 u8 trans_gap;
212 int ret;
213
214 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
215
216 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true);
217
218 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
219 if (ret)
220 return ret;
221
222 trans_gap = pause_param->pause_trans_gap;
223 trans_time = le16_to_cpu(pause_param->pause_trans_time);
224
225 return hclge_pause_param_cfg(hdev, mac_addr, trans_gap, trans_time);
226 }
227
hclge_fill_pri_array(struct hclge_dev * hdev,u8 * pri,u8 pri_id)228 static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id)
229 {
230 u8 tc;
231
232 tc = hdev->tm_info.prio_tc[pri_id];
233
234 if (tc >= hdev->tm_info.num_tc)
235 return -EINVAL;
236
237 /**
238 * the register for priority has four bytes, the first bytes includes
239 * priority0 and priority1, the higher 4bit stands for priority1
240 * while the lower 4bit stands for priority0, as below:
241 * first byte: | pri_1 | pri_0 |
242 * second byte: | pri_3 | pri_2 |
243 * third byte: | pri_5 | pri_4 |
244 * fourth byte: | pri_7 | pri_6 |
245 */
246 pri[pri_id >> 1] |= tc << ((pri_id & 1) * 4);
247
248 return 0;
249 }
250
hclge_up_to_tc_map(struct hclge_dev * hdev)251 static int hclge_up_to_tc_map(struct hclge_dev *hdev)
252 {
253 struct hclge_desc desc;
254 u8 *pri = (u8 *)desc.data;
255 u8 pri_id;
256 int ret;
257
258 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false);
259
260 for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) {
261 ret = hclge_fill_pri_array(hdev, pri, pri_id);
262 if (ret)
263 return ret;
264 }
265
266 return hclge_cmd_send(&hdev->hw, &desc, 1);
267 }
268
hclge_tm_pg_to_pri_map_cfg(struct hclge_dev * hdev,u8 pg_id,u8 pri_bit_map)269 static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev,
270 u8 pg_id, u8 pri_bit_map)
271 {
272 struct hclge_pg_to_pri_link_cmd *map;
273 struct hclge_desc desc;
274
275 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, false);
276
277 map = (struct hclge_pg_to_pri_link_cmd *)desc.data;
278
279 map->pg_id = pg_id;
280 map->pri_bit_map = pri_bit_map;
281
282 return hclge_cmd_send(&hdev->hw, &desc, 1);
283 }
284
hclge_tm_qs_to_pri_map_cfg(struct hclge_dev * hdev,u16 qs_id,u8 pri)285 static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev,
286 u16 qs_id, u8 pri)
287 {
288 struct hclge_qs_to_pri_link_cmd *map;
289 struct hclge_desc desc;
290
291 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, false);
292
293 map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
294
295 map->qs_id = cpu_to_le16(qs_id);
296 map->priority = pri;
297 map->link_vld = HCLGE_TM_QS_PRI_LINK_VLD_MSK;
298
299 return hclge_cmd_send(&hdev->hw, &desc, 1);
300 }
301
hclge_tm_q_to_qs_map_cfg(struct hclge_dev * hdev,u16 q_id,u16 qs_id)302 static int hclge_tm_q_to_qs_map_cfg(struct hclge_dev *hdev,
303 u16 q_id, u16 qs_id)
304 {
305 struct hclge_nq_to_qs_link_cmd *map;
306 struct hclge_desc desc;
307 u16 qs_id_l;
308 u16 qs_id_h;
309
310 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, false);
311
312 map = (struct hclge_nq_to_qs_link_cmd *)desc.data;
313
314 map->nq_id = cpu_to_le16(q_id);
315
316 /* convert qs_id to the following format to support qset_id >= 1024
317 * qs_id: | 15 | 14 ~ 10 | 9 ~ 0 |
318 * / / \ \
319 * / / \ \
320 * qset_id: | 15 ~ 11 | 10 | 9 ~ 0 |
321 * | qs_id_h | vld | qs_id_l |
322 */
323 qs_id_l = hnae3_get_field(qs_id, HCLGE_TM_QS_ID_L_MSK,
324 HCLGE_TM_QS_ID_L_S);
325 qs_id_h = hnae3_get_field(qs_id, HCLGE_TM_QS_ID_H_MSK,
326 HCLGE_TM_QS_ID_H_S);
327 hnae3_set_field(qs_id, HCLGE_TM_QS_ID_L_MSK, HCLGE_TM_QS_ID_L_S,
328 qs_id_l);
329 hnae3_set_field(qs_id, HCLGE_TM_QS_ID_H_EXT_MSK, HCLGE_TM_QS_ID_H_EXT_S,
330 qs_id_h);
331 map->qset_id = cpu_to_le16(qs_id | HCLGE_TM_Q_QS_LINK_VLD_MSK);
332
333 return hclge_cmd_send(&hdev->hw, &desc, 1);
334 }
335
hclge_tm_pg_weight_cfg(struct hclge_dev * hdev,u8 pg_id,u8 dwrr)336 static int hclge_tm_pg_weight_cfg(struct hclge_dev *hdev, u8 pg_id,
337 u8 dwrr)
338 {
339 struct hclge_pg_weight_cmd *weight;
340 struct hclge_desc desc;
341
342 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, false);
343
344 weight = (struct hclge_pg_weight_cmd *)desc.data;
345
346 weight->pg_id = pg_id;
347 weight->dwrr = dwrr;
348
349 return hclge_cmd_send(&hdev->hw, &desc, 1);
350 }
351
hclge_tm_pri_weight_cfg(struct hclge_dev * hdev,u8 pri_id,u8 dwrr)352 static int hclge_tm_pri_weight_cfg(struct hclge_dev *hdev, u8 pri_id,
353 u8 dwrr)
354 {
355 struct hclge_priority_weight_cmd *weight;
356 struct hclge_desc desc;
357
358 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, false);
359
360 weight = (struct hclge_priority_weight_cmd *)desc.data;
361
362 weight->pri_id = pri_id;
363 weight->dwrr = dwrr;
364
365 return hclge_cmd_send(&hdev->hw, &desc, 1);
366 }
367
hclge_tm_qs_weight_cfg(struct hclge_dev * hdev,u16 qs_id,u8 dwrr)368 static int hclge_tm_qs_weight_cfg(struct hclge_dev *hdev, u16 qs_id,
369 u8 dwrr)
370 {
371 struct hclge_qs_weight_cmd *weight;
372 struct hclge_desc desc;
373
374 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, false);
375
376 weight = (struct hclge_qs_weight_cmd *)desc.data;
377
378 weight->qs_id = cpu_to_le16(qs_id);
379 weight->dwrr = dwrr;
380
381 return hclge_cmd_send(&hdev->hw, &desc, 1);
382 }
383
hclge_tm_get_shapping_para(u8 ir_b,u8 ir_u,u8 ir_s,u8 bs_b,u8 bs_s)384 static u32 hclge_tm_get_shapping_para(u8 ir_b, u8 ir_u, u8 ir_s,
385 u8 bs_b, u8 bs_s)
386 {
387 u32 shapping_para = 0;
388
389 hclge_tm_set_field(shapping_para, IR_B, ir_b);
390 hclge_tm_set_field(shapping_para, IR_U, ir_u);
391 hclge_tm_set_field(shapping_para, IR_S, ir_s);
392 hclge_tm_set_field(shapping_para, BS_B, bs_b);
393 hclge_tm_set_field(shapping_para, BS_S, bs_s);
394
395 return shapping_para;
396 }
397
hclge_tm_pg_shapping_cfg(struct hclge_dev * hdev,enum hclge_shap_bucket bucket,u8 pg_id,u32 shapping_para,u32 rate)398 static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev,
399 enum hclge_shap_bucket bucket, u8 pg_id,
400 u32 shapping_para, u32 rate)
401 {
402 struct hclge_pg_shapping_cmd *shap_cfg_cmd;
403 enum hclge_opcode_type opcode;
404 struct hclge_desc desc;
405
406 opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING :
407 HCLGE_OPC_TM_PG_C_SHAPPING;
408 hclge_cmd_setup_basic_desc(&desc, opcode, false);
409
410 shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
411
412 shap_cfg_cmd->pg_id = pg_id;
413
414 shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para);
415
416 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1);
417
418 shap_cfg_cmd->pg_rate = cpu_to_le32(rate);
419
420 return hclge_cmd_send(&hdev->hw, &desc, 1);
421 }
422
hclge_tm_port_shaper_cfg(struct hclge_dev * hdev)423 static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev)
424 {
425 struct hclge_port_shapping_cmd *shap_cfg_cmd;
426 struct hclge_shaper_ir_para ir_para;
427 struct hclge_desc desc;
428 u32 shapping_para;
429 int ret;
430
431 ret = hclge_shaper_para_calc(hdev->hw.mac.speed, HCLGE_SHAPER_LVL_PORT,
432 &ir_para,
433 hdev->ae_dev->dev_specs.max_tm_rate);
434 if (ret)
435 return ret;
436
437 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, false);
438 shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data;
439
440 shapping_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
441 ir_para.ir_s,
442 HCLGE_SHAPER_BS_U_DEF,
443 HCLGE_SHAPER_BS_S_DEF);
444
445 shap_cfg_cmd->port_shapping_para = cpu_to_le32(shapping_para);
446
447 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1);
448
449 shap_cfg_cmd->port_rate = cpu_to_le32(hdev->hw.mac.speed);
450
451 return hclge_cmd_send(&hdev->hw, &desc, 1);
452 }
453
hclge_tm_pri_shapping_cfg(struct hclge_dev * hdev,enum hclge_shap_bucket bucket,u8 pri_id,u32 shapping_para,u32 rate)454 static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev,
455 enum hclge_shap_bucket bucket, u8 pri_id,
456 u32 shapping_para, u32 rate)
457 {
458 struct hclge_pri_shapping_cmd *shap_cfg_cmd;
459 enum hclge_opcode_type opcode;
460 struct hclge_desc desc;
461
462 opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING :
463 HCLGE_OPC_TM_PRI_C_SHAPPING;
464
465 hclge_cmd_setup_basic_desc(&desc, opcode, false);
466
467 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
468
469 shap_cfg_cmd->pri_id = pri_id;
470
471 shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para);
472
473 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1);
474
475 shap_cfg_cmd->pri_rate = cpu_to_le32(rate);
476
477 return hclge_cmd_send(&hdev->hw, &desc, 1);
478 }
479
hclge_tm_pg_schd_mode_cfg(struct hclge_dev * hdev,u8 pg_id)480 static int hclge_tm_pg_schd_mode_cfg(struct hclge_dev *hdev, u8 pg_id)
481 {
482 struct hclge_desc desc;
483
484 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, false);
485
486 if (hdev->tm_info.pg_info[pg_id].pg_sch_mode == HCLGE_SCH_MODE_DWRR)
487 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
488 else
489 desc.data[1] = 0;
490
491 desc.data[0] = cpu_to_le32(pg_id);
492
493 return hclge_cmd_send(&hdev->hw, &desc, 1);
494 }
495
hclge_tm_pri_schd_mode_cfg(struct hclge_dev * hdev,u8 pri_id)496 static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id)
497 {
498 struct hclge_desc desc;
499
500 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, false);
501
502 if (hdev->tm_info.tc_info[pri_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR)
503 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
504 else
505 desc.data[1] = 0;
506
507 desc.data[0] = cpu_to_le32(pri_id);
508
509 return hclge_cmd_send(&hdev->hw, &desc, 1);
510 }
511
hclge_tm_qs_schd_mode_cfg(struct hclge_dev * hdev,u16 qs_id,u8 mode)512 static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode)
513 {
514 struct hclge_desc desc;
515
516 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false);
517
518 if (mode == HCLGE_SCH_MODE_DWRR)
519 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
520 else
521 desc.data[1] = 0;
522
523 desc.data[0] = cpu_to_le32(qs_id);
524
525 return hclge_cmd_send(&hdev->hw, &desc, 1);
526 }
527
hclge_tm_qs_bp_cfg(struct hclge_dev * hdev,u8 tc,u8 grp_id,u32 bit_map)528 static int hclge_tm_qs_bp_cfg(struct hclge_dev *hdev, u8 tc, u8 grp_id,
529 u32 bit_map)
530 {
531 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
532 struct hclge_desc desc;
533
534 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_BP_TO_QSET_MAPPING,
535 false);
536
537 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data;
538
539 bp_to_qs_map_cmd->tc_id = tc;
540 bp_to_qs_map_cmd->qs_group_id = grp_id;
541 bp_to_qs_map_cmd->qs_bit_map = cpu_to_le32(bit_map);
542
543 return hclge_cmd_send(&hdev->hw, &desc, 1);
544 }
545
hclge_tm_qs_shaper_cfg(struct hclge_vport * vport,int max_tx_rate)546 int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate)
547 {
548 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
549 struct hclge_qs_shapping_cmd *shap_cfg_cmd;
550 struct hclge_shaper_ir_para ir_para;
551 struct hclge_dev *hdev = vport->back;
552 struct hclge_desc desc;
553 u32 shaper_para;
554 int ret, i;
555
556 if (!max_tx_rate)
557 max_tx_rate = hdev->ae_dev->dev_specs.max_tm_rate;
558
559 ret = hclge_shaper_para_calc(max_tx_rate, HCLGE_SHAPER_LVL_QSET,
560 &ir_para,
561 hdev->ae_dev->dev_specs.max_tm_rate);
562 if (ret)
563 return ret;
564
565 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
566 ir_para.ir_s,
567 HCLGE_SHAPER_BS_U_DEF,
568 HCLGE_SHAPER_BS_S_DEF);
569
570 for (i = 0; i < kinfo->tc_info.num_tc; i++) {
571 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QCN_SHAPPING_CFG,
572 false);
573
574 shap_cfg_cmd = (struct hclge_qs_shapping_cmd *)desc.data;
575 shap_cfg_cmd->qs_id = cpu_to_le16(vport->qs_offset + i);
576 shap_cfg_cmd->qs_shapping_para = cpu_to_le32(shaper_para);
577
578 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1);
579 shap_cfg_cmd->qs_rate = cpu_to_le32(max_tx_rate);
580
581 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
582 if (ret) {
583 dev_err(&hdev->pdev->dev,
584 "vf%u, qs%u failed to set tx_rate:%d, ret=%d\n",
585 vport->vport_id, shap_cfg_cmd->qs_id,
586 max_tx_rate, ret);
587 return ret;
588 }
589 }
590
591 return 0;
592 }
593
hclge_vport_get_max_rss_size(struct hclge_vport * vport)594 static u16 hclge_vport_get_max_rss_size(struct hclge_vport *vport)
595 {
596 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
597 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
598 struct hclge_dev *hdev = vport->back;
599 u16 max_rss_size = 0;
600 int i;
601
602 if (!tc_info->mqprio_active)
603 return vport->alloc_tqps / tc_info->num_tc;
604
605 for (i = 0; i < HNAE3_MAX_TC; i++) {
606 if (!(hdev->hw_tc_map & BIT(i)) || i >= tc_info->num_tc)
607 continue;
608 if (max_rss_size < tc_info->tqp_count[i])
609 max_rss_size = tc_info->tqp_count[i];
610 }
611
612 return max_rss_size;
613 }
614
hclge_vport_get_tqp_num(struct hclge_vport * vport)615 static u16 hclge_vport_get_tqp_num(struct hclge_vport *vport)
616 {
617 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
618 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
619 struct hclge_dev *hdev = vport->back;
620 int sum = 0;
621 int i;
622
623 if (!tc_info->mqprio_active)
624 return kinfo->rss_size * tc_info->num_tc;
625
626 for (i = 0; i < HNAE3_MAX_TC; i++) {
627 if (hdev->hw_tc_map & BIT(i) && i < tc_info->num_tc)
628 sum += tc_info->tqp_count[i];
629 }
630
631 return sum;
632 }
633
hclge_tm_update_kinfo_rss_size(struct hclge_vport * vport)634 static void hclge_tm_update_kinfo_rss_size(struct hclge_vport *vport)
635 {
636 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
637 struct hclge_dev *hdev = vport->back;
638 u16 vport_max_rss_size;
639 u16 max_rss_size;
640
641 /* TC configuration is shared by PF/VF in one port, only allow
642 * one tc for VF for simplicity. VF's vport_id is non zero.
643 */
644 if (vport->vport_id) {
645 kinfo->tc_info.num_tc = 1;
646 vport->qs_offset = HNAE3_MAX_TC +
647 vport->vport_id - HCLGE_VF_VPORT_START_NUM;
648 vport_max_rss_size = hdev->vf_rss_size_max;
649 } else {
650 kinfo->tc_info.num_tc =
651 min_t(u16, vport->alloc_tqps, hdev->tm_info.num_tc);
652 vport->qs_offset = 0;
653 vport_max_rss_size = hdev->pf_rss_size_max;
654 }
655
656 max_rss_size = min_t(u16, vport_max_rss_size,
657 hclge_vport_get_max_rss_size(vport));
658
659 /* Set to user value, no larger than max_rss_size. */
660 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
661 kinfo->req_rss_size <= max_rss_size) {
662 dev_info(&hdev->pdev->dev, "rss changes from %u to %u\n",
663 kinfo->rss_size, kinfo->req_rss_size);
664 kinfo->rss_size = kinfo->req_rss_size;
665 } else if (kinfo->rss_size > max_rss_size ||
666 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) {
667 /* Set to the maximum specification value (max_rss_size). */
668 kinfo->rss_size = max_rss_size;
669 }
670 }
671
hclge_tm_vport_tc_info_update(struct hclge_vport * vport)672 static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
673 {
674 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
675 struct hclge_dev *hdev = vport->back;
676 u8 i;
677
678 hclge_tm_update_kinfo_rss_size(vport);
679 kinfo->num_tqps = hclge_vport_get_tqp_num(vport);
680 vport->dwrr = 100; /* 100 percent as init */
681 vport->alloc_rss_size = kinfo->rss_size;
682 vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit;
683
684 /* when enable mqprio, the tc_info has been updated. */
685 if (kinfo->tc_info.mqprio_active)
686 return;
687
688 for (i = 0; i < HNAE3_MAX_TC; i++) {
689 if (hdev->hw_tc_map & BIT(i) && i < kinfo->tc_info.num_tc) {
690 set_bit(i, &kinfo->tc_info.tc_en);
691 kinfo->tc_info.tqp_offset[i] = i * kinfo->rss_size;
692 kinfo->tc_info.tqp_count[i] = kinfo->rss_size;
693 } else {
694 /* Set to default queue if TC is disable */
695 clear_bit(i, &kinfo->tc_info.tc_en);
696 kinfo->tc_info.tqp_offset[i] = 0;
697 kinfo->tc_info.tqp_count[i] = 1;
698 }
699 }
700
701 memcpy(kinfo->tc_info.prio_tc, hdev->tm_info.prio_tc,
702 sizeof_field(struct hnae3_tc_info, prio_tc));
703 }
704
hclge_tm_vport_info_update(struct hclge_dev * hdev)705 static void hclge_tm_vport_info_update(struct hclge_dev *hdev)
706 {
707 struct hclge_vport *vport = hdev->vport;
708 u32 i;
709
710 for (i = 0; i < hdev->num_alloc_vport; i++) {
711 hclge_tm_vport_tc_info_update(vport);
712
713 vport++;
714 }
715 }
716
hclge_tm_tc_info_init(struct hclge_dev * hdev)717 static void hclge_tm_tc_info_init(struct hclge_dev *hdev)
718 {
719 u8 i;
720
721 for (i = 0; i < hdev->tm_info.num_tc; i++) {
722 hdev->tm_info.tc_info[i].tc_id = i;
723 hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR;
724 hdev->tm_info.tc_info[i].pgid = 0;
725 hdev->tm_info.tc_info[i].bw_limit =
726 hdev->tm_info.pg_info[0].bw_limit;
727 }
728
729 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
730 hdev->tm_info.prio_tc[i] =
731 (i >= hdev->tm_info.num_tc) ? 0 : i;
732
733 /* DCB is enabled if we have more than 1 TC or pfc_en is
734 * non-zero.
735 */
736 if (hdev->tm_info.num_tc > 1 || hdev->tm_info.pfc_en)
737 hdev->flag |= HCLGE_FLAG_DCB_ENABLE;
738 else
739 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
740 }
741
hclge_tm_pg_info_init(struct hclge_dev * hdev)742 static void hclge_tm_pg_info_init(struct hclge_dev *hdev)
743 {
744 #define BW_PERCENT 100
745
746 u8 i;
747
748 for (i = 0; i < hdev->tm_info.num_pg; i++) {
749 int k;
750
751 hdev->tm_info.pg_dwrr[i] = i ? 0 : BW_PERCENT;
752
753 hdev->tm_info.pg_info[i].pg_id = i;
754 hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR;
755
756 hdev->tm_info.pg_info[i].bw_limit =
757 hdev->ae_dev->dev_specs.max_tm_rate;
758
759 if (i != 0)
760 continue;
761
762 hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map;
763 for (k = 0; k < hdev->tm_info.num_tc; k++)
764 hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT;
765 }
766 }
767
hclge_update_fc_mode_by_dcb_flag(struct hclge_dev * hdev)768 static void hclge_update_fc_mode_by_dcb_flag(struct hclge_dev *hdev)
769 {
770 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE)) {
771 if (hdev->fc_mode_last_time == HCLGE_FC_PFC)
772 dev_warn(&hdev->pdev->dev,
773 "DCB is disable, but last mode is FC_PFC\n");
774
775 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
776 } else if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) {
777 /* fc_mode_last_time record the last fc_mode when
778 * DCB is enabled, so that fc_mode can be set to
779 * the correct value when DCB is disabled.
780 */
781 hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
782 hdev->tm_info.fc_mode = HCLGE_FC_PFC;
783 }
784 }
785
hclge_update_fc_mode(struct hclge_dev * hdev)786 static void hclge_update_fc_mode(struct hclge_dev *hdev)
787 {
788 if (!hdev->tm_info.pfc_en) {
789 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
790 return;
791 }
792
793 if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) {
794 hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
795 hdev->tm_info.fc_mode = HCLGE_FC_PFC;
796 }
797 }
798
hclge_pfc_info_init(struct hclge_dev * hdev)799 static void hclge_pfc_info_init(struct hclge_dev *hdev)
800 {
801 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
802 hclge_update_fc_mode(hdev);
803 else
804 hclge_update_fc_mode_by_dcb_flag(hdev);
805 }
806
hclge_tm_schd_info_init(struct hclge_dev * hdev)807 static void hclge_tm_schd_info_init(struct hclge_dev *hdev)
808 {
809 hclge_tm_pg_info_init(hdev);
810
811 hclge_tm_tc_info_init(hdev);
812
813 hclge_tm_vport_info_update(hdev);
814
815 hclge_pfc_info_init(hdev);
816 }
817
hclge_tm_pg_to_pri_map(struct hclge_dev * hdev)818 static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev)
819 {
820 int ret;
821 u32 i;
822
823 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
824 return 0;
825
826 for (i = 0; i < hdev->tm_info.num_pg; i++) {
827 /* Cfg mapping */
828 ret = hclge_tm_pg_to_pri_map_cfg(
829 hdev, i, hdev->tm_info.pg_info[i].tc_bit_map);
830 if (ret)
831 return ret;
832 }
833
834 return 0;
835 }
836
hclge_tm_pg_shaper_cfg(struct hclge_dev * hdev)837 static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev)
838 {
839 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
840 struct hclge_shaper_ir_para ir_para;
841 u32 shaper_para;
842 int ret;
843 u32 i;
844
845 /* Cfg pg schd */
846 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
847 return 0;
848
849 /* Pg to pri */
850 for (i = 0; i < hdev->tm_info.num_pg; i++) {
851 u32 rate = hdev->tm_info.pg_info[i].bw_limit;
852
853 /* Calc shaper para */
854 ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PG,
855 &ir_para, max_tm_rate);
856 if (ret)
857 return ret;
858
859 shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
860 HCLGE_SHAPER_BS_U_DEF,
861 HCLGE_SHAPER_BS_S_DEF);
862 ret = hclge_tm_pg_shapping_cfg(hdev,
863 HCLGE_TM_SHAP_C_BUCKET, i,
864 shaper_para, rate);
865 if (ret)
866 return ret;
867
868 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b,
869 ir_para.ir_u,
870 ir_para.ir_s,
871 HCLGE_SHAPER_BS_U_DEF,
872 HCLGE_SHAPER_BS_S_DEF);
873 ret = hclge_tm_pg_shapping_cfg(hdev,
874 HCLGE_TM_SHAP_P_BUCKET, i,
875 shaper_para, rate);
876 if (ret)
877 return ret;
878 }
879
880 return 0;
881 }
882
hclge_tm_pg_dwrr_cfg(struct hclge_dev * hdev)883 static int hclge_tm_pg_dwrr_cfg(struct hclge_dev *hdev)
884 {
885 int ret;
886 u32 i;
887
888 /* cfg pg schd */
889 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
890 return 0;
891
892 /* pg to prio */
893 for (i = 0; i < hdev->tm_info.num_pg; i++) {
894 /* Cfg dwrr */
895 ret = hclge_tm_pg_weight_cfg(hdev, i, hdev->tm_info.pg_dwrr[i]);
896 if (ret)
897 return ret;
898 }
899
900 return 0;
901 }
902
hclge_vport_q_to_qs_map(struct hclge_dev * hdev,struct hclge_vport * vport)903 static int hclge_vport_q_to_qs_map(struct hclge_dev *hdev,
904 struct hclge_vport *vport)
905 {
906 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
907 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
908 struct hnae3_queue **tqp = kinfo->tqp;
909 u32 i, j;
910 int ret;
911
912 for (i = 0; i < tc_info->num_tc; i++) {
913 for (j = 0; j < tc_info->tqp_count[i]; j++) {
914 struct hnae3_queue *q = tqp[tc_info->tqp_offset[i] + j];
915
916 ret = hclge_tm_q_to_qs_map_cfg(hdev,
917 hclge_get_queue_id(q),
918 vport->qs_offset + i);
919 if (ret)
920 return ret;
921 }
922 }
923
924 return 0;
925 }
926
hclge_tm_pri_q_qs_cfg(struct hclge_dev * hdev)927 static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev)
928 {
929 struct hclge_vport *vport = hdev->vport;
930 int ret;
931 u32 i, k;
932
933 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
934 /* Cfg qs -> pri mapping, one by one mapping */
935 for (k = 0; k < hdev->num_alloc_vport; k++) {
936 struct hnae3_knic_private_info *kinfo =
937 &vport[k].nic.kinfo;
938
939 for (i = 0; i < kinfo->tc_info.num_tc; i++) {
940 ret = hclge_tm_qs_to_pri_map_cfg(
941 hdev, vport[k].qs_offset + i, i);
942 if (ret)
943 return ret;
944 }
945 }
946 } else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) {
947 /* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */
948 for (k = 0; k < hdev->num_alloc_vport; k++)
949 for (i = 0; i < HNAE3_MAX_TC; i++) {
950 ret = hclge_tm_qs_to_pri_map_cfg(
951 hdev, vport[k].qs_offset + i, k);
952 if (ret)
953 return ret;
954 }
955 } else {
956 return -EINVAL;
957 }
958
959 /* Cfg q -> qs mapping */
960 for (i = 0; i < hdev->num_alloc_vport; i++) {
961 ret = hclge_vport_q_to_qs_map(hdev, vport);
962 if (ret)
963 return ret;
964
965 vport++;
966 }
967
968 return 0;
969 }
970
hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev * hdev)971 static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
972 {
973 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
974 struct hclge_shaper_ir_para ir_para;
975 u32 shaper_para;
976 int ret;
977 u32 i;
978
979 for (i = 0; i < hdev->tm_info.num_tc; i++) {
980 u32 rate = hdev->tm_info.tc_info[i].bw_limit;
981
982 ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PRI,
983 &ir_para, max_tm_rate);
984 if (ret)
985 return ret;
986
987 shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
988 HCLGE_SHAPER_BS_U_DEF,
989 HCLGE_SHAPER_BS_S_DEF);
990 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, i,
991 shaper_para, rate);
992 if (ret)
993 return ret;
994
995 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b,
996 ir_para.ir_u,
997 ir_para.ir_s,
998 HCLGE_SHAPER_BS_U_DEF,
999 HCLGE_SHAPER_BS_S_DEF);
1000 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, i,
1001 shaper_para, rate);
1002 if (ret)
1003 return ret;
1004 }
1005
1006 return 0;
1007 }
1008
hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport * vport)1009 static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport)
1010 {
1011 struct hclge_dev *hdev = vport->back;
1012 struct hclge_shaper_ir_para ir_para;
1013 u32 shaper_para;
1014 int ret;
1015
1016 ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF,
1017 &ir_para,
1018 hdev->ae_dev->dev_specs.max_tm_rate);
1019 if (ret)
1020 return ret;
1021
1022 shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
1023 HCLGE_SHAPER_BS_U_DEF,
1024 HCLGE_SHAPER_BS_S_DEF);
1025 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET,
1026 vport->vport_id, shaper_para,
1027 vport->bw_limit);
1028 if (ret)
1029 return ret;
1030
1031 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
1032 ir_para.ir_s,
1033 HCLGE_SHAPER_BS_U_DEF,
1034 HCLGE_SHAPER_BS_S_DEF);
1035 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET,
1036 vport->vport_id, shaper_para,
1037 vport->bw_limit);
1038 if (ret)
1039 return ret;
1040
1041 return 0;
1042 }
1043
hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport * vport)1044 static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport)
1045 {
1046 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1047 struct hclge_dev *hdev = vport->back;
1048 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
1049 struct hclge_shaper_ir_para ir_para;
1050 u32 i;
1051 int ret;
1052
1053 for (i = 0; i < kinfo->tc_info.num_tc; i++) {
1054 ret = hclge_shaper_para_calc(hdev->tm_info.tc_info[i].bw_limit,
1055 HCLGE_SHAPER_LVL_QSET,
1056 &ir_para, max_tm_rate);
1057 if (ret)
1058 return ret;
1059 }
1060
1061 return 0;
1062 }
1063
hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev * hdev)1064 static int hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev *hdev)
1065 {
1066 struct hclge_vport *vport = hdev->vport;
1067 int ret;
1068 u32 i;
1069
1070 /* Need config vport shaper */
1071 for (i = 0; i < hdev->num_alloc_vport; i++) {
1072 ret = hclge_tm_pri_vnet_base_shaper_pri_cfg(vport);
1073 if (ret)
1074 return ret;
1075
1076 ret = hclge_tm_pri_vnet_base_shaper_qs_cfg(vport);
1077 if (ret)
1078 return ret;
1079
1080 vport++;
1081 }
1082
1083 return 0;
1084 }
1085
hclge_tm_pri_shaper_cfg(struct hclge_dev * hdev)1086 static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev)
1087 {
1088 int ret;
1089
1090 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1091 ret = hclge_tm_pri_tc_base_shaper_cfg(hdev);
1092 if (ret)
1093 return ret;
1094 } else {
1095 ret = hclge_tm_pri_vnet_base_shaper_cfg(hdev);
1096 if (ret)
1097 return ret;
1098 }
1099
1100 return 0;
1101 }
1102
hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev * hdev)1103 static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
1104 {
1105 struct hclge_vport *vport = hdev->vport;
1106 struct hclge_pg_info *pg_info;
1107 u8 dwrr;
1108 int ret;
1109 u32 i, k;
1110
1111 for (i = 0; i < hdev->tm_info.num_tc; i++) {
1112 pg_info =
1113 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
1114 dwrr = pg_info->tc_dwrr[i];
1115
1116 ret = hclge_tm_pri_weight_cfg(hdev, i, dwrr);
1117 if (ret)
1118 return ret;
1119
1120 for (k = 0; k < hdev->num_alloc_vport; k++) {
1121 ret = hclge_tm_qs_weight_cfg(
1122 hdev, vport[k].qs_offset + i,
1123 vport[k].dwrr);
1124 if (ret)
1125 return ret;
1126 }
1127 }
1128
1129 return 0;
1130 }
1131
hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev * hdev)1132 static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev)
1133 {
1134 #define DEFAULT_TC_WEIGHT 1
1135 #define DEFAULT_TC_OFFSET 14
1136
1137 struct hclge_ets_tc_weight_cmd *ets_weight;
1138 struct hclge_desc desc;
1139 unsigned int i;
1140
1141 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, false);
1142 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data;
1143
1144 for (i = 0; i < HNAE3_MAX_TC; i++) {
1145 struct hclge_pg_info *pg_info;
1146
1147 ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT;
1148
1149 if (!(hdev->hw_tc_map & BIT(i)))
1150 continue;
1151
1152 pg_info =
1153 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
1154 ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
1155 }
1156
1157 ets_weight->weight_offset = DEFAULT_TC_OFFSET;
1158
1159 return hclge_cmd_send(&hdev->hw, &desc, 1);
1160 }
1161
hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport * vport)1162 static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport)
1163 {
1164 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1165 struct hclge_dev *hdev = vport->back;
1166 int ret;
1167 u8 i;
1168
1169 /* Vf dwrr */
1170 ret = hclge_tm_pri_weight_cfg(hdev, vport->vport_id, vport->dwrr);
1171 if (ret)
1172 return ret;
1173
1174 /* Qset dwrr */
1175 for (i = 0; i < kinfo->tc_info.num_tc; i++) {
1176 ret = hclge_tm_qs_weight_cfg(
1177 hdev, vport->qs_offset + i,
1178 hdev->tm_info.pg_info[0].tc_dwrr[i]);
1179 if (ret)
1180 return ret;
1181 }
1182
1183 return 0;
1184 }
1185
hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev * hdev)1186 static int hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev *hdev)
1187 {
1188 struct hclge_vport *vport = hdev->vport;
1189 int ret;
1190 u32 i;
1191
1192 for (i = 0; i < hdev->num_alloc_vport; i++) {
1193 ret = hclge_tm_pri_vnet_base_dwrr_pri_cfg(vport);
1194 if (ret)
1195 return ret;
1196
1197 vport++;
1198 }
1199
1200 return 0;
1201 }
1202
hclge_tm_pri_dwrr_cfg(struct hclge_dev * hdev)1203 static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev)
1204 {
1205 int ret;
1206
1207 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1208 ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev);
1209 if (ret)
1210 return ret;
1211
1212 if (!hnae3_dev_dcb_supported(hdev))
1213 return 0;
1214
1215 ret = hclge_tm_ets_tc_dwrr_cfg(hdev);
1216 if (ret == -EOPNOTSUPP) {
1217 dev_warn(&hdev->pdev->dev,
1218 "fw %08x does't support ets tc weight cmd\n",
1219 hdev->fw_version);
1220 ret = 0;
1221 }
1222
1223 return ret;
1224 } else {
1225 ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev);
1226 if (ret)
1227 return ret;
1228 }
1229
1230 return 0;
1231 }
1232
hclge_tm_map_cfg(struct hclge_dev * hdev)1233 static int hclge_tm_map_cfg(struct hclge_dev *hdev)
1234 {
1235 int ret;
1236
1237 ret = hclge_up_to_tc_map(hdev);
1238 if (ret)
1239 return ret;
1240
1241 ret = hclge_tm_pg_to_pri_map(hdev);
1242 if (ret)
1243 return ret;
1244
1245 return hclge_tm_pri_q_qs_cfg(hdev);
1246 }
1247
hclge_tm_shaper_cfg(struct hclge_dev * hdev)1248 static int hclge_tm_shaper_cfg(struct hclge_dev *hdev)
1249 {
1250 int ret;
1251
1252 ret = hclge_tm_port_shaper_cfg(hdev);
1253 if (ret)
1254 return ret;
1255
1256 ret = hclge_tm_pg_shaper_cfg(hdev);
1257 if (ret)
1258 return ret;
1259
1260 return hclge_tm_pri_shaper_cfg(hdev);
1261 }
1262
hclge_tm_dwrr_cfg(struct hclge_dev * hdev)1263 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev)
1264 {
1265 int ret;
1266
1267 ret = hclge_tm_pg_dwrr_cfg(hdev);
1268 if (ret)
1269 return ret;
1270
1271 return hclge_tm_pri_dwrr_cfg(hdev);
1272 }
1273
hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev * hdev)1274 static int hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev *hdev)
1275 {
1276 int ret;
1277 u8 i;
1278
1279 /* Only being config on TC-Based scheduler mode */
1280 if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE)
1281 return 0;
1282
1283 for (i = 0; i < hdev->tm_info.num_pg; i++) {
1284 ret = hclge_tm_pg_schd_mode_cfg(hdev, i);
1285 if (ret)
1286 return ret;
1287 }
1288
1289 return 0;
1290 }
1291
hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport * vport)1292 static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport)
1293 {
1294 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1295 struct hclge_dev *hdev = vport->back;
1296 int ret;
1297 u8 i;
1298
1299 if (vport->vport_id >= HNAE3_MAX_TC)
1300 return -EINVAL;
1301
1302 ret = hclge_tm_pri_schd_mode_cfg(hdev, vport->vport_id);
1303 if (ret)
1304 return ret;
1305
1306 for (i = 0; i < kinfo->tc_info.num_tc; i++) {
1307 u8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode;
1308
1309 ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i,
1310 sch_mode);
1311 if (ret)
1312 return ret;
1313 }
1314
1315 return 0;
1316 }
1317
hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev * hdev)1318 static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)
1319 {
1320 struct hclge_vport *vport = hdev->vport;
1321 int ret;
1322 u8 i, k;
1323
1324 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1325 for (i = 0; i < hdev->tm_info.num_tc; i++) {
1326 ret = hclge_tm_pri_schd_mode_cfg(hdev, i);
1327 if (ret)
1328 return ret;
1329
1330 for (k = 0; k < hdev->num_alloc_vport; k++) {
1331 ret = hclge_tm_qs_schd_mode_cfg(
1332 hdev, vport[k].qs_offset + i,
1333 HCLGE_SCH_MODE_DWRR);
1334 if (ret)
1335 return ret;
1336 }
1337 }
1338 } else {
1339 for (i = 0; i < hdev->num_alloc_vport; i++) {
1340 ret = hclge_tm_schd_mode_vnet_base_cfg(vport);
1341 if (ret)
1342 return ret;
1343
1344 vport++;
1345 }
1346 }
1347
1348 return 0;
1349 }
1350
hclge_tm_schd_mode_hw(struct hclge_dev * hdev)1351 static int hclge_tm_schd_mode_hw(struct hclge_dev *hdev)
1352 {
1353 int ret;
1354
1355 ret = hclge_tm_lvl2_schd_mode_cfg(hdev);
1356 if (ret)
1357 return ret;
1358
1359 return hclge_tm_lvl34_schd_mode_cfg(hdev);
1360 }
1361
hclge_tm_schd_setup_hw(struct hclge_dev * hdev)1362 int hclge_tm_schd_setup_hw(struct hclge_dev *hdev)
1363 {
1364 int ret;
1365
1366 /* Cfg tm mapping */
1367 ret = hclge_tm_map_cfg(hdev);
1368 if (ret)
1369 return ret;
1370
1371 /* Cfg tm shaper */
1372 ret = hclge_tm_shaper_cfg(hdev);
1373 if (ret)
1374 return ret;
1375
1376 /* Cfg dwrr */
1377 ret = hclge_tm_dwrr_cfg(hdev);
1378 if (ret)
1379 return ret;
1380
1381 /* Cfg schd mode for each level schd */
1382 return hclge_tm_schd_mode_hw(hdev);
1383 }
1384
hclge_pause_param_setup_hw(struct hclge_dev * hdev)1385 static int hclge_pause_param_setup_hw(struct hclge_dev *hdev)
1386 {
1387 struct hclge_mac *mac = &hdev->hw.mac;
1388
1389 return hclge_pause_param_cfg(hdev, mac->mac_addr,
1390 HCLGE_DEFAULT_PAUSE_TRANS_GAP,
1391 HCLGE_DEFAULT_PAUSE_TRANS_TIME);
1392 }
1393
hclge_pfc_setup_hw(struct hclge_dev * hdev)1394 static int hclge_pfc_setup_hw(struct hclge_dev *hdev)
1395 {
1396 u8 enable_bitmap = 0;
1397
1398 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
1399 enable_bitmap = HCLGE_TX_MAC_PAUSE_EN_MSK |
1400 HCLGE_RX_MAC_PAUSE_EN_MSK;
1401
1402 return hclge_pfc_pause_en_cfg(hdev, enable_bitmap,
1403 hdev->tm_info.pfc_en);
1404 }
1405
1406 /* for the queues that use for backpress, divides to several groups,
1407 * each group contains 32 queue sets, which can be represented by u32 bitmap.
1408 */
hclge_bp_setup_hw(struct hclge_dev * hdev,u8 tc)1409 static int hclge_bp_setup_hw(struct hclge_dev *hdev, u8 tc)
1410 {
1411 u16 grp_id_shift = HCLGE_BP_GRP_ID_S;
1412 u16 grp_id_mask = HCLGE_BP_GRP_ID_M;
1413 u8 grp_num = HCLGE_BP_GRP_NUM;
1414 int i;
1415
1416 if (hdev->num_tqps > HCLGE_TQP_MAX_SIZE_DEV_V2) {
1417 grp_num = HCLGE_BP_EXT_GRP_NUM;
1418 grp_id_mask = HCLGE_BP_EXT_GRP_ID_M;
1419 grp_id_shift = HCLGE_BP_EXT_GRP_ID_S;
1420 }
1421
1422 for (i = 0; i < grp_num; i++) {
1423 u32 qs_bitmap = 0;
1424 int k, ret;
1425
1426 for (k = 0; k < hdev->num_alloc_vport; k++) {
1427 struct hclge_vport *vport = &hdev->vport[k];
1428 u16 qs_id = vport->qs_offset + tc;
1429 u8 grp, sub_grp;
1430
1431 grp = hnae3_get_field(qs_id, grp_id_mask, grp_id_shift);
1432 sub_grp = hnae3_get_field(qs_id, HCLGE_BP_SUB_GRP_ID_M,
1433 HCLGE_BP_SUB_GRP_ID_S);
1434 if (i == grp)
1435 qs_bitmap |= (1 << sub_grp);
1436 }
1437
1438 ret = hclge_tm_qs_bp_cfg(hdev, tc, i, qs_bitmap);
1439 if (ret)
1440 return ret;
1441 }
1442
1443 return 0;
1444 }
1445
hclge_mac_pause_setup_hw(struct hclge_dev * hdev)1446 static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev)
1447 {
1448 bool tx_en, rx_en;
1449
1450 switch (hdev->tm_info.fc_mode) {
1451 case HCLGE_FC_NONE:
1452 tx_en = false;
1453 rx_en = false;
1454 break;
1455 case HCLGE_FC_RX_PAUSE:
1456 tx_en = false;
1457 rx_en = true;
1458 break;
1459 case HCLGE_FC_TX_PAUSE:
1460 tx_en = true;
1461 rx_en = false;
1462 break;
1463 case HCLGE_FC_FULL:
1464 tx_en = true;
1465 rx_en = true;
1466 break;
1467 case HCLGE_FC_PFC:
1468 tx_en = false;
1469 rx_en = false;
1470 break;
1471 default:
1472 tx_en = true;
1473 rx_en = true;
1474 }
1475
1476 return hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
1477 }
1478
hclge_tm_bp_setup(struct hclge_dev * hdev)1479 static int hclge_tm_bp_setup(struct hclge_dev *hdev)
1480 {
1481 int ret;
1482 int i;
1483
1484 for (i = 0; i < hdev->tm_info.num_tc; i++) {
1485 ret = hclge_bp_setup_hw(hdev, i);
1486 if (ret)
1487 return ret;
1488 }
1489
1490 return 0;
1491 }
1492
hclge_pause_setup_hw(struct hclge_dev * hdev,bool init)1493 int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init)
1494 {
1495 int ret;
1496
1497 ret = hclge_pause_param_setup_hw(hdev);
1498 if (ret)
1499 return ret;
1500
1501 ret = hclge_mac_pause_setup_hw(hdev);
1502 if (ret)
1503 return ret;
1504
1505 /* Only DCB-supported dev supports qset back pressure and pfc cmd */
1506 if (!hnae3_dev_dcb_supported(hdev))
1507 return 0;
1508
1509 /* GE MAC does not support PFC, when driver is initializing and MAC
1510 * is in GE Mode, ignore the error here, otherwise initialization
1511 * will fail.
1512 */
1513 ret = hclge_pfc_setup_hw(hdev);
1514 if (init && ret == -EOPNOTSUPP)
1515 dev_warn(&hdev->pdev->dev, "GE MAC does not support pfc\n");
1516 else if (ret) {
1517 dev_err(&hdev->pdev->dev, "config pfc failed! ret = %d\n",
1518 ret);
1519 return ret;
1520 }
1521
1522 return hclge_tm_bp_setup(hdev);
1523 }
1524
hclge_tm_prio_tc_info_update(struct hclge_dev * hdev,u8 * prio_tc)1525 void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc)
1526 {
1527 struct hclge_vport *vport = hdev->vport;
1528 struct hnae3_knic_private_info *kinfo;
1529 u32 i, k;
1530
1531 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
1532 hdev->tm_info.prio_tc[i] = prio_tc[i];
1533
1534 for (k = 0; k < hdev->num_alloc_vport; k++) {
1535 kinfo = &vport[k].nic.kinfo;
1536 kinfo->tc_info.prio_tc[i] = prio_tc[i];
1537 }
1538 }
1539 }
1540
hclge_tm_schd_info_update(struct hclge_dev * hdev,u8 num_tc)1541 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc)
1542 {
1543 u8 bit_map = 0;
1544 u8 i;
1545
1546 hdev->tm_info.num_tc = num_tc;
1547
1548 for (i = 0; i < hdev->tm_info.num_tc; i++)
1549 bit_map |= BIT(i);
1550
1551 if (!bit_map) {
1552 bit_map = 1;
1553 hdev->tm_info.num_tc = 1;
1554 }
1555
1556 hdev->hw_tc_map = bit_map;
1557
1558 hclge_tm_schd_info_init(hdev);
1559 }
1560
hclge_tm_pfc_info_update(struct hclge_dev * hdev)1561 void hclge_tm_pfc_info_update(struct hclge_dev *hdev)
1562 {
1563 /* DCB is enabled if we have more than 1 TC or pfc_en is
1564 * non-zero.
1565 */
1566 if (hdev->tm_info.num_tc > 1 || hdev->tm_info.pfc_en)
1567 hdev->flag |= HCLGE_FLAG_DCB_ENABLE;
1568 else
1569 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
1570
1571 hclge_pfc_info_init(hdev);
1572 }
1573
hclge_tm_init_hw(struct hclge_dev * hdev,bool init)1574 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init)
1575 {
1576 int ret;
1577
1578 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) &&
1579 (hdev->tx_sch_mode != HCLGE_FLAG_VNET_BASE_SCH_MODE))
1580 return -ENOTSUPP;
1581
1582 ret = hclge_tm_schd_setup_hw(hdev);
1583 if (ret)
1584 return ret;
1585
1586 ret = hclge_pause_setup_hw(hdev, init);
1587 if (ret)
1588 return ret;
1589
1590 return 0;
1591 }
1592
hclge_tm_schd_init(struct hclge_dev * hdev)1593 int hclge_tm_schd_init(struct hclge_dev *hdev)
1594 {
1595 /* fc_mode is HCLGE_FC_FULL on reset */
1596 hdev->tm_info.fc_mode = HCLGE_FC_FULL;
1597 hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
1598
1599 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE &&
1600 hdev->tm_info.num_pg != 1)
1601 return -EINVAL;
1602
1603 hclge_tm_schd_info_init(hdev);
1604
1605 return hclge_tm_init_hw(hdev, true);
1606 }
1607
hclge_tm_vport_map_update(struct hclge_dev * hdev)1608 int hclge_tm_vport_map_update(struct hclge_dev *hdev)
1609 {
1610 struct hclge_vport *vport = hdev->vport;
1611 int ret;
1612
1613 hclge_tm_vport_tc_info_update(vport);
1614
1615 ret = hclge_vport_q_to_qs_map(hdev, vport);
1616 if (ret)
1617 return ret;
1618
1619 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE))
1620 return 0;
1621
1622 return hclge_tm_bp_setup(hdev);
1623 }
1624
hclge_tm_get_qset_num(struct hclge_dev * hdev,u16 * qset_num)1625 int hclge_tm_get_qset_num(struct hclge_dev *hdev, u16 *qset_num)
1626 {
1627 struct hclge_tm_nodes_cmd *nodes;
1628 struct hclge_desc desc;
1629 int ret;
1630
1631 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) {
1632 /* Each PF has 8 qsets and each VF has 1 qset */
1633 *qset_num = HCLGE_TM_PF_MAX_QSET_NUM + pci_num_vf(hdev->pdev);
1634 return 0;
1635 }
1636
1637 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true);
1638 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1639 if (ret) {
1640 dev_err(&hdev->pdev->dev,
1641 "failed to get qset num, ret = %d\n", ret);
1642 return ret;
1643 }
1644
1645 nodes = (struct hclge_tm_nodes_cmd *)desc.data;
1646 *qset_num = le16_to_cpu(nodes->qset_num);
1647 return 0;
1648 }
1649
hclge_tm_get_pri_num(struct hclge_dev * hdev,u8 * pri_num)1650 int hclge_tm_get_pri_num(struct hclge_dev *hdev, u8 *pri_num)
1651 {
1652 struct hclge_tm_nodes_cmd *nodes;
1653 struct hclge_desc desc;
1654 int ret;
1655
1656 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) {
1657 *pri_num = HCLGE_TM_PF_MAX_PRI_NUM;
1658 return 0;
1659 }
1660
1661 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true);
1662 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1663 if (ret) {
1664 dev_err(&hdev->pdev->dev,
1665 "failed to get pri num, ret = %d\n", ret);
1666 return ret;
1667 }
1668
1669 nodes = (struct hclge_tm_nodes_cmd *)desc.data;
1670 *pri_num = nodes->pri_num;
1671 return 0;
1672 }
1673
hclge_tm_get_qset_map_pri(struct hclge_dev * hdev,u16 qset_id,u8 * priority,u8 * link_vld)1674 int hclge_tm_get_qset_map_pri(struct hclge_dev *hdev, u16 qset_id, u8 *priority,
1675 u8 *link_vld)
1676 {
1677 struct hclge_qs_to_pri_link_cmd *map;
1678 struct hclge_desc desc;
1679 int ret;
1680
1681 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, true);
1682 map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
1683 map->qs_id = cpu_to_le16(qset_id);
1684 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1685 if (ret) {
1686 dev_err(&hdev->pdev->dev,
1687 "failed to get qset map priority, ret = %d\n", ret);
1688 return ret;
1689 }
1690
1691 *priority = map->priority;
1692 *link_vld = map->link_vld;
1693 return 0;
1694 }
1695
hclge_tm_get_qset_sch_mode(struct hclge_dev * hdev,u16 qset_id,u8 * mode)1696 int hclge_tm_get_qset_sch_mode(struct hclge_dev *hdev, u16 qset_id, u8 *mode)
1697 {
1698 struct hclge_qs_sch_mode_cfg_cmd *qs_sch_mode;
1699 struct hclge_desc desc;
1700 int ret;
1701
1702 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, true);
1703 qs_sch_mode = (struct hclge_qs_sch_mode_cfg_cmd *)desc.data;
1704 qs_sch_mode->qs_id = cpu_to_le16(qset_id);
1705 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1706 if (ret) {
1707 dev_err(&hdev->pdev->dev,
1708 "failed to get qset sch mode, ret = %d\n", ret);
1709 return ret;
1710 }
1711
1712 *mode = qs_sch_mode->sch_mode;
1713 return 0;
1714 }
1715
hclge_tm_get_qset_weight(struct hclge_dev * hdev,u16 qset_id,u8 * weight)1716 int hclge_tm_get_qset_weight(struct hclge_dev *hdev, u16 qset_id, u8 *weight)
1717 {
1718 struct hclge_qs_weight_cmd *qs_weight;
1719 struct hclge_desc desc;
1720 int ret;
1721
1722 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, true);
1723 qs_weight = (struct hclge_qs_weight_cmd *)desc.data;
1724 qs_weight->qs_id = cpu_to_le16(qset_id);
1725 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1726 if (ret) {
1727 dev_err(&hdev->pdev->dev,
1728 "failed to get qset weight, ret = %d\n", ret);
1729 return ret;
1730 }
1731
1732 *weight = qs_weight->dwrr;
1733 return 0;
1734 }
1735
hclge_tm_get_pri_sch_mode(struct hclge_dev * hdev,u8 pri_id,u8 * mode)1736 int hclge_tm_get_pri_sch_mode(struct hclge_dev *hdev, u8 pri_id, u8 *mode)
1737 {
1738 struct hclge_pri_sch_mode_cfg_cmd *pri_sch_mode;
1739 struct hclge_desc desc;
1740 int ret;
1741
1742 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, true);
1743 pri_sch_mode = (struct hclge_pri_sch_mode_cfg_cmd *)desc.data;
1744 pri_sch_mode->pri_id = pri_id;
1745 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1746 if (ret) {
1747 dev_err(&hdev->pdev->dev,
1748 "failed to get priority sch mode, ret = %d\n", ret);
1749 return ret;
1750 }
1751
1752 *mode = pri_sch_mode->sch_mode;
1753 return 0;
1754 }
1755
hclge_tm_get_pri_weight(struct hclge_dev * hdev,u8 pri_id,u8 * weight)1756 int hclge_tm_get_pri_weight(struct hclge_dev *hdev, u8 pri_id, u8 *weight)
1757 {
1758 struct hclge_priority_weight_cmd *priority_weight;
1759 struct hclge_desc desc;
1760 int ret;
1761
1762 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, true);
1763 priority_weight = (struct hclge_priority_weight_cmd *)desc.data;
1764 priority_weight->pri_id = pri_id;
1765 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1766 if (ret) {
1767 dev_err(&hdev->pdev->dev,
1768 "failed to get priority weight, ret = %d\n", ret);
1769 return ret;
1770 }
1771
1772 *weight = priority_weight->dwrr;
1773 return 0;
1774 }
1775
hclge_tm_get_pri_shaper(struct hclge_dev * hdev,u8 pri_id,enum hclge_opcode_type cmd,struct hclge_pri_shaper_para * para)1776 int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id,
1777 enum hclge_opcode_type cmd,
1778 struct hclge_pri_shaper_para *para)
1779 {
1780 struct hclge_pri_shapping_cmd *shap_cfg_cmd;
1781 struct hclge_desc desc;
1782 u32 shapping_para;
1783 int ret;
1784
1785 if (cmd != HCLGE_OPC_TM_PRI_C_SHAPPING &&
1786 cmd != HCLGE_OPC_TM_PRI_P_SHAPPING)
1787 return -EINVAL;
1788
1789 hclge_cmd_setup_basic_desc(&desc, cmd, true);
1790 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
1791 shap_cfg_cmd->pri_id = pri_id;
1792 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1793 if (ret) {
1794 dev_err(&hdev->pdev->dev,
1795 "failed to get priority shaper(%#x), ret = %d\n",
1796 cmd, ret);
1797 return ret;
1798 }
1799
1800 shapping_para = le32_to_cpu(shap_cfg_cmd->pri_shapping_para);
1801 para->ir_b = hclge_tm_get_field(shapping_para, IR_B);
1802 para->ir_u = hclge_tm_get_field(shapping_para, IR_U);
1803 para->ir_s = hclge_tm_get_field(shapping_para, IR_S);
1804 para->bs_b = hclge_tm_get_field(shapping_para, BS_B);
1805 para->bs_s = hclge_tm_get_field(shapping_para, BS_S);
1806 para->flag = shap_cfg_cmd->flag;
1807 para->rate = le32_to_cpu(shap_cfg_cmd->pri_rate);
1808 return 0;
1809 }
1810