1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2019, Mellanox Technologies */ 3 4 #ifndef MLX5_IFC_DR_H 5 #define MLX5_IFC_DR_H 6 7 enum { 8 MLX5DR_STE_LU_TYPE_DONT_CARE = 0x0f, 9 }; 10 11 enum mlx5dr_ste_entry_type { 12 MLX5DR_STE_TYPE_TX = 1, 13 MLX5DR_STE_TYPE_RX = 2, 14 MLX5DR_STE_TYPE_MODIFY_PKT = 6, 15 }; 16 17 struct mlx5_ifc_ste_general_bits { 18 u8 entry_type[0x4]; 19 u8 reserved_at_4[0x4]; 20 u8 entry_sub_type[0x8]; 21 u8 byte_mask[0x10]; 22 23 u8 next_table_base_63_48[0x10]; 24 u8 next_lu_type[0x8]; 25 u8 next_table_base_39_32_size[0x8]; 26 27 u8 next_table_base_31_5_size[0x1b]; 28 u8 linear_hash_enable[0x1]; 29 u8 reserved_at_5c[0x2]; 30 u8 next_table_rank[0x2]; 31 32 u8 reserved_at_60[0xa0]; 33 u8 tag_value[0x60]; 34 u8 bit_mask[0x60]; 35 }; 36 37 struct mlx5_ifc_ste_sx_transmit_bits { 38 u8 entry_type[0x4]; 39 u8 reserved_at_4[0x4]; 40 u8 entry_sub_type[0x8]; 41 u8 byte_mask[0x10]; 42 43 u8 next_table_base_63_48[0x10]; 44 u8 next_lu_type[0x8]; 45 u8 next_table_base_39_32_size[0x8]; 46 47 u8 next_table_base_31_5_size[0x1b]; 48 u8 linear_hash_enable[0x1]; 49 u8 reserved_at_5c[0x2]; 50 u8 next_table_rank[0x2]; 51 52 u8 sx_wire[0x1]; 53 u8 sx_func_lb[0x1]; 54 u8 sx_sniffer[0x1]; 55 u8 sx_wire_enable[0x1]; 56 u8 sx_func_lb_enable[0x1]; 57 u8 sx_sniffer_enable[0x1]; 58 u8 action_type[0x3]; 59 u8 reserved_at_69[0x1]; 60 u8 action_description[0x6]; 61 u8 gvmi[0x10]; 62 63 u8 encap_pointer_vlan_data[0x20]; 64 65 u8 loopback_syndome_en[0x8]; 66 u8 loopback_syndome[0x8]; 67 u8 counter_trigger[0x10]; 68 69 u8 miss_address_63_48[0x10]; 70 u8 counter_trigger_23_16[0x8]; 71 u8 miss_address_39_32[0x8]; 72 73 u8 miss_address_31_6[0x1a]; 74 u8 learning_point[0x1]; 75 u8 go_back[0x1]; 76 u8 match_polarity[0x1]; 77 u8 mask_mode[0x1]; 78 u8 miss_rank[0x2]; 79 }; 80 81 struct mlx5_ifc_ste_rx_steering_mult_bits { 82 u8 entry_type[0x4]; 83 u8 reserved_at_4[0x4]; 84 u8 entry_sub_type[0x8]; 85 u8 byte_mask[0x10]; 86 87 u8 next_table_base_63_48[0x10]; 88 u8 next_lu_type[0x8]; 89 u8 next_table_base_39_32_size[0x8]; 90 91 u8 next_table_base_31_5_size[0x1b]; 92 u8 linear_hash_enable[0x1]; 93 u8 reserved_at_[0x2]; 94 u8 next_table_rank[0x2]; 95 96 u8 member_count[0x10]; 97 u8 gvmi[0x10]; 98 99 u8 qp_list_pointer[0x20]; 100 101 u8 reserved_at_a0[0x1]; 102 u8 tunneling_action[0x3]; 103 u8 action_description[0x4]; 104 u8 reserved_at_a8[0x8]; 105 u8 counter_trigger_15_0[0x10]; 106 107 u8 miss_address_63_48[0x10]; 108 u8 counter_trigger_23_16[0x08]; 109 u8 miss_address_39_32[0x8]; 110 111 u8 miss_address_31_6[0x1a]; 112 u8 learning_point[0x1]; 113 u8 fail_on_error[0x1]; 114 u8 match_polarity[0x1]; 115 u8 mask_mode[0x1]; 116 u8 miss_rank[0x2]; 117 }; 118 119 struct mlx5_ifc_ste_modify_packet_bits { 120 u8 entry_type[0x4]; 121 u8 reserved_at_4[0x4]; 122 u8 entry_sub_type[0x8]; 123 u8 byte_mask[0x10]; 124 125 u8 next_table_base_63_48[0x10]; 126 u8 next_lu_type[0x8]; 127 u8 next_table_base_39_32_size[0x8]; 128 129 u8 next_table_base_31_5_size[0x1b]; 130 u8 linear_hash_enable[0x1]; 131 u8 reserved_at_[0x2]; 132 u8 next_table_rank[0x2]; 133 134 u8 number_of_re_write_actions[0x10]; 135 u8 gvmi[0x10]; 136 137 u8 header_re_write_actions_pointer[0x20]; 138 139 u8 reserved_at_a0[0x1]; 140 u8 tunneling_action[0x3]; 141 u8 action_description[0x4]; 142 u8 reserved_at_a8[0x8]; 143 u8 counter_trigger_15_0[0x10]; 144 145 u8 miss_address_63_48[0x10]; 146 u8 counter_trigger_23_16[0x08]; 147 u8 miss_address_39_32[0x8]; 148 149 u8 miss_address_31_6[0x1a]; 150 u8 learning_point[0x1]; 151 u8 fail_on_error[0x1]; 152 u8 match_polarity[0x1]; 153 u8 mask_mode[0x1]; 154 u8 miss_rank[0x2]; 155 }; 156 157 struct mlx5_ifc_ste_eth_l2_src_bits { 158 u8 smac_47_16[0x20]; 159 160 u8 smac_15_0[0x10]; 161 u8 l3_ethertype[0x10]; 162 163 u8 qp_type[0x2]; 164 u8 ethertype_filter[0x1]; 165 u8 reserved_at_43[0x1]; 166 u8 sx_sniffer[0x1]; 167 u8 force_lb[0x1]; 168 u8 functional_lb[0x1]; 169 u8 port[0x1]; 170 u8 reserved_at_48[0x4]; 171 u8 first_priority[0x3]; 172 u8 first_cfi[0x1]; 173 u8 first_vlan_qualifier[0x2]; 174 u8 reserved_at_52[0x2]; 175 u8 first_vlan_id[0xc]; 176 177 u8 ip_fragmented[0x1]; 178 u8 tcp_syn[0x1]; 179 u8 encp_type[0x2]; 180 u8 l3_type[0x2]; 181 u8 l4_type[0x2]; 182 u8 reserved_at_68[0x4]; 183 u8 second_priority[0x3]; 184 u8 second_cfi[0x1]; 185 u8 second_vlan_qualifier[0x2]; 186 u8 reserved_at_72[0x2]; 187 u8 second_vlan_id[0xc]; 188 }; 189 190 struct mlx5_ifc_ste_eth_l2_dst_bits { 191 u8 dmac_47_16[0x20]; 192 193 u8 dmac_15_0[0x10]; 194 u8 l3_ethertype[0x10]; 195 196 u8 qp_type[0x2]; 197 u8 ethertype_filter[0x1]; 198 u8 reserved_at_43[0x1]; 199 u8 sx_sniffer[0x1]; 200 u8 force_lb[0x1]; 201 u8 functional_lb[0x1]; 202 u8 port[0x1]; 203 u8 reserved_at_48[0x4]; 204 u8 first_priority[0x3]; 205 u8 first_cfi[0x1]; 206 u8 first_vlan_qualifier[0x2]; 207 u8 reserved_at_52[0x2]; 208 u8 first_vlan_id[0xc]; 209 210 u8 ip_fragmented[0x1]; 211 u8 tcp_syn[0x1]; 212 u8 encp_type[0x2]; 213 u8 l3_type[0x2]; 214 u8 l4_type[0x2]; 215 u8 reserved_at_68[0x4]; 216 u8 second_priority[0x3]; 217 u8 second_cfi[0x1]; 218 u8 second_vlan_qualifier[0x2]; 219 u8 reserved_at_72[0x2]; 220 u8 second_vlan_id[0xc]; 221 }; 222 223 struct mlx5_ifc_ste_eth_l2_src_dst_bits { 224 u8 dmac_47_16[0x20]; 225 226 u8 dmac_15_0[0x10]; 227 u8 smac_47_32[0x10]; 228 229 u8 smac_31_0[0x20]; 230 231 u8 sx_sniffer[0x1]; 232 u8 force_lb[0x1]; 233 u8 functional_lb[0x1]; 234 u8 port[0x1]; 235 u8 l3_type[0x2]; 236 u8 reserved_at_66[0x6]; 237 u8 first_priority[0x3]; 238 u8 first_cfi[0x1]; 239 u8 first_vlan_qualifier[0x2]; 240 u8 reserved_at_72[0x2]; 241 u8 first_vlan_id[0xc]; 242 }; 243 244 struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_bits { 245 u8 destination_address[0x20]; 246 247 u8 source_address[0x20]; 248 249 u8 source_port[0x10]; 250 u8 destination_port[0x10]; 251 252 u8 fragmented[0x1]; 253 u8 first_fragment[0x1]; 254 u8 reserved_at_62[0x2]; 255 u8 reserved_at_64[0x1]; 256 u8 ecn[0x2]; 257 u8 tcp_ns[0x1]; 258 u8 tcp_cwr[0x1]; 259 u8 tcp_ece[0x1]; 260 u8 tcp_urg[0x1]; 261 u8 tcp_ack[0x1]; 262 u8 tcp_psh[0x1]; 263 u8 tcp_rst[0x1]; 264 u8 tcp_syn[0x1]; 265 u8 tcp_fin[0x1]; 266 u8 dscp[0x6]; 267 u8 reserved_at_76[0x2]; 268 u8 protocol[0x8]; 269 }; 270 271 struct mlx5_ifc_ste_eth_l3_ipv6_dst_bits { 272 u8 dst_ip_127_96[0x20]; 273 274 u8 dst_ip_95_64[0x20]; 275 276 u8 dst_ip_63_32[0x20]; 277 278 u8 dst_ip_31_0[0x20]; 279 }; 280 281 struct mlx5_ifc_ste_eth_l2_tnl_bits { 282 u8 dmac_47_16[0x20]; 283 284 u8 dmac_15_0[0x10]; 285 u8 l3_ethertype[0x10]; 286 287 u8 l2_tunneling_network_id[0x20]; 288 289 u8 ip_fragmented[0x1]; 290 u8 tcp_syn[0x1]; 291 u8 encp_type[0x2]; 292 u8 l3_type[0x2]; 293 u8 l4_type[0x2]; 294 u8 first_priority[0x3]; 295 u8 first_cfi[0x1]; 296 u8 reserved_at_6c[0x3]; 297 u8 gre_key_flag[0x1]; 298 u8 first_vlan_qualifier[0x2]; 299 u8 reserved_at_72[0x2]; 300 u8 first_vlan_id[0xc]; 301 }; 302 303 struct mlx5_ifc_ste_eth_l3_ipv6_src_bits { 304 u8 src_ip_127_96[0x20]; 305 306 u8 src_ip_95_64[0x20]; 307 308 u8 src_ip_63_32[0x20]; 309 310 u8 src_ip_31_0[0x20]; 311 }; 312 313 struct mlx5_ifc_ste_eth_l3_ipv4_misc_bits { 314 u8 version[0x4]; 315 u8 ihl[0x4]; 316 u8 reserved_at_8[0x8]; 317 u8 total_length[0x10]; 318 319 u8 identification[0x10]; 320 u8 flags[0x3]; 321 u8 fragment_offset[0xd]; 322 323 u8 time_to_live[0x8]; 324 u8 reserved_at_48[0x8]; 325 u8 checksum[0x10]; 326 327 u8 reserved_at_60[0x20]; 328 }; 329 330 struct mlx5_ifc_ste_eth_l4_bits { 331 u8 fragmented[0x1]; 332 u8 first_fragment[0x1]; 333 u8 reserved_at_2[0x6]; 334 u8 protocol[0x8]; 335 u8 dst_port[0x10]; 336 337 u8 ipv6_version[0x4]; 338 u8 reserved_at_24[0x1]; 339 u8 ecn[0x2]; 340 u8 tcp_ns[0x1]; 341 u8 tcp_cwr[0x1]; 342 u8 tcp_ece[0x1]; 343 u8 tcp_urg[0x1]; 344 u8 tcp_ack[0x1]; 345 u8 tcp_psh[0x1]; 346 u8 tcp_rst[0x1]; 347 u8 tcp_syn[0x1]; 348 u8 tcp_fin[0x1]; 349 u8 src_port[0x10]; 350 351 u8 ipv6_payload_length[0x10]; 352 u8 ipv6_hop_limit[0x8]; 353 u8 dscp[0x6]; 354 u8 reserved_at_5e[0x2]; 355 356 u8 tcp_data_offset[0x4]; 357 u8 reserved_at_64[0x8]; 358 u8 flow_label[0x14]; 359 }; 360 361 struct mlx5_ifc_ste_eth_l4_misc_bits { 362 u8 checksum[0x10]; 363 u8 length[0x10]; 364 365 u8 seq_num[0x20]; 366 367 u8 ack_num[0x20]; 368 369 u8 urgent_pointer[0x10]; 370 u8 window_size[0x10]; 371 }; 372 373 struct mlx5_ifc_ste_mpls_bits { 374 u8 mpls0_label[0x14]; 375 u8 mpls0_exp[0x3]; 376 u8 mpls0_s_bos[0x1]; 377 u8 mpls0_ttl[0x8]; 378 379 u8 mpls1_label[0x20]; 380 381 u8 mpls2_label[0x20]; 382 383 u8 reserved_at_60[0x16]; 384 u8 mpls4_s_bit[0x1]; 385 u8 mpls4_qualifier[0x1]; 386 u8 mpls3_s_bit[0x1]; 387 u8 mpls3_qualifier[0x1]; 388 u8 mpls2_s_bit[0x1]; 389 u8 mpls2_qualifier[0x1]; 390 u8 mpls1_s_bit[0x1]; 391 u8 mpls1_qualifier[0x1]; 392 u8 mpls0_s_bit[0x1]; 393 u8 mpls0_qualifier[0x1]; 394 }; 395 396 struct mlx5_ifc_ste_register_0_bits { 397 u8 register_0_h[0x20]; 398 399 u8 register_0_l[0x20]; 400 401 u8 register_1_h[0x20]; 402 403 u8 register_1_l[0x20]; 404 }; 405 406 struct mlx5_ifc_ste_register_1_bits { 407 u8 register_2_h[0x20]; 408 409 u8 register_2_l[0x20]; 410 411 u8 register_3_h[0x20]; 412 413 u8 register_3_l[0x20]; 414 }; 415 416 struct mlx5_ifc_ste_gre_bits { 417 u8 gre_c_present[0x1]; 418 u8 reserved_at_30[0x1]; 419 u8 gre_k_present[0x1]; 420 u8 gre_s_present[0x1]; 421 u8 strict_src_route[0x1]; 422 u8 recur[0x3]; 423 u8 flags[0x5]; 424 u8 version[0x3]; 425 u8 gre_protocol[0x10]; 426 427 u8 checksum[0x10]; 428 u8 offset[0x10]; 429 430 u8 gre_key_h[0x18]; 431 u8 gre_key_l[0x8]; 432 433 u8 seq_num[0x20]; 434 }; 435 436 struct mlx5_ifc_ste_flex_parser_0_bits { 437 u8 flex_parser_3[0x20]; 438 439 u8 flex_parser_2[0x20]; 440 441 u8 flex_parser_1[0x20]; 442 443 u8 flex_parser_0[0x20]; 444 }; 445 446 struct mlx5_ifc_ste_flex_parser_1_bits { 447 u8 flex_parser_7[0x20]; 448 449 u8 flex_parser_6[0x20]; 450 451 u8 flex_parser_5[0x20]; 452 453 u8 flex_parser_4[0x20]; 454 }; 455 456 struct mlx5_ifc_ste_flex_parser_tnl_bits { 457 u8 flex_parser_tunneling_header_63_32[0x20]; 458 459 u8 flex_parser_tunneling_header_31_0[0x20]; 460 461 u8 reserved_at_40[0x40]; 462 }; 463 464 struct mlx5_ifc_ste_flex_parser_tnl_vxlan_gpe_bits { 465 u8 outer_vxlan_gpe_flags[0x8]; 466 u8 reserved_at_8[0x10]; 467 u8 outer_vxlan_gpe_next_protocol[0x8]; 468 469 u8 outer_vxlan_gpe_vni[0x18]; 470 u8 reserved_at_38[0x8]; 471 472 u8 reserved_at_40[0x40]; 473 }; 474 475 struct mlx5_ifc_ste_flex_parser_tnl_geneve_bits { 476 u8 reserved_at_0[0x2]; 477 u8 geneve_opt_len[0x6]; 478 u8 geneve_oam[0x1]; 479 u8 reserved_at_9[0x7]; 480 u8 geneve_protocol_type[0x10]; 481 482 u8 geneve_vni[0x18]; 483 u8 reserved_at_38[0x8]; 484 485 u8 reserved_at_40[0x40]; 486 }; 487 488 struct mlx5_ifc_ste_flex_parser_tnl_gtpu_bits { 489 u8 reserved_at_0[0x5]; 490 u8 gtpu_msg_flags[0x3]; 491 u8 gtpu_msg_type[0x8]; 492 u8 reserved_at_10[0x10]; 493 494 u8 gtpu_teid[0x20]; 495 496 u8 reserved_at_40[0x40]; 497 }; 498 499 struct mlx5_ifc_ste_general_purpose_bits { 500 u8 general_purpose_lookup_field[0x20]; 501 502 u8 reserved_at_20[0x20]; 503 504 u8 reserved_at_40[0x20]; 505 506 u8 reserved_at_60[0x20]; 507 }; 508 509 struct mlx5_ifc_ste_src_gvmi_qp_bits { 510 u8 loopback_syndrome[0x8]; 511 u8 reserved_at_8[0x8]; 512 u8 source_gvmi[0x10]; 513 514 u8 reserved_at_20[0x5]; 515 u8 force_lb[0x1]; 516 u8 functional_lb[0x1]; 517 u8 source_is_requestor[0x1]; 518 u8 source_qp[0x18]; 519 520 u8 reserved_at_40[0x20]; 521 522 u8 reserved_at_60[0x20]; 523 }; 524 525 struct mlx5_ifc_l2_hdr_bits { 526 u8 dmac_47_16[0x20]; 527 528 u8 dmac_15_0[0x10]; 529 u8 smac_47_32[0x10]; 530 531 u8 smac_31_0[0x20]; 532 533 u8 ethertype[0x10]; 534 u8 vlan_type[0x10]; 535 536 u8 vlan[0x10]; 537 u8 reserved_at_90[0x10]; 538 }; 539 540 /* Both HW set and HW add share the same HW format with different opcodes */ 541 struct mlx5_ifc_dr_action_hw_set_bits { 542 u8 opcode[0x8]; 543 u8 destination_field_code[0x8]; 544 u8 reserved_at_10[0x2]; 545 u8 destination_left_shifter[0x6]; 546 u8 reserved_at_18[0x3]; 547 u8 destination_length[0x5]; 548 549 u8 inline_data[0x20]; 550 }; 551 552 struct mlx5_ifc_dr_action_hw_copy_bits { 553 u8 opcode[0x8]; 554 u8 destination_field_code[0x8]; 555 u8 reserved_at_10[0x2]; 556 u8 destination_left_shifter[0x6]; 557 u8 reserved_at_18[0x2]; 558 u8 destination_length[0x6]; 559 560 u8 reserved_at_20[0x8]; 561 u8 source_field_code[0x8]; 562 u8 reserved_at_30[0x2]; 563 u8 source_left_shifter[0x6]; 564 u8 reserved_at_38[0x8]; 565 }; 566 567 #endif /* MLX5_IFC_DR_H */ 568