1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * MDIO bus driver for the Xilinx Axi Ethernet device
4  *
5  * Copyright (c) 2009 Secret Lab Technologies, Ltd.
6  * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
7  * Copyright (c) 2010 - 2011 PetaLogix
8  * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
9  * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
10  */
11 
12 #include <linux/clk.h>
13 #include <linux/of_address.h>
14 #include <linux/of_mdio.h>
15 #include <linux/jiffies.h>
16 #include <linux/iopoll.h>
17 
18 #include "xilinx_axienet.h"
19 
20 #define MAX_MDIO_FREQ		2500000 /* 2.5 MHz */
21 #define DEFAULT_HOST_CLOCK	150000000 /* 150 MHz */
22 
23 /* Wait till MDIO interface is ready to accept a new transaction.*/
axienet_mdio_wait_until_ready(struct axienet_local * lp)24 static int axienet_mdio_wait_until_ready(struct axienet_local *lp)
25 {
26 	u32 val;
27 
28 	return readx_poll_timeout(axinet_ior_read_mcr, lp,
29 				  val, val & XAE_MDIO_MCR_READY_MASK,
30 				  1, 20000);
31 }
32 
33 /* Enable the MDIO MDC. Called prior to a read/write operation */
axienet_mdio_mdc_enable(struct axienet_local * lp)34 static void axienet_mdio_mdc_enable(struct axienet_local *lp)
35 {
36 	axienet_iow(lp, XAE_MDIO_MC_OFFSET,
37 		    ((u32)lp->mii_clk_div | XAE_MDIO_MC_MDIOEN_MASK));
38 }
39 
40 /* Disable the MDIO MDC. Called after a read/write operation*/
axienet_mdio_mdc_disable(struct axienet_local * lp)41 static void axienet_mdio_mdc_disable(struct axienet_local *lp)
42 {
43 	u32 mc_reg;
44 
45 	mc_reg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
46 	axienet_iow(lp, XAE_MDIO_MC_OFFSET,
47 		    (mc_reg & ~XAE_MDIO_MC_MDIOEN_MASK));
48 }
49 
50 /**
51  * axienet_mdio_read - MDIO interface read function
52  * @bus:	Pointer to mii bus structure
53  * @phy_id:	Address of the PHY device
54  * @reg:	PHY register to read
55  *
56  * Return:	The register contents on success, -ETIMEDOUT on a timeout
57  *
58  * Reads the contents of the requested register from the requested PHY
59  * address by first writing the details into MCR register. After a while
60  * the register MRD is read to obtain the PHY register content.
61  */
axienet_mdio_read(struct mii_bus * bus,int phy_id,int reg)62 static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg)
63 {
64 	u32 rc;
65 	int ret;
66 	struct axienet_local *lp = bus->priv;
67 
68 	axienet_mdio_mdc_enable(lp);
69 
70 	ret = axienet_mdio_wait_until_ready(lp);
71 	if (ret < 0) {
72 		axienet_mdio_mdc_disable(lp);
73 		return ret;
74 	}
75 
76 	axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
77 		    (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
78 		      XAE_MDIO_MCR_PHYAD_MASK) |
79 		     ((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
80 		      XAE_MDIO_MCR_REGAD_MASK) |
81 		     XAE_MDIO_MCR_INITIATE_MASK |
82 		     XAE_MDIO_MCR_OP_READ_MASK));
83 
84 	ret = axienet_mdio_wait_until_ready(lp);
85 	if (ret < 0) {
86 		axienet_mdio_mdc_disable(lp);
87 		return ret;
88 	}
89 
90 	rc = axienet_ior(lp, XAE_MDIO_MRD_OFFSET) & 0x0000FFFF;
91 
92 	dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n",
93 		phy_id, reg, rc);
94 
95 	axienet_mdio_mdc_disable(lp);
96 	return rc;
97 }
98 
99 /**
100  * axienet_mdio_write - MDIO interface write function
101  * @bus:	Pointer to mii bus structure
102  * @phy_id:	Address of the PHY device
103  * @reg:	PHY register to write to
104  * @val:	Value to be written into the register
105  *
106  * Return:	0 on success, -ETIMEDOUT on a timeout
107  *
108  * Writes the value to the requested register by first writing the value
109  * into MWD register. The the MCR register is then appropriately setup
110  * to finish the write operation.
111  */
axienet_mdio_write(struct mii_bus * bus,int phy_id,int reg,u16 val)112 static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,
113 			      u16 val)
114 {
115 	int ret;
116 	struct axienet_local *lp = bus->priv;
117 
118 	dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
119 		phy_id, reg, val);
120 
121 	axienet_mdio_mdc_enable(lp);
122 
123 	ret = axienet_mdio_wait_until_ready(lp);
124 	if (ret < 0) {
125 		axienet_mdio_mdc_disable(lp);
126 		return ret;
127 	}
128 
129 	axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32) val);
130 	axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
131 		    (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
132 		      XAE_MDIO_MCR_PHYAD_MASK) |
133 		     ((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
134 		      XAE_MDIO_MCR_REGAD_MASK) |
135 		     XAE_MDIO_MCR_INITIATE_MASK |
136 		     XAE_MDIO_MCR_OP_WRITE_MASK));
137 
138 	ret = axienet_mdio_wait_until_ready(lp);
139 	if (ret < 0) {
140 		axienet_mdio_mdc_disable(lp);
141 		return ret;
142 	}
143 	axienet_mdio_mdc_disable(lp);
144 	return 0;
145 }
146 
147 /**
148  * axienet_mdio_enable - MDIO hardware setup function
149  * @lp:		Pointer to axienet local data structure.
150  *
151  * Return:	0 on success, -ETIMEDOUT on a timeout.
152  *
153  * Sets up the MDIO interface by initializing the MDIO clock and enabling the
154  * MDIO interface in hardware.
155  **/
axienet_mdio_enable(struct axienet_local * lp)156 int axienet_mdio_enable(struct axienet_local *lp)
157 {
158 	u32 host_clock;
159 
160 	lp->mii_clk_div = 0;
161 
162 	if (lp->axi_clk) {
163 		host_clock = clk_get_rate(lp->axi_clk);
164 	} else {
165 		struct device_node *np1;
166 
167 		/* Legacy fallback: detect CPU clock frequency and use as AXI
168 		 * bus clock frequency. This only works on certain platforms.
169 		 */
170 		np1 = of_find_node_by_name(NULL, "cpu");
171 		if (!np1) {
172 			netdev_warn(lp->ndev, "Could not find CPU device node.\n");
173 			host_clock = DEFAULT_HOST_CLOCK;
174 		} else {
175 			int ret = of_property_read_u32(np1, "clock-frequency",
176 						       &host_clock);
177 			if (ret) {
178 				netdev_warn(lp->ndev, "CPU clock-frequency property not found.\n");
179 				host_clock = DEFAULT_HOST_CLOCK;
180 			}
181 			of_node_put(np1);
182 		}
183 		netdev_info(lp->ndev, "Setting assumed host clock to %u\n",
184 			    host_clock);
185 	}
186 
187 	/* clk_div can be calculated by deriving it from the equation:
188 	 * fMDIO = fHOST / ((1 + clk_div) * 2)
189 	 *
190 	 * Where fMDIO <= 2500000, so we get:
191 	 * fHOST / ((1 + clk_div) * 2) <= 2500000
192 	 *
193 	 * Then we get:
194 	 * 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST)
195 	 *
196 	 * Then we get:
197 	 * 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST)
198 	 *
199 	 * Then we get:
200 	 * 1 / (1 + clk_div) <= (5000000 / fHOST)
201 	 *
202 	 * So:
203 	 * (1 + clk_div) >= (fHOST / 5000000)
204 	 *
205 	 * And finally:
206 	 * clk_div >= (fHOST / 5000000) - 1
207 	 *
208 	 * fHOST can be read from the flattened device tree as property
209 	 * "clock-frequency" from the CPU
210 	 */
211 
212 	lp->mii_clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;
213 	/* If there is any remainder from the division of
214 	 * fHOST / (MAX_MDIO_FREQ * 2), then we need to add
215 	 * 1 to the clock divisor or we will surely be above 2.5 MHz
216 	 */
217 	if (host_clock % (MAX_MDIO_FREQ * 2))
218 		lp->mii_clk_div++;
219 
220 	netdev_dbg(lp->ndev,
221 		   "Setting MDIO clock divisor to %u/%u Hz host clock.\n",
222 		   lp->mii_clk_div, host_clock);
223 
224 	axienet_iow(lp, XAE_MDIO_MC_OFFSET, lp->mii_clk_div | XAE_MDIO_MC_MDIOEN_MASK);
225 
226 	return axienet_mdio_wait_until_ready(lp);
227 }
228 
229 /**
230  * axienet_mdio_disable - MDIO hardware disable function
231  * @lp:		Pointer to axienet local data structure.
232  *
233  * Disable the MDIO interface in hardware.
234  **/
axienet_mdio_disable(struct axienet_local * lp)235 void axienet_mdio_disable(struct axienet_local *lp)
236 {
237 	axienet_iow(lp, XAE_MDIO_MC_OFFSET, 0);
238 }
239 
240 /**
241  * axienet_mdio_setup - MDIO setup function
242  * @lp:		Pointer to axienet local data structure.
243  *
244  * Return:	0 on success, -ETIMEDOUT on a timeout, -ENOMEM when
245  *		mdiobus_alloc (to allocate memory for mii bus structure) fails.
246  *
247  * Sets up the MDIO interface by initializing the MDIO clock.
248  * Register the MDIO interface.
249  **/
axienet_mdio_setup(struct axienet_local * lp)250 int axienet_mdio_setup(struct axienet_local *lp)
251 {
252 	struct device_node *mdio_node;
253 	struct mii_bus *bus;
254 	int ret;
255 
256 	ret = axienet_mdio_enable(lp);
257 	if (ret < 0)
258 		return ret;
259 
260 	bus = mdiobus_alloc();
261 	if (!bus)
262 		return -ENOMEM;
263 
264 	snprintf(bus->id, MII_BUS_ID_SIZE, "axienet-%.8llx",
265 		 (unsigned long long)lp->regs_start);
266 
267 	bus->priv = lp;
268 	bus->name = "Xilinx Axi Ethernet MDIO";
269 	bus->read = axienet_mdio_read;
270 	bus->write = axienet_mdio_write;
271 	bus->parent = lp->dev;
272 	lp->mii_bus = bus;
273 
274 	mdio_node = of_get_child_by_name(lp->dev->of_node, "mdio");
275 	ret = of_mdiobus_register(bus, mdio_node);
276 	of_node_put(mdio_node);
277 	if (ret) {
278 		mdiobus_free(bus);
279 		lp->mii_bus = NULL;
280 		return ret;
281 	}
282 	axienet_mdio_mdc_disable(lp);
283 	return 0;
284 }
285 
286 /**
287  * axienet_mdio_teardown - MDIO remove function
288  * @lp:		Pointer to axienet local data structure.
289  *
290  * Unregisters the MDIO and frees any associate memory for mii bus.
291  */
axienet_mdio_teardown(struct axienet_local * lp)292 void axienet_mdio_teardown(struct axienet_local *lp)
293 {
294 	mdiobus_unregister(lp->mii_bus);
295 	mdiobus_free(lp->mii_bus);
296 	lp->mii_bus = NULL;
297 }
298