1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 */
5
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
18 #include <linux/ip.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
30
31 /* Information for net-next */
32 #define NETNEXT_VERSION "12"
33
34 /* Information for net */
35 #define NET_VERSION "11"
36
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41
42 #define R8152_PHY_ID 32
43
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RCR1 0xc012
47 #define PLA_RMS 0xc016
48 #define PLA_RXFIFO_CTRL0 0xc0a0
49 #define PLA_RXFIFO_FULL 0xc0a2
50 #define PLA_RXFIFO_CTRL1 0xc0a4
51 #define PLA_RX_FIFO_FULL 0xc0a6
52 #define PLA_RXFIFO_CTRL2 0xc0a8
53 #define PLA_RX_FIFO_EMPTY 0xc0aa
54 #define PLA_DMY_REG0 0xc0b0
55 #define PLA_FMC 0xc0b4
56 #define PLA_CFG_WOL 0xc0b6
57 #define PLA_TEREDO_CFG 0xc0bc
58 #define PLA_TEREDO_WAKE_BASE 0xc0c4
59 #define PLA_MAR 0xcd00
60 #define PLA_BACKUP 0xd000
61 #define PLA_BDC_CR 0xd1a0
62 #define PLA_TEREDO_TIMER 0xd2cc
63 #define PLA_REALWOW_TIMER 0xd2e8
64 #define PLA_UPHY_TIMER 0xd388
65 #define PLA_SUSPEND_FLAG 0xd38a
66 #define PLA_INDICATE_FALG 0xd38c
67 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
68 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
69 #define PLA_EXTRA_STATUS 0xd398
70 #define PLA_GPHY_CTRL 0xd3ae
71 #define PLA_POL_GPIO_CTRL 0xdc6a
72 #define PLA_EFUSE_DATA 0xdd00
73 #define PLA_EFUSE_CMD 0xdd02
74 #define PLA_LEDSEL 0xdd90
75 #define PLA_LED_FEATURE 0xdd92
76 #define PLA_PHYAR 0xde00
77 #define PLA_BOOT_CTRL 0xe004
78 #define PLA_LWAKE_CTRL_REG 0xe007
79 #define PLA_GPHY_INTR_IMR 0xe022
80 #define PLA_EEE_CR 0xe040
81 #define PLA_EEE_TXTWSYS 0xe04c
82 #define PLA_EEE_TXTWSYS_2P5G 0xe058
83 #define PLA_EEEP_CR 0xe080
84 #define PLA_MAC_PWR_CTRL 0xe0c0
85 #define PLA_MAC_PWR_CTRL2 0xe0ca
86 #define PLA_MAC_PWR_CTRL3 0xe0cc
87 #define PLA_MAC_PWR_CTRL4 0xe0ce
88 #define PLA_WDT6_CTRL 0xe428
89 #define PLA_TCR0 0xe610
90 #define PLA_TCR1 0xe612
91 #define PLA_MTPS 0xe615
92 #define PLA_TXFIFO_CTRL 0xe618
93 #define PLA_TXFIFO_FULL 0xe61a
94 #define PLA_RSTTALLY 0xe800
95 #define PLA_CR 0xe813
96 #define PLA_CRWECR 0xe81c
97 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
98 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
99 #define PLA_CONFIG5 0xe822
100 #define PLA_PHY_PWR 0xe84c
101 #define PLA_OOB_CTRL 0xe84f
102 #define PLA_CPCR 0xe854
103 #define PLA_MISC_0 0xe858
104 #define PLA_MISC_1 0xe85a
105 #define PLA_OCP_GPHY_BASE 0xe86c
106 #define PLA_TALLYCNT 0xe890
107 #define PLA_SFF_STS_7 0xe8de
108 #define PLA_PHYSTATUS 0xe908
109 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
110 #define PLA_USB_CFG 0xe952
111 #define PLA_BP_BA 0xfc26
112 #define PLA_BP_0 0xfc28
113 #define PLA_BP_1 0xfc2a
114 #define PLA_BP_2 0xfc2c
115 #define PLA_BP_3 0xfc2e
116 #define PLA_BP_4 0xfc30
117 #define PLA_BP_5 0xfc32
118 #define PLA_BP_6 0xfc34
119 #define PLA_BP_7 0xfc36
120 #define PLA_BP_EN 0xfc38
121
122 #define USB_USB2PHY 0xb41e
123 #define USB_SSPHYLINK1 0xb426
124 #define USB_SSPHYLINK2 0xb428
125 #define USB_L1_CTRL 0xb45e
126 #define USB_U2P3_CTRL 0xb460
127 #define USB_CSR_DUMMY1 0xb464
128 #define USB_CSR_DUMMY2 0xb466
129 #define USB_DEV_STAT 0xb808
130 #define USB_CONNECT_TIMER 0xcbf8
131 #define USB_MSC_TIMER 0xcbfc
132 #define USB_BURST_SIZE 0xcfc0
133 #define USB_FW_FIX_EN0 0xcfca
134 #define USB_FW_FIX_EN1 0xcfcc
135 #define USB_LPM_CONFIG 0xcfd8
136 #define USB_ECM_OPTION 0xcfee
137 #define USB_CSTMR 0xcfef /* RTL8153A */
138 #define USB_MISC_2 0xcfff
139 #define USB_ECM_OP 0xd26b
140 #define USB_GPHY_CTRL 0xd284
141 #define USB_SPEED_OPTION 0xd32a
142 #define USB_FW_CTRL 0xd334 /* RTL8153B */
143 #define USB_FC_TIMER 0xd340
144 #define USB_USB_CTRL 0xd406
145 #define USB_PHY_CTRL 0xd408
146 #define USB_TX_AGG 0xd40a
147 #define USB_RX_BUF_TH 0xd40c
148 #define USB_USB_TIMER 0xd428
149 #define USB_RX_EARLY_TIMEOUT 0xd42c
150 #define USB_RX_EARLY_SIZE 0xd42e
151 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
152 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
153 #define USB_TX_DMA 0xd434
154 #define USB_UPT_RXDMA_OWN 0xd437
155 #define USB_UPHY3_MDCMDIO 0xd480
156 #define USB_TOLERANCE 0xd490
157 #define USB_LPM_CTRL 0xd41a
158 #define USB_BMU_RESET 0xd4b0
159 #define USB_BMU_CONFIG 0xd4b4
160 #define USB_U1U2_TIMER 0xd4da
161 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
162 #define USB_RX_AGGR_NUM 0xd4ee
163 #define USB_UPS_CTRL 0xd800
164 #define USB_POWER_CUT 0xd80a
165 #define USB_MISC_0 0xd81a
166 #define USB_MISC_1 0xd81f
167 #define USB_AFE_CTRL2 0xd824
168 #define USB_UPHY_XTAL 0xd826
169 #define USB_UPS_CFG 0xd842
170 #define USB_UPS_FLAGS 0xd848
171 #define USB_WDT1_CTRL 0xe404
172 #define USB_WDT11_CTRL 0xe43c
173 #define USB_BP_BA PLA_BP_BA
174 #define USB_BP_0 PLA_BP_0
175 #define USB_BP_1 PLA_BP_1
176 #define USB_BP_2 PLA_BP_2
177 #define USB_BP_3 PLA_BP_3
178 #define USB_BP_4 PLA_BP_4
179 #define USB_BP_5 PLA_BP_5
180 #define USB_BP_6 PLA_BP_6
181 #define USB_BP_7 PLA_BP_7
182 #define USB_BP_EN PLA_BP_EN /* RTL8153A */
183 #define USB_BP_8 0xfc38 /* RTL8153B */
184 #define USB_BP_9 0xfc3a
185 #define USB_BP_10 0xfc3c
186 #define USB_BP_11 0xfc3e
187 #define USB_BP_12 0xfc40
188 #define USB_BP_13 0xfc42
189 #define USB_BP_14 0xfc44
190 #define USB_BP_15 0xfc46
191 #define USB_BP2_EN 0xfc48
192
193 /* OCP Registers */
194 #define OCP_ALDPS_CONFIG 0x2010
195 #define OCP_EEE_CONFIG1 0x2080
196 #define OCP_EEE_CONFIG2 0x2092
197 #define OCP_EEE_CONFIG3 0x2094
198 #define OCP_BASE_MII 0xa400
199 #define OCP_EEE_AR 0xa41a
200 #define OCP_EEE_DATA 0xa41c
201 #define OCP_PHY_STATUS 0xa420
202 #define OCP_NCTL_CFG 0xa42c
203 #define OCP_POWER_CFG 0xa430
204 #define OCP_EEE_CFG 0xa432
205 #define OCP_SRAM_ADDR 0xa436
206 #define OCP_SRAM_DATA 0xa438
207 #define OCP_DOWN_SPEED 0xa442
208 #define OCP_EEE_ABLE 0xa5c4
209 #define OCP_EEE_ADV 0xa5d0
210 #define OCP_EEE_LPABLE 0xa5d2
211 #define OCP_10GBT_CTRL 0xa5d4
212 #define OCP_10GBT_STAT 0xa5d6
213 #define OCP_EEE_ADV2 0xa6d4
214 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
215 #define OCP_PHY_PATCH_STAT 0xb800
216 #define OCP_PHY_PATCH_CMD 0xb820
217 #define OCP_PHY_LOCK 0xb82e
218 #define OCP_ADC_IOFFSET 0xbcfc
219 #define OCP_ADC_CFG 0xbc06
220 #define OCP_SYSCLK_CFG 0xc416
221
222 /* SRAM Register */
223 #define SRAM_GREEN_CFG 0x8011
224 #define SRAM_LPF_CFG 0x8012
225 #define SRAM_GPHY_FW_VER 0x801e
226 #define SRAM_10M_AMP1 0x8080
227 #define SRAM_10M_AMP2 0x8082
228 #define SRAM_IMPEDANCE 0x8084
229 #define SRAM_PHY_LOCK 0xb82e
230
231 /* PLA_RCR */
232 #define RCR_AAP 0x00000001
233 #define RCR_APM 0x00000002
234 #define RCR_AM 0x00000004
235 #define RCR_AB 0x00000008
236 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
237 #define SLOT_EN BIT(11)
238
239 /* PLA_RCR1 */
240 #define OUTER_VLAN BIT(7)
241 #define INNER_VLAN BIT(6)
242
243 /* PLA_RXFIFO_CTRL0 */
244 #define RXFIFO_THR1_NORMAL 0x00080002
245 #define RXFIFO_THR1_OOB 0x01800003
246
247 /* PLA_RXFIFO_FULL */
248 #define RXFIFO_FULL_MASK 0xfff
249
250 /* PLA_RXFIFO_CTRL1 */
251 #define RXFIFO_THR2_FULL 0x00000060
252 #define RXFIFO_THR2_HIGH 0x00000038
253 #define RXFIFO_THR2_OOB 0x0000004a
254 #define RXFIFO_THR2_NORMAL 0x00a0
255
256 /* PLA_RXFIFO_CTRL2 */
257 #define RXFIFO_THR3_FULL 0x00000078
258 #define RXFIFO_THR3_HIGH 0x00000048
259 #define RXFIFO_THR3_OOB 0x0000005a
260 #define RXFIFO_THR3_NORMAL 0x0110
261
262 /* PLA_TXFIFO_CTRL */
263 #define TXFIFO_THR_NORMAL 0x00400008
264 #define TXFIFO_THR_NORMAL2 0x01000008
265
266 /* PLA_DMY_REG0 */
267 #define ECM_ALDPS 0x0002
268
269 /* PLA_FMC */
270 #define FMC_FCR_MCU_EN 0x0001
271
272 /* PLA_EEEP_CR */
273 #define EEEP_CR_EEEP_TX 0x0002
274
275 /* PLA_WDT6_CTRL */
276 #define WDT6_SET_MODE 0x0010
277
278 /* PLA_TCR0 */
279 #define TCR0_TX_EMPTY 0x0800
280 #define TCR0_AUTO_FIFO 0x0080
281
282 /* PLA_TCR1 */
283 #define VERSION_MASK 0x7cf0
284 #define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
285 #define IFG_144NS BIT(9)
286 #define IFG_96NS (BIT(9) | BIT(8))
287
288 /* PLA_MTPS */
289 #define MTPS_JUMBO (12 * 1024 / 64)
290 #define MTPS_DEFAULT (6 * 1024 / 64)
291
292 /* PLA_RSTTALLY */
293 #define TALLY_RESET 0x0001
294
295 /* PLA_CR */
296 #define CR_RST 0x10
297 #define CR_RE 0x08
298 #define CR_TE 0x04
299
300 /* PLA_CRWECR */
301 #define CRWECR_NORAML 0x00
302 #define CRWECR_CONFIG 0xc0
303
304 /* PLA_OOB_CTRL */
305 #define NOW_IS_OOB 0x80
306 #define TXFIFO_EMPTY 0x20
307 #define RXFIFO_EMPTY 0x10
308 #define LINK_LIST_READY 0x02
309 #define DIS_MCU_CLROOB 0x01
310 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
311
312 /* PLA_MISC_1 */
313 #define RXDY_GATED_EN 0x0008
314
315 /* PLA_SFF_STS_7 */
316 #define RE_INIT_LL 0x8000
317 #define MCU_BORW_EN 0x4000
318
319 /* PLA_CPCR */
320 #define FLOW_CTRL_EN BIT(0)
321 #define CPCR_RX_VLAN 0x0040
322
323 /* PLA_CFG_WOL */
324 #define MAGIC_EN 0x0001
325
326 /* PLA_TEREDO_CFG */
327 #define TEREDO_SEL 0x8000
328 #define TEREDO_WAKE_MASK 0x7f00
329 #define TEREDO_RS_EVENT_MASK 0x00fe
330 #define OOB_TEREDO_EN 0x0001
331
332 /* PLA_BDC_CR */
333 #define ALDPS_PROXY_MODE 0x0001
334
335 /* PLA_EFUSE_CMD */
336 #define EFUSE_READ_CMD BIT(15)
337 #define EFUSE_DATA_BIT16 BIT(7)
338
339 /* PLA_CONFIG34 */
340 #define LINK_ON_WAKE_EN 0x0010
341 #define LINK_OFF_WAKE_EN 0x0008
342
343 /* PLA_CONFIG6 */
344 #define LANWAKE_CLR_EN BIT(0)
345
346 /* PLA_USB_CFG */
347 #define EN_XG_LIP BIT(1)
348 #define EN_G_LIP BIT(2)
349
350 /* PLA_CONFIG5 */
351 #define BWF_EN 0x0040
352 #define MWF_EN 0x0020
353 #define UWF_EN 0x0010
354 #define LAN_WAKE_EN 0x0002
355
356 /* PLA_LED_FEATURE */
357 #define LED_MODE_MASK 0x0700
358
359 /* PLA_PHY_PWR */
360 #define TX_10M_IDLE_EN 0x0080
361 #define PFM_PWM_SWITCH 0x0040
362 #define TEST_IO_OFF BIT(4)
363
364 /* PLA_MAC_PWR_CTRL */
365 #define D3_CLK_GATED_EN 0x00004000
366 #define MCU_CLK_RATIO 0x07010f07
367 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
368 #define ALDPS_SPDWN_RATIO 0x0f87
369
370 /* PLA_MAC_PWR_CTRL2 */
371 #define EEE_SPDWN_RATIO 0x8007
372 #define MAC_CLK_SPDWN_EN BIT(15)
373 #define EEE_SPDWN_RATIO_MASK 0xff
374
375 /* PLA_MAC_PWR_CTRL3 */
376 #define PLA_MCU_SPDWN_EN BIT(14)
377 #define PKT_AVAIL_SPDWN_EN 0x0100
378 #define SUSPEND_SPDWN_EN 0x0004
379 #define U1U2_SPDWN_EN 0x0002
380 #define L1_SPDWN_EN 0x0001
381
382 /* PLA_MAC_PWR_CTRL4 */
383 #define PWRSAVE_SPDWN_EN 0x1000
384 #define RXDV_SPDWN_EN 0x0800
385 #define TX10MIDLE_EN 0x0100
386 #define IDLE_SPDWN_EN BIT(6)
387 #define TP100_SPDWN_EN 0x0020
388 #define TP500_SPDWN_EN 0x0010
389 #define TP1000_SPDWN_EN 0x0008
390 #define EEE_SPDWN_EN 0x0001
391
392 /* PLA_GPHY_INTR_IMR */
393 #define GPHY_STS_MSK 0x0001
394 #define SPEED_DOWN_MSK 0x0002
395 #define SPDWN_RXDV_MSK 0x0004
396 #define SPDWN_LINKCHG_MSK 0x0008
397
398 /* PLA_PHYAR */
399 #define PHYAR_FLAG 0x80000000
400
401 /* PLA_EEE_CR */
402 #define EEE_RX_EN 0x0001
403 #define EEE_TX_EN 0x0002
404
405 /* PLA_BOOT_CTRL */
406 #define AUTOLOAD_DONE 0x0002
407
408 /* PLA_LWAKE_CTRL_REG */
409 #define LANWAKE_PIN BIT(7)
410
411 /* PLA_SUSPEND_FLAG */
412 #define LINK_CHG_EVENT BIT(0)
413
414 /* PLA_INDICATE_FALG */
415 #define UPCOMING_RUNTIME_D3 BIT(0)
416
417 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
418 #define DEBUG_OE BIT(0)
419 #define DEBUG_LTSSM 0x0082
420
421 /* PLA_EXTRA_STATUS */
422 #define CUR_LINK_OK BIT(15)
423 #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
424 #define LINK_CHANGE_FLAG BIT(8)
425 #define POLL_LINK_CHG BIT(0)
426
427 /* PLA_GPHY_CTRL */
428 #define GPHY_FLASH BIT(1)
429
430 /* PLA_POL_GPIO_CTRL */
431 #define DACK_DET_EN BIT(15)
432 #define POL_GPHY_PATCH BIT(4)
433
434 /* USB_USB2PHY */
435 #define USB2PHY_SUSPEND 0x0001
436 #define USB2PHY_L1 0x0002
437
438 /* USB_SSPHYLINK1 */
439 #define DELAY_PHY_PWR_CHG BIT(1)
440
441 /* USB_SSPHYLINK2 */
442 #define pwd_dn_scale_mask 0x3ffe
443 #define pwd_dn_scale(x) ((x) << 1)
444
445 /* USB_CSR_DUMMY1 */
446 #define DYNAMIC_BURST 0x0001
447
448 /* USB_CSR_DUMMY2 */
449 #define EP4_FULL_FC 0x0001
450
451 /* USB_DEV_STAT */
452 #define STAT_SPEED_MASK 0x0006
453 #define STAT_SPEED_HIGH 0x0000
454 #define STAT_SPEED_FULL 0x0002
455
456 /* USB_FW_FIX_EN0 */
457 #define FW_FIX_SUSPEND BIT(14)
458
459 /* USB_FW_FIX_EN1 */
460 #define FW_IP_RESET_EN BIT(9)
461
462 /* USB_LPM_CONFIG */
463 #define LPM_U1U2_EN BIT(0)
464
465 /* USB_TX_AGG */
466 #define TX_AGG_MAX_THRESHOLD 0x03
467
468 /* USB_RX_BUF_TH */
469 #define RX_THR_SUPPER 0x0c350180
470 #define RX_THR_HIGH 0x7a120180
471 #define RX_THR_SLOW 0xffff0180
472 #define RX_THR_B 0x00010001
473
474 /* USB_TX_DMA */
475 #define TEST_MODE_DISABLE 0x00000001
476 #define TX_SIZE_ADJUST1 0x00000100
477
478 /* USB_BMU_RESET */
479 #define BMU_RESET_EP_IN 0x01
480 #define BMU_RESET_EP_OUT 0x02
481
482 /* USB_BMU_CONFIG */
483 #define ACT_ODMA BIT(1)
484
485 /* USB_UPT_RXDMA_OWN */
486 #define OWN_UPDATE BIT(0)
487 #define OWN_CLEAR BIT(1)
488
489 /* USB_FW_TASK */
490 #define FC_PATCH_TASK BIT(1)
491
492 /* USB_RX_AGGR_NUM */
493 #define RX_AGGR_NUM_MASK 0x1ff
494
495 /* USB_UPS_CTRL */
496 #define POWER_CUT 0x0100
497
498 /* USB_PM_CTRL_STATUS */
499 #define RESUME_INDICATE 0x0001
500
501 /* USB_ECM_OPTION */
502 #define BYPASS_MAC_RESET BIT(5)
503
504 /* USB_CSTMR */
505 #define FORCE_SUPER BIT(0)
506
507 /* USB_MISC_2 */
508 #define UPS_FORCE_PWR_DOWN BIT(0)
509
510 /* USB_ECM_OP */
511 #define EN_ALL_SPEED BIT(0)
512
513 /* USB_GPHY_CTRL */
514 #define GPHY_PATCH_DONE BIT(2)
515 #define BYPASS_FLASH BIT(5)
516 #define BACKUP_RESTRORE BIT(6)
517
518 /* USB_SPEED_OPTION */
519 #define RG_PWRDN_EN BIT(8)
520 #define ALL_SPEED_OFF BIT(9)
521
522 /* USB_FW_CTRL */
523 #define FLOW_CTRL_PATCH_OPT BIT(1)
524 #define AUTO_SPEEDUP BIT(3)
525 #define FLOW_CTRL_PATCH_2 BIT(8)
526
527 /* USB_FC_TIMER */
528 #define CTRL_TIMER_EN BIT(15)
529
530 /* USB_USB_CTRL */
531 #define CDC_ECM_EN BIT(3)
532 #define RX_AGG_DISABLE 0x0010
533 #define RX_ZERO_EN 0x0080
534
535 /* USB_U2P3_CTRL */
536 #define U2P3_ENABLE 0x0001
537 #define RX_DETECT8 BIT(3)
538
539 /* USB_POWER_CUT */
540 #define PWR_EN 0x0001
541 #define PHASE2_EN 0x0008
542 #define UPS_EN BIT(4)
543 #define USP_PREWAKE BIT(5)
544
545 /* USB_MISC_0 */
546 #define PCUT_STATUS 0x0001
547
548 /* USB_RX_EARLY_TIMEOUT */
549 #define COALESCE_SUPER 85000U
550 #define COALESCE_HIGH 250000U
551 #define COALESCE_SLOW 524280U
552
553 /* USB_WDT1_CTRL */
554 #define WTD1_EN BIT(0)
555
556 /* USB_WDT11_CTRL */
557 #define TIMER11_EN 0x0001
558
559 /* USB_LPM_CTRL */
560 /* bit 4 ~ 5: fifo empty boundary */
561 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
562 /* bit 2 ~ 3: LMP timer */
563 #define LPM_TIMER_MASK 0x0c
564 #define LPM_TIMER_500MS 0x04 /* 500 ms */
565 #define LPM_TIMER_500US 0x0c /* 500 us */
566 #define ROK_EXIT_LPM 0x02
567
568 /* USB_AFE_CTRL2 */
569 #define SEN_VAL_MASK 0xf800
570 #define SEN_VAL_NORMAL 0xa000
571 #define SEL_RXIDLE 0x0100
572
573 /* USB_UPHY_XTAL */
574 #define OOBS_POLLING BIT(8)
575
576 /* USB_UPS_CFG */
577 #define SAW_CNT_1MS_MASK 0x0fff
578 #define MID_REVERSE BIT(5) /* RTL8156A */
579
580 /* USB_UPS_FLAGS */
581 #define UPS_FLAGS_R_TUNE BIT(0)
582 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
583 #define UPS_FLAGS_250M_CKDIV BIT(2)
584 #define UPS_FLAGS_EN_ALDPS BIT(3)
585 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
586 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
587 #define ups_flags_speed(x) ((x) << 16)
588 #define UPS_FLAGS_EN_EEE BIT(20)
589 #define UPS_FLAGS_EN_500M_EEE BIT(21)
590 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
591 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
592 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
593 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
594 #define UPS_FLAGS_EN_GREEN BIT(26)
595 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
596
597 enum spd_duplex {
598 NWAY_10M_HALF,
599 NWAY_10M_FULL,
600 NWAY_100M_HALF,
601 NWAY_100M_FULL,
602 NWAY_1000M_FULL,
603 FORCE_10M_HALF,
604 FORCE_10M_FULL,
605 FORCE_100M_HALF,
606 FORCE_100M_FULL,
607 FORCE_1000M_FULL,
608 NWAY_2500M_FULL,
609 };
610
611 /* OCP_ALDPS_CONFIG */
612 #define ENPWRSAVE 0x8000
613 #define ENPDNPS 0x0200
614 #define LINKENA 0x0100
615 #define DIS_SDSAVE 0x0010
616
617 /* OCP_PHY_STATUS */
618 #define PHY_STAT_MASK 0x0007
619 #define PHY_STAT_EXT_INIT 2
620 #define PHY_STAT_LAN_ON 3
621 #define PHY_STAT_PWRDN 5
622
623 /* OCP_NCTL_CFG */
624 #define PGA_RETURN_EN BIT(1)
625
626 /* OCP_POWER_CFG */
627 #define EEE_CLKDIV_EN 0x8000
628 #define EN_ALDPS 0x0004
629 #define EN_10M_PLLOFF 0x0001
630
631 /* OCP_EEE_CONFIG1 */
632 #define RG_TXLPI_MSK_HFDUP 0x8000
633 #define RG_MATCLR_EN 0x4000
634 #define EEE_10_CAP 0x2000
635 #define EEE_NWAY_EN 0x1000
636 #define TX_QUIET_EN 0x0200
637 #define RX_QUIET_EN 0x0100
638 #define sd_rise_time_mask 0x0070
639 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
640 #define RG_RXLPI_MSK_HFDUP 0x0008
641 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
642
643 /* OCP_EEE_CONFIG2 */
644 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
645 #define RG_DACQUIET_EN 0x0400
646 #define RG_LDVQUIET_EN 0x0200
647 #define RG_CKRSEL 0x0020
648 #define RG_EEEPRG_EN 0x0010
649
650 /* OCP_EEE_CONFIG3 */
651 #define fast_snr_mask 0xff80
652 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
653 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
654 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
655
656 /* OCP_EEE_AR */
657 /* bit[15:14] function */
658 #define FUN_ADDR 0x0000
659 #define FUN_DATA 0x4000
660 /* bit[4:0] device addr */
661
662 /* OCP_EEE_CFG */
663 #define CTAP_SHORT_EN 0x0040
664 #define EEE10_EN 0x0010
665
666 /* OCP_DOWN_SPEED */
667 #define EN_EEE_CMODE BIT(14)
668 #define EN_EEE_1000 BIT(13)
669 #define EN_EEE_100 BIT(12)
670 #define EN_10M_CLKDIV BIT(11)
671 #define EN_10M_BGOFF 0x0080
672
673 /* OCP_10GBT_CTRL */
674 #define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
675
676 /* OCP_PHY_STATE */
677 #define TXDIS_STATE 0x01
678 #define ABD_STATE 0x02
679
680 /* OCP_PHY_PATCH_STAT */
681 #define PATCH_READY BIT(6)
682
683 /* OCP_PHY_PATCH_CMD */
684 #define PATCH_REQUEST BIT(4)
685
686 /* OCP_PHY_LOCK */
687 #define PATCH_LOCK BIT(0)
688
689 /* OCP_ADC_CFG */
690 #define CKADSEL_L 0x0100
691 #define ADC_EN 0x0080
692 #define EN_EMI_L 0x0040
693
694 /* OCP_SYSCLK_CFG */
695 #define sysclk_div_expo(x) (min(x, 5) << 8)
696 #define clk_div_expo(x) (min(x, 5) << 4)
697
698 /* SRAM_GREEN_CFG */
699 #define GREEN_ETH_EN BIT(15)
700 #define R_TUNE_EN BIT(11)
701
702 /* SRAM_LPF_CFG */
703 #define LPF_AUTO_TUNE 0x8000
704
705 /* SRAM_10M_AMP1 */
706 #define GDAC_IB_UPALL 0x0008
707
708 /* SRAM_10M_AMP2 */
709 #define AMP_DN 0x0200
710
711 /* SRAM_IMPEDANCE */
712 #define RX_DRIVING_MASK 0x6000
713
714 /* SRAM_PHY_LOCK */
715 #define PHY_PATCH_LOCK 0x0001
716
717 /* MAC PASSTHRU */
718 #define AD_MASK 0xfee0
719 #define BND_MASK 0x0004
720 #define BD_MASK 0x0001
721 #define EFUSE 0xcfdb
722 #define PASS_THRU_MASK 0x1
723
724 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
725
726 enum rtl_register_content {
727 _2500bps = BIT(10),
728 _1250bps = BIT(9),
729 _500bps = BIT(8),
730 _tx_flow = BIT(6),
731 _rx_flow = BIT(5),
732 _1000bps = 0x10,
733 _100bps = 0x08,
734 _10bps = 0x04,
735 LINK_STATUS = 0x02,
736 FULL_DUP = 0x01,
737 };
738
739 #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
740 #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
741
742 #define RTL8152_MAX_TX 4
743 #define RTL8152_MAX_RX 10
744 #define INTBUFSIZE 2
745 #define TX_ALIGN 4
746 #define RX_ALIGN 8
747
748 #define RTL8152_RX_MAX_PENDING 4096
749 #define RTL8152_RXFG_HEADSZ 256
750
751 #define INTR_LINK 0x0004
752
753 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
754 #define RTL8153_RMS RTL8153_MAX_PACKET
755 #define RTL8152_TX_TIMEOUT (5 * HZ)
756 #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
757 #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
758 #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
759
760 /* rtl8152 flags */
761 enum rtl8152_flags {
762 RTL8152_UNPLUG = 0,
763 RTL8152_SET_RX_MODE,
764 WORK_ENABLE,
765 RTL8152_LINK_CHG,
766 SELECTIVE_SUSPEND,
767 PHY_RESET,
768 SCHEDULE_TASKLET,
769 GREEN_ETHERNET,
770 };
771
772 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
773 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
774
775 struct tally_counter {
776 __le64 tx_packets;
777 __le64 rx_packets;
778 __le64 tx_errors;
779 __le32 rx_errors;
780 __le16 rx_missed;
781 __le16 align_errors;
782 __le32 tx_one_collision;
783 __le32 tx_multi_collision;
784 __le64 rx_unicast;
785 __le64 rx_broadcast;
786 __le32 rx_multicast;
787 __le16 tx_aborted;
788 __le16 tx_underrun;
789 };
790
791 struct rx_desc {
792 __le32 opts1;
793 #define RX_LEN_MASK 0x7fff
794
795 __le32 opts2;
796 #define RD_UDP_CS BIT(23)
797 #define RD_TCP_CS BIT(22)
798 #define RD_IPV6_CS BIT(20)
799 #define RD_IPV4_CS BIT(19)
800
801 __le32 opts3;
802 #define IPF BIT(23) /* IP checksum fail */
803 #define UDPF BIT(22) /* UDP checksum fail */
804 #define TCPF BIT(21) /* TCP checksum fail */
805 #define RX_VLAN_TAG BIT(16)
806
807 __le32 opts4;
808 __le32 opts5;
809 __le32 opts6;
810 };
811
812 struct tx_desc {
813 __le32 opts1;
814 #define TX_FS BIT(31) /* First segment of a packet */
815 #define TX_LS BIT(30) /* Final segment of a packet */
816 #define GTSENDV4 BIT(28)
817 #define GTSENDV6 BIT(27)
818 #define GTTCPHO_SHIFT 18
819 #define GTTCPHO_MAX 0x7fU
820 #define TX_LEN_MAX 0x3ffffU
821
822 __le32 opts2;
823 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
824 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
825 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
826 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
827 #define MSS_SHIFT 17
828 #define MSS_MAX 0x7ffU
829 #define TCPHO_SHIFT 17
830 #define TCPHO_MAX 0x7ffU
831 #define TX_VLAN_TAG BIT(16)
832 };
833
834 struct r8152;
835
836 struct rx_agg {
837 struct list_head list, info_list;
838 struct urb *urb;
839 struct r8152 *context;
840 struct page *page;
841 void *buffer;
842 };
843
844 struct tx_agg {
845 struct list_head list;
846 struct urb *urb;
847 struct r8152 *context;
848 void *buffer;
849 void *head;
850 u32 skb_num;
851 u32 skb_len;
852 };
853
854 struct r8152 {
855 unsigned long flags;
856 struct usb_device *udev;
857 struct napi_struct napi;
858 struct usb_interface *intf;
859 struct net_device *netdev;
860 struct urb *intr_urb;
861 struct tx_agg tx_info[RTL8152_MAX_TX];
862 struct list_head rx_info, rx_used;
863 struct list_head rx_done, tx_free;
864 struct sk_buff_head tx_queue, rx_queue;
865 spinlock_t rx_lock, tx_lock;
866 struct delayed_work schedule, hw_phy_work;
867 struct mii_if_info mii;
868 struct mutex control; /* use for hw setting */
869 #ifdef CONFIG_PM_SLEEP
870 struct notifier_block pm_notifier;
871 #endif
872 struct tasklet_struct tx_tl;
873
874 struct rtl_ops {
875 void (*init)(struct r8152 *tp);
876 int (*enable)(struct r8152 *tp);
877 void (*disable)(struct r8152 *tp);
878 void (*up)(struct r8152 *tp);
879 void (*down)(struct r8152 *tp);
880 void (*unload)(struct r8152 *tp);
881 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
882 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
883 bool (*in_nway)(struct r8152 *tp);
884 void (*hw_phy_cfg)(struct r8152 *tp);
885 void (*autosuspend_en)(struct r8152 *tp, bool enable);
886 void (*change_mtu)(struct r8152 *tp);
887 } rtl_ops;
888
889 struct ups_info {
890 u32 r_tune:1;
891 u32 _10m_ckdiv:1;
892 u32 _250m_ckdiv:1;
893 u32 aldps:1;
894 u32 lite_mode:2;
895 u32 speed_duplex:4;
896 u32 eee:1;
897 u32 eee_lite:1;
898 u32 eee_ckdiv:1;
899 u32 eee_plloff_100:1;
900 u32 eee_plloff_giga:1;
901 u32 eee_cmod_lv:1;
902 u32 green:1;
903 u32 flow_control:1;
904 u32 ctap_short_off:1;
905 } ups_info;
906
907 #define RTL_VER_SIZE 32
908
909 struct rtl_fw {
910 const char *fw_name;
911 const struct firmware *fw;
912
913 char version[RTL_VER_SIZE];
914 int (*pre_fw)(struct r8152 *tp);
915 int (*post_fw)(struct r8152 *tp);
916
917 bool retry;
918 } rtl_fw;
919
920 atomic_t rx_count;
921
922 bool eee_en;
923 int intr_interval;
924 u32 saved_wolopts;
925 u32 msg_enable;
926 u32 tx_qlen;
927 u32 coalesce;
928 u32 advertising;
929 u32 rx_buf_sz;
930 u32 rx_copybreak;
931 u32 rx_pending;
932 u32 fc_pause_on, fc_pause_off;
933
934 u32 support_2500full:1;
935 u32 lenovo_macpassthru:1;
936 u32 dell_tb_rx_agg_bug:1;
937 u16 ocp_base;
938 u16 speed;
939 u16 eee_adv;
940 u8 *intr_buff;
941 u8 version;
942 u8 duplex;
943 u8 autoneg;
944 };
945
946 /**
947 * struct fw_block - block type and total length
948 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
949 * RTL_FW_USB and so on.
950 * @length: total length of the current block.
951 */
952 struct fw_block {
953 __le32 type;
954 __le32 length;
955 } __packed;
956
957 /**
958 * struct fw_header - header of the firmware file
959 * @checksum: checksum of sha256 which is calculated from the whole file
960 * except the checksum field of the file. That is, calculate sha256
961 * from the version field to the end of the file.
962 * @version: version of this firmware.
963 * @blocks: the first firmware block of the file
964 */
965 struct fw_header {
966 u8 checksum[32];
967 char version[RTL_VER_SIZE];
968 struct fw_block blocks[];
969 } __packed;
970
971 enum rtl8152_fw_flags {
972 FW_FLAGS_USB = 0,
973 FW_FLAGS_PLA,
974 FW_FLAGS_START,
975 FW_FLAGS_STOP,
976 FW_FLAGS_NC,
977 FW_FLAGS_NC1,
978 FW_FLAGS_NC2,
979 FW_FLAGS_UC2,
980 FW_FLAGS_UC,
981 FW_FLAGS_SPEED_UP,
982 FW_FLAGS_VER,
983 };
984
985 enum rtl8152_fw_fixup_cmd {
986 FW_FIXUP_AND = 0,
987 FW_FIXUP_OR,
988 FW_FIXUP_NOT,
989 FW_FIXUP_XOR,
990 };
991
992 struct fw_phy_set {
993 __le16 addr;
994 __le16 data;
995 } __packed;
996
997 struct fw_phy_speed_up {
998 struct fw_block blk_hdr;
999 __le16 fw_offset;
1000 __le16 version;
1001 __le16 fw_reg;
1002 __le16 reserved;
1003 char info[];
1004 } __packed;
1005
1006 struct fw_phy_ver {
1007 struct fw_block blk_hdr;
1008 struct fw_phy_set ver;
1009 __le32 reserved;
1010 } __packed;
1011
1012 struct fw_phy_fixup {
1013 struct fw_block blk_hdr;
1014 struct fw_phy_set setting;
1015 __le16 bit_cmd;
1016 __le16 reserved;
1017 } __packed;
1018
1019 struct fw_phy_union {
1020 struct fw_block blk_hdr;
1021 __le16 fw_offset;
1022 __le16 fw_reg;
1023 struct fw_phy_set pre_set[2];
1024 struct fw_phy_set bp[8];
1025 struct fw_phy_set bp_en;
1026 u8 pre_num;
1027 u8 bp_num;
1028 char info[];
1029 } __packed;
1030
1031 /**
1032 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1033 * The layout of the firmware block is:
1034 * <struct fw_mac> + <info> + <firmware data>.
1035 * @blk_hdr: firmware descriptor (type, length)
1036 * @fw_offset: offset of the firmware binary data. The start address of
1037 * the data would be the address of struct fw_mac + @fw_offset.
1038 * @fw_reg: the register to load the firmware. Depends on chip.
1039 * @bp_ba_addr: the register to write break point base address. Depends on
1040 * chip.
1041 * @bp_ba_value: break point base address. Depends on chip.
1042 * @bp_en_addr: the register to write break point enabled mask. Depends
1043 * on chip.
1044 * @bp_en_value: break point enabled mask. Depends on the firmware.
1045 * @bp_start: the start register of break points. Depends on chip.
1046 * @bp_num: the break point number which needs to be set for this firmware.
1047 * Depends on the firmware.
1048 * @bp: break points. Depends on firmware.
1049 * @reserved: reserved space (unused)
1050 * @fw_ver_reg: the register to store the fw version.
1051 * @fw_ver_data: the firmware version of the current type.
1052 * @info: additional information for debugging, and is followed by the
1053 * binary data of firmware.
1054 */
1055 struct fw_mac {
1056 struct fw_block blk_hdr;
1057 __le16 fw_offset;
1058 __le16 fw_reg;
1059 __le16 bp_ba_addr;
1060 __le16 bp_ba_value;
1061 __le16 bp_en_addr;
1062 __le16 bp_en_value;
1063 __le16 bp_start;
1064 __le16 bp_num;
1065 __le16 bp[16]; /* any value determined by firmware */
1066 __le32 reserved;
1067 __le16 fw_ver_reg;
1068 u8 fw_ver_data;
1069 char info[];
1070 } __packed;
1071
1072 /**
1073 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1074 * This is used to set patch key when loading the firmware of PHY.
1075 * @blk_hdr: firmware descriptor (type, length)
1076 * @key_reg: the register to write the patch key.
1077 * @key_data: patch key.
1078 * @reserved: reserved space (unused)
1079 */
1080 struct fw_phy_patch_key {
1081 struct fw_block blk_hdr;
1082 __le16 key_reg;
1083 __le16 key_data;
1084 __le32 reserved;
1085 } __packed;
1086
1087 /**
1088 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1089 * The layout of the firmware block is:
1090 * <struct fw_phy_nc> + <info> + <firmware data>.
1091 * @blk_hdr: firmware descriptor (type, length)
1092 * @fw_offset: offset of the firmware binary data. The start address of
1093 * the data would be the address of struct fw_phy_nc + @fw_offset.
1094 * @fw_reg: the register to load the firmware. Depends on chip.
1095 * @ba_reg: the register to write the base address. Depends on chip.
1096 * @ba_data: base address. Depends on chip.
1097 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
1098 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
1099 * @mode_reg: the regitster of switching the mode.
1100 * @mode_pre: the mode needing to be set before loading the firmware.
1101 * @mode_post: the mode to be set when finishing to load the firmware.
1102 * @reserved: reserved space (unused)
1103 * @bp_start: the start register of break points. Depends on chip.
1104 * @bp_num: the break point number which needs to be set for this firmware.
1105 * Depends on the firmware.
1106 * @bp: break points. Depends on firmware.
1107 * @info: additional information for debugging, and is followed by the
1108 * binary data of firmware.
1109 */
1110 struct fw_phy_nc {
1111 struct fw_block blk_hdr;
1112 __le16 fw_offset;
1113 __le16 fw_reg;
1114 __le16 ba_reg;
1115 __le16 ba_data;
1116 __le16 patch_en_addr;
1117 __le16 patch_en_value;
1118 __le16 mode_reg;
1119 __le16 mode_pre;
1120 __le16 mode_post;
1121 __le16 reserved;
1122 __le16 bp_start;
1123 __le16 bp_num;
1124 __le16 bp[4];
1125 char info[];
1126 } __packed;
1127
1128 enum rtl_fw_type {
1129 RTL_FW_END = 0,
1130 RTL_FW_PLA,
1131 RTL_FW_USB,
1132 RTL_FW_PHY_START,
1133 RTL_FW_PHY_STOP,
1134 RTL_FW_PHY_NC,
1135 RTL_FW_PHY_FIXUP,
1136 RTL_FW_PHY_UNION_NC,
1137 RTL_FW_PHY_UNION_NC1,
1138 RTL_FW_PHY_UNION_NC2,
1139 RTL_FW_PHY_UNION_UC2,
1140 RTL_FW_PHY_UNION_UC,
1141 RTL_FW_PHY_UNION_MISC,
1142 RTL_FW_PHY_SPEED_UP,
1143 RTL_FW_PHY_VER,
1144 };
1145
1146 enum rtl_version {
1147 RTL_VER_UNKNOWN = 0,
1148 RTL_VER_01,
1149 RTL_VER_02,
1150 RTL_VER_03,
1151 RTL_VER_04,
1152 RTL_VER_05,
1153 RTL_VER_06,
1154 RTL_VER_07,
1155 RTL_VER_08,
1156 RTL_VER_09,
1157
1158 RTL_TEST_01,
1159 RTL_VER_10,
1160 RTL_VER_11,
1161 RTL_VER_12,
1162 RTL_VER_13,
1163 RTL_VER_14,
1164 RTL_VER_15,
1165
1166 RTL_VER_MAX
1167 };
1168
1169 enum tx_csum_stat {
1170 TX_CSUM_SUCCESS = 0,
1171 TX_CSUM_TSO,
1172 TX_CSUM_NONE
1173 };
1174
1175 #define RTL_ADVERTISED_10_HALF BIT(0)
1176 #define RTL_ADVERTISED_10_FULL BIT(1)
1177 #define RTL_ADVERTISED_100_HALF BIT(2)
1178 #define RTL_ADVERTISED_100_FULL BIT(3)
1179 #define RTL_ADVERTISED_1000_HALF BIT(4)
1180 #define RTL_ADVERTISED_1000_FULL BIT(5)
1181 #define RTL_ADVERTISED_2500_FULL BIT(6)
1182
1183 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1184 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1185 */
1186 static const int multicast_filter_limit = 32;
1187 static unsigned int agg_buf_sz = 16384;
1188
1189 #define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1190
1191 static
get_registers(struct r8152 * tp,u16 value,u16 index,u16 size,void * data)1192 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1193 {
1194 int ret;
1195 void *tmp;
1196
1197 tmp = kmalloc(size, GFP_KERNEL);
1198 if (!tmp)
1199 return -ENOMEM;
1200
1201 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
1202 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1203 value, index, tmp, size, 500);
1204 if (ret < 0)
1205 memset(data, 0xff, size);
1206 else
1207 memcpy(data, tmp, size);
1208
1209 kfree(tmp);
1210
1211 return ret;
1212 }
1213
1214 static
set_registers(struct r8152 * tp,u16 value,u16 index,u16 size,void * data)1215 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1216 {
1217 int ret;
1218 void *tmp;
1219
1220 tmp = kmemdup(data, size, GFP_KERNEL);
1221 if (!tmp)
1222 return -ENOMEM;
1223
1224 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
1225 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1226 value, index, tmp, size, 500);
1227
1228 kfree(tmp);
1229
1230 return ret;
1231 }
1232
rtl_set_unplug(struct r8152 * tp)1233 static void rtl_set_unplug(struct r8152 *tp)
1234 {
1235 if (tp->udev->state == USB_STATE_NOTATTACHED) {
1236 set_bit(RTL8152_UNPLUG, &tp->flags);
1237 smp_mb__after_atomic();
1238 }
1239 }
1240
generic_ocp_read(struct r8152 * tp,u16 index,u16 size,void * data,u16 type)1241 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1242 void *data, u16 type)
1243 {
1244 u16 limit = 64;
1245 int ret = 0;
1246
1247 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1248 return -ENODEV;
1249
1250 /* both size and indix must be 4 bytes align */
1251 if ((size & 3) || !size || (index & 3) || !data)
1252 return -EPERM;
1253
1254 if ((u32)index + (u32)size > 0xffff)
1255 return -EPERM;
1256
1257 while (size) {
1258 if (size > limit) {
1259 ret = get_registers(tp, index, type, limit, data);
1260 if (ret < 0)
1261 break;
1262
1263 index += limit;
1264 data += limit;
1265 size -= limit;
1266 } else {
1267 ret = get_registers(tp, index, type, size, data);
1268 if (ret < 0)
1269 break;
1270
1271 index += size;
1272 data += size;
1273 size = 0;
1274 break;
1275 }
1276 }
1277
1278 if (ret == -ENODEV)
1279 rtl_set_unplug(tp);
1280
1281 return ret;
1282 }
1283
generic_ocp_write(struct r8152 * tp,u16 index,u16 byteen,u16 size,void * data,u16 type)1284 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1285 u16 size, void *data, u16 type)
1286 {
1287 int ret;
1288 u16 byteen_start, byteen_end, byen;
1289 u16 limit = 512;
1290
1291 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1292 return -ENODEV;
1293
1294 /* both size and indix must be 4 bytes align */
1295 if ((size & 3) || !size || (index & 3) || !data)
1296 return -EPERM;
1297
1298 if ((u32)index + (u32)size > 0xffff)
1299 return -EPERM;
1300
1301 byteen_start = byteen & BYTE_EN_START_MASK;
1302 byteen_end = byteen & BYTE_EN_END_MASK;
1303
1304 byen = byteen_start | (byteen_start << 4);
1305 ret = set_registers(tp, index, type | byen, 4, data);
1306 if (ret < 0)
1307 goto error1;
1308
1309 index += 4;
1310 data += 4;
1311 size -= 4;
1312
1313 if (size) {
1314 size -= 4;
1315
1316 while (size) {
1317 if (size > limit) {
1318 ret = set_registers(tp, index,
1319 type | BYTE_EN_DWORD,
1320 limit, data);
1321 if (ret < 0)
1322 goto error1;
1323
1324 index += limit;
1325 data += limit;
1326 size -= limit;
1327 } else {
1328 ret = set_registers(tp, index,
1329 type | BYTE_EN_DWORD,
1330 size, data);
1331 if (ret < 0)
1332 goto error1;
1333
1334 index += size;
1335 data += size;
1336 size = 0;
1337 break;
1338 }
1339 }
1340
1341 byen = byteen_end | (byteen_end >> 4);
1342 ret = set_registers(tp, index, type | byen, 4, data);
1343 if (ret < 0)
1344 goto error1;
1345 }
1346
1347 error1:
1348 if (ret == -ENODEV)
1349 rtl_set_unplug(tp);
1350
1351 return ret;
1352 }
1353
1354 static inline
pla_ocp_read(struct r8152 * tp,u16 index,u16 size,void * data)1355 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1356 {
1357 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1358 }
1359
1360 static inline
pla_ocp_write(struct r8152 * tp,u16 index,u16 byteen,u16 size,void * data)1361 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1362 {
1363 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1364 }
1365
1366 static inline
usb_ocp_write(struct r8152 * tp,u16 index,u16 byteen,u16 size,void * data)1367 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1368 {
1369 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1370 }
1371
ocp_read_dword(struct r8152 * tp,u16 type,u16 index)1372 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1373 {
1374 __le32 data;
1375
1376 generic_ocp_read(tp, index, sizeof(data), &data, type);
1377
1378 return __le32_to_cpu(data);
1379 }
1380
ocp_write_dword(struct r8152 * tp,u16 type,u16 index,u32 data)1381 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1382 {
1383 __le32 tmp = __cpu_to_le32(data);
1384
1385 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1386 }
1387
ocp_read_word(struct r8152 * tp,u16 type,u16 index)1388 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1389 {
1390 u32 data;
1391 __le32 tmp;
1392 u16 byen = BYTE_EN_WORD;
1393 u8 shift = index & 2;
1394
1395 index &= ~3;
1396 byen <<= shift;
1397
1398 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1399
1400 data = __le32_to_cpu(tmp);
1401 data >>= (shift * 8);
1402 data &= 0xffff;
1403
1404 return (u16)data;
1405 }
1406
ocp_write_word(struct r8152 * tp,u16 type,u16 index,u32 data)1407 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1408 {
1409 u32 mask = 0xffff;
1410 __le32 tmp;
1411 u16 byen = BYTE_EN_WORD;
1412 u8 shift = index & 2;
1413
1414 data &= mask;
1415
1416 if (index & 2) {
1417 byen <<= shift;
1418 mask <<= (shift * 8);
1419 data <<= (shift * 8);
1420 index &= ~3;
1421 }
1422
1423 tmp = __cpu_to_le32(data);
1424
1425 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1426 }
1427
ocp_read_byte(struct r8152 * tp,u16 type,u16 index)1428 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1429 {
1430 u32 data;
1431 __le32 tmp;
1432 u8 shift = index & 3;
1433
1434 index &= ~3;
1435
1436 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1437
1438 data = __le32_to_cpu(tmp);
1439 data >>= (shift * 8);
1440 data &= 0xff;
1441
1442 return (u8)data;
1443 }
1444
ocp_write_byte(struct r8152 * tp,u16 type,u16 index,u32 data)1445 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1446 {
1447 u32 mask = 0xff;
1448 __le32 tmp;
1449 u16 byen = BYTE_EN_BYTE;
1450 u8 shift = index & 3;
1451
1452 data &= mask;
1453
1454 if (index & 3) {
1455 byen <<= shift;
1456 mask <<= (shift * 8);
1457 data <<= (shift * 8);
1458 index &= ~3;
1459 }
1460
1461 tmp = __cpu_to_le32(data);
1462
1463 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1464 }
1465
ocp_reg_read(struct r8152 * tp,u16 addr)1466 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1467 {
1468 u16 ocp_base, ocp_index;
1469
1470 ocp_base = addr & 0xf000;
1471 if (ocp_base != tp->ocp_base) {
1472 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1473 tp->ocp_base = ocp_base;
1474 }
1475
1476 ocp_index = (addr & 0x0fff) | 0xb000;
1477 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1478 }
1479
ocp_reg_write(struct r8152 * tp,u16 addr,u16 data)1480 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1481 {
1482 u16 ocp_base, ocp_index;
1483
1484 ocp_base = addr & 0xf000;
1485 if (ocp_base != tp->ocp_base) {
1486 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1487 tp->ocp_base = ocp_base;
1488 }
1489
1490 ocp_index = (addr & 0x0fff) | 0xb000;
1491 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1492 }
1493
r8152_mdio_write(struct r8152 * tp,u32 reg_addr,u32 value)1494 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1495 {
1496 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1497 }
1498
r8152_mdio_read(struct r8152 * tp,u32 reg_addr)1499 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1500 {
1501 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1502 }
1503
sram_write(struct r8152 * tp,u16 addr,u16 data)1504 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1505 {
1506 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1507 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1508 }
1509
sram_read(struct r8152 * tp,u16 addr)1510 static u16 sram_read(struct r8152 *tp, u16 addr)
1511 {
1512 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1513 return ocp_reg_read(tp, OCP_SRAM_DATA);
1514 }
1515
read_mii_word(struct net_device * netdev,int phy_id,int reg)1516 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1517 {
1518 struct r8152 *tp = netdev_priv(netdev);
1519 int ret;
1520
1521 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1522 return -ENODEV;
1523
1524 if (phy_id != R8152_PHY_ID)
1525 return -EINVAL;
1526
1527 ret = r8152_mdio_read(tp, reg);
1528
1529 return ret;
1530 }
1531
1532 static
write_mii_word(struct net_device * netdev,int phy_id,int reg,int val)1533 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1534 {
1535 struct r8152 *tp = netdev_priv(netdev);
1536
1537 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1538 return;
1539
1540 if (phy_id != R8152_PHY_ID)
1541 return;
1542
1543 r8152_mdio_write(tp, reg, val);
1544 }
1545
1546 static int
1547 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1548
1549 static int
1550 rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1551 u32 advertising);
1552
rtl8152_set_mac_address(struct net_device * netdev,void * p)1553 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1554 {
1555 struct r8152 *tp = netdev_priv(netdev);
1556 struct sockaddr *addr = p;
1557 int ret = -EADDRNOTAVAIL;
1558
1559 if (!is_valid_ether_addr(addr->sa_data))
1560 goto out1;
1561
1562 ret = usb_autopm_get_interface(tp->intf);
1563 if (ret < 0)
1564 goto out1;
1565
1566 mutex_lock(&tp->control);
1567
1568 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1569
1570 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1571 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1572 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1573
1574 mutex_unlock(&tp->control);
1575
1576 usb_autopm_put_interface(tp->intf);
1577 out1:
1578 return ret;
1579 }
1580
1581 /* Devices containing proper chips can support a persistent
1582 * host system provided MAC address.
1583 * Examples of this are Dell TB15 and Dell WD15 docks
1584 */
vendor_mac_passthru_addr_read(struct r8152 * tp,struct sockaddr * sa)1585 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1586 {
1587 acpi_status status;
1588 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1589 union acpi_object *obj;
1590 int ret = -EINVAL;
1591 u32 ocp_data;
1592 unsigned char buf[6];
1593 char *mac_obj_name;
1594 acpi_object_type mac_obj_type;
1595 int mac_strlen;
1596
1597 if (tp->lenovo_macpassthru) {
1598 mac_obj_name = "\\MACA";
1599 mac_obj_type = ACPI_TYPE_STRING;
1600 mac_strlen = 0x16;
1601 } else {
1602 /* test for -AD variant of RTL8153 */
1603 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1604 if ((ocp_data & AD_MASK) == 0x1000) {
1605 /* test for MAC address pass-through bit */
1606 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1607 if ((ocp_data & PASS_THRU_MASK) != 1) {
1608 netif_dbg(tp, probe, tp->netdev,
1609 "No efuse for RTL8153-AD MAC pass through\n");
1610 return -ENODEV;
1611 }
1612 } else {
1613 /* test for RTL8153-BND and RTL8153-BD */
1614 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1615 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1616 netif_dbg(tp, probe, tp->netdev,
1617 "Invalid variant for MAC pass through\n");
1618 return -ENODEV;
1619 }
1620 }
1621
1622 mac_obj_name = "\\_SB.AMAC";
1623 mac_obj_type = ACPI_TYPE_BUFFER;
1624 mac_strlen = 0x17;
1625 }
1626
1627 /* returns _AUXMAC_#AABBCCDDEEFF# */
1628 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1629 obj = (union acpi_object *)buffer.pointer;
1630 if (!ACPI_SUCCESS(status))
1631 return -ENODEV;
1632 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1633 netif_warn(tp, probe, tp->netdev,
1634 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1635 obj->type, obj->string.length);
1636 goto amacout;
1637 }
1638
1639 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1640 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1641 netif_warn(tp, probe, tp->netdev,
1642 "Invalid header when reading pass-thru MAC addr\n");
1643 goto amacout;
1644 }
1645 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1646 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1647 netif_warn(tp, probe, tp->netdev,
1648 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1649 ret, buf);
1650 ret = -EINVAL;
1651 goto amacout;
1652 }
1653 memcpy(sa->sa_data, buf, 6);
1654 netif_info(tp, probe, tp->netdev,
1655 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1656
1657 amacout:
1658 kfree(obj);
1659 return ret;
1660 }
1661
determine_ethernet_addr(struct r8152 * tp,struct sockaddr * sa)1662 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1663 {
1664 struct net_device *dev = tp->netdev;
1665 int ret;
1666
1667 sa->sa_family = dev->type;
1668
1669 ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1670 if (ret < 0) {
1671 if (tp->version == RTL_VER_01) {
1672 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1673 } else {
1674 /* if device doesn't support MAC pass through this will
1675 * be expected to be non-zero
1676 */
1677 ret = vendor_mac_passthru_addr_read(tp, sa);
1678 if (ret < 0)
1679 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1680 sa->sa_data);
1681 }
1682 }
1683
1684 if (ret < 0) {
1685 netif_err(tp, probe, dev, "Get ether addr fail\n");
1686 } else if (!is_valid_ether_addr(sa->sa_data)) {
1687 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1688 sa->sa_data);
1689 eth_hw_addr_random(dev);
1690 ether_addr_copy(sa->sa_data, dev->dev_addr);
1691 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1692 sa->sa_data);
1693 return 0;
1694 }
1695
1696 return ret;
1697 }
1698
set_ethernet_addr(struct r8152 * tp)1699 static int set_ethernet_addr(struct r8152 *tp)
1700 {
1701 struct net_device *dev = tp->netdev;
1702 struct sockaddr sa;
1703 int ret;
1704
1705 ret = determine_ethernet_addr(tp, &sa);
1706 if (ret < 0)
1707 return ret;
1708
1709 if (tp->version == RTL_VER_01)
1710 ether_addr_copy(dev->dev_addr, sa.sa_data);
1711 else
1712 ret = rtl8152_set_mac_address(dev, &sa);
1713
1714 return ret;
1715 }
1716
read_bulk_callback(struct urb * urb)1717 static void read_bulk_callback(struct urb *urb)
1718 {
1719 struct net_device *netdev;
1720 int status = urb->status;
1721 struct rx_agg *agg;
1722 struct r8152 *tp;
1723 unsigned long flags;
1724
1725 agg = urb->context;
1726 if (!agg)
1727 return;
1728
1729 tp = agg->context;
1730 if (!tp)
1731 return;
1732
1733 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1734 return;
1735
1736 if (!test_bit(WORK_ENABLE, &tp->flags))
1737 return;
1738
1739 netdev = tp->netdev;
1740
1741 /* When link down, the driver would cancel all bulks. */
1742 /* This avoid the re-submitting bulk */
1743 if (!netif_carrier_ok(netdev))
1744 return;
1745
1746 usb_mark_last_busy(tp->udev);
1747
1748 switch (status) {
1749 case 0:
1750 if (urb->actual_length < ETH_ZLEN)
1751 break;
1752
1753 spin_lock_irqsave(&tp->rx_lock, flags);
1754 list_add_tail(&agg->list, &tp->rx_done);
1755 spin_unlock_irqrestore(&tp->rx_lock, flags);
1756 napi_schedule(&tp->napi);
1757 return;
1758 case -ESHUTDOWN:
1759 rtl_set_unplug(tp);
1760 netif_device_detach(tp->netdev);
1761 return;
1762 case -ENOENT:
1763 return; /* the urb is in unlink state */
1764 case -ETIME:
1765 if (net_ratelimit())
1766 netdev_warn(netdev, "maybe reset is needed?\n");
1767 break;
1768 default:
1769 if (net_ratelimit())
1770 netdev_warn(netdev, "Rx status %d\n", status);
1771 break;
1772 }
1773
1774 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1775 }
1776
write_bulk_callback(struct urb * urb)1777 static void write_bulk_callback(struct urb *urb)
1778 {
1779 struct net_device_stats *stats;
1780 struct net_device *netdev;
1781 struct tx_agg *agg;
1782 struct r8152 *tp;
1783 unsigned long flags;
1784 int status = urb->status;
1785
1786 agg = urb->context;
1787 if (!agg)
1788 return;
1789
1790 tp = agg->context;
1791 if (!tp)
1792 return;
1793
1794 netdev = tp->netdev;
1795 stats = &netdev->stats;
1796 if (status) {
1797 if (net_ratelimit())
1798 netdev_warn(netdev, "Tx status %d\n", status);
1799 stats->tx_errors += agg->skb_num;
1800 } else {
1801 stats->tx_packets += agg->skb_num;
1802 stats->tx_bytes += agg->skb_len;
1803 }
1804
1805 spin_lock_irqsave(&tp->tx_lock, flags);
1806 list_add_tail(&agg->list, &tp->tx_free);
1807 spin_unlock_irqrestore(&tp->tx_lock, flags);
1808
1809 usb_autopm_put_interface_async(tp->intf);
1810
1811 if (!netif_carrier_ok(netdev))
1812 return;
1813
1814 if (!test_bit(WORK_ENABLE, &tp->flags))
1815 return;
1816
1817 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1818 return;
1819
1820 if (!skb_queue_empty(&tp->tx_queue))
1821 tasklet_schedule(&tp->tx_tl);
1822 }
1823
intr_callback(struct urb * urb)1824 static void intr_callback(struct urb *urb)
1825 {
1826 struct r8152 *tp;
1827 __le16 *d;
1828 int status = urb->status;
1829 int res;
1830
1831 tp = urb->context;
1832 if (!tp)
1833 return;
1834
1835 if (!test_bit(WORK_ENABLE, &tp->flags))
1836 return;
1837
1838 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1839 return;
1840
1841 switch (status) {
1842 case 0: /* success */
1843 break;
1844 case -ECONNRESET: /* unlink */
1845 case -ESHUTDOWN:
1846 netif_device_detach(tp->netdev);
1847 fallthrough;
1848 case -ENOENT:
1849 case -EPROTO:
1850 netif_info(tp, intr, tp->netdev,
1851 "Stop submitting intr, status %d\n", status);
1852 return;
1853 case -EOVERFLOW:
1854 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1855 goto resubmit;
1856 /* -EPIPE: should clear the halt */
1857 default:
1858 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1859 goto resubmit;
1860 }
1861
1862 d = urb->transfer_buffer;
1863 if (INTR_LINK & __le16_to_cpu(d[0])) {
1864 if (!netif_carrier_ok(tp->netdev)) {
1865 set_bit(RTL8152_LINK_CHG, &tp->flags);
1866 schedule_delayed_work(&tp->schedule, 0);
1867 }
1868 } else {
1869 if (netif_carrier_ok(tp->netdev)) {
1870 netif_stop_queue(tp->netdev);
1871 set_bit(RTL8152_LINK_CHG, &tp->flags);
1872 schedule_delayed_work(&tp->schedule, 0);
1873 }
1874 }
1875
1876 resubmit:
1877 res = usb_submit_urb(urb, GFP_ATOMIC);
1878 if (res == -ENODEV) {
1879 rtl_set_unplug(tp);
1880 netif_device_detach(tp->netdev);
1881 } else if (res) {
1882 netif_err(tp, intr, tp->netdev,
1883 "can't resubmit intr, status %d\n", res);
1884 }
1885 }
1886
rx_agg_align(void * data)1887 static inline void *rx_agg_align(void *data)
1888 {
1889 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1890 }
1891
tx_agg_align(void * data)1892 static inline void *tx_agg_align(void *data)
1893 {
1894 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1895 }
1896
free_rx_agg(struct r8152 * tp,struct rx_agg * agg)1897 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1898 {
1899 list_del(&agg->info_list);
1900
1901 usb_free_urb(agg->urb);
1902 put_page(agg->page);
1903 kfree(agg);
1904
1905 atomic_dec(&tp->rx_count);
1906 }
1907
alloc_rx_agg(struct r8152 * tp,gfp_t mflags)1908 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1909 {
1910 struct net_device *netdev = tp->netdev;
1911 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1912 unsigned int order = get_order(tp->rx_buf_sz);
1913 struct rx_agg *rx_agg;
1914 unsigned long flags;
1915
1916 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1917 if (!rx_agg)
1918 return NULL;
1919
1920 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1921 if (!rx_agg->page)
1922 goto free_rx;
1923
1924 rx_agg->buffer = page_address(rx_agg->page);
1925
1926 rx_agg->urb = usb_alloc_urb(0, mflags);
1927 if (!rx_agg->urb)
1928 goto free_buf;
1929
1930 rx_agg->context = tp;
1931
1932 INIT_LIST_HEAD(&rx_agg->list);
1933 INIT_LIST_HEAD(&rx_agg->info_list);
1934 spin_lock_irqsave(&tp->rx_lock, flags);
1935 list_add_tail(&rx_agg->info_list, &tp->rx_info);
1936 spin_unlock_irqrestore(&tp->rx_lock, flags);
1937
1938 atomic_inc(&tp->rx_count);
1939
1940 return rx_agg;
1941
1942 free_buf:
1943 __free_pages(rx_agg->page, order);
1944 free_rx:
1945 kfree(rx_agg);
1946 return NULL;
1947 }
1948
free_all_mem(struct r8152 * tp)1949 static void free_all_mem(struct r8152 *tp)
1950 {
1951 struct rx_agg *agg, *agg_next;
1952 unsigned long flags;
1953 int i;
1954
1955 spin_lock_irqsave(&tp->rx_lock, flags);
1956
1957 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1958 free_rx_agg(tp, agg);
1959
1960 spin_unlock_irqrestore(&tp->rx_lock, flags);
1961
1962 WARN_ON(atomic_read(&tp->rx_count));
1963
1964 for (i = 0; i < RTL8152_MAX_TX; i++) {
1965 usb_free_urb(tp->tx_info[i].urb);
1966 tp->tx_info[i].urb = NULL;
1967
1968 kfree(tp->tx_info[i].buffer);
1969 tp->tx_info[i].buffer = NULL;
1970 tp->tx_info[i].head = NULL;
1971 }
1972
1973 usb_free_urb(tp->intr_urb);
1974 tp->intr_urb = NULL;
1975
1976 kfree(tp->intr_buff);
1977 tp->intr_buff = NULL;
1978 }
1979
alloc_all_mem(struct r8152 * tp)1980 static int alloc_all_mem(struct r8152 *tp)
1981 {
1982 struct net_device *netdev = tp->netdev;
1983 struct usb_interface *intf = tp->intf;
1984 struct usb_host_interface *alt = intf->cur_altsetting;
1985 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1986 int node, i;
1987
1988 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1989
1990 spin_lock_init(&tp->rx_lock);
1991 spin_lock_init(&tp->tx_lock);
1992 INIT_LIST_HEAD(&tp->rx_info);
1993 INIT_LIST_HEAD(&tp->tx_free);
1994 INIT_LIST_HEAD(&tp->rx_done);
1995 skb_queue_head_init(&tp->tx_queue);
1996 skb_queue_head_init(&tp->rx_queue);
1997 atomic_set(&tp->rx_count, 0);
1998
1999 for (i = 0; i < RTL8152_MAX_RX; i++) {
2000 if (!alloc_rx_agg(tp, GFP_KERNEL))
2001 goto err1;
2002 }
2003
2004 for (i = 0; i < RTL8152_MAX_TX; i++) {
2005 struct urb *urb;
2006 u8 *buf;
2007
2008 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
2009 if (!buf)
2010 goto err1;
2011
2012 if (buf != tx_agg_align(buf)) {
2013 kfree(buf);
2014 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
2015 node);
2016 if (!buf)
2017 goto err1;
2018 }
2019
2020 urb = usb_alloc_urb(0, GFP_KERNEL);
2021 if (!urb) {
2022 kfree(buf);
2023 goto err1;
2024 }
2025
2026 INIT_LIST_HEAD(&tp->tx_info[i].list);
2027 tp->tx_info[i].context = tp;
2028 tp->tx_info[i].urb = urb;
2029 tp->tx_info[i].buffer = buf;
2030 tp->tx_info[i].head = tx_agg_align(buf);
2031
2032 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
2033 }
2034
2035 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
2036 if (!tp->intr_urb)
2037 goto err1;
2038
2039 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
2040 if (!tp->intr_buff)
2041 goto err1;
2042
2043 tp->intr_interval = (int)ep_intr->desc.bInterval;
2044 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
2045 tp->intr_buff, INTBUFSIZE, intr_callback,
2046 tp, tp->intr_interval);
2047
2048 return 0;
2049
2050 err1:
2051 free_all_mem(tp);
2052 return -ENOMEM;
2053 }
2054
r8152_get_tx_agg(struct r8152 * tp)2055 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
2056 {
2057 struct tx_agg *agg = NULL;
2058 unsigned long flags;
2059
2060 if (list_empty(&tp->tx_free))
2061 return NULL;
2062
2063 spin_lock_irqsave(&tp->tx_lock, flags);
2064 if (!list_empty(&tp->tx_free)) {
2065 struct list_head *cursor;
2066
2067 cursor = tp->tx_free.next;
2068 list_del_init(cursor);
2069 agg = list_entry(cursor, struct tx_agg, list);
2070 }
2071 spin_unlock_irqrestore(&tp->tx_lock, flags);
2072
2073 return agg;
2074 }
2075
2076 /* r8152_csum_workaround()
2077 * The hw limits the value of the transport offset. When the offset is out of
2078 * range, calculate the checksum by sw.
2079 */
r8152_csum_workaround(struct r8152 * tp,struct sk_buff * skb,struct sk_buff_head * list)2080 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
2081 struct sk_buff_head *list)
2082 {
2083 if (skb_shinfo(skb)->gso_size) {
2084 netdev_features_t features = tp->netdev->features;
2085 struct sk_buff *segs, *seg, *next;
2086 struct sk_buff_head seg_list;
2087
2088 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
2089 segs = skb_gso_segment(skb, features);
2090 if (IS_ERR(segs) || !segs)
2091 goto drop;
2092
2093 __skb_queue_head_init(&seg_list);
2094
2095 skb_list_walk_safe(segs, seg, next) {
2096 skb_mark_not_on_list(seg);
2097 __skb_queue_tail(&seg_list, seg);
2098 }
2099
2100 skb_queue_splice(&seg_list, list);
2101 dev_kfree_skb(skb);
2102 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2103 if (skb_checksum_help(skb) < 0)
2104 goto drop;
2105
2106 __skb_queue_head(list, skb);
2107 } else {
2108 struct net_device_stats *stats;
2109
2110 drop:
2111 stats = &tp->netdev->stats;
2112 stats->tx_dropped++;
2113 dev_kfree_skb(skb);
2114 }
2115 }
2116
rtl_tx_vlan_tag(struct tx_desc * desc,struct sk_buff * skb)2117 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
2118 {
2119 if (skb_vlan_tag_present(skb)) {
2120 u32 opts2;
2121
2122 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
2123 desc->opts2 |= cpu_to_le32(opts2);
2124 }
2125 }
2126
rtl_rx_vlan_tag(struct rx_desc * desc,struct sk_buff * skb)2127 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
2128 {
2129 u32 opts2 = le32_to_cpu(desc->opts2);
2130
2131 if (opts2 & RX_VLAN_TAG)
2132 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2133 swab16(opts2 & 0xffff));
2134 }
2135
r8152_tx_csum(struct r8152 * tp,struct tx_desc * desc,struct sk_buff * skb,u32 len,u32 transport_offset)2136 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
2137 struct sk_buff *skb, u32 len, u32 transport_offset)
2138 {
2139 u32 mss = skb_shinfo(skb)->gso_size;
2140 u32 opts1, opts2 = 0;
2141 int ret = TX_CSUM_SUCCESS;
2142
2143 WARN_ON_ONCE(len > TX_LEN_MAX);
2144
2145 opts1 = len | TX_FS | TX_LS;
2146
2147 if (mss) {
2148 if (transport_offset > GTTCPHO_MAX) {
2149 netif_warn(tp, tx_err, tp->netdev,
2150 "Invalid transport offset 0x%x for TSO\n",
2151 transport_offset);
2152 ret = TX_CSUM_TSO;
2153 goto unavailable;
2154 }
2155
2156 switch (vlan_get_protocol(skb)) {
2157 case htons(ETH_P_IP):
2158 opts1 |= GTSENDV4;
2159 break;
2160
2161 case htons(ETH_P_IPV6):
2162 if (skb_cow_head(skb, 0)) {
2163 ret = TX_CSUM_TSO;
2164 goto unavailable;
2165 }
2166 tcp_v6_gso_csum_prep(skb);
2167 opts1 |= GTSENDV6;
2168 break;
2169
2170 default:
2171 WARN_ON_ONCE(1);
2172 break;
2173 }
2174
2175 opts1 |= transport_offset << GTTCPHO_SHIFT;
2176 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2177 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2178 u8 ip_protocol;
2179
2180 if (transport_offset > TCPHO_MAX) {
2181 netif_warn(tp, tx_err, tp->netdev,
2182 "Invalid transport offset 0x%x\n",
2183 transport_offset);
2184 ret = TX_CSUM_NONE;
2185 goto unavailable;
2186 }
2187
2188 switch (vlan_get_protocol(skb)) {
2189 case htons(ETH_P_IP):
2190 opts2 |= IPV4_CS;
2191 ip_protocol = ip_hdr(skb)->protocol;
2192 break;
2193
2194 case htons(ETH_P_IPV6):
2195 opts2 |= IPV6_CS;
2196 ip_protocol = ipv6_hdr(skb)->nexthdr;
2197 break;
2198
2199 default:
2200 ip_protocol = IPPROTO_RAW;
2201 break;
2202 }
2203
2204 if (ip_protocol == IPPROTO_TCP)
2205 opts2 |= TCP_CS;
2206 else if (ip_protocol == IPPROTO_UDP)
2207 opts2 |= UDP_CS;
2208 else
2209 WARN_ON_ONCE(1);
2210
2211 opts2 |= transport_offset << TCPHO_SHIFT;
2212 }
2213
2214 desc->opts2 = cpu_to_le32(opts2);
2215 desc->opts1 = cpu_to_le32(opts1);
2216
2217 unavailable:
2218 return ret;
2219 }
2220
r8152_tx_agg_fill(struct r8152 * tp,struct tx_agg * agg)2221 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2222 {
2223 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2224 int remain, ret;
2225 u8 *tx_data;
2226
2227 __skb_queue_head_init(&skb_head);
2228 spin_lock(&tx_queue->lock);
2229 skb_queue_splice_init(tx_queue, &skb_head);
2230 spin_unlock(&tx_queue->lock);
2231
2232 tx_data = agg->head;
2233 agg->skb_num = 0;
2234 agg->skb_len = 0;
2235 remain = agg_buf_sz;
2236
2237 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2238 struct tx_desc *tx_desc;
2239 struct sk_buff *skb;
2240 unsigned int len;
2241 u32 offset;
2242
2243 skb = __skb_dequeue(&skb_head);
2244 if (!skb)
2245 break;
2246
2247 len = skb->len + sizeof(*tx_desc);
2248
2249 if (len > remain) {
2250 __skb_queue_head(&skb_head, skb);
2251 break;
2252 }
2253
2254 tx_data = tx_agg_align(tx_data);
2255 tx_desc = (struct tx_desc *)tx_data;
2256
2257 offset = (u32)skb_transport_offset(skb);
2258
2259 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2260 r8152_csum_workaround(tp, skb, &skb_head);
2261 continue;
2262 }
2263
2264 rtl_tx_vlan_tag(tx_desc, skb);
2265
2266 tx_data += sizeof(*tx_desc);
2267
2268 len = skb->len;
2269 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2270 struct net_device_stats *stats = &tp->netdev->stats;
2271
2272 stats->tx_dropped++;
2273 dev_kfree_skb_any(skb);
2274 tx_data -= sizeof(*tx_desc);
2275 continue;
2276 }
2277
2278 tx_data += len;
2279 agg->skb_len += len;
2280 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2281
2282 dev_kfree_skb_any(skb);
2283
2284 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2285
2286 if (tp->dell_tb_rx_agg_bug)
2287 break;
2288 }
2289
2290 if (!skb_queue_empty(&skb_head)) {
2291 spin_lock(&tx_queue->lock);
2292 skb_queue_splice(&skb_head, tx_queue);
2293 spin_unlock(&tx_queue->lock);
2294 }
2295
2296 netif_tx_lock(tp->netdev);
2297
2298 if (netif_queue_stopped(tp->netdev) &&
2299 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2300 netif_wake_queue(tp->netdev);
2301
2302 netif_tx_unlock(tp->netdev);
2303
2304 ret = usb_autopm_get_interface_async(tp->intf);
2305 if (ret < 0)
2306 goto out_tx_fill;
2307
2308 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2309 agg->head, (int)(tx_data - (u8 *)agg->head),
2310 (usb_complete_t)write_bulk_callback, agg);
2311
2312 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2313 if (ret < 0)
2314 usb_autopm_put_interface_async(tp->intf);
2315
2316 out_tx_fill:
2317 return ret;
2318 }
2319
r8152_rx_csum(struct r8152 * tp,struct rx_desc * rx_desc)2320 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2321 {
2322 u8 checksum = CHECKSUM_NONE;
2323 u32 opts2, opts3;
2324
2325 if (!(tp->netdev->features & NETIF_F_RXCSUM))
2326 goto return_result;
2327
2328 opts2 = le32_to_cpu(rx_desc->opts2);
2329 opts3 = le32_to_cpu(rx_desc->opts3);
2330
2331 if (opts2 & RD_IPV4_CS) {
2332 if (opts3 & IPF)
2333 checksum = CHECKSUM_NONE;
2334 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2335 checksum = CHECKSUM_UNNECESSARY;
2336 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2337 checksum = CHECKSUM_UNNECESSARY;
2338 } else if (opts2 & RD_IPV6_CS) {
2339 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2340 checksum = CHECKSUM_UNNECESSARY;
2341 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2342 checksum = CHECKSUM_UNNECESSARY;
2343 }
2344
2345 return_result:
2346 return checksum;
2347 }
2348
rx_count_exceed(struct r8152 * tp)2349 static inline bool rx_count_exceed(struct r8152 *tp)
2350 {
2351 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2352 }
2353
agg_offset(struct rx_agg * agg,void * addr)2354 static inline int agg_offset(struct rx_agg *agg, void *addr)
2355 {
2356 return (int)(addr - agg->buffer);
2357 }
2358
rtl_get_free_rx(struct r8152 * tp,gfp_t mflags)2359 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2360 {
2361 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2362 unsigned long flags;
2363
2364 spin_lock_irqsave(&tp->rx_lock, flags);
2365
2366 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2367 if (page_count(agg->page) == 1) {
2368 if (!agg_free) {
2369 list_del_init(&agg->list);
2370 agg_free = agg;
2371 continue;
2372 }
2373 if (rx_count_exceed(tp)) {
2374 list_del_init(&agg->list);
2375 free_rx_agg(tp, agg);
2376 }
2377 break;
2378 }
2379 }
2380
2381 spin_unlock_irqrestore(&tp->rx_lock, flags);
2382
2383 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2384 agg_free = alloc_rx_agg(tp, mflags);
2385
2386 return agg_free;
2387 }
2388
rx_bottom(struct r8152 * tp,int budget)2389 static int rx_bottom(struct r8152 *tp, int budget)
2390 {
2391 unsigned long flags;
2392 struct list_head *cursor, *next, rx_queue;
2393 int ret = 0, work_done = 0;
2394 struct napi_struct *napi = &tp->napi;
2395
2396 if (!skb_queue_empty(&tp->rx_queue)) {
2397 while (work_done < budget) {
2398 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2399 struct net_device *netdev = tp->netdev;
2400 struct net_device_stats *stats = &netdev->stats;
2401 unsigned int pkt_len;
2402
2403 if (!skb)
2404 break;
2405
2406 pkt_len = skb->len;
2407 napi_gro_receive(napi, skb);
2408 work_done++;
2409 stats->rx_packets++;
2410 stats->rx_bytes += pkt_len;
2411 }
2412 }
2413
2414 if (list_empty(&tp->rx_done))
2415 goto out1;
2416
2417 INIT_LIST_HEAD(&rx_queue);
2418 spin_lock_irqsave(&tp->rx_lock, flags);
2419 list_splice_init(&tp->rx_done, &rx_queue);
2420 spin_unlock_irqrestore(&tp->rx_lock, flags);
2421
2422 list_for_each_safe(cursor, next, &rx_queue) {
2423 struct rx_desc *rx_desc;
2424 struct rx_agg *agg, *agg_free;
2425 int len_used = 0;
2426 struct urb *urb;
2427 u8 *rx_data;
2428
2429 list_del_init(cursor);
2430
2431 agg = list_entry(cursor, struct rx_agg, list);
2432 urb = agg->urb;
2433 if (urb->actual_length < ETH_ZLEN)
2434 goto submit;
2435
2436 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2437
2438 rx_desc = agg->buffer;
2439 rx_data = agg->buffer;
2440 len_used += sizeof(struct rx_desc);
2441
2442 while (urb->actual_length > len_used) {
2443 struct net_device *netdev = tp->netdev;
2444 struct net_device_stats *stats = &netdev->stats;
2445 unsigned int pkt_len, rx_frag_head_sz;
2446 struct sk_buff *skb;
2447
2448 /* limite the skb numbers for rx_queue */
2449 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2450 break;
2451
2452 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2453 if (pkt_len < ETH_ZLEN)
2454 break;
2455
2456 len_used += pkt_len;
2457 if (urb->actual_length < len_used)
2458 break;
2459
2460 pkt_len -= ETH_FCS_LEN;
2461 rx_data += sizeof(struct rx_desc);
2462
2463 if (!agg_free || tp->rx_copybreak > pkt_len)
2464 rx_frag_head_sz = pkt_len;
2465 else
2466 rx_frag_head_sz = tp->rx_copybreak;
2467
2468 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2469 if (!skb) {
2470 stats->rx_dropped++;
2471 goto find_next_rx;
2472 }
2473
2474 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2475 memcpy(skb->data, rx_data, rx_frag_head_sz);
2476 skb_put(skb, rx_frag_head_sz);
2477 pkt_len -= rx_frag_head_sz;
2478 rx_data += rx_frag_head_sz;
2479 if (pkt_len) {
2480 skb_add_rx_frag(skb, 0, agg->page,
2481 agg_offset(agg, rx_data),
2482 pkt_len,
2483 SKB_DATA_ALIGN(pkt_len));
2484 get_page(agg->page);
2485 }
2486
2487 skb->protocol = eth_type_trans(skb, netdev);
2488 rtl_rx_vlan_tag(rx_desc, skb);
2489 if (work_done < budget) {
2490 work_done++;
2491 stats->rx_packets++;
2492 stats->rx_bytes += skb->len;
2493 napi_gro_receive(napi, skb);
2494 } else {
2495 __skb_queue_tail(&tp->rx_queue, skb);
2496 }
2497
2498 find_next_rx:
2499 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2500 rx_desc = (struct rx_desc *)rx_data;
2501 len_used = agg_offset(agg, rx_data);
2502 len_used += sizeof(struct rx_desc);
2503 }
2504
2505 WARN_ON(!agg_free && page_count(agg->page) > 1);
2506
2507 if (agg_free) {
2508 spin_lock_irqsave(&tp->rx_lock, flags);
2509 if (page_count(agg->page) == 1) {
2510 list_add(&agg_free->list, &tp->rx_used);
2511 } else {
2512 list_add_tail(&agg->list, &tp->rx_used);
2513 agg = agg_free;
2514 urb = agg->urb;
2515 }
2516 spin_unlock_irqrestore(&tp->rx_lock, flags);
2517 }
2518
2519 submit:
2520 if (!ret) {
2521 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2522 } else {
2523 urb->actual_length = 0;
2524 list_add_tail(&agg->list, next);
2525 }
2526 }
2527
2528 if (!list_empty(&rx_queue)) {
2529 spin_lock_irqsave(&tp->rx_lock, flags);
2530 list_splice_tail(&rx_queue, &tp->rx_done);
2531 spin_unlock_irqrestore(&tp->rx_lock, flags);
2532 }
2533
2534 out1:
2535 return work_done;
2536 }
2537
tx_bottom(struct r8152 * tp)2538 static void tx_bottom(struct r8152 *tp)
2539 {
2540 int res;
2541
2542 do {
2543 struct net_device *netdev = tp->netdev;
2544 struct tx_agg *agg;
2545
2546 if (skb_queue_empty(&tp->tx_queue))
2547 break;
2548
2549 agg = r8152_get_tx_agg(tp);
2550 if (!agg)
2551 break;
2552
2553 res = r8152_tx_agg_fill(tp, agg);
2554 if (!res)
2555 continue;
2556
2557 if (res == -ENODEV) {
2558 rtl_set_unplug(tp);
2559 netif_device_detach(netdev);
2560 } else {
2561 struct net_device_stats *stats = &netdev->stats;
2562 unsigned long flags;
2563
2564 netif_warn(tp, tx_err, netdev,
2565 "failed tx_urb %d\n", res);
2566 stats->tx_dropped += agg->skb_num;
2567
2568 spin_lock_irqsave(&tp->tx_lock, flags);
2569 list_add_tail(&agg->list, &tp->tx_free);
2570 spin_unlock_irqrestore(&tp->tx_lock, flags);
2571 }
2572 } while (res == 0);
2573 }
2574
bottom_half(struct tasklet_struct * t)2575 static void bottom_half(struct tasklet_struct *t)
2576 {
2577 struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2578
2579 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2580 return;
2581
2582 if (!test_bit(WORK_ENABLE, &tp->flags))
2583 return;
2584
2585 /* When link down, the driver would cancel all bulks. */
2586 /* This avoid the re-submitting bulk */
2587 if (!netif_carrier_ok(tp->netdev))
2588 return;
2589
2590 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2591
2592 tx_bottom(tp);
2593 }
2594
r8152_poll(struct napi_struct * napi,int budget)2595 static int r8152_poll(struct napi_struct *napi, int budget)
2596 {
2597 struct r8152 *tp = container_of(napi, struct r8152, napi);
2598 int work_done;
2599
2600 work_done = rx_bottom(tp, budget);
2601
2602 if (work_done < budget) {
2603 if (!napi_complete_done(napi, work_done))
2604 goto out;
2605 if (!list_empty(&tp->rx_done))
2606 napi_schedule(napi);
2607 }
2608
2609 out:
2610 return work_done;
2611 }
2612
2613 static
r8152_submit_rx(struct r8152 * tp,struct rx_agg * agg,gfp_t mem_flags)2614 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2615 {
2616 int ret;
2617
2618 /* The rx would be stopped, so skip submitting */
2619 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2620 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2621 return 0;
2622
2623 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2624 agg->buffer, tp->rx_buf_sz,
2625 (usb_complete_t)read_bulk_callback, agg);
2626
2627 ret = usb_submit_urb(agg->urb, mem_flags);
2628 if (ret == -ENODEV) {
2629 rtl_set_unplug(tp);
2630 netif_device_detach(tp->netdev);
2631 } else if (ret) {
2632 struct urb *urb = agg->urb;
2633 unsigned long flags;
2634
2635 urb->actual_length = 0;
2636 spin_lock_irqsave(&tp->rx_lock, flags);
2637 list_add_tail(&agg->list, &tp->rx_done);
2638 spin_unlock_irqrestore(&tp->rx_lock, flags);
2639
2640 netif_err(tp, rx_err, tp->netdev,
2641 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2642
2643 napi_schedule(&tp->napi);
2644 }
2645
2646 return ret;
2647 }
2648
rtl_drop_queued_tx(struct r8152 * tp)2649 static void rtl_drop_queued_tx(struct r8152 *tp)
2650 {
2651 struct net_device_stats *stats = &tp->netdev->stats;
2652 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2653 struct sk_buff *skb;
2654
2655 if (skb_queue_empty(tx_queue))
2656 return;
2657
2658 __skb_queue_head_init(&skb_head);
2659 spin_lock_bh(&tx_queue->lock);
2660 skb_queue_splice_init(tx_queue, &skb_head);
2661 spin_unlock_bh(&tx_queue->lock);
2662
2663 while ((skb = __skb_dequeue(&skb_head))) {
2664 dev_kfree_skb(skb);
2665 stats->tx_dropped++;
2666 }
2667 }
2668
rtl8152_tx_timeout(struct net_device * netdev,unsigned int txqueue)2669 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2670 {
2671 struct r8152 *tp = netdev_priv(netdev);
2672
2673 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2674
2675 usb_queue_reset_device(tp->intf);
2676 }
2677
rtl8152_set_rx_mode(struct net_device * netdev)2678 static void rtl8152_set_rx_mode(struct net_device *netdev)
2679 {
2680 struct r8152 *tp = netdev_priv(netdev);
2681
2682 if (netif_carrier_ok(netdev)) {
2683 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2684 schedule_delayed_work(&tp->schedule, 0);
2685 }
2686 }
2687
_rtl8152_set_rx_mode(struct net_device * netdev)2688 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2689 {
2690 struct r8152 *tp = netdev_priv(netdev);
2691 u32 mc_filter[2]; /* Multicast hash filter */
2692 __le32 tmp[2];
2693 u32 ocp_data;
2694
2695 netif_stop_queue(netdev);
2696 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2697 ocp_data &= ~RCR_ACPT_ALL;
2698 ocp_data |= RCR_AB | RCR_APM;
2699
2700 if (netdev->flags & IFF_PROMISC) {
2701 /* Unconditionally log net taps. */
2702 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2703 ocp_data |= RCR_AM | RCR_AAP;
2704 mc_filter[1] = 0xffffffff;
2705 mc_filter[0] = 0xffffffff;
2706 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2707 (netdev->flags & IFF_ALLMULTI)) {
2708 /* Too many to filter perfectly -- accept all multicasts. */
2709 ocp_data |= RCR_AM;
2710 mc_filter[1] = 0xffffffff;
2711 mc_filter[0] = 0xffffffff;
2712 } else {
2713 struct netdev_hw_addr *ha;
2714
2715 mc_filter[1] = 0;
2716 mc_filter[0] = 0;
2717 netdev_for_each_mc_addr(ha, netdev) {
2718 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2719
2720 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2721 ocp_data |= RCR_AM;
2722 }
2723 }
2724
2725 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2726 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2727
2728 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2729 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2730 netif_wake_queue(netdev);
2731 }
2732
2733 static netdev_features_t
rtl8152_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2734 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2735 netdev_features_t features)
2736 {
2737 u32 mss = skb_shinfo(skb)->gso_size;
2738 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2739 int offset = skb_transport_offset(skb);
2740
2741 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2742 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2743 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2744 features &= ~NETIF_F_GSO_MASK;
2745
2746 return features;
2747 }
2748
rtl8152_start_xmit(struct sk_buff * skb,struct net_device * netdev)2749 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2750 struct net_device *netdev)
2751 {
2752 struct r8152 *tp = netdev_priv(netdev);
2753
2754 skb_tx_timestamp(skb);
2755
2756 skb_queue_tail(&tp->tx_queue, skb);
2757
2758 if (!list_empty(&tp->tx_free)) {
2759 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2760 set_bit(SCHEDULE_TASKLET, &tp->flags);
2761 schedule_delayed_work(&tp->schedule, 0);
2762 } else {
2763 usb_mark_last_busy(tp->udev);
2764 tasklet_schedule(&tp->tx_tl);
2765 }
2766 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2767 netif_stop_queue(netdev);
2768 }
2769
2770 return NETDEV_TX_OK;
2771 }
2772
r8152b_reset_packet_filter(struct r8152 * tp)2773 static void r8152b_reset_packet_filter(struct r8152 *tp)
2774 {
2775 u32 ocp_data;
2776
2777 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2778 ocp_data &= ~FMC_FCR_MCU_EN;
2779 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2780 ocp_data |= FMC_FCR_MCU_EN;
2781 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2782 }
2783
rtl8152_nic_reset(struct r8152 * tp)2784 static void rtl8152_nic_reset(struct r8152 *tp)
2785 {
2786 u32 ocp_data;
2787 int i;
2788
2789 switch (tp->version) {
2790 case RTL_TEST_01:
2791 case RTL_VER_10:
2792 case RTL_VER_11:
2793 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2794 ocp_data &= ~CR_TE;
2795 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2796
2797 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2798 ocp_data &= ~BMU_RESET_EP_IN;
2799 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2800
2801 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2802 ocp_data |= CDC_ECM_EN;
2803 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2804
2805 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2806 ocp_data &= ~CR_RE;
2807 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2808
2809 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2810 ocp_data |= BMU_RESET_EP_IN;
2811 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2812
2813 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2814 ocp_data &= ~CDC_ECM_EN;
2815 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2816 break;
2817
2818 default:
2819 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2820
2821 for (i = 0; i < 1000; i++) {
2822 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2823 break;
2824 usleep_range(100, 400);
2825 }
2826 break;
2827 }
2828 }
2829
set_tx_qlen(struct r8152 * tp)2830 static void set_tx_qlen(struct r8152 *tp)
2831 {
2832 tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
2833 }
2834
rtl8152_get_speed(struct r8152 * tp)2835 static inline u16 rtl8152_get_speed(struct r8152 *tp)
2836 {
2837 return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2838 }
2839
rtl_eee_plus_en(struct r8152 * tp,bool enable)2840 static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
2841 {
2842 u32 ocp_data;
2843
2844 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2845 if (enable)
2846 ocp_data |= EEEP_CR_EEEP_TX;
2847 else
2848 ocp_data &= ~EEEP_CR_EEEP_TX;
2849 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2850 }
2851
rtl_set_eee_plus(struct r8152 * tp)2852 static void rtl_set_eee_plus(struct r8152 *tp)
2853 {
2854 if (rtl8152_get_speed(tp) & _10bps)
2855 rtl_eee_plus_en(tp, true);
2856 else
2857 rtl_eee_plus_en(tp, false);
2858 }
2859
rxdy_gated_en(struct r8152 * tp,bool enable)2860 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2861 {
2862 u32 ocp_data;
2863
2864 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2865 if (enable)
2866 ocp_data |= RXDY_GATED_EN;
2867 else
2868 ocp_data &= ~RXDY_GATED_EN;
2869 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2870 }
2871
rtl_start_rx(struct r8152 * tp)2872 static int rtl_start_rx(struct r8152 *tp)
2873 {
2874 struct rx_agg *agg, *agg_next;
2875 struct list_head tmp_list;
2876 unsigned long flags;
2877 int ret = 0, i = 0;
2878
2879 INIT_LIST_HEAD(&tmp_list);
2880
2881 spin_lock_irqsave(&tp->rx_lock, flags);
2882
2883 INIT_LIST_HEAD(&tp->rx_done);
2884 INIT_LIST_HEAD(&tp->rx_used);
2885
2886 list_splice_init(&tp->rx_info, &tmp_list);
2887
2888 spin_unlock_irqrestore(&tp->rx_lock, flags);
2889
2890 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2891 INIT_LIST_HEAD(&agg->list);
2892
2893 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2894 if (++i > RTL8152_MAX_RX) {
2895 spin_lock_irqsave(&tp->rx_lock, flags);
2896 list_add_tail(&agg->list, &tp->rx_used);
2897 spin_unlock_irqrestore(&tp->rx_lock, flags);
2898 } else if (unlikely(ret < 0)) {
2899 spin_lock_irqsave(&tp->rx_lock, flags);
2900 list_add_tail(&agg->list, &tp->rx_done);
2901 spin_unlock_irqrestore(&tp->rx_lock, flags);
2902 } else {
2903 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2904 }
2905 }
2906
2907 spin_lock_irqsave(&tp->rx_lock, flags);
2908 WARN_ON(!list_empty(&tp->rx_info));
2909 list_splice(&tmp_list, &tp->rx_info);
2910 spin_unlock_irqrestore(&tp->rx_lock, flags);
2911
2912 return ret;
2913 }
2914
rtl_stop_rx(struct r8152 * tp)2915 static int rtl_stop_rx(struct r8152 *tp)
2916 {
2917 struct rx_agg *agg, *agg_next;
2918 struct list_head tmp_list;
2919 unsigned long flags;
2920
2921 INIT_LIST_HEAD(&tmp_list);
2922
2923 /* The usb_kill_urb() couldn't be used in atomic.
2924 * Therefore, move the list of rx_info to a tmp one.
2925 * Then, list_for_each_entry_safe could be used without
2926 * spin lock.
2927 */
2928
2929 spin_lock_irqsave(&tp->rx_lock, flags);
2930 list_splice_init(&tp->rx_info, &tmp_list);
2931 spin_unlock_irqrestore(&tp->rx_lock, flags);
2932
2933 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2934 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2935 * equal to 1, so the other ones could be freed safely.
2936 */
2937 if (page_count(agg->page) > 1)
2938 free_rx_agg(tp, agg);
2939 else
2940 usb_kill_urb(agg->urb);
2941 }
2942
2943 /* Move back the list of temp to the rx_info */
2944 spin_lock_irqsave(&tp->rx_lock, flags);
2945 WARN_ON(!list_empty(&tp->rx_info));
2946 list_splice(&tmp_list, &tp->rx_info);
2947 spin_unlock_irqrestore(&tp->rx_lock, flags);
2948
2949 while (!skb_queue_empty(&tp->rx_queue))
2950 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2951
2952 return 0;
2953 }
2954
rtl_set_ifg(struct r8152 * tp,u16 speed)2955 static void rtl_set_ifg(struct r8152 *tp, u16 speed)
2956 {
2957 u32 ocp_data;
2958
2959 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2960 ocp_data &= ~IFG_MASK;
2961 if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
2962 ocp_data |= IFG_144NS;
2963 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
2964
2965 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
2966 ocp_data &= ~TX10MIDLE_EN;
2967 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
2968 } else {
2969 ocp_data |= IFG_96NS;
2970 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
2971
2972 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
2973 ocp_data |= TX10MIDLE_EN;
2974 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
2975 }
2976 }
2977
r8153b_rx_agg_chg_indicate(struct r8152 * tp)2978 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2979 {
2980 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2981 OWN_UPDATE | OWN_CLEAR);
2982 }
2983
rtl_enable(struct r8152 * tp)2984 static int rtl_enable(struct r8152 *tp)
2985 {
2986 u32 ocp_data;
2987
2988 r8152b_reset_packet_filter(tp);
2989
2990 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2991 ocp_data |= CR_RE | CR_TE;
2992 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2993
2994 switch (tp->version) {
2995 case RTL_VER_08:
2996 case RTL_VER_09:
2997 case RTL_VER_14:
2998 r8153b_rx_agg_chg_indicate(tp);
2999 break;
3000 default:
3001 break;
3002 }
3003
3004 rxdy_gated_en(tp, false);
3005
3006 return 0;
3007 }
3008
rtl8152_enable(struct r8152 * tp)3009 static int rtl8152_enable(struct r8152 *tp)
3010 {
3011 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3012 return -ENODEV;
3013
3014 set_tx_qlen(tp);
3015 rtl_set_eee_plus(tp);
3016
3017 return rtl_enable(tp);
3018 }
3019
r8153_set_rx_early_timeout(struct r8152 * tp)3020 static void r8153_set_rx_early_timeout(struct r8152 *tp)
3021 {
3022 u32 ocp_data = tp->coalesce / 8;
3023
3024 switch (tp->version) {
3025 case RTL_VER_03:
3026 case RTL_VER_04:
3027 case RTL_VER_05:
3028 case RTL_VER_06:
3029 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3030 ocp_data);
3031 break;
3032
3033 case RTL_VER_08:
3034 case RTL_VER_09:
3035 case RTL_VER_14:
3036 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3037 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3038 */
3039 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3040 128 / 8);
3041 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3042 ocp_data);
3043 break;
3044
3045 case RTL_VER_10:
3046 case RTL_VER_11:
3047 case RTL_VER_12:
3048 case RTL_VER_13:
3049 case RTL_VER_15:
3050 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3051 640 / 8);
3052 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3053 ocp_data);
3054 r8153b_rx_agg_chg_indicate(tp);
3055 break;
3056
3057 default:
3058 break;
3059 }
3060 }
3061
r8153_set_rx_early_size(struct r8152 * tp)3062 static void r8153_set_rx_early_size(struct r8152 *tp)
3063 {
3064 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
3065
3066 switch (tp->version) {
3067 case RTL_VER_03:
3068 case RTL_VER_04:
3069 case RTL_VER_05:
3070 case RTL_VER_06:
3071 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3072 ocp_data / 4);
3073 break;
3074 case RTL_VER_08:
3075 case RTL_VER_09:
3076 case RTL_VER_14:
3077 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3078 ocp_data / 8);
3079 break;
3080 case RTL_TEST_01:
3081 case RTL_VER_10:
3082 case RTL_VER_11:
3083 case RTL_VER_12:
3084 case RTL_VER_13:
3085 case RTL_VER_15:
3086 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3087 ocp_data / 8);
3088 r8153b_rx_agg_chg_indicate(tp);
3089 break;
3090 default:
3091 WARN_ON_ONCE(1);
3092 break;
3093 }
3094 }
3095
rtl8153_enable(struct r8152 * tp)3096 static int rtl8153_enable(struct r8152 *tp)
3097 {
3098 u32 ocp_data;
3099
3100 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3101 return -ENODEV;
3102
3103 set_tx_qlen(tp);
3104 rtl_set_eee_plus(tp);
3105 r8153_set_rx_early_timeout(tp);
3106 r8153_set_rx_early_size(tp);
3107
3108 rtl_set_ifg(tp, rtl8152_get_speed(tp));
3109
3110 switch (tp->version) {
3111 case RTL_VER_09:
3112 case RTL_VER_14:
3113 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3114 ocp_data &= ~FC_PATCH_TASK;
3115 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3116 usleep_range(1000, 2000);
3117 ocp_data |= FC_PATCH_TASK;
3118 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3119 break;
3120 default:
3121 break;
3122 }
3123
3124 return rtl_enable(tp);
3125 }
3126
rtl_disable(struct r8152 * tp)3127 static void rtl_disable(struct r8152 *tp)
3128 {
3129 u32 ocp_data;
3130 int i;
3131
3132 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3133 rtl_drop_queued_tx(tp);
3134 return;
3135 }
3136
3137 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3138 ocp_data &= ~RCR_ACPT_ALL;
3139 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3140
3141 rtl_drop_queued_tx(tp);
3142
3143 for (i = 0; i < RTL8152_MAX_TX; i++)
3144 usb_kill_urb(tp->tx_info[i].urb);
3145
3146 rxdy_gated_en(tp, true);
3147
3148 for (i = 0; i < 1000; i++) {
3149 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3150 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
3151 break;
3152 usleep_range(1000, 2000);
3153 }
3154
3155 for (i = 0; i < 1000; i++) {
3156 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
3157 break;
3158 usleep_range(1000, 2000);
3159 }
3160
3161 rtl_stop_rx(tp);
3162
3163 rtl8152_nic_reset(tp);
3164 }
3165
r8152_power_cut_en(struct r8152 * tp,bool enable)3166 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3167 {
3168 u32 ocp_data;
3169
3170 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3171 if (enable)
3172 ocp_data |= POWER_CUT;
3173 else
3174 ocp_data &= ~POWER_CUT;
3175 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
3176
3177 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3178 ocp_data &= ~RESUME_INDICATE;
3179 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
3180 }
3181
rtl_rx_vlan_en(struct r8152 * tp,bool enable)3182 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3183 {
3184 u32 ocp_data;
3185
3186 switch (tp->version) {
3187 case RTL_VER_01:
3188 case RTL_VER_02:
3189 case RTL_VER_03:
3190 case RTL_VER_04:
3191 case RTL_VER_05:
3192 case RTL_VER_06:
3193 case RTL_VER_07:
3194 case RTL_VER_08:
3195 case RTL_VER_09:
3196 case RTL_VER_14:
3197 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3198 if (enable)
3199 ocp_data |= CPCR_RX_VLAN;
3200 else
3201 ocp_data &= ~CPCR_RX_VLAN;
3202 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
3203 break;
3204
3205 case RTL_TEST_01:
3206 case RTL_VER_10:
3207 case RTL_VER_11:
3208 case RTL_VER_12:
3209 case RTL_VER_13:
3210 case RTL_VER_15:
3211 default:
3212 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3213 if (enable)
3214 ocp_data |= OUTER_VLAN | INNER_VLAN;
3215 else
3216 ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3217 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
3218 break;
3219 }
3220 }
3221
rtl8152_set_features(struct net_device * dev,netdev_features_t features)3222 static int rtl8152_set_features(struct net_device *dev,
3223 netdev_features_t features)
3224 {
3225 netdev_features_t changed = features ^ dev->features;
3226 struct r8152 *tp = netdev_priv(dev);
3227 int ret;
3228
3229 ret = usb_autopm_get_interface(tp->intf);
3230 if (ret < 0)
3231 goto out;
3232
3233 mutex_lock(&tp->control);
3234
3235 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
3236 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3237 rtl_rx_vlan_en(tp, true);
3238 else
3239 rtl_rx_vlan_en(tp, false);
3240 }
3241
3242 mutex_unlock(&tp->control);
3243
3244 usb_autopm_put_interface(tp->intf);
3245
3246 out:
3247 return ret;
3248 }
3249
3250 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3251
__rtl_get_wol(struct r8152 * tp)3252 static u32 __rtl_get_wol(struct r8152 *tp)
3253 {
3254 u32 ocp_data;
3255 u32 wolopts = 0;
3256
3257 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3258 if (ocp_data & LINK_ON_WAKE_EN)
3259 wolopts |= WAKE_PHY;
3260
3261 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3262 if (ocp_data & UWF_EN)
3263 wolopts |= WAKE_UCAST;
3264 if (ocp_data & BWF_EN)
3265 wolopts |= WAKE_BCAST;
3266 if (ocp_data & MWF_EN)
3267 wolopts |= WAKE_MCAST;
3268
3269 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3270 if (ocp_data & MAGIC_EN)
3271 wolopts |= WAKE_MAGIC;
3272
3273 return wolopts;
3274 }
3275
__rtl_set_wol(struct r8152 * tp,u32 wolopts)3276 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3277 {
3278 u32 ocp_data;
3279
3280 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3281
3282 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3283 ocp_data &= ~LINK_ON_WAKE_EN;
3284 if (wolopts & WAKE_PHY)
3285 ocp_data |= LINK_ON_WAKE_EN;
3286 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3287
3288 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3289 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3290 if (wolopts & WAKE_UCAST)
3291 ocp_data |= UWF_EN;
3292 if (wolopts & WAKE_BCAST)
3293 ocp_data |= BWF_EN;
3294 if (wolopts & WAKE_MCAST)
3295 ocp_data |= MWF_EN;
3296 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3297
3298 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3299
3300 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3301 ocp_data &= ~MAGIC_EN;
3302 if (wolopts & WAKE_MAGIC)
3303 ocp_data |= MAGIC_EN;
3304 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3305
3306 if (wolopts & WAKE_ANY)
3307 device_set_wakeup_enable(&tp->udev->dev, true);
3308 else
3309 device_set_wakeup_enable(&tp->udev->dev, false);
3310 }
3311
r8153_mac_clk_speed_down(struct r8152 * tp,bool enable)3312 static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3313 {
3314 u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3315
3316 /* MAC clock speed down */
3317 if (enable)
3318 ocp_data |= MAC_CLK_SPDWN_EN;
3319 else
3320 ocp_data &= ~MAC_CLK_SPDWN_EN;
3321
3322 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3323 }
3324
r8156_mac_clk_spd(struct r8152 * tp,bool enable)3325 static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3326 {
3327 u32 ocp_data;
3328
3329 /* MAC clock speed down */
3330 if (enable) {
3331 /* aldps_spdwn_ratio, tp10_spdwn_ratio */
3332 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3333 0x0403);
3334
3335 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3336 ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3337 ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3338 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3339 } else {
3340 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3341 ocp_data &= ~MAC_CLK_SPDWN_EN;
3342 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3343 }
3344 }
3345
r8153_u1u2en(struct r8152 * tp,bool enable)3346 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3347 {
3348 u8 u1u2[8];
3349
3350 if (enable)
3351 memset(u1u2, 0xff, sizeof(u1u2));
3352 else
3353 memset(u1u2, 0x00, sizeof(u1u2));
3354
3355 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3356 }
3357
r8153b_u1u2en(struct r8152 * tp,bool enable)3358 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3359 {
3360 u32 ocp_data;
3361
3362 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3363 if (enable)
3364 ocp_data |= LPM_U1U2_EN;
3365 else
3366 ocp_data &= ~LPM_U1U2_EN;
3367
3368 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3369 }
3370
r8153_u2p3en(struct r8152 * tp,bool enable)3371 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3372 {
3373 u32 ocp_data;
3374
3375 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3376 if (enable)
3377 ocp_data |= U2P3_ENABLE;
3378 else
3379 ocp_data &= ~U2P3_ENABLE;
3380 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3381 }
3382
r8153b_ups_flags(struct r8152 * tp)3383 static void r8153b_ups_flags(struct r8152 *tp)
3384 {
3385 u32 ups_flags = 0;
3386
3387 if (tp->ups_info.green)
3388 ups_flags |= UPS_FLAGS_EN_GREEN;
3389
3390 if (tp->ups_info.aldps)
3391 ups_flags |= UPS_FLAGS_EN_ALDPS;
3392
3393 if (tp->ups_info.eee)
3394 ups_flags |= UPS_FLAGS_EN_EEE;
3395
3396 if (tp->ups_info.flow_control)
3397 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3398
3399 if (tp->ups_info.eee_ckdiv)
3400 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3401
3402 if (tp->ups_info.eee_cmod_lv)
3403 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3404
3405 if (tp->ups_info.r_tune)
3406 ups_flags |= UPS_FLAGS_R_TUNE;
3407
3408 if (tp->ups_info._10m_ckdiv)
3409 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3410
3411 if (tp->ups_info.eee_plloff_100)
3412 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3413
3414 if (tp->ups_info.eee_plloff_giga)
3415 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3416
3417 if (tp->ups_info._250m_ckdiv)
3418 ups_flags |= UPS_FLAGS_250M_CKDIV;
3419
3420 if (tp->ups_info.ctap_short_off)
3421 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3422
3423 switch (tp->ups_info.speed_duplex) {
3424 case NWAY_10M_HALF:
3425 ups_flags |= ups_flags_speed(1);
3426 break;
3427 case NWAY_10M_FULL:
3428 ups_flags |= ups_flags_speed(2);
3429 break;
3430 case NWAY_100M_HALF:
3431 ups_flags |= ups_flags_speed(3);
3432 break;
3433 case NWAY_100M_FULL:
3434 ups_flags |= ups_flags_speed(4);
3435 break;
3436 case NWAY_1000M_FULL:
3437 ups_flags |= ups_flags_speed(5);
3438 break;
3439 case FORCE_10M_HALF:
3440 ups_flags |= ups_flags_speed(6);
3441 break;
3442 case FORCE_10M_FULL:
3443 ups_flags |= ups_flags_speed(7);
3444 break;
3445 case FORCE_100M_HALF:
3446 ups_flags |= ups_flags_speed(8);
3447 break;
3448 case FORCE_100M_FULL:
3449 ups_flags |= ups_flags_speed(9);
3450 break;
3451 default:
3452 break;
3453 }
3454
3455 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3456 }
3457
r8156_ups_flags(struct r8152 * tp)3458 static void r8156_ups_flags(struct r8152 *tp)
3459 {
3460 u32 ups_flags = 0;
3461
3462 if (tp->ups_info.green)
3463 ups_flags |= UPS_FLAGS_EN_GREEN;
3464
3465 if (tp->ups_info.aldps)
3466 ups_flags |= UPS_FLAGS_EN_ALDPS;
3467
3468 if (tp->ups_info.eee)
3469 ups_flags |= UPS_FLAGS_EN_EEE;
3470
3471 if (tp->ups_info.flow_control)
3472 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3473
3474 if (tp->ups_info.eee_ckdiv)
3475 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3476
3477 if (tp->ups_info._10m_ckdiv)
3478 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3479
3480 if (tp->ups_info.eee_plloff_100)
3481 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3482
3483 if (tp->ups_info.eee_plloff_giga)
3484 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3485
3486 if (tp->ups_info._250m_ckdiv)
3487 ups_flags |= UPS_FLAGS_250M_CKDIV;
3488
3489 switch (tp->ups_info.speed_duplex) {
3490 case FORCE_10M_HALF:
3491 ups_flags |= ups_flags_speed(0);
3492 break;
3493 case FORCE_10M_FULL:
3494 ups_flags |= ups_flags_speed(1);
3495 break;
3496 case FORCE_100M_HALF:
3497 ups_flags |= ups_flags_speed(2);
3498 break;
3499 case FORCE_100M_FULL:
3500 ups_flags |= ups_flags_speed(3);
3501 break;
3502 case NWAY_10M_HALF:
3503 ups_flags |= ups_flags_speed(4);
3504 break;
3505 case NWAY_10M_FULL:
3506 ups_flags |= ups_flags_speed(5);
3507 break;
3508 case NWAY_100M_HALF:
3509 ups_flags |= ups_flags_speed(6);
3510 break;
3511 case NWAY_100M_FULL:
3512 ups_flags |= ups_flags_speed(7);
3513 break;
3514 case NWAY_1000M_FULL:
3515 ups_flags |= ups_flags_speed(8);
3516 break;
3517 case NWAY_2500M_FULL:
3518 ups_flags |= ups_flags_speed(9);
3519 break;
3520 default:
3521 break;
3522 }
3523
3524 switch (tp->ups_info.lite_mode) {
3525 case 1:
3526 ups_flags |= 0 << 5;
3527 break;
3528 case 2:
3529 ups_flags |= 2 << 5;
3530 break;
3531 case 0:
3532 default:
3533 ups_flags |= 1 << 5;
3534 break;
3535 }
3536
3537 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3538 }
3539
rtl_green_en(struct r8152 * tp,bool enable)3540 static void rtl_green_en(struct r8152 *tp, bool enable)
3541 {
3542 u16 data;
3543
3544 data = sram_read(tp, SRAM_GREEN_CFG);
3545 if (enable)
3546 data |= GREEN_ETH_EN;
3547 else
3548 data &= ~GREEN_ETH_EN;
3549 sram_write(tp, SRAM_GREEN_CFG, data);
3550
3551 tp->ups_info.green = enable;
3552 }
3553
r8153b_green_en(struct r8152 * tp,bool enable)3554 static void r8153b_green_en(struct r8152 *tp, bool enable)
3555 {
3556 if (enable) {
3557 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
3558 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3559 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3560 } else {
3561 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3562 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3563 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3564 }
3565
3566 rtl_green_en(tp, true);
3567 }
3568
r8153_phy_status(struct r8152 * tp,u16 desired)3569 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3570 {
3571 u16 data;
3572 int i;
3573
3574 for (i = 0; i < 500; i++) {
3575 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3576 data &= PHY_STAT_MASK;
3577 if (desired) {
3578 if (data == desired)
3579 break;
3580 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3581 data == PHY_STAT_EXT_INIT) {
3582 break;
3583 }
3584
3585 msleep(20);
3586 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3587 break;
3588 }
3589
3590 return data;
3591 }
3592
r8153b_ups_en(struct r8152 * tp,bool enable)3593 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3594 {
3595 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3596
3597 if (enable) {
3598 r8153b_ups_flags(tp);
3599
3600 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3601 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3602
3603 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3604 ocp_data |= UPS_FORCE_PWR_DOWN;
3605 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3606 } else {
3607 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3608 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3609
3610 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3611 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3612 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3613
3614 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3615 int i;
3616
3617 for (i = 0; i < 500; i++) {
3618 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3619 AUTOLOAD_DONE)
3620 break;
3621 msleep(20);
3622 }
3623
3624 tp->rtl_ops.hw_phy_cfg(tp);
3625
3626 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3627 tp->duplex, tp->advertising);
3628 }
3629 }
3630 }
3631
r8153c_ups_en(struct r8152 * tp,bool enable)3632 static void r8153c_ups_en(struct r8152 *tp, bool enable)
3633 {
3634 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3635
3636 if (enable) {
3637 r8153b_ups_flags(tp);
3638
3639 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3640 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3641
3642 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3643 ocp_data |= UPS_FORCE_PWR_DOWN;
3644 ocp_data &= ~BIT(7);
3645 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3646 } else {
3647 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3648 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3649
3650 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3651 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3652 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3653
3654 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3655 int i;
3656
3657 for (i = 0; i < 500; i++) {
3658 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3659 AUTOLOAD_DONE)
3660 break;
3661 msleep(20);
3662 }
3663
3664 tp->rtl_ops.hw_phy_cfg(tp);
3665
3666 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3667 tp->duplex, tp->advertising);
3668 }
3669
3670 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3671
3672 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3673 ocp_data |= BIT(8);
3674 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3675
3676 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3677 }
3678 }
3679
r8156_ups_en(struct r8152 * tp,bool enable)3680 static void r8156_ups_en(struct r8152 *tp, bool enable)
3681 {
3682 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3683
3684 if (enable) {
3685 r8156_ups_flags(tp);
3686
3687 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3688 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3689
3690 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3691 ocp_data |= UPS_FORCE_PWR_DOWN;
3692 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3693
3694 switch (tp->version) {
3695 case RTL_VER_13:
3696 case RTL_VER_15:
3697 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3698 ocp_data &= ~OOBS_POLLING;
3699 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
3700 break;
3701 default:
3702 break;
3703 }
3704 } else {
3705 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3706 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3707
3708 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3709 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3710 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3711
3712 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3713 tp->rtl_ops.hw_phy_cfg(tp);
3714
3715 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3716 tp->duplex, tp->advertising);
3717 }
3718 }
3719 }
3720
r8153_power_cut_en(struct r8152 * tp,bool enable)3721 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3722 {
3723 u32 ocp_data;
3724
3725 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3726 if (enable)
3727 ocp_data |= PWR_EN | PHASE2_EN;
3728 else
3729 ocp_data &= ~(PWR_EN | PHASE2_EN);
3730 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3731
3732 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3733 ocp_data &= ~PCUT_STATUS;
3734 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3735 }
3736
r8153b_power_cut_en(struct r8152 * tp,bool enable)3737 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3738 {
3739 u32 ocp_data;
3740
3741 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3742 if (enable)
3743 ocp_data |= PWR_EN | PHASE2_EN;
3744 else
3745 ocp_data &= ~PWR_EN;
3746 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3747
3748 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3749 ocp_data &= ~PCUT_STATUS;
3750 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3751 }
3752
r8153_queue_wake(struct r8152 * tp,bool enable)3753 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3754 {
3755 u32 ocp_data;
3756
3757 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3758 if (enable)
3759 ocp_data |= UPCOMING_RUNTIME_D3;
3760 else
3761 ocp_data &= ~UPCOMING_RUNTIME_D3;
3762 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3763
3764 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3765 ocp_data &= ~LINK_CHG_EVENT;
3766 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3767
3768 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3769 ocp_data &= ~LINK_CHANGE_FLAG;
3770 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3771 }
3772
rtl_can_wakeup(struct r8152 * tp)3773 static bool rtl_can_wakeup(struct r8152 *tp)
3774 {
3775 struct usb_device *udev = tp->udev;
3776
3777 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3778 }
3779
rtl_runtime_suspend_enable(struct r8152 * tp,bool enable)3780 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3781 {
3782 if (enable) {
3783 u32 ocp_data;
3784
3785 __rtl_set_wol(tp, WAKE_ANY);
3786
3787 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3788
3789 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3790 ocp_data |= LINK_OFF_WAKE_EN;
3791 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3792
3793 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3794 } else {
3795 u32 ocp_data;
3796
3797 __rtl_set_wol(tp, tp->saved_wolopts);
3798
3799 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3800
3801 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3802 ocp_data &= ~LINK_OFF_WAKE_EN;
3803 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3804
3805 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3806 }
3807 }
3808
rtl8153_runtime_enable(struct r8152 * tp,bool enable)3809 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3810 {
3811 if (enable) {
3812 r8153_u1u2en(tp, false);
3813 r8153_u2p3en(tp, false);
3814 rtl_runtime_suspend_enable(tp, true);
3815 } else {
3816 rtl_runtime_suspend_enable(tp, false);
3817
3818 switch (tp->version) {
3819 case RTL_VER_03:
3820 case RTL_VER_04:
3821 break;
3822 case RTL_VER_05:
3823 case RTL_VER_06:
3824 default:
3825 r8153_u2p3en(tp, true);
3826 break;
3827 }
3828
3829 r8153_u1u2en(tp, true);
3830 }
3831 }
3832
rtl8153b_runtime_enable(struct r8152 * tp,bool enable)3833 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3834 {
3835 if (enable) {
3836 r8153_queue_wake(tp, true);
3837 r8153b_u1u2en(tp, false);
3838 r8153_u2p3en(tp, false);
3839 rtl_runtime_suspend_enable(tp, true);
3840 r8153b_ups_en(tp, true);
3841 } else {
3842 r8153b_ups_en(tp, false);
3843 r8153_queue_wake(tp, false);
3844 rtl_runtime_suspend_enable(tp, false);
3845 if (tp->udev->speed >= USB_SPEED_SUPER)
3846 r8153b_u1u2en(tp, true);
3847 }
3848 }
3849
rtl8153c_runtime_enable(struct r8152 * tp,bool enable)3850 static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
3851 {
3852 if (enable) {
3853 r8153_queue_wake(tp, true);
3854 r8153b_u1u2en(tp, false);
3855 r8153_u2p3en(tp, false);
3856 rtl_runtime_suspend_enable(tp, true);
3857 r8153c_ups_en(tp, true);
3858 } else {
3859 r8153c_ups_en(tp, false);
3860 r8153_queue_wake(tp, false);
3861 rtl_runtime_suspend_enable(tp, false);
3862 r8153b_u1u2en(tp, true);
3863 }
3864 }
3865
rtl8156_runtime_enable(struct r8152 * tp,bool enable)3866 static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
3867 {
3868 if (enable) {
3869 r8153_queue_wake(tp, true);
3870 r8153b_u1u2en(tp, false);
3871 r8153_u2p3en(tp, false);
3872 rtl_runtime_suspend_enable(tp, true);
3873 } else {
3874 r8153_queue_wake(tp, false);
3875 rtl_runtime_suspend_enable(tp, false);
3876 r8153_u2p3en(tp, true);
3877 if (tp->udev->speed >= USB_SPEED_SUPER)
3878 r8153b_u1u2en(tp, true);
3879 }
3880 }
3881
r8153_teredo_off(struct r8152 * tp)3882 static void r8153_teredo_off(struct r8152 *tp)
3883 {
3884 u32 ocp_data;
3885
3886 switch (tp->version) {
3887 case RTL_VER_01:
3888 case RTL_VER_02:
3889 case RTL_VER_03:
3890 case RTL_VER_04:
3891 case RTL_VER_05:
3892 case RTL_VER_06:
3893 case RTL_VER_07:
3894 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3895 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3896 OOB_TEREDO_EN);
3897 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3898 break;
3899
3900 case RTL_VER_08:
3901 case RTL_VER_09:
3902 case RTL_TEST_01:
3903 case RTL_VER_10:
3904 case RTL_VER_11:
3905 case RTL_VER_12:
3906 case RTL_VER_13:
3907 case RTL_VER_14:
3908 case RTL_VER_15:
3909 default:
3910 /* The bit 0 ~ 7 are relative with teredo settings. They are
3911 * W1C (write 1 to clear), so set all 1 to disable it.
3912 */
3913 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3914 break;
3915 }
3916
3917 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3918 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3919 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3920 }
3921
rtl_reset_bmu(struct r8152 * tp)3922 static void rtl_reset_bmu(struct r8152 *tp)
3923 {
3924 u32 ocp_data;
3925
3926 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3927 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3928 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3929 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3930 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3931 }
3932
3933 /* Clear the bp to stop the firmware before loading a new one */
rtl_clear_bp(struct r8152 * tp,u16 type)3934 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3935 {
3936 switch (tp->version) {
3937 case RTL_VER_01:
3938 case RTL_VER_02:
3939 case RTL_VER_07:
3940 break;
3941 case RTL_VER_03:
3942 case RTL_VER_04:
3943 case RTL_VER_05:
3944 case RTL_VER_06:
3945 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3946 break;
3947 case RTL_VER_08:
3948 case RTL_VER_09:
3949 case RTL_VER_10:
3950 case RTL_VER_11:
3951 case RTL_VER_12:
3952 case RTL_VER_13:
3953 case RTL_VER_14:
3954 case RTL_VER_15:
3955 default:
3956 if (type == MCU_TYPE_USB) {
3957 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3958
3959 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3960 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3961 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3962 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3963 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3964 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3965 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3966 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3967 } else {
3968 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3969 }
3970 break;
3971 }
3972
3973 ocp_write_word(tp, type, PLA_BP_0, 0);
3974 ocp_write_word(tp, type, PLA_BP_1, 0);
3975 ocp_write_word(tp, type, PLA_BP_2, 0);
3976 ocp_write_word(tp, type, PLA_BP_3, 0);
3977 ocp_write_word(tp, type, PLA_BP_4, 0);
3978 ocp_write_word(tp, type, PLA_BP_5, 0);
3979 ocp_write_word(tp, type, PLA_BP_6, 0);
3980 ocp_write_word(tp, type, PLA_BP_7, 0);
3981
3982 /* wait 3 ms to make sure the firmware is stopped */
3983 usleep_range(3000, 6000);
3984 ocp_write_word(tp, type, PLA_BP_BA, 0);
3985 }
3986
rtl_phy_patch_request(struct r8152 * tp,bool request,bool wait)3987 static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
3988 {
3989 u16 data, check;
3990 int i;
3991
3992 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3993 if (request) {
3994 data |= PATCH_REQUEST;
3995 check = 0;
3996 } else {
3997 data &= ~PATCH_REQUEST;
3998 check = PATCH_READY;
3999 }
4000 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4001
4002 for (i = 0; wait && i < 5000; i++) {
4003 u32 ocp_data;
4004
4005 usleep_range(1000, 2000);
4006 ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
4007 if ((ocp_data & PATCH_READY) ^ check)
4008 break;
4009 }
4010
4011 if (request && wait &&
4012 !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4013 dev_err(&tp->intf->dev, "PHY patch request fail\n");
4014 rtl_phy_patch_request(tp, false, false);
4015 return -ETIME;
4016 } else {
4017 return 0;
4018 }
4019 }
4020
rtl_patch_key_set(struct r8152 * tp,u16 key_addr,u16 patch_key)4021 static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
4022 {
4023 if (patch_key && key_addr) {
4024 sram_write(tp, key_addr, patch_key);
4025 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4026 } else if (key_addr) {
4027 u16 data;
4028
4029 sram_write(tp, 0x0000, 0x0000);
4030
4031 data = ocp_reg_read(tp, OCP_PHY_LOCK);
4032 data &= ~PATCH_LOCK;
4033 ocp_reg_write(tp, OCP_PHY_LOCK, data);
4034
4035 sram_write(tp, key_addr, 0x0000);
4036 } else {
4037 WARN_ON_ONCE(1);
4038 }
4039 }
4040
4041 static int
rtl_pre_ram_code(struct r8152 * tp,u16 key_addr,u16 patch_key,bool wait)4042 rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
4043 {
4044 if (rtl_phy_patch_request(tp, true, wait))
4045 return -ETIME;
4046
4047 rtl_patch_key_set(tp, key_addr, patch_key);
4048
4049 return 0;
4050 }
4051
rtl_post_ram_code(struct r8152 * tp,u16 key_addr,bool wait)4052 static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
4053 {
4054 rtl_patch_key_set(tp, key_addr, 0);
4055
4056 rtl_phy_patch_request(tp, false, wait);
4057
4058 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
4059
4060 return 0;
4061 }
4062
rtl8152_is_fw_phy_speed_up_ok(struct r8152 * tp,struct fw_phy_speed_up * phy)4063 static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
4064 {
4065 u16 fw_offset;
4066 u32 length;
4067 bool rc = false;
4068
4069 switch (tp->version) {
4070 case RTL_VER_01:
4071 case RTL_VER_02:
4072 case RTL_VER_03:
4073 case RTL_VER_04:
4074 case RTL_VER_05:
4075 case RTL_VER_06:
4076 case RTL_VER_07:
4077 case RTL_VER_08:
4078 case RTL_VER_09:
4079 case RTL_VER_10:
4080 case RTL_VER_11:
4081 case RTL_VER_12:
4082 case RTL_VER_14:
4083 goto out;
4084 case RTL_VER_13:
4085 case RTL_VER_15:
4086 default:
4087 break;
4088 }
4089
4090 fw_offset = __le16_to_cpu(phy->fw_offset);
4091 length = __le32_to_cpu(phy->blk_hdr.length);
4092 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4093 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4094 goto out;
4095 }
4096
4097 length -= fw_offset;
4098 if (length & 3) {
4099 dev_err(&tp->intf->dev, "invalid block length\n");
4100 goto out;
4101 }
4102
4103 if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
4104 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4105 goto out;
4106 }
4107
4108 rc = true;
4109 out:
4110 return rc;
4111 }
4112
rtl8152_is_fw_phy_ver_ok(struct r8152 * tp,struct fw_phy_ver * ver)4113 static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
4114 {
4115 bool rc = false;
4116
4117 switch (tp->version) {
4118 case RTL_VER_10:
4119 case RTL_VER_11:
4120 case RTL_VER_12:
4121 case RTL_VER_13:
4122 case RTL_VER_15:
4123 break;
4124 default:
4125 goto out;
4126 }
4127
4128 if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
4129 dev_err(&tp->intf->dev, "invalid block length\n");
4130 goto out;
4131 }
4132
4133 if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
4134 dev_err(&tp->intf->dev, "invalid phy ver addr\n");
4135 goto out;
4136 }
4137
4138 rc = true;
4139 out:
4140 return rc;
4141 }
4142
rtl8152_is_fw_phy_fixup_ok(struct r8152 * tp,struct fw_phy_fixup * fix)4143 static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
4144 {
4145 bool rc = false;
4146
4147 switch (tp->version) {
4148 case RTL_VER_10:
4149 case RTL_VER_11:
4150 case RTL_VER_12:
4151 case RTL_VER_13:
4152 case RTL_VER_15:
4153 break;
4154 default:
4155 goto out;
4156 }
4157
4158 if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
4159 dev_err(&tp->intf->dev, "invalid block length\n");
4160 goto out;
4161 }
4162
4163 if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
4164 __le16_to_cpu(fix->setting.data) != BIT(7)) {
4165 dev_err(&tp->intf->dev, "invalid phy fixup\n");
4166 goto out;
4167 }
4168
4169 rc = true;
4170 out:
4171 return rc;
4172 }
4173
rtl8152_is_fw_phy_union_ok(struct r8152 * tp,struct fw_phy_union * phy)4174 static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
4175 {
4176 u16 fw_offset;
4177 u32 length;
4178 bool rc = false;
4179
4180 switch (tp->version) {
4181 case RTL_VER_10:
4182 case RTL_VER_11:
4183 case RTL_VER_12:
4184 case RTL_VER_13:
4185 case RTL_VER_15:
4186 break;
4187 default:
4188 goto out;
4189 }
4190
4191 fw_offset = __le16_to_cpu(phy->fw_offset);
4192 length = __le32_to_cpu(phy->blk_hdr.length);
4193 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4194 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4195 goto out;
4196 }
4197
4198 length -= fw_offset;
4199 if (length & 1) {
4200 dev_err(&tp->intf->dev, "invalid block length\n");
4201 goto out;
4202 }
4203
4204 if (phy->pre_num > 2) {
4205 dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
4206 goto out;
4207 }
4208
4209 if (phy->bp_num > 8) {
4210 dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
4211 goto out;
4212 }
4213
4214 rc = true;
4215 out:
4216 return rc;
4217 }
4218
rtl8152_is_fw_phy_nc_ok(struct r8152 * tp,struct fw_phy_nc * phy)4219 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
4220 {
4221 u32 length;
4222 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
4223 bool rc = false;
4224
4225 switch (tp->version) {
4226 case RTL_VER_04:
4227 case RTL_VER_05:
4228 case RTL_VER_06:
4229 fw_reg = 0xa014;
4230 ba_reg = 0xa012;
4231 patch_en_addr = 0xa01a;
4232 mode_reg = 0xb820;
4233 bp_start = 0xa000;
4234 break;
4235 default:
4236 goto out;
4237 }
4238
4239 fw_offset = __le16_to_cpu(phy->fw_offset);
4240 if (fw_offset < sizeof(*phy)) {
4241 dev_err(&tp->intf->dev, "fw_offset too small\n");
4242 goto out;
4243 }
4244
4245 length = __le32_to_cpu(phy->blk_hdr.length);
4246 if (length < fw_offset) {
4247 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4248 goto out;
4249 }
4250
4251 length -= __le16_to_cpu(phy->fw_offset);
4252 if (!length || (length & 1)) {
4253 dev_err(&tp->intf->dev, "invalid block length\n");
4254 goto out;
4255 }
4256
4257 if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
4258 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4259 goto out;
4260 }
4261
4262 if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
4263 dev_err(&tp->intf->dev, "invalid base address register\n");
4264 goto out;
4265 }
4266
4267 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
4268 dev_err(&tp->intf->dev,
4269 "invalid patch mode enabled register\n");
4270 goto out;
4271 }
4272
4273 if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
4274 dev_err(&tp->intf->dev,
4275 "invalid register to switch the mode\n");
4276 goto out;
4277 }
4278
4279 if (__le16_to_cpu(phy->bp_start) != bp_start) {
4280 dev_err(&tp->intf->dev,
4281 "invalid start register of break point\n");
4282 goto out;
4283 }
4284
4285 if (__le16_to_cpu(phy->bp_num) > 4) {
4286 dev_err(&tp->intf->dev, "invalid break point number\n");
4287 goto out;
4288 }
4289
4290 rc = true;
4291 out:
4292 return rc;
4293 }
4294
rtl8152_is_fw_mac_ok(struct r8152 * tp,struct fw_mac * mac)4295 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
4296 {
4297 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
4298 bool rc = false;
4299 u32 length, type;
4300 int i, max_bp;
4301
4302 type = __le32_to_cpu(mac->blk_hdr.type);
4303 if (type == RTL_FW_PLA) {
4304 switch (tp->version) {
4305 case RTL_VER_01:
4306 case RTL_VER_02:
4307 case RTL_VER_07:
4308 fw_reg = 0xf800;
4309 bp_ba_addr = PLA_BP_BA;
4310 bp_en_addr = 0;
4311 bp_start = PLA_BP_0;
4312 max_bp = 8;
4313 break;
4314 case RTL_VER_03:
4315 case RTL_VER_04:
4316 case RTL_VER_05:
4317 case RTL_VER_06:
4318 case RTL_VER_08:
4319 case RTL_VER_09:
4320 case RTL_VER_11:
4321 case RTL_VER_12:
4322 case RTL_VER_13:
4323 case RTL_VER_14:
4324 case RTL_VER_15:
4325 fw_reg = 0xf800;
4326 bp_ba_addr = PLA_BP_BA;
4327 bp_en_addr = PLA_BP_EN;
4328 bp_start = PLA_BP_0;
4329 max_bp = 8;
4330 break;
4331 default:
4332 goto out;
4333 }
4334 } else if (type == RTL_FW_USB) {
4335 switch (tp->version) {
4336 case RTL_VER_03:
4337 case RTL_VER_04:
4338 case RTL_VER_05:
4339 case RTL_VER_06:
4340 fw_reg = 0xf800;
4341 bp_ba_addr = USB_BP_BA;
4342 bp_en_addr = USB_BP_EN;
4343 bp_start = USB_BP_0;
4344 max_bp = 8;
4345 break;
4346 case RTL_VER_08:
4347 case RTL_VER_09:
4348 case RTL_VER_11:
4349 case RTL_VER_12:
4350 case RTL_VER_13:
4351 case RTL_VER_14:
4352 case RTL_VER_15:
4353 fw_reg = 0xe600;
4354 bp_ba_addr = USB_BP_BA;
4355 bp_en_addr = USB_BP2_EN;
4356 bp_start = USB_BP_0;
4357 max_bp = 16;
4358 break;
4359 case RTL_VER_01:
4360 case RTL_VER_02:
4361 case RTL_VER_07:
4362 default:
4363 goto out;
4364 }
4365 } else {
4366 goto out;
4367 }
4368
4369 fw_offset = __le16_to_cpu(mac->fw_offset);
4370 if (fw_offset < sizeof(*mac)) {
4371 dev_err(&tp->intf->dev, "fw_offset too small\n");
4372 goto out;
4373 }
4374
4375 length = __le32_to_cpu(mac->blk_hdr.length);
4376 if (length < fw_offset) {
4377 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4378 goto out;
4379 }
4380
4381 length -= fw_offset;
4382 if (length < 4 || (length & 3)) {
4383 dev_err(&tp->intf->dev, "invalid block length\n");
4384 goto out;
4385 }
4386
4387 if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
4388 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4389 goto out;
4390 }
4391
4392 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
4393 dev_err(&tp->intf->dev, "invalid base address register\n");
4394 goto out;
4395 }
4396
4397 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
4398 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
4399 goto out;
4400 }
4401
4402 if (__le16_to_cpu(mac->bp_start) != bp_start) {
4403 dev_err(&tp->intf->dev,
4404 "invalid start register of break point\n");
4405 goto out;
4406 }
4407
4408 if (__le16_to_cpu(mac->bp_num) > max_bp) {
4409 dev_err(&tp->intf->dev, "invalid break point number\n");
4410 goto out;
4411 }
4412
4413 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
4414 if (mac->bp[i]) {
4415 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
4416 goto out;
4417 }
4418 }
4419
4420 rc = true;
4421 out:
4422 return rc;
4423 }
4424
4425 /* Verify the checksum for the firmware file. It is calculated from the version
4426 * field to the end of the file. Compare the result with the checksum field to
4427 * make sure the file is correct.
4428 */
rtl8152_fw_verify_checksum(struct r8152 * tp,struct fw_header * fw_hdr,size_t size)4429 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
4430 struct fw_header *fw_hdr, size_t size)
4431 {
4432 unsigned char checksum[sizeof(fw_hdr->checksum)];
4433 struct crypto_shash *alg;
4434 struct shash_desc *sdesc;
4435 size_t len;
4436 long rc;
4437
4438 alg = crypto_alloc_shash("sha256", 0, 0);
4439 if (IS_ERR(alg)) {
4440 rc = PTR_ERR(alg);
4441 goto out;
4442 }
4443
4444 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
4445 rc = -EFAULT;
4446 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
4447 crypto_shash_digestsize(alg));
4448 goto free_shash;
4449 }
4450
4451 len = sizeof(*sdesc) + crypto_shash_descsize(alg);
4452 sdesc = kmalloc(len, GFP_KERNEL);
4453 if (!sdesc) {
4454 rc = -ENOMEM;
4455 goto free_shash;
4456 }
4457 sdesc->tfm = alg;
4458
4459 len = size - sizeof(fw_hdr->checksum);
4460 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
4461 kfree(sdesc);
4462 if (rc)
4463 goto free_shash;
4464
4465 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
4466 dev_err(&tp->intf->dev, "checksum fail\n");
4467 rc = -EFAULT;
4468 }
4469
4470 free_shash:
4471 crypto_free_shash(alg);
4472 out:
4473 return rc;
4474 }
4475
rtl8152_check_firmware(struct r8152 * tp,struct rtl_fw * rtl_fw)4476 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
4477 {
4478 const struct firmware *fw = rtl_fw->fw;
4479 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4480 unsigned long fw_flags = 0;
4481 long ret = -EFAULT;
4482 int i;
4483
4484 if (fw->size < sizeof(*fw_hdr)) {
4485 dev_err(&tp->intf->dev, "file too small\n");
4486 goto fail;
4487 }
4488
4489 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
4490 if (ret)
4491 goto fail;
4492
4493 ret = -EFAULT;
4494
4495 for (i = sizeof(*fw_hdr); i < fw->size;) {
4496 struct fw_block *block = (struct fw_block *)&fw->data[i];
4497 u32 type;
4498
4499 if ((i + sizeof(*block)) > fw->size)
4500 goto fail;
4501
4502 type = __le32_to_cpu(block->type);
4503 switch (type) {
4504 case RTL_FW_END:
4505 if (__le32_to_cpu(block->length) != sizeof(*block))
4506 goto fail;
4507 goto fw_end;
4508 case RTL_FW_PLA:
4509 if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
4510 dev_err(&tp->intf->dev,
4511 "multiple PLA firmware encountered");
4512 goto fail;
4513 }
4514
4515 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4516 dev_err(&tp->intf->dev,
4517 "check PLA firmware failed\n");
4518 goto fail;
4519 }
4520 __set_bit(FW_FLAGS_PLA, &fw_flags);
4521 break;
4522 case RTL_FW_USB:
4523 if (test_bit(FW_FLAGS_USB, &fw_flags)) {
4524 dev_err(&tp->intf->dev,
4525 "multiple USB firmware encountered");
4526 goto fail;
4527 }
4528
4529 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4530 dev_err(&tp->intf->dev,
4531 "check USB firmware failed\n");
4532 goto fail;
4533 }
4534 __set_bit(FW_FLAGS_USB, &fw_flags);
4535 break;
4536 case RTL_FW_PHY_START:
4537 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4538 test_bit(FW_FLAGS_NC, &fw_flags) ||
4539 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4540 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4541 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4542 test_bit(FW_FLAGS_UC, &fw_flags) ||
4543 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4544 dev_err(&tp->intf->dev,
4545 "check PHY_START fail\n");
4546 goto fail;
4547 }
4548
4549 if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
4550 dev_err(&tp->intf->dev,
4551 "Invalid length for PHY_START\n");
4552 goto fail;
4553 }
4554 __set_bit(FW_FLAGS_START, &fw_flags);
4555 break;
4556 case RTL_FW_PHY_STOP:
4557 if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
4558 !test_bit(FW_FLAGS_START, &fw_flags)) {
4559 dev_err(&tp->intf->dev,
4560 "Check PHY_STOP fail\n");
4561 goto fail;
4562 }
4563
4564 if (__le32_to_cpu(block->length) != sizeof(*block)) {
4565 dev_err(&tp->intf->dev,
4566 "Invalid length for PHY_STOP\n");
4567 goto fail;
4568 }
4569 __set_bit(FW_FLAGS_STOP, &fw_flags);
4570 break;
4571 case RTL_FW_PHY_NC:
4572 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4573 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4574 dev_err(&tp->intf->dev,
4575 "check PHY_NC fail\n");
4576 goto fail;
4577 }
4578
4579 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4580 dev_err(&tp->intf->dev,
4581 "multiple PHY NC encountered\n");
4582 goto fail;
4583 }
4584
4585 if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {
4586 dev_err(&tp->intf->dev,
4587 "check PHY NC firmware failed\n");
4588 goto fail;
4589 }
4590 __set_bit(FW_FLAGS_NC, &fw_flags);
4591 break;
4592 case RTL_FW_PHY_UNION_NC:
4593 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4594 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4595 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4596 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4597 test_bit(FW_FLAGS_UC, &fw_flags) ||
4598 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4599 dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
4600 goto fail;
4601 }
4602
4603 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4604 dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
4605 goto fail;
4606 }
4607
4608 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4609 dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
4610 goto fail;
4611 }
4612 __set_bit(FW_FLAGS_NC, &fw_flags);
4613 break;
4614 case RTL_FW_PHY_UNION_NC1:
4615 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4616 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4617 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4618 test_bit(FW_FLAGS_UC, &fw_flags) ||
4619 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4620 dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
4621 goto fail;
4622 }
4623
4624 if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
4625 dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
4626 goto fail;
4627 }
4628
4629 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4630 dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
4631 goto fail;
4632 }
4633 __set_bit(FW_FLAGS_NC1, &fw_flags);
4634 break;
4635 case RTL_FW_PHY_UNION_NC2:
4636 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4637 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4638 test_bit(FW_FLAGS_UC, &fw_flags) ||
4639 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4640 dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
4641 goto fail;
4642 }
4643
4644 if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
4645 dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
4646 goto fail;
4647 }
4648
4649 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4650 dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
4651 goto fail;
4652 }
4653 __set_bit(FW_FLAGS_NC2, &fw_flags);
4654 break;
4655 case RTL_FW_PHY_UNION_UC2:
4656 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4657 test_bit(FW_FLAGS_UC, &fw_flags) ||
4658 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4659 dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
4660 goto fail;
4661 }
4662
4663 if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
4664 dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
4665 goto fail;
4666 }
4667
4668 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4669 dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
4670 goto fail;
4671 }
4672 __set_bit(FW_FLAGS_UC2, &fw_flags);
4673 break;
4674 case RTL_FW_PHY_UNION_UC:
4675 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4676 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4677 dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
4678 goto fail;
4679 }
4680
4681 if (test_bit(FW_FLAGS_UC, &fw_flags)) {
4682 dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
4683 goto fail;
4684 }
4685
4686 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4687 dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
4688 goto fail;
4689 }
4690 __set_bit(FW_FLAGS_UC, &fw_flags);
4691 break;
4692 case RTL_FW_PHY_UNION_MISC:
4693 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4694 dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
4695 goto fail;
4696 }
4697 break;
4698 case RTL_FW_PHY_FIXUP:
4699 if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {
4700 dev_err(&tp->intf->dev, "check PHY fixup failed\n");
4701 goto fail;
4702 }
4703 break;
4704 case RTL_FW_PHY_SPEED_UP:
4705 if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
4706 dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
4707 goto fail;
4708 }
4709
4710 if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {
4711 dev_err(&tp->intf->dev, "check PHY speed up failed\n");
4712 goto fail;
4713 }
4714 __set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
4715 break;
4716 case RTL_FW_PHY_VER:
4717 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4718 test_bit(FW_FLAGS_NC, &fw_flags) ||
4719 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4720 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4721 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4722 test_bit(FW_FLAGS_UC, &fw_flags) ||
4723 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4724 dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
4725 goto fail;
4726 }
4727
4728 if (test_bit(FW_FLAGS_VER, &fw_flags)) {
4729 dev_err(&tp->intf->dev, "multiple PHY version encountered");
4730 goto fail;
4731 }
4732
4733 if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {
4734 dev_err(&tp->intf->dev, "check PHY version failed\n");
4735 goto fail;
4736 }
4737 __set_bit(FW_FLAGS_VER, &fw_flags);
4738 break;
4739 default:
4740 dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
4741 type);
4742 break;
4743 }
4744
4745 /* next block */
4746 i += ALIGN(__le32_to_cpu(block->length), 8);
4747 }
4748
4749 fw_end:
4750 if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
4751 dev_err(&tp->intf->dev, "without PHY_STOP\n");
4752 goto fail;
4753 }
4754
4755 return 0;
4756 fail:
4757 return ret;
4758 }
4759
rtl_ram_code_speed_up(struct r8152 * tp,struct fw_phy_speed_up * phy,bool wait)4760 static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
4761 {
4762 u32 len;
4763 u8 *data;
4764
4765 if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
4766 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4767 return;
4768 }
4769
4770 len = __le32_to_cpu(phy->blk_hdr.length);
4771 len -= __le16_to_cpu(phy->fw_offset);
4772 data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
4773
4774 if (rtl_phy_patch_request(tp, true, wait))
4775 return;
4776
4777 while (len) {
4778 u32 ocp_data, size;
4779 int i;
4780
4781 if (len < 2048)
4782 size = len;
4783 else
4784 size = 2048;
4785
4786 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4787 ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4788 ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);
4789
4790 generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);
4791
4792 data += size;
4793 len -= size;
4794
4795 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4796 ocp_data |= POL_GPHY_PATCH;
4797 ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);
4798
4799 for (i = 0; i < 1000; i++) {
4800 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
4801 break;
4802 }
4803
4804 if (i == 1000) {
4805 dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
4806 break;
4807 }
4808 }
4809
4810 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
4811 rtl_phy_patch_request(tp, false, wait);
4812
4813 if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
4814 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4815 else
4816 dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
4817 }
4818
rtl8152_fw_phy_ver(struct r8152 * tp,struct fw_phy_ver * phy_ver)4819 static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
4820 {
4821 u16 ver_addr, ver;
4822
4823 ver_addr = __le16_to_cpu(phy_ver->ver.addr);
4824 ver = __le16_to_cpu(phy_ver->ver.data);
4825
4826 if (sram_read(tp, ver_addr) >= ver) {
4827 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4828 return 0;
4829 }
4830
4831 sram_write(tp, ver_addr, ver);
4832
4833 dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
4834
4835 return ver;
4836 }
4837
rtl8152_fw_phy_fixup(struct r8152 * tp,struct fw_phy_fixup * fix)4838 static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
4839 {
4840 u16 addr, data;
4841
4842 addr = __le16_to_cpu(fix->setting.addr);
4843 data = ocp_reg_read(tp, addr);
4844
4845 switch (__le16_to_cpu(fix->bit_cmd)) {
4846 case FW_FIXUP_AND:
4847 data &= __le16_to_cpu(fix->setting.data);
4848 break;
4849 case FW_FIXUP_OR:
4850 data |= __le16_to_cpu(fix->setting.data);
4851 break;
4852 case FW_FIXUP_NOT:
4853 data &= ~__le16_to_cpu(fix->setting.data);
4854 break;
4855 case FW_FIXUP_XOR:
4856 data ^= __le16_to_cpu(fix->setting.data);
4857 break;
4858 default:
4859 return;
4860 }
4861
4862 ocp_reg_write(tp, addr, data);
4863
4864 dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
4865 }
4866
rtl8152_fw_phy_union_apply(struct r8152 * tp,struct fw_phy_union * phy)4867 static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
4868 {
4869 __le16 *data;
4870 u32 length;
4871 int i, num;
4872
4873 num = phy->pre_num;
4874 for (i = 0; i < num; i++)
4875 sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
4876 __le16_to_cpu(phy->pre_set[i].data));
4877
4878 length = __le32_to_cpu(phy->blk_hdr.length);
4879 length -= __le16_to_cpu(phy->fw_offset);
4880 num = length / 2;
4881 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4882
4883 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4884 for (i = 0; i < num; i++)
4885 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4886
4887 num = phy->bp_num;
4888 for (i = 0; i < num; i++)
4889 sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
4890
4891 if (phy->bp_num && phy->bp_en.addr)
4892 sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
4893
4894 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4895 }
4896
rtl8152_fw_phy_nc_apply(struct r8152 * tp,struct fw_phy_nc * phy)4897 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
4898 {
4899 u16 mode_reg, bp_index;
4900 u32 length, i, num;
4901 __le16 *data;
4902
4903 mode_reg = __le16_to_cpu(phy->mode_reg);
4904 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
4905 sram_write(tp, __le16_to_cpu(phy->ba_reg),
4906 __le16_to_cpu(phy->ba_data));
4907
4908 length = __le32_to_cpu(phy->blk_hdr.length);
4909 length -= __le16_to_cpu(phy->fw_offset);
4910 num = length / 2;
4911 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4912
4913 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4914 for (i = 0; i < num; i++)
4915 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4916
4917 sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
4918 __le16_to_cpu(phy->patch_en_value));
4919
4920 bp_index = __le16_to_cpu(phy->bp_start);
4921 num = __le16_to_cpu(phy->bp_num);
4922 for (i = 0; i < num; i++) {
4923 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
4924 bp_index += 2;
4925 }
4926
4927 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
4928
4929 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4930 }
4931
rtl8152_fw_mac_apply(struct r8152 * tp,struct fw_mac * mac)4932 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
4933 {
4934 u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
4935 u32 length;
4936 u8 *data;
4937 int i;
4938
4939 switch (__le32_to_cpu(mac->blk_hdr.type)) {
4940 case RTL_FW_PLA:
4941 type = MCU_TYPE_PLA;
4942 break;
4943 case RTL_FW_USB:
4944 type = MCU_TYPE_USB;
4945 break;
4946 default:
4947 return;
4948 }
4949
4950 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
4951 if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {
4952 dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
4953 return;
4954 }
4955
4956 rtl_clear_bp(tp, type);
4957
4958 /* Enable backup/restore of MACDBG. This is required after clearing PLA
4959 * break points and before applying the PLA firmware.
4960 */
4961 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
4962 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
4963 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
4964 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
4965 }
4966
4967 length = __le32_to_cpu(mac->blk_hdr.length);
4968 length -= __le16_to_cpu(mac->fw_offset);
4969
4970 data = (u8 *)mac;
4971 data += __le16_to_cpu(mac->fw_offset);
4972
4973 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
4974 type);
4975
4976 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
4977 __le16_to_cpu(mac->bp_ba_value));
4978
4979 bp_index = __le16_to_cpu(mac->bp_start);
4980 bp_num = __le16_to_cpu(mac->bp_num);
4981 for (i = 0; i < bp_num; i++) {
4982 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
4983 bp_index += 2;
4984 }
4985
4986 bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
4987 if (bp_en_addr)
4988 ocp_write_word(tp, type, bp_en_addr,
4989 __le16_to_cpu(mac->bp_en_value));
4990
4991 if (fw_ver_reg)
4992 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
4993 mac->fw_ver_data);
4994
4995 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
4996 }
4997
rtl8152_apply_firmware(struct r8152 * tp,bool power_cut)4998 static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
4999 {
5000 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5001 const struct firmware *fw;
5002 struct fw_header *fw_hdr;
5003 struct fw_phy_patch_key *key;
5004 u16 key_addr = 0;
5005 int i, patch_phy = 1;
5006
5007 if (IS_ERR_OR_NULL(rtl_fw->fw))
5008 return;
5009
5010 fw = rtl_fw->fw;
5011 fw_hdr = (struct fw_header *)fw->data;
5012
5013 if (rtl_fw->pre_fw)
5014 rtl_fw->pre_fw(tp);
5015
5016 for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
5017 struct fw_block *block = (struct fw_block *)&fw->data[i];
5018
5019 switch (__le32_to_cpu(block->type)) {
5020 case RTL_FW_END:
5021 goto post_fw;
5022 case RTL_FW_PLA:
5023 case RTL_FW_USB:
5024 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
5025 break;
5026 case RTL_FW_PHY_START:
5027 if (!patch_phy)
5028 break;
5029 key = (struct fw_phy_patch_key *)block;
5030 key_addr = __le16_to_cpu(key->key_reg);
5031 rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
5032 break;
5033 case RTL_FW_PHY_STOP:
5034 if (!patch_phy)
5035 break;
5036 WARN_ON(!key_addr);
5037 rtl_post_ram_code(tp, key_addr, !power_cut);
5038 break;
5039 case RTL_FW_PHY_NC:
5040 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
5041 break;
5042 case RTL_FW_PHY_VER:
5043 patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);
5044 break;
5045 case RTL_FW_PHY_UNION_NC:
5046 case RTL_FW_PHY_UNION_NC1:
5047 case RTL_FW_PHY_UNION_NC2:
5048 case RTL_FW_PHY_UNION_UC2:
5049 case RTL_FW_PHY_UNION_UC:
5050 case RTL_FW_PHY_UNION_MISC:
5051 if (patch_phy)
5052 rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);
5053 break;
5054 case RTL_FW_PHY_FIXUP:
5055 if (patch_phy)
5056 rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);
5057 break;
5058 case RTL_FW_PHY_SPEED_UP:
5059 rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);
5060 break;
5061 default:
5062 break;
5063 }
5064
5065 i += ALIGN(__le32_to_cpu(block->length), 8);
5066 }
5067
5068 post_fw:
5069 if (rtl_fw->post_fw)
5070 rtl_fw->post_fw(tp);
5071
5072 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
5073 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
5074 }
5075
rtl8152_release_firmware(struct r8152 * tp)5076 static void rtl8152_release_firmware(struct r8152 *tp)
5077 {
5078 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5079
5080 if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
5081 release_firmware(rtl_fw->fw);
5082 rtl_fw->fw = NULL;
5083 }
5084 }
5085
rtl8152_request_firmware(struct r8152 * tp)5086 static int rtl8152_request_firmware(struct r8152 *tp)
5087 {
5088 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5089 long rc;
5090
5091 if (rtl_fw->fw || !rtl_fw->fw_name) {
5092 dev_info(&tp->intf->dev, "skip request firmware\n");
5093 rc = 0;
5094 goto result;
5095 }
5096
5097 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
5098 if (rc < 0)
5099 goto result;
5100
5101 rc = rtl8152_check_firmware(tp, rtl_fw);
5102 if (rc < 0)
5103 release_firmware(rtl_fw->fw);
5104
5105 result:
5106 if (rc) {
5107 rtl_fw->fw = ERR_PTR(rc);
5108
5109 dev_warn(&tp->intf->dev,
5110 "unable to load firmware patch %s (%ld)\n",
5111 rtl_fw->fw_name, rc);
5112 }
5113
5114 return rc;
5115 }
5116
r8152_aldps_en(struct r8152 * tp,bool enable)5117 static void r8152_aldps_en(struct r8152 *tp, bool enable)
5118 {
5119 if (enable) {
5120 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
5121 LINKENA | DIS_SDSAVE);
5122 } else {
5123 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
5124 DIS_SDSAVE);
5125 msleep(20);
5126 }
5127 }
5128
r8152_mmd_indirect(struct r8152 * tp,u16 dev,u16 reg)5129 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
5130 {
5131 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
5132 ocp_reg_write(tp, OCP_EEE_DATA, reg);
5133 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
5134 }
5135
r8152_mmd_read(struct r8152 * tp,u16 dev,u16 reg)5136 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
5137 {
5138 u16 data;
5139
5140 r8152_mmd_indirect(tp, dev, reg);
5141 data = ocp_reg_read(tp, OCP_EEE_DATA);
5142 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5143
5144 return data;
5145 }
5146
r8152_mmd_write(struct r8152 * tp,u16 dev,u16 reg,u16 data)5147 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
5148 {
5149 r8152_mmd_indirect(tp, dev, reg);
5150 ocp_reg_write(tp, OCP_EEE_DATA, data);
5151 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5152 }
5153
r8152_eee_en(struct r8152 * tp,bool enable)5154 static void r8152_eee_en(struct r8152 *tp, bool enable)
5155 {
5156 u16 config1, config2, config3;
5157 u32 ocp_data;
5158
5159 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5160 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5161 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5162 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5163
5164 if (enable) {
5165 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5166 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5167 config1 |= sd_rise_time(1);
5168 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5169 config3 |= fast_snr(42);
5170 } else {
5171 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5172 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5173 RX_QUIET_EN);
5174 config1 |= sd_rise_time(7);
5175 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5176 config3 |= fast_snr(511);
5177 }
5178
5179 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5180 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
5181 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
5182 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
5183 }
5184
r8153_eee_en(struct r8152 * tp,bool enable)5185 static void r8153_eee_en(struct r8152 *tp, bool enable)
5186 {
5187 u32 ocp_data;
5188 u16 config;
5189
5190 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5191 config = ocp_reg_read(tp, OCP_EEE_CFG);
5192
5193 if (enable) {
5194 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5195 config |= EEE10_EN;
5196 } else {
5197 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5198 config &= ~EEE10_EN;
5199 }
5200
5201 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5202 ocp_reg_write(tp, OCP_EEE_CFG, config);
5203
5204 tp->ups_info.eee = enable;
5205 }
5206
r8156_eee_en(struct r8152 * tp,bool enable)5207 static void r8156_eee_en(struct r8152 *tp, bool enable)
5208 {
5209 u16 config;
5210
5211 r8153_eee_en(tp, enable);
5212
5213 config = ocp_reg_read(tp, OCP_EEE_ADV2);
5214
5215 if (enable)
5216 config |= MDIO_EEE_2_5GT;
5217 else
5218 config &= ~MDIO_EEE_2_5GT;
5219
5220 ocp_reg_write(tp, OCP_EEE_ADV2, config);
5221 }
5222
rtl_eee_enable(struct r8152 * tp,bool enable)5223 static void rtl_eee_enable(struct r8152 *tp, bool enable)
5224 {
5225 switch (tp->version) {
5226 case RTL_VER_01:
5227 case RTL_VER_02:
5228 case RTL_VER_07:
5229 if (enable) {
5230 r8152_eee_en(tp, true);
5231 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
5232 tp->eee_adv);
5233 } else {
5234 r8152_eee_en(tp, false);
5235 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
5236 }
5237 break;
5238 case RTL_VER_03:
5239 case RTL_VER_04:
5240 case RTL_VER_05:
5241 case RTL_VER_06:
5242 case RTL_VER_08:
5243 case RTL_VER_09:
5244 case RTL_VER_14:
5245 if (enable) {
5246 r8153_eee_en(tp, true);
5247 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5248 } else {
5249 r8153_eee_en(tp, false);
5250 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5251 }
5252 break;
5253 case RTL_VER_10:
5254 case RTL_VER_11:
5255 case RTL_VER_12:
5256 case RTL_VER_13:
5257 case RTL_VER_15:
5258 if (enable) {
5259 r8156_eee_en(tp, true);
5260 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5261 } else {
5262 r8156_eee_en(tp, false);
5263 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5264 }
5265 break;
5266 default:
5267 break;
5268 }
5269 }
5270
r8152b_enable_fc(struct r8152 * tp)5271 static void r8152b_enable_fc(struct r8152 *tp)
5272 {
5273 u16 anar;
5274
5275 anar = r8152_mdio_read(tp, MII_ADVERTISE);
5276 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5277 r8152_mdio_write(tp, MII_ADVERTISE, anar);
5278
5279 tp->ups_info.flow_control = true;
5280 }
5281
rtl8152_disable(struct r8152 * tp)5282 static void rtl8152_disable(struct r8152 *tp)
5283 {
5284 r8152_aldps_en(tp, false);
5285 rtl_disable(tp);
5286 r8152_aldps_en(tp, true);
5287 }
5288
r8152b_hw_phy_cfg(struct r8152 * tp)5289 static void r8152b_hw_phy_cfg(struct r8152 *tp)
5290 {
5291 rtl8152_apply_firmware(tp, false);
5292 rtl_eee_enable(tp, tp->eee_en);
5293 r8152_aldps_en(tp, true);
5294 r8152b_enable_fc(tp);
5295
5296 set_bit(PHY_RESET, &tp->flags);
5297 }
5298
wait_oob_link_list_ready(struct r8152 * tp)5299 static void wait_oob_link_list_ready(struct r8152 *tp)
5300 {
5301 u32 ocp_data;
5302 int i;
5303
5304 for (i = 0; i < 1000; i++) {
5305 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5306 if (ocp_data & LINK_LIST_READY)
5307 break;
5308 usleep_range(1000, 2000);
5309 }
5310 }
5311
r8156b_wait_loading_flash(struct r8152 * tp)5312 static void r8156b_wait_loading_flash(struct r8152 *tp)
5313 {
5314 if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
5315 !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
5316 int i;
5317
5318 for (i = 0; i < 100; i++) {
5319 if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
5320 break;
5321 usleep_range(1000, 2000);
5322 }
5323 }
5324 }
5325
r8152b_exit_oob(struct r8152 * tp)5326 static void r8152b_exit_oob(struct r8152 *tp)
5327 {
5328 u32 ocp_data;
5329
5330 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5331 ocp_data &= ~RCR_ACPT_ALL;
5332 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5333
5334 rxdy_gated_en(tp, true);
5335 r8153_teredo_off(tp);
5336 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5337 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
5338
5339 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5340 ocp_data &= ~NOW_IS_OOB;
5341 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5342
5343 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5344 ocp_data &= ~MCU_BORW_EN;
5345 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5346
5347 wait_oob_link_list_ready(tp);
5348
5349 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5350 ocp_data |= RE_INIT_LL;
5351 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5352
5353 wait_oob_link_list_ready(tp);
5354
5355 rtl8152_nic_reset(tp);
5356
5357 /* rx share fifo credit full threshold */
5358 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5359
5360 if (tp->udev->speed == USB_SPEED_FULL ||
5361 tp->udev->speed == USB_SPEED_LOW) {
5362 /* rx share fifo credit near full threshold */
5363 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5364 RXFIFO_THR2_FULL);
5365 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5366 RXFIFO_THR3_FULL);
5367 } else {
5368 /* rx share fifo credit near full threshold */
5369 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5370 RXFIFO_THR2_HIGH);
5371 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5372 RXFIFO_THR3_HIGH);
5373 }
5374
5375 /* TX share fifo free credit full threshold */
5376 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5377
5378 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
5379 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
5380 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
5381 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
5382
5383 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5384
5385 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5386
5387 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5388 ocp_data |= TCR0_AUTO_FIFO;
5389 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5390 }
5391
r8152b_enter_oob(struct r8152 * tp)5392 static void r8152b_enter_oob(struct r8152 *tp)
5393 {
5394 u32 ocp_data;
5395
5396 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5397 ocp_data &= ~NOW_IS_OOB;
5398 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5399
5400 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5401 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5402 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5403
5404 rtl_disable(tp);
5405
5406 wait_oob_link_list_ready(tp);
5407
5408 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5409 ocp_data |= RE_INIT_LL;
5410 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5411
5412 wait_oob_link_list_ready(tp);
5413
5414 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5415
5416 rtl_rx_vlan_en(tp, true);
5417
5418 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5419 ocp_data |= ALDPS_PROXY_MODE;
5420 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5421
5422 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5423 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5424 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5425
5426 rxdy_gated_en(tp, false);
5427
5428 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5429 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5430 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5431 }
5432
r8153_pre_firmware_1(struct r8152 * tp)5433 static int r8153_pre_firmware_1(struct r8152 *tp)
5434 {
5435 int i;
5436
5437 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
5438 for (i = 0; i < 104; i++) {
5439 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
5440
5441 if (!(ocp_data & WTD1_EN))
5442 break;
5443 usleep_range(1000, 2000);
5444 }
5445
5446 return 0;
5447 }
5448
r8153_post_firmware_1(struct r8152 * tp)5449 static int r8153_post_firmware_1(struct r8152 *tp)
5450 {
5451 /* set USB_BP_4 to support USB_SPEED_SUPER only */
5452 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5453 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
5454
5455 /* reset UPHY timer to 36 ms */
5456 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5457
5458 return 0;
5459 }
5460
r8153_pre_firmware_2(struct r8152 * tp)5461 static int r8153_pre_firmware_2(struct r8152 *tp)
5462 {
5463 u32 ocp_data;
5464
5465 r8153_pre_firmware_1(tp);
5466
5467 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5468 ocp_data &= ~FW_FIX_SUSPEND;
5469 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5470
5471 return 0;
5472 }
5473
r8153_post_firmware_2(struct r8152 * tp)5474 static int r8153_post_firmware_2(struct r8152 *tp)
5475 {
5476 u32 ocp_data;
5477
5478 /* enable bp0 if support USB_SPEED_SUPER only */
5479 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5480 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5481 ocp_data |= BIT(0);
5482 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5483 }
5484
5485 /* reset UPHY timer to 36 ms */
5486 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5487
5488 /* enable U3P3 check, set the counter to 4 */
5489 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5490
5491 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5492 ocp_data |= FW_FIX_SUSPEND;
5493 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5494
5495 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5496 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5497 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5498
5499 return 0;
5500 }
5501
r8153_post_firmware_3(struct r8152 * tp)5502 static int r8153_post_firmware_3(struct r8152 *tp)
5503 {
5504 u32 ocp_data;
5505
5506 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5507 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5508 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5509
5510 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5511 ocp_data |= FW_IP_RESET_EN;
5512 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5513
5514 return 0;
5515 }
5516
r8153b_pre_firmware_1(struct r8152 * tp)5517 static int r8153b_pre_firmware_1(struct r8152 *tp)
5518 {
5519 /* enable fc timer and set timer to 1 second. */
5520 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
5521 CTRL_TIMER_EN | (1000 / 8));
5522
5523 return 0;
5524 }
5525
r8153b_post_firmware_1(struct r8152 * tp)5526 static int r8153b_post_firmware_1(struct r8152 *tp)
5527 {
5528 u32 ocp_data;
5529
5530 /* enable bp0 for RTL8153-BND */
5531 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5532 if (ocp_data & BND_MASK) {
5533 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5534 ocp_data |= BIT(0);
5535 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5536 }
5537
5538 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5539 ocp_data |= FLOW_CTRL_PATCH_OPT;
5540 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5541
5542 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5543 ocp_data |= FC_PATCH_TASK;
5544 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5545
5546 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5547 ocp_data |= FW_IP_RESET_EN;
5548 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5549
5550 return 0;
5551 }
5552
r8153c_post_firmware_1(struct r8152 * tp)5553 static int r8153c_post_firmware_1(struct r8152 *tp)
5554 {
5555 u32 ocp_data;
5556
5557 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5558 ocp_data |= FLOW_CTRL_PATCH_2;
5559 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5560
5561 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5562 ocp_data |= FC_PATCH_TASK;
5563 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5564
5565 return 0;
5566 }
5567
r8156a_post_firmware_1(struct r8152 * tp)5568 static int r8156a_post_firmware_1(struct r8152 *tp)
5569 {
5570 u32 ocp_data;
5571
5572 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5573 ocp_data |= FW_IP_RESET_EN;
5574 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5575
5576 /* Modify U3PHY parameter for compatibility issue */
5577 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);
5578 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);
5579
5580 return 0;
5581 }
5582
r8153_aldps_en(struct r8152 * tp,bool enable)5583 static void r8153_aldps_en(struct r8152 *tp, bool enable)
5584 {
5585 u16 data;
5586
5587 data = ocp_reg_read(tp, OCP_POWER_CFG);
5588 if (enable) {
5589 data |= EN_ALDPS;
5590 ocp_reg_write(tp, OCP_POWER_CFG, data);
5591 } else {
5592 int i;
5593
5594 data &= ~EN_ALDPS;
5595 ocp_reg_write(tp, OCP_POWER_CFG, data);
5596 for (i = 0; i < 20; i++) {
5597 usleep_range(1000, 2000);
5598 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
5599 break;
5600 }
5601 }
5602
5603 tp->ups_info.aldps = enable;
5604 }
5605
r8153_hw_phy_cfg(struct r8152 * tp)5606 static void r8153_hw_phy_cfg(struct r8152 *tp)
5607 {
5608 u32 ocp_data;
5609 u16 data;
5610
5611 /* disable ALDPS before updating the PHY parameters */
5612 r8153_aldps_en(tp, false);
5613
5614 /* disable EEE before updating the PHY parameters */
5615 rtl_eee_enable(tp, false);
5616
5617 rtl8152_apply_firmware(tp, false);
5618
5619 if (tp->version == RTL_VER_03) {
5620 data = ocp_reg_read(tp, OCP_EEE_CFG);
5621 data &= ~CTAP_SHORT_EN;
5622 ocp_reg_write(tp, OCP_EEE_CFG, data);
5623 }
5624
5625 data = ocp_reg_read(tp, OCP_POWER_CFG);
5626 data |= EEE_CLKDIV_EN;
5627 ocp_reg_write(tp, OCP_POWER_CFG, data);
5628
5629 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5630 data |= EN_10M_BGOFF;
5631 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5632 data = ocp_reg_read(tp, OCP_POWER_CFG);
5633 data |= EN_10M_PLLOFF;
5634 ocp_reg_write(tp, OCP_POWER_CFG, data);
5635 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
5636
5637 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5638 ocp_data |= PFM_PWM_SWITCH;
5639 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5640
5641 /* Enable LPF corner auto tune */
5642 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
5643
5644 /* Adjust 10M Amplitude */
5645 sram_write(tp, SRAM_10M_AMP1, 0x00af);
5646 sram_write(tp, SRAM_10M_AMP2, 0x0208);
5647
5648 if (tp->eee_en)
5649 rtl_eee_enable(tp, true);
5650
5651 r8153_aldps_en(tp, true);
5652 r8152b_enable_fc(tp);
5653
5654 switch (tp->version) {
5655 case RTL_VER_03:
5656 case RTL_VER_04:
5657 break;
5658 case RTL_VER_05:
5659 case RTL_VER_06:
5660 default:
5661 r8153_u2p3en(tp, true);
5662 break;
5663 }
5664
5665 set_bit(PHY_RESET, &tp->flags);
5666 }
5667
r8152_efuse_read(struct r8152 * tp,u8 addr)5668 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
5669 {
5670 u32 ocp_data;
5671
5672 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
5673 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
5674 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
5675 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
5676
5677 return ocp_data;
5678 }
5679
r8153b_hw_phy_cfg(struct r8152 * tp)5680 static void r8153b_hw_phy_cfg(struct r8152 *tp)
5681 {
5682 u32 ocp_data;
5683 u16 data;
5684
5685 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5686 if (ocp_data & PCUT_STATUS) {
5687 ocp_data &= ~PCUT_STATUS;
5688 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
5689 }
5690
5691 /* disable ALDPS before updating the PHY parameters */
5692 r8153_aldps_en(tp, false);
5693
5694 /* disable EEE before updating the PHY parameters */
5695 rtl_eee_enable(tp, false);
5696
5697 /* U1/U2/L1 idle timer. 500 us */
5698 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5699
5700 data = r8153_phy_status(tp, 0);
5701
5702 switch (data) {
5703 case PHY_STAT_PWRDN:
5704 case PHY_STAT_EXT_INIT:
5705 rtl8152_apply_firmware(tp, true);
5706
5707 data = r8152_mdio_read(tp, MII_BMCR);
5708 data &= ~BMCR_PDOWN;
5709 r8152_mdio_write(tp, MII_BMCR, data);
5710 break;
5711 case PHY_STAT_LAN_ON:
5712 default:
5713 rtl8152_apply_firmware(tp, false);
5714 break;
5715 }
5716
5717 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5718
5719 data = sram_read(tp, SRAM_GREEN_CFG);
5720 data |= R_TUNE_EN;
5721 sram_write(tp, SRAM_GREEN_CFG, data);
5722 data = ocp_reg_read(tp, OCP_NCTL_CFG);
5723 data |= PGA_RETURN_EN;
5724 ocp_reg_write(tp, OCP_NCTL_CFG, data);
5725
5726 /* ADC Bias Calibration:
5727 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5728 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
5729 * ADC ioffset.
5730 */
5731 ocp_data = r8152_efuse_read(tp, 0x7d);
5732 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
5733 if (data != 0xffff)
5734 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
5735
5736 /* ups mode tx-link-pulse timing adjustment:
5737 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5738 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5739 */
5740 ocp_data = ocp_reg_read(tp, 0xc426);
5741 ocp_data &= 0x3fff;
5742 if (ocp_data) {
5743 u32 swr_cnt_1ms_ini;
5744
5745 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5746 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5747 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5748 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
5749 }
5750
5751 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5752 ocp_data |= PFM_PWM_SWITCH;
5753 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5754
5755 /* Advnace EEE */
5756 if (!rtl_phy_patch_request(tp, true, true)) {
5757 data = ocp_reg_read(tp, OCP_POWER_CFG);
5758 data |= EEE_CLKDIV_EN;
5759 ocp_reg_write(tp, OCP_POWER_CFG, data);
5760 tp->ups_info.eee_ckdiv = true;
5761
5762 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5763 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5764 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5765 tp->ups_info.eee_cmod_lv = true;
5766 tp->ups_info._10m_ckdiv = true;
5767 tp->ups_info.eee_plloff_giga = true;
5768
5769 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
5770 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
5771 tp->ups_info._250m_ckdiv = true;
5772
5773 rtl_phy_patch_request(tp, false, true);
5774 }
5775
5776 if (tp->eee_en)
5777 rtl_eee_enable(tp, true);
5778
5779 r8153_aldps_en(tp, true);
5780 r8152b_enable_fc(tp);
5781
5782 set_bit(PHY_RESET, &tp->flags);
5783 }
5784
r8153c_hw_phy_cfg(struct r8152 * tp)5785 static void r8153c_hw_phy_cfg(struct r8152 *tp)
5786 {
5787 r8153b_hw_phy_cfg(tp);
5788
5789 tp->ups_info.r_tune = true;
5790 }
5791
rtl8153_change_mtu(struct r8152 * tp)5792 static void rtl8153_change_mtu(struct r8152 *tp)
5793 {
5794 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5795 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
5796 }
5797
r8153_first_init(struct r8152 * tp)5798 static void r8153_first_init(struct r8152 *tp)
5799 {
5800 u32 ocp_data;
5801
5802 rxdy_gated_en(tp, true);
5803 r8153_teredo_off(tp);
5804
5805 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5806 ocp_data &= ~RCR_ACPT_ALL;
5807 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5808
5809 rtl8152_nic_reset(tp);
5810 rtl_reset_bmu(tp);
5811
5812 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5813 ocp_data &= ~NOW_IS_OOB;
5814 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5815
5816 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5817 ocp_data &= ~MCU_BORW_EN;
5818 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5819
5820 wait_oob_link_list_ready(tp);
5821
5822 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5823 ocp_data |= RE_INIT_LL;
5824 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5825
5826 wait_oob_link_list_ready(tp);
5827
5828 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5829
5830 rtl8153_change_mtu(tp);
5831
5832 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5833 ocp_data |= TCR0_AUTO_FIFO;
5834 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5835
5836 rtl8152_nic_reset(tp);
5837
5838 /* rx share fifo credit full threshold */
5839 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5840 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
5841 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
5842 /* TX share fifo free credit full threshold */
5843 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5844 }
5845
r8153_enter_oob(struct r8152 * tp)5846 static void r8153_enter_oob(struct r8152 *tp)
5847 {
5848 u32 ocp_data;
5849
5850 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5851 ocp_data &= ~NOW_IS_OOB;
5852 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5853
5854 rtl_disable(tp);
5855 rtl_reset_bmu(tp);
5856
5857 wait_oob_link_list_ready(tp);
5858
5859 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5860 ocp_data |= RE_INIT_LL;
5861 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5862
5863 wait_oob_link_list_ready(tp);
5864
5865 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5866
5867 switch (tp->version) {
5868 case RTL_VER_03:
5869 case RTL_VER_04:
5870 case RTL_VER_05:
5871 case RTL_VER_06:
5872 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
5873 ocp_data &= ~TEREDO_WAKE_MASK;
5874 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
5875 break;
5876
5877 case RTL_VER_08:
5878 case RTL_VER_09:
5879 case RTL_VER_14:
5880 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
5881 * type. Set it to zero. bits[7:0] are the W1C bits about
5882 * the events. Set them to all 1 to clear them.
5883 */
5884 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
5885 break;
5886
5887 default:
5888 break;
5889 }
5890
5891 rtl_rx_vlan_en(tp, true);
5892
5893 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5894 ocp_data |= ALDPS_PROXY_MODE;
5895 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5896
5897 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5898 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5899 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5900
5901 rxdy_gated_en(tp, false);
5902
5903 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5904 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5905 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5906 }
5907
rtl8153_disable(struct r8152 * tp)5908 static void rtl8153_disable(struct r8152 *tp)
5909 {
5910 r8153_aldps_en(tp, false);
5911 rtl_disable(tp);
5912 rtl_reset_bmu(tp);
5913 r8153_aldps_en(tp, true);
5914 }
5915
rtl8156_enable(struct r8152 * tp)5916 static int rtl8156_enable(struct r8152 *tp)
5917 {
5918 u32 ocp_data;
5919 u16 speed;
5920
5921 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5922 return -ENODEV;
5923
5924 set_tx_qlen(tp);
5925 rtl_set_eee_plus(tp);
5926 r8153_set_rx_early_timeout(tp);
5927 r8153_set_rx_early_size(tp);
5928
5929 speed = rtl8152_get_speed(tp);
5930 rtl_set_ifg(tp, speed);
5931
5932 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
5933 if (speed & _2500bps)
5934 ocp_data &= ~IDLE_SPDWN_EN;
5935 else
5936 ocp_data |= IDLE_SPDWN_EN;
5937 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
5938
5939 if (speed & _1000bps)
5940 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
5941 else if (speed & _500bps)
5942 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
5943
5944 if (tp->udev->speed == USB_SPEED_HIGH) {
5945 /* USB 0xb45e[3:0] l1_nyet_hird */
5946 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
5947 ocp_data &= ~0xf;
5948 if (is_flow_control(speed))
5949 ocp_data |= 0xf;
5950 else
5951 ocp_data |= 0x1;
5952 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
5953 }
5954
5955 return rtl_enable(tp);
5956 }
5957
rtl8156b_enable(struct r8152 * tp)5958 static int rtl8156b_enable(struct r8152 *tp)
5959 {
5960 u32 ocp_data;
5961 u16 speed;
5962
5963 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5964 return -ENODEV;
5965
5966 set_tx_qlen(tp);
5967 rtl_set_eee_plus(tp);
5968
5969 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
5970 ocp_data &= ~RX_AGGR_NUM_MASK;
5971 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
5972
5973 r8153_set_rx_early_timeout(tp);
5974 r8153_set_rx_early_size(tp);
5975
5976 speed = rtl8152_get_speed(tp);
5977 rtl_set_ifg(tp, speed);
5978
5979 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
5980 if (speed & _2500bps)
5981 ocp_data &= ~IDLE_SPDWN_EN;
5982 else
5983 ocp_data |= IDLE_SPDWN_EN;
5984 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
5985
5986 if (tp->udev->speed == USB_SPEED_HIGH) {
5987 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
5988 ocp_data &= ~0xf;
5989 if (is_flow_control(speed))
5990 ocp_data |= 0xf;
5991 else
5992 ocp_data |= 0x1;
5993 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
5994 }
5995
5996 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5997 ocp_data &= ~FC_PATCH_TASK;
5998 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5999 usleep_range(1000, 2000);
6000 ocp_data |= FC_PATCH_TASK;
6001 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6002
6003 return rtl_enable(tp);
6004 }
6005
rtl8152_set_speed(struct r8152 * tp,u8 autoneg,u32 speed,u8 duplex,u32 advertising)6006 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
6007 u32 advertising)
6008 {
6009 u16 bmcr;
6010 int ret = 0;
6011
6012 if (autoneg == AUTONEG_DISABLE) {
6013 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
6014 return -EINVAL;
6015
6016 switch (speed) {
6017 case SPEED_10:
6018 bmcr = BMCR_SPEED10;
6019 if (duplex == DUPLEX_FULL) {
6020 bmcr |= BMCR_FULLDPLX;
6021 tp->ups_info.speed_duplex = FORCE_10M_FULL;
6022 } else {
6023 tp->ups_info.speed_duplex = FORCE_10M_HALF;
6024 }
6025 break;
6026 case SPEED_100:
6027 bmcr = BMCR_SPEED100;
6028 if (duplex == DUPLEX_FULL) {
6029 bmcr |= BMCR_FULLDPLX;
6030 tp->ups_info.speed_duplex = FORCE_100M_FULL;
6031 } else {
6032 tp->ups_info.speed_duplex = FORCE_100M_HALF;
6033 }
6034 break;
6035 case SPEED_1000:
6036 if (tp->mii.supports_gmii) {
6037 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
6038 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6039 break;
6040 }
6041 fallthrough;
6042 default:
6043 ret = -EINVAL;
6044 goto out;
6045 }
6046
6047 if (duplex == DUPLEX_FULL)
6048 tp->mii.full_duplex = 1;
6049 else
6050 tp->mii.full_duplex = 0;
6051
6052 tp->mii.force_media = 1;
6053 } else {
6054 u16 orig, new1;
6055 u32 support;
6056
6057 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6058 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6059
6060 if (tp->mii.supports_gmii) {
6061 support |= RTL_ADVERTISED_1000_FULL;
6062
6063 if (tp->support_2500full)
6064 support |= RTL_ADVERTISED_2500_FULL;
6065 }
6066
6067 if (!(advertising & support))
6068 return -EINVAL;
6069
6070 orig = r8152_mdio_read(tp, MII_ADVERTISE);
6071 new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
6072 ADVERTISE_100HALF | ADVERTISE_100FULL);
6073 if (advertising & RTL_ADVERTISED_10_HALF) {
6074 new1 |= ADVERTISE_10HALF;
6075 tp->ups_info.speed_duplex = NWAY_10M_HALF;
6076 }
6077 if (advertising & RTL_ADVERTISED_10_FULL) {
6078 new1 |= ADVERTISE_10FULL;
6079 tp->ups_info.speed_duplex = NWAY_10M_FULL;
6080 }
6081
6082 if (advertising & RTL_ADVERTISED_100_HALF) {
6083 new1 |= ADVERTISE_100HALF;
6084 tp->ups_info.speed_duplex = NWAY_100M_HALF;
6085 }
6086 if (advertising & RTL_ADVERTISED_100_FULL) {
6087 new1 |= ADVERTISE_100FULL;
6088 tp->ups_info.speed_duplex = NWAY_100M_FULL;
6089 }
6090
6091 if (orig != new1) {
6092 r8152_mdio_write(tp, MII_ADVERTISE, new1);
6093 tp->mii.advertising = new1;
6094 }
6095
6096 if (tp->mii.supports_gmii) {
6097 orig = r8152_mdio_read(tp, MII_CTRL1000);
6098 new1 = orig & ~(ADVERTISE_1000FULL |
6099 ADVERTISE_1000HALF);
6100
6101 if (advertising & RTL_ADVERTISED_1000_FULL) {
6102 new1 |= ADVERTISE_1000FULL;
6103 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6104 }
6105
6106 if (orig != new1)
6107 r8152_mdio_write(tp, MII_CTRL1000, new1);
6108 }
6109
6110 if (tp->support_2500full) {
6111 orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
6112 new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
6113
6114 if (advertising & RTL_ADVERTISED_2500_FULL) {
6115 new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
6116 tp->ups_info.speed_duplex = NWAY_2500M_FULL;
6117 }
6118
6119 if (orig != new1)
6120 ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
6121 }
6122
6123 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
6124
6125 tp->mii.force_media = 0;
6126 }
6127
6128 if (test_and_clear_bit(PHY_RESET, &tp->flags))
6129 bmcr |= BMCR_RESET;
6130
6131 r8152_mdio_write(tp, MII_BMCR, bmcr);
6132
6133 if (bmcr & BMCR_RESET) {
6134 int i;
6135
6136 for (i = 0; i < 50; i++) {
6137 msleep(20);
6138 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
6139 break;
6140 }
6141 }
6142
6143 out:
6144 return ret;
6145 }
6146
rtl8152_up(struct r8152 * tp)6147 static void rtl8152_up(struct r8152 *tp)
6148 {
6149 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6150 return;
6151
6152 r8152_aldps_en(tp, false);
6153 r8152b_exit_oob(tp);
6154 r8152_aldps_en(tp, true);
6155 }
6156
rtl8152_down(struct r8152 * tp)6157 static void rtl8152_down(struct r8152 *tp)
6158 {
6159 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6160 rtl_drop_queued_tx(tp);
6161 return;
6162 }
6163
6164 r8152_power_cut_en(tp, false);
6165 r8152_aldps_en(tp, false);
6166 r8152b_enter_oob(tp);
6167 r8152_aldps_en(tp, true);
6168 }
6169
rtl8153_up(struct r8152 * tp)6170 static void rtl8153_up(struct r8152 *tp)
6171 {
6172 u32 ocp_data;
6173
6174 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6175 return;
6176
6177 r8153_u1u2en(tp, false);
6178 r8153_u2p3en(tp, false);
6179 r8153_aldps_en(tp, false);
6180 r8153_first_init(tp);
6181
6182 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6183 ocp_data |= LANWAKE_CLR_EN;
6184 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6185
6186 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6187 ocp_data &= ~LANWAKE_PIN;
6188 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6189
6190 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6191 ocp_data &= ~DELAY_PHY_PWR_CHG;
6192 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
6193
6194 r8153_aldps_en(tp, true);
6195
6196 switch (tp->version) {
6197 case RTL_VER_03:
6198 case RTL_VER_04:
6199 break;
6200 case RTL_VER_05:
6201 case RTL_VER_06:
6202 default:
6203 r8153_u2p3en(tp, true);
6204 break;
6205 }
6206
6207 r8153_u1u2en(tp, true);
6208 }
6209
rtl8153_down(struct r8152 * tp)6210 static void rtl8153_down(struct r8152 *tp)
6211 {
6212 u32 ocp_data;
6213
6214 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6215 rtl_drop_queued_tx(tp);
6216 return;
6217 }
6218
6219 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6220 ocp_data &= ~LANWAKE_CLR_EN;
6221 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6222
6223 r8153_u1u2en(tp, false);
6224 r8153_u2p3en(tp, false);
6225 r8153_power_cut_en(tp, false);
6226 r8153_aldps_en(tp, false);
6227 r8153_enter_oob(tp);
6228 r8153_aldps_en(tp, true);
6229 }
6230
rtl8153b_up(struct r8152 * tp)6231 static void rtl8153b_up(struct r8152 *tp)
6232 {
6233 u32 ocp_data;
6234
6235 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6236 return;
6237
6238 r8153b_u1u2en(tp, false);
6239 r8153_u2p3en(tp, false);
6240 r8153_aldps_en(tp, false);
6241
6242 r8153_first_init(tp);
6243 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6244
6245 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6246 ocp_data &= ~PLA_MCU_SPDWN_EN;
6247 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6248
6249 r8153_aldps_en(tp, true);
6250
6251 if (tp->udev->speed >= USB_SPEED_SUPER)
6252 r8153b_u1u2en(tp, true);
6253 }
6254
rtl8153b_down(struct r8152 * tp)6255 static void rtl8153b_down(struct r8152 *tp)
6256 {
6257 u32 ocp_data;
6258
6259 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6260 rtl_drop_queued_tx(tp);
6261 return;
6262 }
6263
6264 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6265 ocp_data |= PLA_MCU_SPDWN_EN;
6266 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6267
6268 r8153b_u1u2en(tp, false);
6269 r8153_u2p3en(tp, false);
6270 r8153b_power_cut_en(tp, false);
6271 r8153_aldps_en(tp, false);
6272 r8153_enter_oob(tp);
6273 r8153_aldps_en(tp, true);
6274 }
6275
rtl8153c_change_mtu(struct r8152 * tp)6276 static void rtl8153c_change_mtu(struct r8152 *tp)
6277 {
6278 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6279 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
6280
6281 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6282
6283 /* Adjust the tx fifo free credit full threshold, otherwise
6284 * the fifo would be too small to send a jumbo frame packet.
6285 */
6286 if (tp->netdev->mtu < 8000)
6287 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
6288 else
6289 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
6290 }
6291
rtl8153c_up(struct r8152 * tp)6292 static void rtl8153c_up(struct r8152 *tp)
6293 {
6294 u32 ocp_data;
6295
6296 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6297 return;
6298
6299 r8153b_u1u2en(tp, false);
6300 r8153_u2p3en(tp, false);
6301 r8153_aldps_en(tp, false);
6302
6303 rxdy_gated_en(tp, true);
6304 r8153_teredo_off(tp);
6305
6306 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6307 ocp_data &= ~RCR_ACPT_ALL;
6308 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6309
6310 rtl8152_nic_reset(tp);
6311 rtl_reset_bmu(tp);
6312
6313 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6314 ocp_data &= ~NOW_IS_OOB;
6315 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6316
6317 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6318 ocp_data &= ~MCU_BORW_EN;
6319 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6320
6321 wait_oob_link_list_ready(tp);
6322
6323 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6324 ocp_data |= RE_INIT_LL;
6325 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6326
6327 wait_oob_link_list_ready(tp);
6328
6329 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6330
6331 rtl8153c_change_mtu(tp);
6332
6333 rtl8152_nic_reset(tp);
6334
6335 /* rx share fifo credit full threshold */
6336 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
6337 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
6338 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6339 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6340
6341 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6342
6343 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6344
6345 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6346 ocp_data |= BIT(8);
6347 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
6348
6349 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6350
6351 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6352 ocp_data &= ~PLA_MCU_SPDWN_EN;
6353 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6354
6355 r8153_aldps_en(tp, true);
6356 r8153b_u1u2en(tp, true);
6357 }
6358
fc_pause_on_auto(struct r8152 * tp)6359 static inline u32 fc_pause_on_auto(struct r8152 *tp)
6360 {
6361 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
6362 }
6363
fc_pause_off_auto(struct r8152 * tp)6364 static inline u32 fc_pause_off_auto(struct r8152 *tp)
6365 {
6366 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
6367 }
6368
r8156_fc_parameter(struct r8152 * tp)6369 static void r8156_fc_parameter(struct r8152 *tp)
6370 {
6371 u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
6372 u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
6373
6374 switch (tp->version) {
6375 case RTL_VER_10:
6376 case RTL_VER_11:
6377 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 8);
6378 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 8);
6379 break;
6380 case RTL_VER_12:
6381 case RTL_VER_13:
6382 case RTL_VER_15:
6383 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
6384 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
6385 break;
6386 default:
6387 break;
6388 }
6389 }
6390
rtl8156_change_mtu(struct r8152 * tp)6391 static void rtl8156_change_mtu(struct r8152 *tp)
6392 {
6393 u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
6394
6395 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
6396 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6397 r8156_fc_parameter(tp);
6398
6399 /* TX share fifo free credit full threshold */
6400 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6401 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
6402 ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
6403 }
6404
rtl8156_up(struct r8152 * tp)6405 static void rtl8156_up(struct r8152 *tp)
6406 {
6407 u32 ocp_data;
6408
6409 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6410 return;
6411
6412 r8153b_u1u2en(tp, false);
6413 r8153_u2p3en(tp, false);
6414 r8153_aldps_en(tp, false);
6415
6416 rxdy_gated_en(tp, true);
6417 r8153_teredo_off(tp);
6418
6419 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6420 ocp_data &= ~RCR_ACPT_ALL;
6421 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6422
6423 rtl8152_nic_reset(tp);
6424 rtl_reset_bmu(tp);
6425
6426 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6427 ocp_data &= ~NOW_IS_OOB;
6428 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6429
6430 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6431 ocp_data &= ~MCU_BORW_EN;
6432 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6433
6434 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6435
6436 rtl8156_change_mtu(tp);
6437
6438 switch (tp->version) {
6439 case RTL_TEST_01:
6440 case RTL_VER_10:
6441 case RTL_VER_11:
6442 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6443 ocp_data |= ACT_ODMA;
6444 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
6445 break;
6446 default:
6447 break;
6448 }
6449
6450 /* share FIFO settings */
6451 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6452 ocp_data &= ~RXFIFO_FULL_MASK;
6453 ocp_data |= 0x08;
6454 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
6455
6456 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6457 ocp_data &= ~PLA_MCU_SPDWN_EN;
6458 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6459
6460 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6461 ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6462 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
6463
6464 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
6465
6466 if (tp->saved_wolopts != __rtl_get_wol(tp)) {
6467 netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
6468 __rtl_set_wol(tp, tp->saved_wolopts);
6469 }
6470
6471 r8153_aldps_en(tp, true);
6472 r8153_u2p3en(tp, true);
6473
6474 if (tp->udev->speed >= USB_SPEED_SUPER)
6475 r8153b_u1u2en(tp, true);
6476 }
6477
rtl8156_down(struct r8152 * tp)6478 static void rtl8156_down(struct r8152 *tp)
6479 {
6480 u32 ocp_data;
6481
6482 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6483 rtl_drop_queued_tx(tp);
6484 return;
6485 }
6486
6487 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6488 ocp_data |= PLA_MCU_SPDWN_EN;
6489 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6490
6491 r8153b_u1u2en(tp, false);
6492 r8153_u2p3en(tp, false);
6493 r8153b_power_cut_en(tp, false);
6494 r8153_aldps_en(tp, false);
6495
6496 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6497 ocp_data &= ~NOW_IS_OOB;
6498 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6499
6500 rtl_disable(tp);
6501 rtl_reset_bmu(tp);
6502
6503 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
6504 * type. Set it to zero. bits[7:0] are the W1C bits about
6505 * the events. Set them to all 1 to clear them.
6506 */
6507 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6508
6509 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6510 ocp_data |= NOW_IS_OOB;
6511 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6512
6513 rtl_rx_vlan_en(tp, true);
6514 rxdy_gated_en(tp, false);
6515
6516 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6517 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6518 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6519
6520 r8153_aldps_en(tp, true);
6521 }
6522
rtl8152_in_nway(struct r8152 * tp)6523 static bool rtl8152_in_nway(struct r8152 *tp)
6524 {
6525 u16 nway_state;
6526
6527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
6528 tp->ocp_base = 0x2000;
6529 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
6530 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
6531
6532 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6533 if (nway_state & 0xc000)
6534 return false;
6535 else
6536 return true;
6537 }
6538
rtl8153_in_nway(struct r8152 * tp)6539 static bool rtl8153_in_nway(struct r8152 *tp)
6540 {
6541 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
6542
6543 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
6544 return false;
6545 else
6546 return true;
6547 }
6548
set_carrier(struct r8152 * tp)6549 static void set_carrier(struct r8152 *tp)
6550 {
6551 struct net_device *netdev = tp->netdev;
6552 struct napi_struct *napi = &tp->napi;
6553 u16 speed;
6554
6555 speed = rtl8152_get_speed(tp);
6556
6557 if (speed & LINK_STATUS) {
6558 if (!netif_carrier_ok(netdev)) {
6559 tp->rtl_ops.enable(tp);
6560 netif_stop_queue(netdev);
6561 napi_disable(napi);
6562 netif_carrier_on(netdev);
6563 rtl_start_rx(tp);
6564 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6565 _rtl8152_set_rx_mode(netdev);
6566 napi_enable(napi);
6567 netif_wake_queue(netdev);
6568 netif_info(tp, link, netdev, "carrier on\n");
6569 } else if (netif_queue_stopped(netdev) &&
6570 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
6571 netif_wake_queue(netdev);
6572 }
6573 } else {
6574 if (netif_carrier_ok(netdev)) {
6575 netif_carrier_off(netdev);
6576 tasklet_disable(&tp->tx_tl);
6577 napi_disable(napi);
6578 tp->rtl_ops.disable(tp);
6579 napi_enable(napi);
6580 tasklet_enable(&tp->tx_tl);
6581 netif_info(tp, link, netdev, "carrier off\n");
6582 }
6583 }
6584 }
6585
rtl_work_func_t(struct work_struct * work)6586 static void rtl_work_func_t(struct work_struct *work)
6587 {
6588 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
6589
6590 /* If the device is unplugged or !netif_running(), the workqueue
6591 * doesn't need to wake the device, and could return directly.
6592 */
6593 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
6594 return;
6595
6596 if (usb_autopm_get_interface(tp->intf) < 0)
6597 return;
6598
6599 if (!test_bit(WORK_ENABLE, &tp->flags))
6600 goto out1;
6601
6602 if (!mutex_trylock(&tp->control)) {
6603 schedule_delayed_work(&tp->schedule, 0);
6604 goto out1;
6605 }
6606
6607 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
6608 set_carrier(tp);
6609
6610 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
6611 _rtl8152_set_rx_mode(tp->netdev);
6612
6613 /* don't schedule tasket before linking */
6614 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
6615 netif_carrier_ok(tp->netdev))
6616 tasklet_schedule(&tp->tx_tl);
6617
6618 mutex_unlock(&tp->control);
6619
6620 out1:
6621 usb_autopm_put_interface(tp->intf);
6622 }
6623
rtl_hw_phy_work_func_t(struct work_struct * work)6624 static void rtl_hw_phy_work_func_t(struct work_struct *work)
6625 {
6626 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
6627
6628 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6629 return;
6630
6631 if (usb_autopm_get_interface(tp->intf) < 0)
6632 return;
6633
6634 mutex_lock(&tp->control);
6635
6636 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
6637 tp->rtl_fw.retry = false;
6638 tp->rtl_fw.fw = NULL;
6639
6640 /* Delay execution in case request_firmware() is not ready yet.
6641 */
6642 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
6643 goto ignore_once;
6644 }
6645
6646 tp->rtl_ops.hw_phy_cfg(tp);
6647
6648 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
6649 tp->advertising);
6650
6651 ignore_once:
6652 mutex_unlock(&tp->control);
6653
6654 usb_autopm_put_interface(tp->intf);
6655 }
6656
6657 #ifdef CONFIG_PM_SLEEP
rtl_notifier(struct notifier_block * nb,unsigned long action,void * data)6658 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
6659 void *data)
6660 {
6661 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
6662
6663 switch (action) {
6664 case PM_HIBERNATION_PREPARE:
6665 case PM_SUSPEND_PREPARE:
6666 usb_autopm_get_interface(tp->intf);
6667 break;
6668
6669 case PM_POST_HIBERNATION:
6670 case PM_POST_SUSPEND:
6671 usb_autopm_put_interface(tp->intf);
6672 break;
6673
6674 case PM_POST_RESTORE:
6675 case PM_RESTORE_PREPARE:
6676 default:
6677 break;
6678 }
6679
6680 return NOTIFY_DONE;
6681 }
6682 #endif
6683
rtl8152_open(struct net_device * netdev)6684 static int rtl8152_open(struct net_device *netdev)
6685 {
6686 struct r8152 *tp = netdev_priv(netdev);
6687 int res = 0;
6688
6689 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
6690 cancel_delayed_work_sync(&tp->hw_phy_work);
6691 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
6692 }
6693
6694 res = alloc_all_mem(tp);
6695 if (res)
6696 goto out;
6697
6698 res = usb_autopm_get_interface(tp->intf);
6699 if (res < 0)
6700 goto out_free;
6701
6702 mutex_lock(&tp->control);
6703
6704 tp->rtl_ops.up(tp);
6705
6706 netif_carrier_off(netdev);
6707 netif_start_queue(netdev);
6708 set_bit(WORK_ENABLE, &tp->flags);
6709
6710 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
6711 if (res) {
6712 if (res == -ENODEV)
6713 netif_device_detach(tp->netdev);
6714 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
6715 res);
6716 goto out_unlock;
6717 }
6718 napi_enable(&tp->napi);
6719 tasklet_enable(&tp->tx_tl);
6720
6721 mutex_unlock(&tp->control);
6722
6723 usb_autopm_put_interface(tp->intf);
6724 #ifdef CONFIG_PM_SLEEP
6725 tp->pm_notifier.notifier_call = rtl_notifier;
6726 register_pm_notifier(&tp->pm_notifier);
6727 #endif
6728 return 0;
6729
6730 out_unlock:
6731 mutex_unlock(&tp->control);
6732 usb_autopm_put_interface(tp->intf);
6733 out_free:
6734 free_all_mem(tp);
6735 out:
6736 return res;
6737 }
6738
rtl8152_close(struct net_device * netdev)6739 static int rtl8152_close(struct net_device *netdev)
6740 {
6741 struct r8152 *tp = netdev_priv(netdev);
6742 int res = 0;
6743
6744 #ifdef CONFIG_PM_SLEEP
6745 unregister_pm_notifier(&tp->pm_notifier);
6746 #endif
6747 tasklet_disable(&tp->tx_tl);
6748 clear_bit(WORK_ENABLE, &tp->flags);
6749 usb_kill_urb(tp->intr_urb);
6750 cancel_delayed_work_sync(&tp->schedule);
6751 napi_disable(&tp->napi);
6752 netif_stop_queue(netdev);
6753
6754 res = usb_autopm_get_interface(tp->intf);
6755 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
6756 rtl_drop_queued_tx(tp);
6757 rtl_stop_rx(tp);
6758 } else {
6759 mutex_lock(&tp->control);
6760
6761 tp->rtl_ops.down(tp);
6762
6763 mutex_unlock(&tp->control);
6764
6765 usb_autopm_put_interface(tp->intf);
6766 }
6767
6768 free_all_mem(tp);
6769
6770 return res;
6771 }
6772
rtl_tally_reset(struct r8152 * tp)6773 static void rtl_tally_reset(struct r8152 *tp)
6774 {
6775 u32 ocp_data;
6776
6777 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
6778 ocp_data |= TALLY_RESET;
6779 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
6780 }
6781
r8152b_init(struct r8152 * tp)6782 static void r8152b_init(struct r8152 *tp)
6783 {
6784 u32 ocp_data;
6785 u16 data;
6786
6787 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6788 return;
6789
6790 data = r8152_mdio_read(tp, MII_BMCR);
6791 if (data & BMCR_PDOWN) {
6792 data &= ~BMCR_PDOWN;
6793 r8152_mdio_write(tp, MII_BMCR, data);
6794 }
6795
6796 r8152_aldps_en(tp, false);
6797
6798 if (tp->version == RTL_VER_01) {
6799 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6800 ocp_data &= ~LED_MODE_MASK;
6801 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
6802 }
6803
6804 r8152_power_cut_en(tp, false);
6805
6806 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
6807 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
6808 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
6809 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
6810 ocp_data &= ~MCU_CLK_RATIO_MASK;
6811 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
6812 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
6813 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
6814 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
6815 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
6816
6817 rtl_tally_reset(tp);
6818
6819 /* enable rx aggregation */
6820 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
6821 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
6822 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
6823 }
6824
r8153_init(struct r8152 * tp)6825 static void r8153_init(struct r8152 *tp)
6826 {
6827 u32 ocp_data;
6828 u16 data;
6829 int i;
6830
6831 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6832 return;
6833
6834 r8153_u1u2en(tp, false);
6835
6836 for (i = 0; i < 500; i++) {
6837 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
6838 AUTOLOAD_DONE)
6839 break;
6840
6841 msleep(20);
6842 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6843 break;
6844 }
6845
6846 data = r8153_phy_status(tp, 0);
6847
6848 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
6849 tp->version == RTL_VER_05)
6850 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
6851
6852 data = r8152_mdio_read(tp, MII_BMCR);
6853 if (data & BMCR_PDOWN) {
6854 data &= ~BMCR_PDOWN;
6855 r8152_mdio_write(tp, MII_BMCR, data);
6856 }
6857
6858 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
6859
6860 r8153_u2p3en(tp, false);
6861
6862 if (tp->version == RTL_VER_04) {
6863 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
6864 ocp_data &= ~pwd_dn_scale_mask;
6865 ocp_data |= pwd_dn_scale(96);
6866 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
6867
6868 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
6869 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
6870 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
6871 } else if (tp->version == RTL_VER_05) {
6872 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
6873 ocp_data &= ~ECM_ALDPS;
6874 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
6875
6876 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6877 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6878 ocp_data &= ~DYNAMIC_BURST;
6879 else
6880 ocp_data |= DYNAMIC_BURST;
6881 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6882 } else if (tp->version == RTL_VER_06) {
6883 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6884 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6885 ocp_data &= ~DYNAMIC_BURST;
6886 else
6887 ocp_data |= DYNAMIC_BURST;
6888 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6889
6890 r8153_queue_wake(tp, false);
6891
6892 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
6893 if (rtl8152_get_speed(tp) & LINK_STATUS)
6894 ocp_data |= CUR_LINK_OK;
6895 else
6896 ocp_data &= ~CUR_LINK_OK;
6897 ocp_data |= POLL_LINK_CHG;
6898 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
6899 }
6900
6901 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
6902 ocp_data |= EP4_FULL_FC;
6903 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
6904
6905 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
6906 ocp_data &= ~TIMER11_EN;
6907 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
6908
6909 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6910 ocp_data &= ~LED_MODE_MASK;
6911 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
6912
6913 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
6914 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
6915 ocp_data |= LPM_TIMER_500MS;
6916 else
6917 ocp_data |= LPM_TIMER_500US;
6918 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
6919
6920 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
6921 ocp_data &= ~SEN_VAL_MASK;
6922 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
6923 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
6924
6925 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
6926
6927 r8153_power_cut_en(tp, false);
6928 rtl_runtime_suspend_enable(tp, false);
6929 r8153_mac_clk_speed_down(tp, false);
6930 r8153_u1u2en(tp, true);
6931 usb_enable_lpm(tp->udev);
6932
6933 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6934 ocp_data |= LANWAKE_CLR_EN;
6935 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6936
6937 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6938 ocp_data &= ~LANWAKE_PIN;
6939 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6940
6941 /* rx aggregation */
6942 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
6943 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
6944 if (tp->dell_tb_rx_agg_bug)
6945 ocp_data |= RX_AGG_DISABLE;
6946
6947 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
6948
6949 rtl_tally_reset(tp);
6950
6951 switch (tp->udev->speed) {
6952 case USB_SPEED_SUPER:
6953 case USB_SPEED_SUPER_PLUS:
6954 tp->coalesce = COALESCE_SUPER;
6955 break;
6956 case USB_SPEED_HIGH:
6957 tp->coalesce = COALESCE_HIGH;
6958 break;
6959 default:
6960 tp->coalesce = COALESCE_SLOW;
6961 break;
6962 }
6963 }
6964
r8153b_init(struct r8152 * tp)6965 static void r8153b_init(struct r8152 *tp)
6966 {
6967 u32 ocp_data;
6968 u16 data;
6969 int i;
6970
6971 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6972 return;
6973
6974 r8153b_u1u2en(tp, false);
6975
6976 for (i = 0; i < 500; i++) {
6977 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
6978 AUTOLOAD_DONE)
6979 break;
6980
6981 msleep(20);
6982 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6983 break;
6984 }
6985
6986 data = r8153_phy_status(tp, 0);
6987
6988 data = r8152_mdio_read(tp, MII_BMCR);
6989 if (data & BMCR_PDOWN) {
6990 data &= ~BMCR_PDOWN;
6991 r8152_mdio_write(tp, MII_BMCR, data);
6992 }
6993
6994 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
6995
6996 r8153_u2p3en(tp, false);
6997
6998 /* MSC timer = 0xfff * 8ms = 32760 ms */
6999 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7000
7001 r8153b_power_cut_en(tp, false);
7002 r8153b_ups_en(tp, false);
7003 r8153_queue_wake(tp, false);
7004 rtl_runtime_suspend_enable(tp, false);
7005
7006 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7007 if (rtl8152_get_speed(tp) & LINK_STATUS)
7008 ocp_data |= CUR_LINK_OK;
7009 else
7010 ocp_data &= ~CUR_LINK_OK;
7011 ocp_data |= POLL_LINK_CHG;
7012 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7013
7014 if (tp->udev->speed >= USB_SPEED_SUPER)
7015 r8153b_u1u2en(tp, true);
7016
7017 usb_enable_lpm(tp->udev);
7018
7019 /* MAC clock speed down */
7020 r8153_mac_clk_speed_down(tp, true);
7021
7022 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7023 ocp_data &= ~PLA_MCU_SPDWN_EN;
7024 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7025
7026 if (tp->version == RTL_VER_09) {
7027 /* Disable Test IO for 32QFN */
7028 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
7029 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7030 ocp_data |= TEST_IO_OFF;
7031 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7032 }
7033 }
7034
7035 set_bit(GREEN_ETHERNET, &tp->flags);
7036
7037 /* rx aggregation */
7038 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7039 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7040 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7041
7042 rtl_tally_reset(tp);
7043
7044 tp->coalesce = 15000; /* 15 us */
7045 }
7046
r8153c_init(struct r8152 * tp)7047 static void r8153c_init(struct r8152 *tp)
7048 {
7049 u32 ocp_data;
7050 u16 data;
7051 int i;
7052
7053 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7054 return;
7055
7056 r8153b_u1u2en(tp, false);
7057
7058 /* Disable spi_en */
7059 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7060 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7061 ocp_data &= ~BIT(3);
7062 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
7063 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
7064 ocp_data |= BIT(1);
7065 ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
7066
7067 for (i = 0; i < 500; i++) {
7068 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7069 AUTOLOAD_DONE)
7070 break;
7071
7072 msleep(20);
7073 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7074 return;
7075 }
7076
7077 data = r8153_phy_status(tp, 0);
7078
7079 data = r8152_mdio_read(tp, MII_BMCR);
7080 if (data & BMCR_PDOWN) {
7081 data &= ~BMCR_PDOWN;
7082 r8152_mdio_write(tp, MII_BMCR, data);
7083 }
7084
7085 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7086
7087 r8153_u2p3en(tp, false);
7088
7089 /* MSC timer = 0xfff * 8ms = 32760 ms */
7090 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7091
7092 r8153b_power_cut_en(tp, false);
7093 r8153c_ups_en(tp, false);
7094 r8153_queue_wake(tp, false);
7095 rtl_runtime_suspend_enable(tp, false);
7096
7097 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7098 if (rtl8152_get_speed(tp) & LINK_STATUS)
7099 ocp_data |= CUR_LINK_OK;
7100 else
7101 ocp_data &= ~CUR_LINK_OK;
7102
7103 ocp_data |= POLL_LINK_CHG;
7104 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7105
7106 r8153b_u1u2en(tp, true);
7107
7108 usb_enable_lpm(tp->udev);
7109
7110 /* MAC clock speed down */
7111 r8153_mac_clk_speed_down(tp, true);
7112
7113 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7114 ocp_data &= ~BIT(7);
7115 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
7116
7117 set_bit(GREEN_ETHERNET, &tp->flags);
7118
7119 /* rx aggregation */
7120 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7121 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7122 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7123
7124 rtl_tally_reset(tp);
7125
7126 tp->coalesce = 15000; /* 15 us */
7127 }
7128
r8156_hw_phy_cfg(struct r8152 * tp)7129 static void r8156_hw_phy_cfg(struct r8152 *tp)
7130 {
7131 u32 ocp_data;
7132 u16 data;
7133
7134 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7135 if (ocp_data & PCUT_STATUS) {
7136 ocp_data &= ~PCUT_STATUS;
7137 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7138 }
7139
7140 data = r8153_phy_status(tp, 0);
7141 switch (data) {
7142 case PHY_STAT_EXT_INIT:
7143 rtl8152_apply_firmware(tp, true);
7144
7145 data = ocp_reg_read(tp, 0xa468);
7146 data &= ~(BIT(3) | BIT(1));
7147 ocp_reg_write(tp, 0xa468, data);
7148 break;
7149 case PHY_STAT_LAN_ON:
7150 case PHY_STAT_PWRDN:
7151 default:
7152 rtl8152_apply_firmware(tp, false);
7153 break;
7154 }
7155
7156 /* disable ALDPS before updating the PHY parameters */
7157 r8153_aldps_en(tp, false);
7158
7159 /* disable EEE before updating the PHY parameters */
7160 rtl_eee_enable(tp, false);
7161
7162 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7163 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7164
7165 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7166 ocp_data |= PFM_PWM_SWITCH;
7167 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7168
7169 switch (tp->version) {
7170 case RTL_VER_10:
7171 data = ocp_reg_read(tp, 0xad40);
7172 data &= ~0x3ff;
7173 data |= BIT(7) | BIT(2);
7174 ocp_reg_write(tp, 0xad40, data);
7175
7176 data = ocp_reg_read(tp, 0xad4e);
7177 data |= BIT(4);
7178 ocp_reg_write(tp, 0xad4e, data);
7179 data = ocp_reg_read(tp, 0xad16);
7180 data &= ~0x3ff;
7181 data |= 0x6;
7182 ocp_reg_write(tp, 0xad16, data);
7183 data = ocp_reg_read(tp, 0xad32);
7184 data &= ~0x3f;
7185 data |= 6;
7186 ocp_reg_write(tp, 0xad32, data);
7187 data = ocp_reg_read(tp, 0xac08);
7188 data &= ~(BIT(12) | BIT(8));
7189 ocp_reg_write(tp, 0xac08, data);
7190 data = ocp_reg_read(tp, 0xac8a);
7191 data |= BIT(12) | BIT(13) | BIT(14);
7192 data &= ~BIT(15);
7193 ocp_reg_write(tp, 0xac8a, data);
7194 data = ocp_reg_read(tp, 0xad18);
7195 data |= BIT(10);
7196 ocp_reg_write(tp, 0xad18, data);
7197 data = ocp_reg_read(tp, 0xad1a);
7198 data |= 0x3ff;
7199 ocp_reg_write(tp, 0xad1a, data);
7200 data = ocp_reg_read(tp, 0xad1c);
7201 data |= 0x3ff;
7202 ocp_reg_write(tp, 0xad1c, data);
7203
7204 data = sram_read(tp, 0x80ea);
7205 data &= ~0xff00;
7206 data |= 0xc400;
7207 sram_write(tp, 0x80ea, data);
7208 data = sram_read(tp, 0x80eb);
7209 data &= ~0x0700;
7210 data |= 0x0300;
7211 sram_write(tp, 0x80eb, data);
7212 data = sram_read(tp, 0x80f8);
7213 data &= ~0xff00;
7214 data |= 0x1c00;
7215 sram_write(tp, 0x80f8, data);
7216 data = sram_read(tp, 0x80f1);
7217 data &= ~0xff00;
7218 data |= 0x3000;
7219 sram_write(tp, 0x80f1, data);
7220
7221 data = sram_read(tp, 0x80fe);
7222 data &= ~0xff00;
7223 data |= 0xa500;
7224 sram_write(tp, 0x80fe, data);
7225 data = sram_read(tp, 0x8102);
7226 data &= ~0xff00;
7227 data |= 0x5000;
7228 sram_write(tp, 0x8102, data);
7229 data = sram_read(tp, 0x8015);
7230 data &= ~0xff00;
7231 data |= 0x3300;
7232 sram_write(tp, 0x8015, data);
7233 data = sram_read(tp, 0x8100);
7234 data &= ~0xff00;
7235 data |= 0x7000;
7236 sram_write(tp, 0x8100, data);
7237 data = sram_read(tp, 0x8014);
7238 data &= ~0xff00;
7239 data |= 0xf000;
7240 sram_write(tp, 0x8014, data);
7241 data = sram_read(tp, 0x8016);
7242 data &= ~0xff00;
7243 data |= 0x6500;
7244 sram_write(tp, 0x8016, data);
7245 data = sram_read(tp, 0x80dc);
7246 data &= ~0xff00;
7247 data |= 0xed00;
7248 sram_write(tp, 0x80dc, data);
7249 data = sram_read(tp, 0x80df);
7250 data |= BIT(8);
7251 sram_write(tp, 0x80df, data);
7252 data = sram_read(tp, 0x80e1);
7253 data &= ~BIT(8);
7254 sram_write(tp, 0x80e1, data);
7255
7256 data = ocp_reg_read(tp, 0xbf06);
7257 data &= ~0x003f;
7258 data |= 0x0038;
7259 ocp_reg_write(tp, 0xbf06, data);
7260
7261 sram_write(tp, 0x819f, 0xddb6);
7262
7263 ocp_reg_write(tp, 0xbc34, 0x5555);
7264 data = ocp_reg_read(tp, 0xbf0a);
7265 data &= ~0x0e00;
7266 data |= 0x0a00;
7267 ocp_reg_write(tp, 0xbf0a, data);
7268
7269 data = ocp_reg_read(tp, 0xbd2c);
7270 data &= ~BIT(13);
7271 ocp_reg_write(tp, 0xbd2c, data);
7272 break;
7273 case RTL_VER_11:
7274 data = ocp_reg_read(tp, 0xad16);
7275 data |= 0x3ff;
7276 ocp_reg_write(tp, 0xad16, data);
7277 data = ocp_reg_read(tp, 0xad32);
7278 data &= ~0x3f;
7279 data |= 6;
7280 ocp_reg_write(tp, 0xad32, data);
7281 data = ocp_reg_read(tp, 0xac08);
7282 data &= ~(BIT(12) | BIT(8));
7283 ocp_reg_write(tp, 0xac08, data);
7284 data = ocp_reg_read(tp, 0xacc0);
7285 data &= ~0x3;
7286 data |= BIT(1);
7287 ocp_reg_write(tp, 0xacc0, data);
7288 data = ocp_reg_read(tp, 0xad40);
7289 data &= ~0xe7;
7290 data |= BIT(6) | BIT(2);
7291 ocp_reg_write(tp, 0xad40, data);
7292 data = ocp_reg_read(tp, 0xac14);
7293 data &= ~BIT(7);
7294 ocp_reg_write(tp, 0xac14, data);
7295 data = ocp_reg_read(tp, 0xac80);
7296 data &= ~(BIT(8) | BIT(9));
7297 ocp_reg_write(tp, 0xac80, data);
7298 data = ocp_reg_read(tp, 0xac5e);
7299 data &= ~0x7;
7300 data |= BIT(1);
7301 ocp_reg_write(tp, 0xac5e, data);
7302 ocp_reg_write(tp, 0xad4c, 0x00a8);
7303 ocp_reg_write(tp, 0xac5c, 0x01ff);
7304 data = ocp_reg_read(tp, 0xac8a);
7305 data &= ~0xf0;
7306 data |= BIT(4) | BIT(5);
7307 ocp_reg_write(tp, 0xac8a, data);
7308 ocp_reg_write(tp, 0xb87c, 0x8157);
7309 data = ocp_reg_read(tp, 0xb87e);
7310 data &= ~0xff00;
7311 data |= 0x0500;
7312 ocp_reg_write(tp, 0xb87e, data);
7313 ocp_reg_write(tp, 0xb87c, 0x8159);
7314 data = ocp_reg_read(tp, 0xb87e);
7315 data &= ~0xff00;
7316 data |= 0x0700;
7317 ocp_reg_write(tp, 0xb87e, data);
7318
7319 /* AAGC */
7320 ocp_reg_write(tp, 0xb87c, 0x80a2);
7321 ocp_reg_write(tp, 0xb87e, 0x0153);
7322 ocp_reg_write(tp, 0xb87c, 0x809c);
7323 ocp_reg_write(tp, 0xb87e, 0x0153);
7324
7325 /* EEE parameter */
7326 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
7327
7328 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7329 ocp_data |= EN_XG_LIP | EN_G_LIP;
7330 ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7331
7332 sram_write(tp, 0x8257, 0x020f); /* XG PLL */
7333 sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
7334
7335 if (rtl_phy_patch_request(tp, true, true))
7336 return;
7337
7338 /* Advance EEE */
7339 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7340 ocp_data |= EEE_SPDWN_EN;
7341 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7342
7343 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7344 data &= ~(EN_EEE_100 | EN_EEE_1000);
7345 data |= EN_10M_CLKDIV;
7346 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7347 tp->ups_info._10m_ckdiv = true;
7348 tp->ups_info.eee_plloff_100 = false;
7349 tp->ups_info.eee_plloff_giga = false;
7350
7351 data = ocp_reg_read(tp, OCP_POWER_CFG);
7352 data &= ~EEE_CLKDIV_EN;
7353 ocp_reg_write(tp, OCP_POWER_CFG, data);
7354 tp->ups_info.eee_ckdiv = false;
7355
7356 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
7357 ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
7358 tp->ups_info._250m_ckdiv = false;
7359
7360 rtl_phy_patch_request(tp, false, true);
7361
7362 /* enable ADC Ibias Cal */
7363 data = ocp_reg_read(tp, 0xd068);
7364 data |= BIT(13);
7365 ocp_reg_write(tp, 0xd068, data);
7366
7367 /* enable Thermal Sensor */
7368 data = sram_read(tp, 0x81a2);
7369 data &= ~BIT(8);
7370 sram_write(tp, 0x81a2, data);
7371 data = ocp_reg_read(tp, 0xb54c);
7372 data &= ~0xff00;
7373 data |= 0xdb00;
7374 ocp_reg_write(tp, 0xb54c, data);
7375
7376 /* Nway 2.5G Lite */
7377 data = ocp_reg_read(tp, 0xa454);
7378 data &= ~BIT(0);
7379 ocp_reg_write(tp, 0xa454, data);
7380
7381 /* CS DSP solution */
7382 data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7383 data |= RTL_ADV2_5G_F_R;
7384 ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7385 data = ocp_reg_read(tp, 0xad4e);
7386 data &= ~BIT(4);
7387 ocp_reg_write(tp, 0xad4e, data);
7388 data = ocp_reg_read(tp, 0xa86a);
7389 data &= ~BIT(0);
7390 ocp_reg_write(tp, 0xa86a, data);
7391
7392 /* MDI SWAP */
7393 if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
7394 (ocp_reg_read(tp, 0xd068) & BIT(1))) {
7395 u16 swap_a, swap_b;
7396
7397 data = ocp_reg_read(tp, 0xd068);
7398 data &= ~0x1f;
7399 data |= 0x1; /* p0 */
7400 ocp_reg_write(tp, 0xd068, data);
7401 swap_a = ocp_reg_read(tp, 0xd06a);
7402 data &= ~0x18;
7403 data |= 0x18; /* p3 */
7404 ocp_reg_write(tp, 0xd068, data);
7405 swap_b = ocp_reg_read(tp, 0xd06a);
7406 data &= ~0x18; /* p0 */
7407 ocp_reg_write(tp, 0xd068, data);
7408 ocp_reg_write(tp, 0xd06a,
7409 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7410 data |= 0x18; /* p3 */
7411 ocp_reg_write(tp, 0xd068, data);
7412 ocp_reg_write(tp, 0xd06a,
7413 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7414 data &= ~0x18;
7415 data |= 0x08; /* p1 */
7416 ocp_reg_write(tp, 0xd068, data);
7417 swap_a = ocp_reg_read(tp, 0xd06a);
7418 data &= ~0x18;
7419 data |= 0x10; /* p2 */
7420 ocp_reg_write(tp, 0xd068, data);
7421 swap_b = ocp_reg_read(tp, 0xd06a);
7422 data &= ~0x18;
7423 data |= 0x08; /* p1 */
7424 ocp_reg_write(tp, 0xd068, data);
7425 ocp_reg_write(tp, 0xd06a,
7426 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7427 data &= ~0x18;
7428 data |= 0x10; /* p2 */
7429 ocp_reg_write(tp, 0xd068, data);
7430 ocp_reg_write(tp, 0xd06a,
7431 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7432 swap_a = ocp_reg_read(tp, 0xbd5a);
7433 swap_b = ocp_reg_read(tp, 0xbd5c);
7434 ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
7435 ((swap_b & 0x1f) << 8) |
7436 ((swap_b >> 8) & 0x1f));
7437 ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
7438 ((swap_a & 0x1f) << 8) |
7439 ((swap_a >> 8) & 0x1f));
7440 swap_a = ocp_reg_read(tp, 0xbc18);
7441 swap_b = ocp_reg_read(tp, 0xbc1a);
7442 ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
7443 ((swap_b & 0x1f) << 8) |
7444 ((swap_b >> 8) & 0x1f));
7445 ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
7446 ((swap_a & 0x1f) << 8) |
7447 ((swap_a >> 8) & 0x1f));
7448 }
7449 break;
7450 default:
7451 break;
7452 }
7453
7454 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7455
7456 data = ocp_reg_read(tp, 0xa428);
7457 data &= ~BIT(9);
7458 ocp_reg_write(tp, 0xa428, data);
7459 data = ocp_reg_read(tp, 0xa5ea);
7460 data &= ~BIT(0);
7461 ocp_reg_write(tp, 0xa5ea, data);
7462 tp->ups_info.lite_mode = 0;
7463
7464 if (tp->eee_en)
7465 rtl_eee_enable(tp, true);
7466
7467 r8153_aldps_en(tp, true);
7468 r8152b_enable_fc(tp);
7469 r8153_u2p3en(tp, true);
7470
7471 set_bit(PHY_RESET, &tp->flags);
7472 }
7473
r8156b_hw_phy_cfg(struct r8152 * tp)7474 static void r8156b_hw_phy_cfg(struct r8152 *tp)
7475 {
7476 u32 ocp_data;
7477 u16 data;
7478
7479 switch (tp->version) {
7480 case RTL_VER_12:
7481 ocp_reg_write(tp, 0xbf86, 0x9000);
7482 data = ocp_reg_read(tp, 0xc402);
7483 data |= BIT(10);
7484 ocp_reg_write(tp, 0xc402, data);
7485 data &= ~BIT(10);
7486 ocp_reg_write(tp, 0xc402, data);
7487 ocp_reg_write(tp, 0xbd86, 0x1010);
7488 ocp_reg_write(tp, 0xbd88, 0x1010);
7489 data = ocp_reg_read(tp, 0xbd4e);
7490 data &= ~(BIT(10) | BIT(11));
7491 data |= BIT(11);
7492 ocp_reg_write(tp, 0xbd4e, data);
7493 data = ocp_reg_read(tp, 0xbf46);
7494 data &= ~0xf00;
7495 data |= 0x700;
7496 ocp_reg_write(tp, 0xbf46, data);
7497 break;
7498 case RTL_VER_13:
7499 case RTL_VER_15:
7500 r8156b_wait_loading_flash(tp);
7501 break;
7502 default:
7503 break;
7504 }
7505
7506 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7507 if (ocp_data & PCUT_STATUS) {
7508 ocp_data &= ~PCUT_STATUS;
7509 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7510 }
7511
7512 data = r8153_phy_status(tp, 0);
7513 switch (data) {
7514 case PHY_STAT_EXT_INIT:
7515 rtl8152_apply_firmware(tp, true);
7516
7517 data = ocp_reg_read(tp, 0xa466);
7518 data &= ~BIT(0);
7519 ocp_reg_write(tp, 0xa466, data);
7520
7521 data = ocp_reg_read(tp, 0xa468);
7522 data &= ~(BIT(3) | BIT(1));
7523 ocp_reg_write(tp, 0xa468, data);
7524 break;
7525 case PHY_STAT_LAN_ON:
7526 case PHY_STAT_PWRDN:
7527 default:
7528 rtl8152_apply_firmware(tp, false);
7529 break;
7530 }
7531
7532 data = r8152_mdio_read(tp, MII_BMCR);
7533 if (data & BMCR_PDOWN) {
7534 data &= ~BMCR_PDOWN;
7535 r8152_mdio_write(tp, MII_BMCR, data);
7536 }
7537
7538 /* disable ALDPS before updating the PHY parameters */
7539 r8153_aldps_en(tp, false);
7540
7541 /* disable EEE before updating the PHY parameters */
7542 rtl_eee_enable(tp, false);
7543
7544 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7545 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7546
7547 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7548 ocp_data |= PFM_PWM_SWITCH;
7549 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7550
7551 switch (tp->version) {
7552 case RTL_VER_12:
7553 data = ocp_reg_read(tp, 0xbc08);
7554 data |= BIT(3) | BIT(2);
7555 ocp_reg_write(tp, 0xbc08, data);
7556
7557 data = sram_read(tp, 0x8fff);
7558 data &= ~0xff00;
7559 data |= 0x0400;
7560 sram_write(tp, 0x8fff, data);
7561
7562 data = ocp_reg_read(tp, 0xacda);
7563 data |= 0xff00;
7564 ocp_reg_write(tp, 0xacda, data);
7565 data = ocp_reg_read(tp, 0xacde);
7566 data |= 0xf000;
7567 ocp_reg_write(tp, 0xacde, data);
7568 ocp_reg_write(tp, 0xac8c, 0x0ffc);
7569 ocp_reg_write(tp, 0xac46, 0xb7b4);
7570 ocp_reg_write(tp, 0xac50, 0x0fbc);
7571 ocp_reg_write(tp, 0xac3c, 0x9240);
7572 ocp_reg_write(tp, 0xac4e, 0x0db4);
7573 ocp_reg_write(tp, 0xacc6, 0x0707);
7574 ocp_reg_write(tp, 0xacc8, 0xa0d3);
7575 ocp_reg_write(tp, 0xad08, 0x0007);
7576
7577 ocp_reg_write(tp, 0xb87c, 0x8560);
7578 ocp_reg_write(tp, 0xb87e, 0x19cc);
7579 ocp_reg_write(tp, 0xb87c, 0x8562);
7580 ocp_reg_write(tp, 0xb87e, 0x19cc);
7581 ocp_reg_write(tp, 0xb87c, 0x8564);
7582 ocp_reg_write(tp, 0xb87e, 0x19cc);
7583 ocp_reg_write(tp, 0xb87c, 0x8566);
7584 ocp_reg_write(tp, 0xb87e, 0x147d);
7585 ocp_reg_write(tp, 0xb87c, 0x8568);
7586 ocp_reg_write(tp, 0xb87e, 0x147d);
7587 ocp_reg_write(tp, 0xb87c, 0x856a);
7588 ocp_reg_write(tp, 0xb87e, 0x147d);
7589 ocp_reg_write(tp, 0xb87c, 0x8ffe);
7590 ocp_reg_write(tp, 0xb87e, 0x0907);
7591 ocp_reg_write(tp, 0xb87c, 0x80d6);
7592 ocp_reg_write(tp, 0xb87e, 0x2801);
7593 ocp_reg_write(tp, 0xb87c, 0x80f2);
7594 ocp_reg_write(tp, 0xb87e, 0x2801);
7595 ocp_reg_write(tp, 0xb87c, 0x80f4);
7596 ocp_reg_write(tp, 0xb87e, 0x6077);
7597 ocp_reg_write(tp, 0xb506, 0x01e7);
7598
7599 ocp_reg_write(tp, 0xb87c, 0x8013);
7600 ocp_reg_write(tp, 0xb87e, 0x0700);
7601 ocp_reg_write(tp, 0xb87c, 0x8fb9);
7602 ocp_reg_write(tp, 0xb87e, 0x2801);
7603 ocp_reg_write(tp, 0xb87c, 0x8fba);
7604 ocp_reg_write(tp, 0xb87e, 0x0100);
7605 ocp_reg_write(tp, 0xb87c, 0x8fbc);
7606 ocp_reg_write(tp, 0xb87e, 0x1900);
7607 ocp_reg_write(tp, 0xb87c, 0x8fbe);
7608 ocp_reg_write(tp, 0xb87e, 0xe100);
7609 ocp_reg_write(tp, 0xb87c, 0x8fc0);
7610 ocp_reg_write(tp, 0xb87e, 0x0800);
7611 ocp_reg_write(tp, 0xb87c, 0x8fc2);
7612 ocp_reg_write(tp, 0xb87e, 0xe500);
7613 ocp_reg_write(tp, 0xb87c, 0x8fc4);
7614 ocp_reg_write(tp, 0xb87e, 0x0f00);
7615 ocp_reg_write(tp, 0xb87c, 0x8fc6);
7616 ocp_reg_write(tp, 0xb87e, 0xf100);
7617 ocp_reg_write(tp, 0xb87c, 0x8fc8);
7618 ocp_reg_write(tp, 0xb87e, 0x0400);
7619 ocp_reg_write(tp, 0xb87c, 0x8fca);
7620 ocp_reg_write(tp, 0xb87e, 0xf300);
7621 ocp_reg_write(tp, 0xb87c, 0x8fcc);
7622 ocp_reg_write(tp, 0xb87e, 0xfd00);
7623 ocp_reg_write(tp, 0xb87c, 0x8fce);
7624 ocp_reg_write(tp, 0xb87e, 0xff00);
7625 ocp_reg_write(tp, 0xb87c, 0x8fd0);
7626 ocp_reg_write(tp, 0xb87e, 0xfb00);
7627 ocp_reg_write(tp, 0xb87c, 0x8fd2);
7628 ocp_reg_write(tp, 0xb87e, 0x0100);
7629 ocp_reg_write(tp, 0xb87c, 0x8fd4);
7630 ocp_reg_write(tp, 0xb87e, 0xf400);
7631 ocp_reg_write(tp, 0xb87c, 0x8fd6);
7632 ocp_reg_write(tp, 0xb87e, 0xff00);
7633 ocp_reg_write(tp, 0xb87c, 0x8fd8);
7634 ocp_reg_write(tp, 0xb87e, 0xf600);
7635
7636 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7637 ocp_data |= EN_XG_LIP | EN_G_LIP;
7638 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7639 ocp_reg_write(tp, 0xb87c, 0x813d);
7640 ocp_reg_write(tp, 0xb87e, 0x390e);
7641 ocp_reg_write(tp, 0xb87c, 0x814f);
7642 ocp_reg_write(tp, 0xb87e, 0x790e);
7643 ocp_reg_write(tp, 0xb87c, 0x80b0);
7644 ocp_reg_write(tp, 0xb87e, 0x0f31);
7645 data = ocp_reg_read(tp, 0xbf4c);
7646 data |= BIT(1);
7647 ocp_reg_write(tp, 0xbf4c, data);
7648 data = ocp_reg_read(tp, 0xbcca);
7649 data |= BIT(9) | BIT(8);
7650 ocp_reg_write(tp, 0xbcca, data);
7651 ocp_reg_write(tp, 0xb87c, 0x8141);
7652 ocp_reg_write(tp, 0xb87e, 0x320e);
7653 ocp_reg_write(tp, 0xb87c, 0x8153);
7654 ocp_reg_write(tp, 0xb87e, 0x720e);
7655 ocp_reg_write(tp, 0xb87c, 0x8529);
7656 ocp_reg_write(tp, 0xb87e, 0x050e);
7657 data = ocp_reg_read(tp, OCP_EEE_CFG);
7658 data &= ~CTAP_SHORT_EN;
7659 ocp_reg_write(tp, OCP_EEE_CFG, data);
7660
7661 sram_write(tp, 0x816c, 0xc4a0);
7662 sram_write(tp, 0x8170, 0xc4a0);
7663 sram_write(tp, 0x8174, 0x04a0);
7664 sram_write(tp, 0x8178, 0x04a0);
7665 sram_write(tp, 0x817c, 0x0719);
7666 sram_write(tp, 0x8ff4, 0x0400);
7667 sram_write(tp, 0x8ff1, 0x0404);
7668
7669 ocp_reg_write(tp, 0xbf4a, 0x001b);
7670 ocp_reg_write(tp, 0xb87c, 0x8033);
7671 ocp_reg_write(tp, 0xb87e, 0x7c13);
7672 ocp_reg_write(tp, 0xb87c, 0x8037);
7673 ocp_reg_write(tp, 0xb87e, 0x7c13);
7674 ocp_reg_write(tp, 0xb87c, 0x803b);
7675 ocp_reg_write(tp, 0xb87e, 0xfc32);
7676 ocp_reg_write(tp, 0xb87c, 0x803f);
7677 ocp_reg_write(tp, 0xb87e, 0x7c13);
7678 ocp_reg_write(tp, 0xb87c, 0x8043);
7679 ocp_reg_write(tp, 0xb87e, 0x7c13);
7680 ocp_reg_write(tp, 0xb87c, 0x8047);
7681 ocp_reg_write(tp, 0xb87e, 0x7c13);
7682
7683 ocp_reg_write(tp, 0xb87c, 0x8145);
7684 ocp_reg_write(tp, 0xb87e, 0x370e);
7685 ocp_reg_write(tp, 0xb87c, 0x8157);
7686 ocp_reg_write(tp, 0xb87e, 0x770e);
7687 ocp_reg_write(tp, 0xb87c, 0x8169);
7688 ocp_reg_write(tp, 0xb87e, 0x0d0a);
7689 ocp_reg_write(tp, 0xb87c, 0x817b);
7690 ocp_reg_write(tp, 0xb87e, 0x1d0a);
7691
7692 data = sram_read(tp, 0x8217);
7693 data &= ~0xff00;
7694 data |= 0x5000;
7695 sram_write(tp, 0x8217, data);
7696 data = sram_read(tp, 0x821a);
7697 data &= ~0xff00;
7698 data |= 0x5000;
7699 sram_write(tp, 0x821a, data);
7700 sram_write(tp, 0x80da, 0x0403);
7701 data = sram_read(tp, 0x80dc);
7702 data &= ~0xff00;
7703 data |= 0x1000;
7704 sram_write(tp, 0x80dc, data);
7705 sram_write(tp, 0x80b3, 0x0384);
7706 sram_write(tp, 0x80b7, 0x2007);
7707 data = sram_read(tp, 0x80ba);
7708 data &= ~0xff00;
7709 data |= 0x6c00;
7710 sram_write(tp, 0x80ba, data);
7711 sram_write(tp, 0x80b5, 0xf009);
7712 data = sram_read(tp, 0x80bd);
7713 data &= ~0xff00;
7714 data |= 0x9f00;
7715 sram_write(tp, 0x80bd, data);
7716 sram_write(tp, 0x80c7, 0xf083);
7717 sram_write(tp, 0x80dd, 0x03f0);
7718 data = sram_read(tp, 0x80df);
7719 data &= ~0xff00;
7720 data |= 0x1000;
7721 sram_write(tp, 0x80df, data);
7722 sram_write(tp, 0x80cb, 0x2007);
7723 data = sram_read(tp, 0x80ce);
7724 data &= ~0xff00;
7725 data |= 0x6c00;
7726 sram_write(tp, 0x80ce, data);
7727 sram_write(tp, 0x80c9, 0x8009);
7728 data = sram_read(tp, 0x80d1);
7729 data &= ~0xff00;
7730 data |= 0x8000;
7731 sram_write(tp, 0x80d1, data);
7732 sram_write(tp, 0x80a3, 0x200a);
7733 sram_write(tp, 0x80a5, 0xf0ad);
7734 sram_write(tp, 0x809f, 0x6073);
7735 sram_write(tp, 0x80a1, 0x000b);
7736 data = sram_read(tp, 0x80a9);
7737 data &= ~0xff00;
7738 data |= 0xc000;
7739 sram_write(tp, 0x80a9, data);
7740
7741 if (rtl_phy_patch_request(tp, true, true))
7742 return;
7743
7744 data = ocp_reg_read(tp, 0xb896);
7745 data &= ~BIT(0);
7746 ocp_reg_write(tp, 0xb896, data);
7747 data = ocp_reg_read(tp, 0xb892);
7748 data &= ~0xff00;
7749 ocp_reg_write(tp, 0xb892, data);
7750 ocp_reg_write(tp, 0xb88e, 0xc23e);
7751 ocp_reg_write(tp, 0xb890, 0x0000);
7752 ocp_reg_write(tp, 0xb88e, 0xc240);
7753 ocp_reg_write(tp, 0xb890, 0x0103);
7754 ocp_reg_write(tp, 0xb88e, 0xc242);
7755 ocp_reg_write(tp, 0xb890, 0x0507);
7756 ocp_reg_write(tp, 0xb88e, 0xc244);
7757 ocp_reg_write(tp, 0xb890, 0x090b);
7758 ocp_reg_write(tp, 0xb88e, 0xc246);
7759 ocp_reg_write(tp, 0xb890, 0x0c0e);
7760 ocp_reg_write(tp, 0xb88e, 0xc248);
7761 ocp_reg_write(tp, 0xb890, 0x1012);
7762 ocp_reg_write(tp, 0xb88e, 0xc24a);
7763 ocp_reg_write(tp, 0xb890, 0x1416);
7764 data = ocp_reg_read(tp, 0xb896);
7765 data |= BIT(0);
7766 ocp_reg_write(tp, 0xb896, data);
7767
7768 rtl_phy_patch_request(tp, false, true);
7769
7770 data = ocp_reg_read(tp, 0xa86a);
7771 data |= BIT(0);
7772 ocp_reg_write(tp, 0xa86a, data);
7773 data = ocp_reg_read(tp, 0xa6f0);
7774 data |= BIT(0);
7775 ocp_reg_write(tp, 0xa6f0, data);
7776
7777 ocp_reg_write(tp, 0xbfa0, 0xd70d);
7778 ocp_reg_write(tp, 0xbfa2, 0x4100);
7779 ocp_reg_write(tp, 0xbfa4, 0xe868);
7780 ocp_reg_write(tp, 0xbfa6, 0xdc59);
7781 ocp_reg_write(tp, 0xb54c, 0x3c18);
7782 data = ocp_reg_read(tp, 0xbfa4);
7783 data &= ~BIT(5);
7784 ocp_reg_write(tp, 0xbfa4, data);
7785 data = sram_read(tp, 0x817d);
7786 data |= BIT(12);
7787 sram_write(tp, 0x817d, data);
7788 break;
7789 case RTL_VER_13:
7790 /* 2.5G INRX */
7791 data = ocp_reg_read(tp, 0xac46);
7792 data &= ~0x00f0;
7793 data |= 0x0090;
7794 ocp_reg_write(tp, 0xac46, data);
7795 data = ocp_reg_read(tp, 0xad30);
7796 data &= ~0x0003;
7797 data |= 0x0001;
7798 ocp_reg_write(tp, 0xad30, data);
7799 fallthrough;
7800 case RTL_VER_15:
7801 /* EEE parameter */
7802 ocp_reg_write(tp, 0xb87c, 0x80f5);
7803 ocp_reg_write(tp, 0xb87e, 0x760e);
7804 ocp_reg_write(tp, 0xb87c, 0x8107);
7805 ocp_reg_write(tp, 0xb87e, 0x360e);
7806 ocp_reg_write(tp, 0xb87c, 0x8551);
7807 data = ocp_reg_read(tp, 0xb87e);
7808 data &= ~0xff00;
7809 data |= 0x0800;
7810 ocp_reg_write(tp, 0xb87e, data);
7811
7812 /* ADC_PGA parameter */
7813 data = ocp_reg_read(tp, 0xbf00);
7814 data &= ~0xe000;
7815 data |= 0xa000;
7816 ocp_reg_write(tp, 0xbf00, data);
7817 data = ocp_reg_read(tp, 0xbf46);
7818 data &= ~0x0f00;
7819 data |= 0x0300;
7820 ocp_reg_write(tp, 0xbf46, data);
7821
7822 /* Green Table-PGA, 1G full viterbi */
7823 sram_write(tp, 0x8044, 0x2417);
7824 sram_write(tp, 0x804a, 0x2417);
7825 sram_write(tp, 0x8050, 0x2417);
7826 sram_write(tp, 0x8056, 0x2417);
7827 sram_write(tp, 0x805c, 0x2417);
7828 sram_write(tp, 0x8062, 0x2417);
7829 sram_write(tp, 0x8068, 0x2417);
7830 sram_write(tp, 0x806e, 0x2417);
7831 sram_write(tp, 0x8074, 0x2417);
7832 sram_write(tp, 0x807a, 0x2417);
7833
7834 /* XG PLL */
7835 data = ocp_reg_read(tp, 0xbf84);
7836 data &= ~0xe000;
7837 data |= 0xa000;
7838 ocp_reg_write(tp, 0xbf84, data);
7839 break;
7840 default:
7841 break;
7842 }
7843
7844 if (rtl_phy_patch_request(tp, true, true))
7845 return;
7846
7847 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7848 ocp_data |= EEE_SPDWN_EN;
7849 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7850
7851 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7852 data &= ~(EN_EEE_100 | EN_EEE_1000);
7853 data |= EN_10M_CLKDIV;
7854 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7855 tp->ups_info._10m_ckdiv = true;
7856 tp->ups_info.eee_plloff_100 = false;
7857 tp->ups_info.eee_plloff_giga = false;
7858
7859 data = ocp_reg_read(tp, OCP_POWER_CFG);
7860 data &= ~EEE_CLKDIV_EN;
7861 ocp_reg_write(tp, OCP_POWER_CFG, data);
7862 tp->ups_info.eee_ckdiv = false;
7863
7864 rtl_phy_patch_request(tp, false, true);
7865
7866 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7867
7868 data = ocp_reg_read(tp, 0xa428);
7869 data &= ~BIT(9);
7870 ocp_reg_write(tp, 0xa428, data);
7871 data = ocp_reg_read(tp, 0xa5ea);
7872 data &= ~BIT(0);
7873 ocp_reg_write(tp, 0xa5ea, data);
7874 tp->ups_info.lite_mode = 0;
7875
7876 if (tp->eee_en)
7877 rtl_eee_enable(tp, true);
7878
7879 r8153_aldps_en(tp, true);
7880 r8152b_enable_fc(tp);
7881 r8153_u2p3en(tp, true);
7882
7883 set_bit(PHY_RESET, &tp->flags);
7884 }
7885
r8156_init(struct r8152 * tp)7886 static void r8156_init(struct r8152 *tp)
7887 {
7888 u32 ocp_data;
7889 u16 data;
7890 int i;
7891
7892 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7893 return;
7894
7895 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
7896 ocp_data &= ~EN_ALL_SPEED;
7897 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
7898
7899 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
7900
7901 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
7902 ocp_data |= BYPASS_MAC_RESET;
7903 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
7904
7905 r8153b_u1u2en(tp, false);
7906
7907 for (i = 0; i < 500; i++) {
7908 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7909 AUTOLOAD_DONE)
7910 break;
7911
7912 msleep(20);
7913 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7914 return;
7915 }
7916
7917 data = r8153_phy_status(tp, 0);
7918 if (data == PHY_STAT_EXT_INIT) {
7919 data = ocp_reg_read(tp, 0xa468);
7920 data &= ~(BIT(3) | BIT(1));
7921 ocp_reg_write(tp, 0xa468, data);
7922 }
7923
7924 data = r8152_mdio_read(tp, MII_BMCR);
7925 if (data & BMCR_PDOWN) {
7926 data &= ~BMCR_PDOWN;
7927 r8152_mdio_write(tp, MII_BMCR, data);
7928 }
7929
7930 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7931 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7932
7933 r8153_u2p3en(tp, false);
7934
7935 /* MSC timer = 0xfff * 8ms = 32760 ms */
7936 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7937
7938 /* U1/U2/L1 idle timer. 500 us */
7939 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
7940
7941 r8153b_power_cut_en(tp, false);
7942 r8156_ups_en(tp, false);
7943 r8153_queue_wake(tp, false);
7944 rtl_runtime_suspend_enable(tp, false);
7945
7946 if (tp->udev->speed >= USB_SPEED_SUPER)
7947 r8153b_u1u2en(tp, true);
7948
7949 usb_enable_lpm(tp->udev);
7950
7951 r8156_mac_clk_spd(tp, true);
7952
7953 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7954 ocp_data &= ~PLA_MCU_SPDWN_EN;
7955 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7956
7957 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7958 if (rtl8152_get_speed(tp) & LINK_STATUS)
7959 ocp_data |= CUR_LINK_OK;
7960 else
7961 ocp_data &= ~CUR_LINK_OK;
7962 ocp_data |= POLL_LINK_CHG;
7963 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7964
7965 set_bit(GREEN_ETHERNET, &tp->flags);
7966
7967 /* rx aggregation */
7968 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7969 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7970 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7971
7972 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
7973 ocp_data |= ACT_ODMA;
7974 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
7975
7976 rtl_tally_reset(tp);
7977
7978 tp->coalesce = 15000; /* 15 us */
7979 }
7980
r8156b_init(struct r8152 * tp)7981 static void r8156b_init(struct r8152 *tp)
7982 {
7983 u32 ocp_data;
7984 u16 data;
7985 int i;
7986
7987 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7988 return;
7989
7990 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
7991 ocp_data &= ~EN_ALL_SPEED;
7992 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
7993
7994 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
7995
7996 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
7997 ocp_data |= BYPASS_MAC_RESET;
7998 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
7999
8000 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
8001 ocp_data |= RX_DETECT8;
8002 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
8003
8004 r8153b_u1u2en(tp, false);
8005
8006 switch (tp->version) {
8007 case RTL_VER_13:
8008 case RTL_VER_15:
8009 r8156b_wait_loading_flash(tp);
8010 break;
8011 default:
8012 break;
8013 }
8014
8015 for (i = 0; i < 500; i++) {
8016 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8017 AUTOLOAD_DONE)
8018 break;
8019
8020 msleep(20);
8021 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8022 return;
8023 }
8024
8025 data = r8153_phy_status(tp, 0);
8026 if (data == PHY_STAT_EXT_INIT) {
8027 data = ocp_reg_read(tp, 0xa468);
8028 data &= ~(BIT(3) | BIT(1));
8029 ocp_reg_write(tp, 0xa468, data);
8030
8031 data = ocp_reg_read(tp, 0xa466);
8032 data &= ~BIT(0);
8033 ocp_reg_write(tp, 0xa466, data);
8034 }
8035
8036 data = r8152_mdio_read(tp, MII_BMCR);
8037 if (data & BMCR_PDOWN) {
8038 data &= ~BMCR_PDOWN;
8039 r8152_mdio_write(tp, MII_BMCR, data);
8040 }
8041
8042 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8043
8044 r8153_u2p3en(tp, false);
8045
8046 /* MSC timer = 0xfff * 8ms = 32760 ms */
8047 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8048
8049 /* U1/U2/L1 idle timer. 500 us */
8050 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8051
8052 r8153b_power_cut_en(tp, false);
8053 r8156_ups_en(tp, false);
8054 r8153_queue_wake(tp, false);
8055 rtl_runtime_suspend_enable(tp, false);
8056
8057 if (tp->udev->speed >= USB_SPEED_SUPER)
8058 r8153b_u1u2en(tp, true);
8059
8060 usb_enable_lpm(tp->udev);
8061
8062 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
8063 ocp_data &= ~SLOT_EN;
8064 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8065
8066 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
8067 ocp_data |= FLOW_CTRL_EN;
8068 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
8069
8070 /* enable fc timer and set timer to 600 ms. */
8071 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
8072 CTRL_TIMER_EN | (600 / 8));
8073
8074 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
8075 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
8076 ocp_data |= FLOW_CTRL_PATCH_2;
8077 ocp_data &= ~AUTO_SPEEDUP;
8078 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
8079
8080 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
8081 ocp_data |= FC_PATCH_TASK;
8082 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
8083
8084 r8156_mac_clk_spd(tp, true);
8085
8086 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8087 ocp_data &= ~PLA_MCU_SPDWN_EN;
8088 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8089
8090 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8091 if (rtl8152_get_speed(tp) & LINK_STATUS)
8092 ocp_data |= CUR_LINK_OK;
8093 else
8094 ocp_data &= ~CUR_LINK_OK;
8095 ocp_data |= POLL_LINK_CHG;
8096 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8097
8098 set_bit(GREEN_ETHERNET, &tp->flags);
8099
8100 /* rx aggregation */
8101 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8102 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8103 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8104
8105 rtl_tally_reset(tp);
8106
8107 tp->coalesce = 15000; /* 15 us */
8108 }
8109
rtl_vendor_mode(struct usb_interface * intf)8110 static bool rtl_vendor_mode(struct usb_interface *intf)
8111 {
8112 struct usb_host_interface *alt = intf->cur_altsetting;
8113 struct usb_device *udev;
8114 struct usb_host_config *c;
8115 int i, num_configs;
8116
8117 if (alt->desc.bInterfaceClass == USB_CLASS_VENDOR_SPEC)
8118 return true;
8119
8120 /* The vendor mode is not always config #1, so to find it out. */
8121 udev = interface_to_usbdev(intf);
8122 c = udev->config;
8123 num_configs = udev->descriptor.bNumConfigurations;
8124 for (i = 0; i < num_configs; (i++, c++)) {
8125 struct usb_interface_descriptor *desc = NULL;
8126
8127 if (c->desc.bNumInterfaces > 0)
8128 desc = &c->intf_cache[0]->altsetting->desc;
8129 else
8130 continue;
8131
8132 if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) {
8133 usb_driver_set_configuration(udev, c->desc.bConfigurationValue);
8134 break;
8135 }
8136 }
8137
8138 WARN_ON_ONCE(i == num_configs);
8139
8140 return false;
8141 }
8142
rtl8152_pre_reset(struct usb_interface * intf)8143 static int rtl8152_pre_reset(struct usb_interface *intf)
8144 {
8145 struct r8152 *tp = usb_get_intfdata(intf);
8146 struct net_device *netdev;
8147
8148 if (!tp)
8149 return 0;
8150
8151 netdev = tp->netdev;
8152 if (!netif_running(netdev))
8153 return 0;
8154
8155 netif_stop_queue(netdev);
8156 tasklet_disable(&tp->tx_tl);
8157 clear_bit(WORK_ENABLE, &tp->flags);
8158 usb_kill_urb(tp->intr_urb);
8159 cancel_delayed_work_sync(&tp->schedule);
8160 napi_disable(&tp->napi);
8161 if (netif_carrier_ok(netdev)) {
8162 mutex_lock(&tp->control);
8163 tp->rtl_ops.disable(tp);
8164 mutex_unlock(&tp->control);
8165 }
8166
8167 return 0;
8168 }
8169
rtl8152_post_reset(struct usb_interface * intf)8170 static int rtl8152_post_reset(struct usb_interface *intf)
8171 {
8172 struct r8152 *tp = usb_get_intfdata(intf);
8173 struct net_device *netdev;
8174 struct sockaddr sa;
8175
8176 if (!tp)
8177 return 0;
8178
8179 /* reset the MAC adddress in case of policy change */
8180 if (determine_ethernet_addr(tp, &sa) >= 0) {
8181 rtnl_lock();
8182 dev_set_mac_address (tp->netdev, &sa, NULL);
8183 rtnl_unlock();
8184 }
8185
8186 netdev = tp->netdev;
8187 if (!netif_running(netdev))
8188 return 0;
8189
8190 set_bit(WORK_ENABLE, &tp->flags);
8191 if (netif_carrier_ok(netdev)) {
8192 mutex_lock(&tp->control);
8193 tp->rtl_ops.enable(tp);
8194 rtl_start_rx(tp);
8195 _rtl8152_set_rx_mode(netdev);
8196 mutex_unlock(&tp->control);
8197 }
8198
8199 napi_enable(&tp->napi);
8200 tasklet_enable(&tp->tx_tl);
8201 netif_wake_queue(netdev);
8202 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
8203
8204 if (!list_empty(&tp->rx_done))
8205 napi_schedule(&tp->napi);
8206
8207 return 0;
8208 }
8209
delay_autosuspend(struct r8152 * tp)8210 static bool delay_autosuspend(struct r8152 *tp)
8211 {
8212 bool sw_linking = !!netif_carrier_ok(tp->netdev);
8213 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
8214
8215 /* This means a linking change occurs and the driver doesn't detect it,
8216 * yet. If the driver has disabled tx/rx and hw is linking on, the
8217 * device wouldn't wake up by receiving any packet.
8218 */
8219 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
8220 return true;
8221
8222 /* If the linking down is occurred by nway, the device may miss the
8223 * linking change event. And it wouldn't wake when linking on.
8224 */
8225 if (!sw_linking && tp->rtl_ops.in_nway(tp))
8226 return true;
8227 else if (!skb_queue_empty(&tp->tx_queue))
8228 return true;
8229 else
8230 return false;
8231 }
8232
rtl8152_runtime_resume(struct r8152 * tp)8233 static int rtl8152_runtime_resume(struct r8152 *tp)
8234 {
8235 struct net_device *netdev = tp->netdev;
8236
8237 if (netif_running(netdev) && netdev->flags & IFF_UP) {
8238 struct napi_struct *napi = &tp->napi;
8239
8240 tp->rtl_ops.autosuspend_en(tp, false);
8241 napi_disable(napi);
8242 set_bit(WORK_ENABLE, &tp->flags);
8243
8244 if (netif_carrier_ok(netdev)) {
8245 if (rtl8152_get_speed(tp) & LINK_STATUS) {
8246 rtl_start_rx(tp);
8247 } else {
8248 netif_carrier_off(netdev);
8249 tp->rtl_ops.disable(tp);
8250 netif_info(tp, link, netdev, "linking down\n");
8251 }
8252 }
8253
8254 napi_enable(napi);
8255 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8256 smp_mb__after_atomic();
8257
8258 if (!list_empty(&tp->rx_done))
8259 napi_schedule(&tp->napi);
8260
8261 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8262 } else {
8263 if (netdev->flags & IFF_UP)
8264 tp->rtl_ops.autosuspend_en(tp, false);
8265
8266 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8267 }
8268
8269 return 0;
8270 }
8271
rtl8152_system_resume(struct r8152 * tp)8272 static int rtl8152_system_resume(struct r8152 *tp)
8273 {
8274 struct net_device *netdev = tp->netdev;
8275
8276 netif_device_attach(netdev);
8277
8278 if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
8279 tp->rtl_ops.up(tp);
8280 netif_carrier_off(netdev);
8281 set_bit(WORK_ENABLE, &tp->flags);
8282 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8283 }
8284
8285 return 0;
8286 }
8287
rtl8152_runtime_suspend(struct r8152 * tp)8288 static int rtl8152_runtime_suspend(struct r8152 *tp)
8289 {
8290 struct net_device *netdev = tp->netdev;
8291 int ret = 0;
8292
8293 if (!tp->rtl_ops.autosuspend_en)
8294 return -EBUSY;
8295
8296 set_bit(SELECTIVE_SUSPEND, &tp->flags);
8297 smp_mb__after_atomic();
8298
8299 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8300 u32 rcr = 0;
8301
8302 if (netif_carrier_ok(netdev)) {
8303 u32 ocp_data;
8304
8305 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
8306 ocp_data = rcr & ~RCR_ACPT_ALL;
8307 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8308 rxdy_gated_en(tp, true);
8309 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
8310 PLA_OOB_CTRL);
8311 if (!(ocp_data & RXFIFO_EMPTY)) {
8312 rxdy_gated_en(tp, false);
8313 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8314 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8315 smp_mb__after_atomic();
8316 ret = -EBUSY;
8317 goto out1;
8318 }
8319 }
8320
8321 clear_bit(WORK_ENABLE, &tp->flags);
8322 usb_kill_urb(tp->intr_urb);
8323
8324 tp->rtl_ops.autosuspend_en(tp, true);
8325
8326 if (netif_carrier_ok(netdev)) {
8327 struct napi_struct *napi = &tp->napi;
8328
8329 napi_disable(napi);
8330 rtl_stop_rx(tp);
8331 rxdy_gated_en(tp, false);
8332 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8333 napi_enable(napi);
8334 }
8335
8336 if (delay_autosuspend(tp)) {
8337 rtl8152_runtime_resume(tp);
8338 ret = -EBUSY;
8339 }
8340 }
8341
8342 out1:
8343 return ret;
8344 }
8345
rtl8152_system_suspend(struct r8152 * tp)8346 static int rtl8152_system_suspend(struct r8152 *tp)
8347 {
8348 struct net_device *netdev = tp->netdev;
8349
8350 netif_device_detach(netdev);
8351
8352 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8353 struct napi_struct *napi = &tp->napi;
8354
8355 clear_bit(WORK_ENABLE, &tp->flags);
8356 usb_kill_urb(tp->intr_urb);
8357 tasklet_disable(&tp->tx_tl);
8358 napi_disable(napi);
8359 cancel_delayed_work_sync(&tp->schedule);
8360 tp->rtl_ops.down(tp);
8361 napi_enable(napi);
8362 tasklet_enable(&tp->tx_tl);
8363 }
8364
8365 return 0;
8366 }
8367
rtl8152_suspend(struct usb_interface * intf,pm_message_t message)8368 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
8369 {
8370 struct r8152 *tp = usb_get_intfdata(intf);
8371 int ret;
8372
8373 mutex_lock(&tp->control);
8374
8375 if (PMSG_IS_AUTO(message))
8376 ret = rtl8152_runtime_suspend(tp);
8377 else
8378 ret = rtl8152_system_suspend(tp);
8379
8380 mutex_unlock(&tp->control);
8381
8382 return ret;
8383 }
8384
rtl8152_resume(struct usb_interface * intf)8385 static int rtl8152_resume(struct usb_interface *intf)
8386 {
8387 struct r8152 *tp = usb_get_intfdata(intf);
8388 int ret;
8389
8390 mutex_lock(&tp->control);
8391
8392 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
8393 ret = rtl8152_runtime_resume(tp);
8394 else
8395 ret = rtl8152_system_resume(tp);
8396
8397 mutex_unlock(&tp->control);
8398
8399 return ret;
8400 }
8401
rtl8152_reset_resume(struct usb_interface * intf)8402 static int rtl8152_reset_resume(struct usb_interface *intf)
8403 {
8404 struct r8152 *tp = usb_get_intfdata(intf);
8405
8406 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8407 tp->rtl_ops.init(tp);
8408 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
8409 set_ethernet_addr(tp);
8410 return rtl8152_resume(intf);
8411 }
8412
rtl8152_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)8413 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8414 {
8415 struct r8152 *tp = netdev_priv(dev);
8416
8417 if (usb_autopm_get_interface(tp->intf) < 0)
8418 return;
8419
8420 if (!rtl_can_wakeup(tp)) {
8421 wol->supported = 0;
8422 wol->wolopts = 0;
8423 } else {
8424 mutex_lock(&tp->control);
8425 wol->supported = WAKE_ANY;
8426 wol->wolopts = __rtl_get_wol(tp);
8427 mutex_unlock(&tp->control);
8428 }
8429
8430 usb_autopm_put_interface(tp->intf);
8431 }
8432
rtl8152_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)8433 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8434 {
8435 struct r8152 *tp = netdev_priv(dev);
8436 int ret;
8437
8438 if (!rtl_can_wakeup(tp))
8439 return -EOPNOTSUPP;
8440
8441 if (wol->wolopts & ~WAKE_ANY)
8442 return -EINVAL;
8443
8444 ret = usb_autopm_get_interface(tp->intf);
8445 if (ret < 0)
8446 goto out_set_wol;
8447
8448 mutex_lock(&tp->control);
8449
8450 __rtl_set_wol(tp, wol->wolopts);
8451 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
8452
8453 mutex_unlock(&tp->control);
8454
8455 usb_autopm_put_interface(tp->intf);
8456
8457 out_set_wol:
8458 return ret;
8459 }
8460
rtl8152_get_msglevel(struct net_device * dev)8461 static u32 rtl8152_get_msglevel(struct net_device *dev)
8462 {
8463 struct r8152 *tp = netdev_priv(dev);
8464
8465 return tp->msg_enable;
8466 }
8467
rtl8152_set_msglevel(struct net_device * dev,u32 value)8468 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
8469 {
8470 struct r8152 *tp = netdev_priv(dev);
8471
8472 tp->msg_enable = value;
8473 }
8474
rtl8152_get_drvinfo(struct net_device * netdev,struct ethtool_drvinfo * info)8475 static void rtl8152_get_drvinfo(struct net_device *netdev,
8476 struct ethtool_drvinfo *info)
8477 {
8478 struct r8152 *tp = netdev_priv(netdev);
8479
8480 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
8481 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
8482 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
8483 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
8484 strlcpy(info->fw_version, tp->rtl_fw.version,
8485 sizeof(info->fw_version));
8486 }
8487
8488 static
rtl8152_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * cmd)8489 int rtl8152_get_link_ksettings(struct net_device *netdev,
8490 struct ethtool_link_ksettings *cmd)
8491 {
8492 struct r8152 *tp = netdev_priv(netdev);
8493 int ret;
8494
8495 if (!tp->mii.mdio_read)
8496 return -EOPNOTSUPP;
8497
8498 ret = usb_autopm_get_interface(tp->intf);
8499 if (ret < 0)
8500 goto out;
8501
8502 mutex_lock(&tp->control);
8503
8504 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
8505
8506 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8507 cmd->link_modes.supported, tp->support_2500full);
8508
8509 if (tp->support_2500full) {
8510 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8511 cmd->link_modes.advertising,
8512 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
8513
8514 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8515 cmd->link_modes.lp_advertising,
8516 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
8517
8518 if (is_speed_2500(rtl8152_get_speed(tp)))
8519 cmd->base.speed = SPEED_2500;
8520 }
8521
8522 mutex_unlock(&tp->control);
8523
8524 usb_autopm_put_interface(tp->intf);
8525
8526 out:
8527 return ret;
8528 }
8529
rtl8152_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)8530 static int rtl8152_set_link_ksettings(struct net_device *dev,
8531 const struct ethtool_link_ksettings *cmd)
8532 {
8533 struct r8152 *tp = netdev_priv(dev);
8534 u32 advertising = 0;
8535 int ret;
8536
8537 ret = usb_autopm_get_interface(tp->intf);
8538 if (ret < 0)
8539 goto out;
8540
8541 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
8542 cmd->link_modes.advertising))
8543 advertising |= RTL_ADVERTISED_10_HALF;
8544
8545 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
8546 cmd->link_modes.advertising))
8547 advertising |= RTL_ADVERTISED_10_FULL;
8548
8549 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
8550 cmd->link_modes.advertising))
8551 advertising |= RTL_ADVERTISED_100_HALF;
8552
8553 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
8554 cmd->link_modes.advertising))
8555 advertising |= RTL_ADVERTISED_100_FULL;
8556
8557 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
8558 cmd->link_modes.advertising))
8559 advertising |= RTL_ADVERTISED_1000_HALF;
8560
8561 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
8562 cmd->link_modes.advertising))
8563 advertising |= RTL_ADVERTISED_1000_FULL;
8564
8565 if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8566 cmd->link_modes.advertising))
8567 advertising |= RTL_ADVERTISED_2500_FULL;
8568
8569 mutex_lock(&tp->control);
8570
8571 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
8572 cmd->base.duplex, advertising);
8573 if (!ret) {
8574 tp->autoneg = cmd->base.autoneg;
8575 tp->speed = cmd->base.speed;
8576 tp->duplex = cmd->base.duplex;
8577 tp->advertising = advertising;
8578 }
8579
8580 mutex_unlock(&tp->control);
8581
8582 usb_autopm_put_interface(tp->intf);
8583
8584 out:
8585 return ret;
8586 }
8587
8588 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
8589 "tx_packets",
8590 "rx_packets",
8591 "tx_errors",
8592 "rx_errors",
8593 "rx_missed",
8594 "align_errors",
8595 "tx_single_collisions",
8596 "tx_multi_collisions",
8597 "rx_unicast",
8598 "rx_broadcast",
8599 "rx_multicast",
8600 "tx_aborted",
8601 "tx_underrun",
8602 };
8603
rtl8152_get_sset_count(struct net_device * dev,int sset)8604 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
8605 {
8606 switch (sset) {
8607 case ETH_SS_STATS:
8608 return ARRAY_SIZE(rtl8152_gstrings);
8609 default:
8610 return -EOPNOTSUPP;
8611 }
8612 }
8613
rtl8152_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)8614 static void rtl8152_get_ethtool_stats(struct net_device *dev,
8615 struct ethtool_stats *stats, u64 *data)
8616 {
8617 struct r8152 *tp = netdev_priv(dev);
8618 struct tally_counter tally;
8619
8620 if (usb_autopm_get_interface(tp->intf) < 0)
8621 return;
8622
8623 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
8624
8625 usb_autopm_put_interface(tp->intf);
8626
8627 data[0] = le64_to_cpu(tally.tx_packets);
8628 data[1] = le64_to_cpu(tally.rx_packets);
8629 data[2] = le64_to_cpu(tally.tx_errors);
8630 data[3] = le32_to_cpu(tally.rx_errors);
8631 data[4] = le16_to_cpu(tally.rx_missed);
8632 data[5] = le16_to_cpu(tally.align_errors);
8633 data[6] = le32_to_cpu(tally.tx_one_collision);
8634 data[7] = le32_to_cpu(tally.tx_multi_collision);
8635 data[8] = le64_to_cpu(tally.rx_unicast);
8636 data[9] = le64_to_cpu(tally.rx_broadcast);
8637 data[10] = le32_to_cpu(tally.rx_multicast);
8638 data[11] = le16_to_cpu(tally.tx_aborted);
8639 data[12] = le16_to_cpu(tally.tx_underrun);
8640 }
8641
rtl8152_get_strings(struct net_device * dev,u32 stringset,u8 * data)8642 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
8643 {
8644 switch (stringset) {
8645 case ETH_SS_STATS:
8646 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
8647 break;
8648 }
8649 }
8650
r8152_get_eee(struct r8152 * tp,struct ethtool_eee * eee)8651 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8652 {
8653 u32 lp, adv, supported = 0;
8654 u16 val;
8655
8656 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
8657 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8658
8659 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
8660 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8661
8662 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
8663 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8664
8665 eee->eee_enabled = tp->eee_en;
8666 eee->eee_active = !!(supported & adv & lp);
8667 eee->supported = supported;
8668 eee->advertised = tp->eee_adv;
8669 eee->lp_advertised = lp;
8670
8671 return 0;
8672 }
8673
r8152_set_eee(struct r8152 * tp,struct ethtool_eee * eee)8674 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
8675 {
8676 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
8677
8678 tp->eee_en = eee->eee_enabled;
8679 tp->eee_adv = val;
8680
8681 rtl_eee_enable(tp, tp->eee_en);
8682
8683 return 0;
8684 }
8685
r8153_get_eee(struct r8152 * tp,struct ethtool_eee * eee)8686 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8687 {
8688 u32 lp, adv, supported = 0;
8689 u16 val;
8690
8691 val = ocp_reg_read(tp, OCP_EEE_ABLE);
8692 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8693
8694 val = ocp_reg_read(tp, OCP_EEE_ADV);
8695 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8696
8697 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
8698 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8699
8700 eee->eee_enabled = tp->eee_en;
8701 eee->eee_active = !!(supported & adv & lp);
8702 eee->supported = supported;
8703 eee->advertised = tp->eee_adv;
8704 eee->lp_advertised = lp;
8705
8706 return 0;
8707 }
8708
8709 static int
rtl_ethtool_get_eee(struct net_device * net,struct ethtool_eee * edata)8710 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
8711 {
8712 struct r8152 *tp = netdev_priv(net);
8713 int ret;
8714
8715 if (!tp->rtl_ops.eee_get) {
8716 ret = -EOPNOTSUPP;
8717 goto out;
8718 }
8719
8720 ret = usb_autopm_get_interface(tp->intf);
8721 if (ret < 0)
8722 goto out;
8723
8724 mutex_lock(&tp->control);
8725
8726 ret = tp->rtl_ops.eee_get(tp, edata);
8727
8728 mutex_unlock(&tp->control);
8729
8730 usb_autopm_put_interface(tp->intf);
8731
8732 out:
8733 return ret;
8734 }
8735
8736 static int
rtl_ethtool_set_eee(struct net_device * net,struct ethtool_eee * edata)8737 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
8738 {
8739 struct r8152 *tp = netdev_priv(net);
8740 int ret;
8741
8742 if (!tp->rtl_ops.eee_set) {
8743 ret = -EOPNOTSUPP;
8744 goto out;
8745 }
8746
8747 ret = usb_autopm_get_interface(tp->intf);
8748 if (ret < 0)
8749 goto out;
8750
8751 mutex_lock(&tp->control);
8752
8753 ret = tp->rtl_ops.eee_set(tp, edata);
8754 if (!ret)
8755 ret = mii_nway_restart(&tp->mii);
8756
8757 mutex_unlock(&tp->control);
8758
8759 usb_autopm_put_interface(tp->intf);
8760
8761 out:
8762 return ret;
8763 }
8764
rtl8152_nway_reset(struct net_device * dev)8765 static int rtl8152_nway_reset(struct net_device *dev)
8766 {
8767 struct r8152 *tp = netdev_priv(dev);
8768 int ret;
8769
8770 ret = usb_autopm_get_interface(tp->intf);
8771 if (ret < 0)
8772 goto out;
8773
8774 mutex_lock(&tp->control);
8775
8776 ret = mii_nway_restart(&tp->mii);
8777
8778 mutex_unlock(&tp->control);
8779
8780 usb_autopm_put_interface(tp->intf);
8781
8782 out:
8783 return ret;
8784 }
8785
rtl8152_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * coalesce)8786 static int rtl8152_get_coalesce(struct net_device *netdev,
8787 struct ethtool_coalesce *coalesce)
8788 {
8789 struct r8152 *tp = netdev_priv(netdev);
8790
8791 switch (tp->version) {
8792 case RTL_VER_01:
8793 case RTL_VER_02:
8794 case RTL_VER_07:
8795 return -EOPNOTSUPP;
8796 default:
8797 break;
8798 }
8799
8800 coalesce->rx_coalesce_usecs = tp->coalesce;
8801
8802 return 0;
8803 }
8804
rtl8152_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * coalesce)8805 static int rtl8152_set_coalesce(struct net_device *netdev,
8806 struct ethtool_coalesce *coalesce)
8807 {
8808 struct r8152 *tp = netdev_priv(netdev);
8809 int ret;
8810
8811 switch (tp->version) {
8812 case RTL_VER_01:
8813 case RTL_VER_02:
8814 case RTL_VER_07:
8815 return -EOPNOTSUPP;
8816 default:
8817 break;
8818 }
8819
8820 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
8821 return -EINVAL;
8822
8823 ret = usb_autopm_get_interface(tp->intf);
8824 if (ret < 0)
8825 return ret;
8826
8827 mutex_lock(&tp->control);
8828
8829 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
8830 tp->coalesce = coalesce->rx_coalesce_usecs;
8831
8832 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
8833 netif_stop_queue(netdev);
8834 napi_disable(&tp->napi);
8835 tp->rtl_ops.disable(tp);
8836 tp->rtl_ops.enable(tp);
8837 rtl_start_rx(tp);
8838 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
8839 _rtl8152_set_rx_mode(netdev);
8840 napi_enable(&tp->napi);
8841 netif_wake_queue(netdev);
8842 }
8843 }
8844
8845 mutex_unlock(&tp->control);
8846
8847 usb_autopm_put_interface(tp->intf);
8848
8849 return ret;
8850 }
8851
rtl8152_get_tunable(struct net_device * netdev,const struct ethtool_tunable * tunable,void * d)8852 static int rtl8152_get_tunable(struct net_device *netdev,
8853 const struct ethtool_tunable *tunable, void *d)
8854 {
8855 struct r8152 *tp = netdev_priv(netdev);
8856
8857 switch (tunable->id) {
8858 case ETHTOOL_RX_COPYBREAK:
8859 *(u32 *)d = tp->rx_copybreak;
8860 break;
8861 default:
8862 return -EOPNOTSUPP;
8863 }
8864
8865 return 0;
8866 }
8867
rtl8152_set_tunable(struct net_device * netdev,const struct ethtool_tunable * tunable,const void * d)8868 static int rtl8152_set_tunable(struct net_device *netdev,
8869 const struct ethtool_tunable *tunable,
8870 const void *d)
8871 {
8872 struct r8152 *tp = netdev_priv(netdev);
8873 u32 val;
8874
8875 switch (tunable->id) {
8876 case ETHTOOL_RX_COPYBREAK:
8877 val = *(u32 *)d;
8878 if (val < ETH_ZLEN) {
8879 netif_err(tp, rx_err, netdev,
8880 "Invalid rx copy break value\n");
8881 return -EINVAL;
8882 }
8883
8884 if (tp->rx_copybreak != val) {
8885 if (netdev->flags & IFF_UP) {
8886 mutex_lock(&tp->control);
8887 napi_disable(&tp->napi);
8888 tp->rx_copybreak = val;
8889 napi_enable(&tp->napi);
8890 mutex_unlock(&tp->control);
8891 } else {
8892 tp->rx_copybreak = val;
8893 }
8894 }
8895 break;
8896 default:
8897 return -EOPNOTSUPP;
8898 }
8899
8900 return 0;
8901 }
8902
rtl8152_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)8903 static void rtl8152_get_ringparam(struct net_device *netdev,
8904 struct ethtool_ringparam *ring)
8905 {
8906 struct r8152 *tp = netdev_priv(netdev);
8907
8908 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
8909 ring->rx_pending = tp->rx_pending;
8910 }
8911
rtl8152_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)8912 static int rtl8152_set_ringparam(struct net_device *netdev,
8913 struct ethtool_ringparam *ring)
8914 {
8915 struct r8152 *tp = netdev_priv(netdev);
8916
8917 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
8918 return -EINVAL;
8919
8920 if (tp->rx_pending != ring->rx_pending) {
8921 if (netdev->flags & IFF_UP) {
8922 mutex_lock(&tp->control);
8923 napi_disable(&tp->napi);
8924 tp->rx_pending = ring->rx_pending;
8925 napi_enable(&tp->napi);
8926 mutex_unlock(&tp->control);
8927 } else {
8928 tp->rx_pending = ring->rx_pending;
8929 }
8930 }
8931
8932 return 0;
8933 }
8934
8935 static const struct ethtool_ops ops = {
8936 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
8937 .get_drvinfo = rtl8152_get_drvinfo,
8938 .get_link = ethtool_op_get_link,
8939 .nway_reset = rtl8152_nway_reset,
8940 .get_msglevel = rtl8152_get_msglevel,
8941 .set_msglevel = rtl8152_set_msglevel,
8942 .get_wol = rtl8152_get_wol,
8943 .set_wol = rtl8152_set_wol,
8944 .get_strings = rtl8152_get_strings,
8945 .get_sset_count = rtl8152_get_sset_count,
8946 .get_ethtool_stats = rtl8152_get_ethtool_stats,
8947 .get_coalesce = rtl8152_get_coalesce,
8948 .set_coalesce = rtl8152_set_coalesce,
8949 .get_eee = rtl_ethtool_get_eee,
8950 .set_eee = rtl_ethtool_set_eee,
8951 .get_link_ksettings = rtl8152_get_link_ksettings,
8952 .set_link_ksettings = rtl8152_set_link_ksettings,
8953 .get_tunable = rtl8152_get_tunable,
8954 .set_tunable = rtl8152_set_tunable,
8955 .get_ringparam = rtl8152_get_ringparam,
8956 .set_ringparam = rtl8152_set_ringparam,
8957 };
8958
rtl8152_ioctl(struct net_device * netdev,struct ifreq * rq,int cmd)8959 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
8960 {
8961 struct r8152 *tp = netdev_priv(netdev);
8962 struct mii_ioctl_data *data = if_mii(rq);
8963 int res;
8964
8965 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8966 return -ENODEV;
8967
8968 res = usb_autopm_get_interface(tp->intf);
8969 if (res < 0)
8970 goto out;
8971
8972 switch (cmd) {
8973 case SIOCGMIIPHY:
8974 data->phy_id = R8152_PHY_ID; /* Internal PHY */
8975 break;
8976
8977 case SIOCGMIIREG:
8978 mutex_lock(&tp->control);
8979 data->val_out = r8152_mdio_read(tp, data->reg_num);
8980 mutex_unlock(&tp->control);
8981 break;
8982
8983 case SIOCSMIIREG:
8984 if (!capable(CAP_NET_ADMIN)) {
8985 res = -EPERM;
8986 break;
8987 }
8988 mutex_lock(&tp->control);
8989 r8152_mdio_write(tp, data->reg_num, data->val_in);
8990 mutex_unlock(&tp->control);
8991 break;
8992
8993 default:
8994 res = -EOPNOTSUPP;
8995 }
8996
8997 usb_autopm_put_interface(tp->intf);
8998
8999 out:
9000 return res;
9001 }
9002
rtl8152_change_mtu(struct net_device * dev,int new_mtu)9003 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
9004 {
9005 struct r8152 *tp = netdev_priv(dev);
9006 int ret;
9007
9008 switch (tp->version) {
9009 case RTL_VER_01:
9010 case RTL_VER_02:
9011 case RTL_VER_07:
9012 dev->mtu = new_mtu;
9013 return 0;
9014 default:
9015 break;
9016 }
9017
9018 ret = usb_autopm_get_interface(tp->intf);
9019 if (ret < 0)
9020 return ret;
9021
9022 mutex_lock(&tp->control);
9023
9024 dev->mtu = new_mtu;
9025
9026 if (netif_running(dev)) {
9027 if (tp->rtl_ops.change_mtu)
9028 tp->rtl_ops.change_mtu(tp);
9029
9030 if (netif_carrier_ok(dev)) {
9031 netif_stop_queue(dev);
9032 napi_disable(&tp->napi);
9033 tasklet_disable(&tp->tx_tl);
9034 tp->rtl_ops.disable(tp);
9035 tp->rtl_ops.enable(tp);
9036 rtl_start_rx(tp);
9037 tasklet_enable(&tp->tx_tl);
9038 napi_enable(&tp->napi);
9039 rtl8152_set_rx_mode(dev);
9040 netif_wake_queue(dev);
9041 }
9042 }
9043
9044 mutex_unlock(&tp->control);
9045
9046 usb_autopm_put_interface(tp->intf);
9047
9048 return ret;
9049 }
9050
9051 static const struct net_device_ops rtl8152_netdev_ops = {
9052 .ndo_open = rtl8152_open,
9053 .ndo_stop = rtl8152_close,
9054 .ndo_do_ioctl = rtl8152_ioctl,
9055 .ndo_start_xmit = rtl8152_start_xmit,
9056 .ndo_tx_timeout = rtl8152_tx_timeout,
9057 .ndo_set_features = rtl8152_set_features,
9058 .ndo_set_rx_mode = rtl8152_set_rx_mode,
9059 .ndo_set_mac_address = rtl8152_set_mac_address,
9060 .ndo_change_mtu = rtl8152_change_mtu,
9061 .ndo_validate_addr = eth_validate_addr,
9062 .ndo_features_check = rtl8152_features_check,
9063 };
9064
rtl8152_unload(struct r8152 * tp)9065 static void rtl8152_unload(struct r8152 *tp)
9066 {
9067 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9068 return;
9069
9070 if (tp->version != RTL_VER_01)
9071 r8152_power_cut_en(tp, true);
9072 }
9073
rtl8153_unload(struct r8152 * tp)9074 static void rtl8153_unload(struct r8152 *tp)
9075 {
9076 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9077 return;
9078
9079 r8153_power_cut_en(tp, false);
9080 }
9081
rtl8153b_unload(struct r8152 * tp)9082 static void rtl8153b_unload(struct r8152 *tp)
9083 {
9084 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9085 return;
9086
9087 r8153b_power_cut_en(tp, false);
9088 }
9089
rtl_ops_init(struct r8152 * tp)9090 static int rtl_ops_init(struct r8152 *tp)
9091 {
9092 struct rtl_ops *ops = &tp->rtl_ops;
9093 int ret = 0;
9094
9095 switch (tp->version) {
9096 case RTL_VER_01:
9097 case RTL_VER_02:
9098 case RTL_VER_07:
9099 ops->init = r8152b_init;
9100 ops->enable = rtl8152_enable;
9101 ops->disable = rtl8152_disable;
9102 ops->up = rtl8152_up;
9103 ops->down = rtl8152_down;
9104 ops->unload = rtl8152_unload;
9105 ops->eee_get = r8152_get_eee;
9106 ops->eee_set = r8152_set_eee;
9107 ops->in_nway = rtl8152_in_nway;
9108 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
9109 ops->autosuspend_en = rtl_runtime_suspend_enable;
9110 tp->rx_buf_sz = 16 * 1024;
9111 tp->eee_en = true;
9112 tp->eee_adv = MDIO_EEE_100TX;
9113 break;
9114
9115 case RTL_VER_03:
9116 case RTL_VER_04:
9117 case RTL_VER_05:
9118 case RTL_VER_06:
9119 ops->init = r8153_init;
9120 ops->enable = rtl8153_enable;
9121 ops->disable = rtl8153_disable;
9122 ops->up = rtl8153_up;
9123 ops->down = rtl8153_down;
9124 ops->unload = rtl8153_unload;
9125 ops->eee_get = r8153_get_eee;
9126 ops->eee_set = r8152_set_eee;
9127 ops->in_nway = rtl8153_in_nway;
9128 ops->hw_phy_cfg = r8153_hw_phy_cfg;
9129 ops->autosuspend_en = rtl8153_runtime_enable;
9130 ops->change_mtu = rtl8153_change_mtu;
9131 if (tp->udev->speed < USB_SPEED_SUPER)
9132 tp->rx_buf_sz = 16 * 1024;
9133 else
9134 tp->rx_buf_sz = 32 * 1024;
9135 tp->eee_en = true;
9136 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9137 break;
9138
9139 case RTL_VER_08:
9140 case RTL_VER_09:
9141 ops->init = r8153b_init;
9142 ops->enable = rtl8153_enable;
9143 ops->disable = rtl8153_disable;
9144 ops->up = rtl8153b_up;
9145 ops->down = rtl8153b_down;
9146 ops->unload = rtl8153b_unload;
9147 ops->eee_get = r8153_get_eee;
9148 ops->eee_set = r8152_set_eee;
9149 ops->in_nway = rtl8153_in_nway;
9150 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
9151 ops->autosuspend_en = rtl8153b_runtime_enable;
9152 ops->change_mtu = rtl8153_change_mtu;
9153 tp->rx_buf_sz = 32 * 1024;
9154 tp->eee_en = true;
9155 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9156 break;
9157
9158 case RTL_VER_11:
9159 tp->eee_en = true;
9160 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9161 fallthrough;
9162 case RTL_VER_10:
9163 ops->init = r8156_init;
9164 ops->enable = rtl8156_enable;
9165 ops->disable = rtl8153_disable;
9166 ops->up = rtl8156_up;
9167 ops->down = rtl8156_down;
9168 ops->unload = rtl8153_unload;
9169 ops->eee_get = r8153_get_eee;
9170 ops->eee_set = r8152_set_eee;
9171 ops->in_nway = rtl8153_in_nway;
9172 ops->hw_phy_cfg = r8156_hw_phy_cfg;
9173 ops->autosuspend_en = rtl8156_runtime_enable;
9174 ops->change_mtu = rtl8156_change_mtu;
9175 tp->rx_buf_sz = 48 * 1024;
9176 tp->support_2500full = 1;
9177 break;
9178
9179 case RTL_VER_12:
9180 case RTL_VER_13:
9181 tp->support_2500full = 1;
9182 fallthrough;
9183 case RTL_VER_15:
9184 tp->eee_en = true;
9185 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9186 ops->init = r8156b_init;
9187 ops->enable = rtl8156b_enable;
9188 ops->disable = rtl8153_disable;
9189 ops->up = rtl8156_up;
9190 ops->down = rtl8156_down;
9191 ops->unload = rtl8153_unload;
9192 ops->eee_get = r8153_get_eee;
9193 ops->eee_set = r8152_set_eee;
9194 ops->in_nway = rtl8153_in_nway;
9195 ops->hw_phy_cfg = r8156b_hw_phy_cfg;
9196 ops->autosuspend_en = rtl8156_runtime_enable;
9197 ops->change_mtu = rtl8156_change_mtu;
9198 tp->rx_buf_sz = 48 * 1024;
9199 break;
9200
9201 case RTL_VER_14:
9202 ops->init = r8153c_init;
9203 ops->enable = rtl8153_enable;
9204 ops->disable = rtl8153_disable;
9205 ops->up = rtl8153c_up;
9206 ops->down = rtl8153b_down;
9207 ops->unload = rtl8153_unload;
9208 ops->eee_get = r8153_get_eee;
9209 ops->eee_set = r8152_set_eee;
9210 ops->in_nway = rtl8153_in_nway;
9211 ops->hw_phy_cfg = r8153c_hw_phy_cfg;
9212 ops->autosuspend_en = rtl8153c_runtime_enable;
9213 ops->change_mtu = rtl8153c_change_mtu;
9214 tp->rx_buf_sz = 32 * 1024;
9215 tp->eee_en = true;
9216 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9217 break;
9218
9219 default:
9220 ret = -ENODEV;
9221 dev_err(&tp->intf->dev, "Unknown Device\n");
9222 break;
9223 }
9224
9225 return ret;
9226 }
9227
9228 #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
9229 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
9230 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
9231 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
9232 #define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
9233 #define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw"
9234 #define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw"
9235
9236 MODULE_FIRMWARE(FIRMWARE_8153A_2);
9237 MODULE_FIRMWARE(FIRMWARE_8153A_3);
9238 MODULE_FIRMWARE(FIRMWARE_8153A_4);
9239 MODULE_FIRMWARE(FIRMWARE_8153B_2);
9240 MODULE_FIRMWARE(FIRMWARE_8153C_1);
9241 MODULE_FIRMWARE(FIRMWARE_8156A_2);
9242 MODULE_FIRMWARE(FIRMWARE_8156B_2);
9243
rtl_fw_init(struct r8152 * tp)9244 static int rtl_fw_init(struct r8152 *tp)
9245 {
9246 struct rtl_fw *rtl_fw = &tp->rtl_fw;
9247
9248 switch (tp->version) {
9249 case RTL_VER_04:
9250 rtl_fw->fw_name = FIRMWARE_8153A_2;
9251 rtl_fw->pre_fw = r8153_pre_firmware_1;
9252 rtl_fw->post_fw = r8153_post_firmware_1;
9253 break;
9254 case RTL_VER_05:
9255 rtl_fw->fw_name = FIRMWARE_8153A_3;
9256 rtl_fw->pre_fw = r8153_pre_firmware_2;
9257 rtl_fw->post_fw = r8153_post_firmware_2;
9258 break;
9259 case RTL_VER_06:
9260 rtl_fw->fw_name = FIRMWARE_8153A_4;
9261 rtl_fw->post_fw = r8153_post_firmware_3;
9262 break;
9263 case RTL_VER_09:
9264 rtl_fw->fw_name = FIRMWARE_8153B_2;
9265 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9266 rtl_fw->post_fw = r8153b_post_firmware_1;
9267 break;
9268 case RTL_VER_11:
9269 rtl_fw->fw_name = FIRMWARE_8156A_2;
9270 rtl_fw->post_fw = r8156a_post_firmware_1;
9271 break;
9272 case RTL_VER_13:
9273 case RTL_VER_15:
9274 rtl_fw->fw_name = FIRMWARE_8156B_2;
9275 break;
9276 case RTL_VER_14:
9277 rtl_fw->fw_name = FIRMWARE_8153C_1;
9278 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9279 rtl_fw->post_fw = r8153c_post_firmware_1;
9280 break;
9281 default:
9282 break;
9283 }
9284
9285 return 0;
9286 }
9287
rtl8152_get_version(struct usb_interface * intf)9288 u8 rtl8152_get_version(struct usb_interface *intf)
9289 {
9290 struct usb_device *udev = interface_to_usbdev(intf);
9291 u32 ocp_data = 0;
9292 __le32 *tmp;
9293 u8 version;
9294 int ret;
9295
9296 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
9297 if (!tmp)
9298 return 0;
9299
9300 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
9301 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
9302 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
9303 if (ret > 0)
9304 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
9305
9306 kfree(tmp);
9307
9308 switch (ocp_data) {
9309 case 0x4c00:
9310 version = RTL_VER_01;
9311 break;
9312 case 0x4c10:
9313 version = RTL_VER_02;
9314 break;
9315 case 0x5c00:
9316 version = RTL_VER_03;
9317 break;
9318 case 0x5c10:
9319 version = RTL_VER_04;
9320 break;
9321 case 0x5c20:
9322 version = RTL_VER_05;
9323 break;
9324 case 0x5c30:
9325 version = RTL_VER_06;
9326 break;
9327 case 0x4800:
9328 version = RTL_VER_07;
9329 break;
9330 case 0x6000:
9331 version = RTL_VER_08;
9332 break;
9333 case 0x6010:
9334 version = RTL_VER_09;
9335 break;
9336 case 0x7010:
9337 version = RTL_TEST_01;
9338 break;
9339 case 0x7020:
9340 version = RTL_VER_10;
9341 break;
9342 case 0x7030:
9343 version = RTL_VER_11;
9344 break;
9345 case 0x7400:
9346 version = RTL_VER_12;
9347 break;
9348 case 0x7410:
9349 version = RTL_VER_13;
9350 break;
9351 case 0x6400:
9352 version = RTL_VER_14;
9353 break;
9354 case 0x7420:
9355 version = RTL_VER_15;
9356 break;
9357 default:
9358 version = RTL_VER_UNKNOWN;
9359 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
9360 break;
9361 }
9362
9363 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
9364
9365 return version;
9366 }
9367 EXPORT_SYMBOL_GPL(rtl8152_get_version);
9368
rtl8152_probe(struct usb_interface * intf,const struct usb_device_id * id)9369 static int rtl8152_probe(struct usb_interface *intf,
9370 const struct usb_device_id *id)
9371 {
9372 struct usb_device *udev = interface_to_usbdev(intf);
9373 u8 version = rtl8152_get_version(intf);
9374 struct r8152 *tp;
9375 struct net_device *netdev;
9376 int ret;
9377
9378 if (version == RTL_VER_UNKNOWN)
9379 return -ENODEV;
9380
9381 if (!rtl_vendor_mode(intf))
9382 return -ENODEV;
9383
9384 if (intf->cur_altsetting->desc.bNumEndpoints < 3)
9385 return -ENODEV;
9386
9387 usb_reset_device(udev);
9388 netdev = alloc_etherdev(sizeof(struct r8152));
9389 if (!netdev) {
9390 dev_err(&intf->dev, "Out of memory\n");
9391 return -ENOMEM;
9392 }
9393
9394 SET_NETDEV_DEV(netdev, &intf->dev);
9395 tp = netdev_priv(netdev);
9396 tp->msg_enable = 0x7FFF;
9397
9398 tp->udev = udev;
9399 tp->netdev = netdev;
9400 tp->intf = intf;
9401 tp->version = version;
9402
9403 switch (version) {
9404 case RTL_VER_01:
9405 case RTL_VER_02:
9406 case RTL_VER_07:
9407 tp->mii.supports_gmii = 0;
9408 break;
9409 default:
9410 tp->mii.supports_gmii = 1;
9411 break;
9412 }
9413
9414 ret = rtl_ops_init(tp);
9415 if (ret)
9416 goto out;
9417
9418 rtl_fw_init(tp);
9419
9420 mutex_init(&tp->control);
9421 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
9422 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
9423 tasklet_setup(&tp->tx_tl, bottom_half);
9424 tasklet_disable(&tp->tx_tl);
9425
9426 netdev->netdev_ops = &rtl8152_netdev_ops;
9427 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
9428
9429 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9430 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
9431 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
9432 NETIF_F_HW_VLAN_CTAG_TX;
9433 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9434 NETIF_F_TSO | NETIF_F_FRAGLIST |
9435 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
9436 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
9437 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
9438 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
9439 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
9440
9441 if (tp->version == RTL_VER_01) {
9442 netdev->features &= ~NETIF_F_RXCSUM;
9443 netdev->hw_features &= ~NETIF_F_RXCSUM;
9444 }
9445
9446 if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
9447 switch (le16_to_cpu(udev->descriptor.idProduct)) {
9448 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
9449 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
9450 tp->lenovo_macpassthru = 1;
9451 }
9452 }
9453
9454 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
9455 (!strcmp(udev->serial, "000001000000") ||
9456 !strcmp(udev->serial, "000002000000"))) {
9457 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
9458 tp->dell_tb_rx_agg_bug = 1;
9459 }
9460
9461 netdev->ethtool_ops = &ops;
9462 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
9463
9464 /* MTU range: 68 - 1500 or 9194 */
9465 netdev->min_mtu = ETH_MIN_MTU;
9466 switch (tp->version) {
9467 case RTL_VER_03:
9468 case RTL_VER_04:
9469 case RTL_VER_05:
9470 case RTL_VER_06:
9471 case RTL_VER_08:
9472 case RTL_VER_09:
9473 case RTL_VER_14:
9474 netdev->max_mtu = size_to_mtu(9 * 1024);
9475 break;
9476 case RTL_VER_10:
9477 case RTL_VER_11:
9478 netdev->max_mtu = size_to_mtu(15 * 1024);
9479 break;
9480 case RTL_VER_12:
9481 case RTL_VER_13:
9482 case RTL_VER_15:
9483 netdev->max_mtu = size_to_mtu(16 * 1024);
9484 break;
9485 case RTL_VER_01:
9486 case RTL_VER_02:
9487 case RTL_VER_07:
9488 default:
9489 netdev->max_mtu = ETH_DATA_LEN;
9490 break;
9491 }
9492
9493 tp->mii.dev = netdev;
9494 tp->mii.mdio_read = read_mii_word;
9495 tp->mii.mdio_write = write_mii_word;
9496 tp->mii.phy_id_mask = 0x3f;
9497 tp->mii.reg_num_mask = 0x1f;
9498 tp->mii.phy_id = R8152_PHY_ID;
9499
9500 tp->autoneg = AUTONEG_ENABLE;
9501 tp->speed = SPEED_100;
9502 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
9503 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
9504 if (tp->mii.supports_gmii) {
9505 if (tp->support_2500full &&
9506 tp->udev->speed >= USB_SPEED_SUPER) {
9507 tp->speed = SPEED_2500;
9508 tp->advertising |= RTL_ADVERTISED_2500_FULL;
9509 } else {
9510 tp->speed = SPEED_1000;
9511 }
9512 tp->advertising |= RTL_ADVERTISED_1000_FULL;
9513 }
9514 tp->duplex = DUPLEX_FULL;
9515
9516 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
9517 tp->rx_pending = 10 * RTL8152_MAX_RX;
9518
9519 intf->needs_remote_wakeup = 1;
9520
9521 if (!rtl_can_wakeup(tp))
9522 __rtl_set_wol(tp, 0);
9523 else
9524 tp->saved_wolopts = __rtl_get_wol(tp);
9525
9526 tp->rtl_ops.init(tp);
9527 #if IS_BUILTIN(CONFIG_USB_RTL8152)
9528 /* Retry in case request_firmware() is not ready yet. */
9529 tp->rtl_fw.retry = true;
9530 #endif
9531 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
9532 set_ethernet_addr(tp);
9533
9534 usb_set_intfdata(intf, tp);
9535
9536 if (tp->support_2500full)
9537 netif_napi_add(netdev, &tp->napi, r8152_poll, 256);
9538 else
9539 netif_napi_add(netdev, &tp->napi, r8152_poll, 64);
9540
9541 ret = register_netdev(netdev);
9542 if (ret != 0) {
9543 dev_err(&intf->dev, "couldn't register the device\n");
9544 goto out1;
9545 }
9546
9547 if (tp->saved_wolopts)
9548 device_set_wakeup_enable(&udev->dev, true);
9549 else
9550 device_set_wakeup_enable(&udev->dev, false);
9551
9552 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
9553
9554 return 0;
9555
9556 out1:
9557 tasklet_kill(&tp->tx_tl);
9558 usb_set_intfdata(intf, NULL);
9559 out:
9560 free_netdev(netdev);
9561 return ret;
9562 }
9563
rtl8152_disconnect(struct usb_interface * intf)9564 static void rtl8152_disconnect(struct usb_interface *intf)
9565 {
9566 struct r8152 *tp = usb_get_intfdata(intf);
9567
9568 usb_set_intfdata(intf, NULL);
9569 if (tp) {
9570 rtl_set_unplug(tp);
9571
9572 unregister_netdev(tp->netdev);
9573 tasklet_kill(&tp->tx_tl);
9574 cancel_delayed_work_sync(&tp->hw_phy_work);
9575 if (tp->rtl_ops.unload)
9576 tp->rtl_ops.unload(tp);
9577 rtl8152_release_firmware(tp);
9578 free_netdev(tp->netdev);
9579 }
9580 }
9581
9582 #define REALTEK_USB_DEVICE(vend, prod) { \
9583 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC), \
9584 }, \
9585 { \
9586 USB_DEVICE_AND_INTERFACE_INFO(vend, prod, USB_CLASS_COMM, \
9587 USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), \
9588 }
9589
9590 /* table of devices that work with this driver */
9591 static const struct usb_device_id rtl8152_table[] = {
9592 /* Realtek */
9593 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050),
9594 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053),
9595 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152),
9596 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153),
9597 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155),
9598 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156),
9599
9600 /* Microsoft */
9601 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab),
9602 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6),
9603 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927),
9604 REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101),
9605 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f),
9606 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062),
9607 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069),
9608 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082),
9609 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205),
9610 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c),
9611 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214),
9612 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e),
9613 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387),
9614 REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041),
9615 REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff),
9616 REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601),
9617 {}
9618 };
9619
9620 MODULE_DEVICE_TABLE(usb, rtl8152_table);
9621
9622 static struct usb_driver rtl8152_driver = {
9623 .name = MODULENAME,
9624 .id_table = rtl8152_table,
9625 .probe = rtl8152_probe,
9626 .disconnect = rtl8152_disconnect,
9627 .suspend = rtl8152_suspend,
9628 .resume = rtl8152_resume,
9629 .reset_resume = rtl8152_reset_resume,
9630 .pre_reset = rtl8152_pre_reset,
9631 .post_reset = rtl8152_post_reset,
9632 .supports_autosuspend = 1,
9633 .disable_hub_initiated_lpm = 1,
9634 };
9635
9636 module_usb_driver(rtl8152_driver);
9637
9638 MODULE_AUTHOR(DRIVER_AUTHOR);
9639 MODULE_DESCRIPTION(DRIVER_DESC);
9640 MODULE_LICENSE("GPL");
9641 MODULE_VERSION(DRIVER_VERSION);
9642