1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Cedrus VPU driver
4 *
5 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
6 * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
7 * Copyright (C) 2018 Bootlin
8 *
9 * Based on the vim2m driver, that is:
10 *
11 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
12 * Pawel Osciak, <pawel@osciak.com>
13 * Marek Szyprowski, <m.szyprowski@samsung.com>
14 */
15
16 #include <linux/platform_device.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/of_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/interrupt.h>
21 #include <linux/clk.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regmap.h>
24 #include <linux/reset.h>
25 #include <linux/soc/sunxi/sunxi_sram.h>
26
27 #include <media/videobuf2-core.h>
28 #include <media/v4l2-mem2mem.h>
29
30 #include "cedrus.h"
31 #include "cedrus_hw.h"
32 #include "cedrus_regs.h"
33
cedrus_engine_enable(struct cedrus_ctx * ctx,enum cedrus_codec codec)34 int cedrus_engine_enable(struct cedrus_ctx *ctx, enum cedrus_codec codec)
35 {
36 u32 reg = 0;
37
38 /*
39 * FIXME: This is only valid on 32-bits DDR's, we should test
40 * it on the A13/A33.
41 */
42 reg |= VE_MODE_REC_WR_MODE_2MB;
43 reg |= VE_MODE_DDR_MODE_BW_128;
44
45 switch (codec) {
46 case CEDRUS_CODEC_MPEG2:
47 reg |= VE_MODE_DEC_MPEG;
48 break;
49
50 /* H.264 and VP8 both use the same decoding mode bit. */
51 case CEDRUS_CODEC_H264:
52 case CEDRUS_CODEC_VP8:
53 reg |= VE_MODE_DEC_H264;
54 break;
55
56 case CEDRUS_CODEC_H265:
57 reg |= VE_MODE_DEC_H265;
58 break;
59
60 default:
61 return -EINVAL;
62 }
63
64 if (ctx->src_fmt.width == 4096)
65 reg |= VE_MODE_PIC_WIDTH_IS_4096;
66 if (ctx->src_fmt.width > 2048)
67 reg |= VE_MODE_PIC_WIDTH_MORE_2048;
68
69 cedrus_write(ctx->dev, VE_MODE, reg);
70
71 return 0;
72 }
73
cedrus_engine_disable(struct cedrus_dev * dev)74 void cedrus_engine_disable(struct cedrus_dev *dev)
75 {
76 cedrus_write(dev, VE_MODE, VE_MODE_DISABLED);
77 }
78
cedrus_dst_format_set(struct cedrus_dev * dev,struct v4l2_pix_format * fmt)79 void cedrus_dst_format_set(struct cedrus_dev *dev,
80 struct v4l2_pix_format *fmt)
81 {
82 unsigned int width = fmt->width;
83 unsigned int height = fmt->height;
84 u32 chroma_size;
85 u32 reg;
86
87 switch (fmt->pixelformat) {
88 case V4L2_PIX_FMT_NV12:
89 chroma_size = ALIGN(width, 16) * ALIGN(height, 16) / 2;
90
91 reg = VE_PRIMARY_OUT_FMT_NV12;
92 cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg);
93
94 reg = chroma_size / 2;
95 cedrus_write(dev, VE_PRIMARY_CHROMA_BUF_LEN, reg);
96
97 reg = VE_PRIMARY_FB_LINE_STRIDE_LUMA(ALIGN(width, 16)) |
98 VE_PRIMARY_FB_LINE_STRIDE_CHROMA(ALIGN(width, 16) / 2);
99 cedrus_write(dev, VE_PRIMARY_FB_LINE_STRIDE, reg);
100
101 break;
102 case V4L2_PIX_FMT_SUNXI_TILED_NV12:
103 default:
104 reg = VE_PRIMARY_OUT_FMT_TILED_32_NV12;
105 cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg);
106
107 reg = VE_SECONDARY_OUT_FMT_TILED_32_NV12;
108 cedrus_write(dev, VE_CHROMA_BUF_LEN, reg);
109
110 break;
111 }
112 }
113
cedrus_irq(int irq,void * data)114 static irqreturn_t cedrus_irq(int irq, void *data)
115 {
116 struct cedrus_dev *dev = data;
117 struct cedrus_ctx *ctx;
118 enum vb2_buffer_state state;
119 enum cedrus_irq_status status;
120
121 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
122 if (!ctx) {
123 v4l2_err(&dev->v4l2_dev,
124 "Instance released before the end of transaction\n");
125 return IRQ_NONE;
126 }
127
128 status = dev->dec_ops[ctx->current_codec]->irq_status(ctx);
129 if (status == CEDRUS_IRQ_NONE)
130 return IRQ_NONE;
131
132 dev->dec_ops[ctx->current_codec]->irq_disable(ctx);
133 dev->dec_ops[ctx->current_codec]->irq_clear(ctx);
134
135 if (status == CEDRUS_IRQ_ERROR)
136 state = VB2_BUF_STATE_ERROR;
137 else
138 state = VB2_BUF_STATE_DONE;
139
140 v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx,
141 state);
142
143 return IRQ_HANDLED;
144 }
145
cedrus_hw_suspend(struct device * device)146 int cedrus_hw_suspend(struct device *device)
147 {
148 struct cedrus_dev *dev = dev_get_drvdata(device);
149
150 reset_control_assert(dev->rstc);
151
152 clk_disable_unprepare(dev->ram_clk);
153 clk_disable_unprepare(dev->mod_clk);
154 clk_disable_unprepare(dev->ahb_clk);
155
156 return 0;
157 }
158
cedrus_hw_resume(struct device * device)159 int cedrus_hw_resume(struct device *device)
160 {
161 struct cedrus_dev *dev = dev_get_drvdata(device);
162 int ret;
163
164 ret = clk_prepare_enable(dev->ahb_clk);
165 if (ret) {
166 dev_err(dev->dev, "Failed to enable AHB clock\n");
167
168 return ret;
169 }
170
171 ret = clk_prepare_enable(dev->mod_clk);
172 if (ret) {
173 dev_err(dev->dev, "Failed to enable MOD clock\n");
174
175 goto err_ahb_clk;
176 }
177
178 ret = clk_prepare_enable(dev->ram_clk);
179 if (ret) {
180 dev_err(dev->dev, "Failed to enable RAM clock\n");
181
182 goto err_mod_clk;
183 }
184
185 ret = reset_control_reset(dev->rstc);
186 if (ret) {
187 dev_err(dev->dev, "Failed to apply reset\n");
188
189 goto err_ram_clk;
190 }
191
192 return 0;
193
194 err_ram_clk:
195 clk_disable_unprepare(dev->ram_clk);
196 err_mod_clk:
197 clk_disable_unprepare(dev->mod_clk);
198 err_ahb_clk:
199 clk_disable_unprepare(dev->ahb_clk);
200
201 return ret;
202 }
203
cedrus_hw_probe(struct cedrus_dev * dev)204 int cedrus_hw_probe(struct cedrus_dev *dev)
205 {
206 const struct cedrus_variant *variant;
207 int irq_dec;
208 int ret;
209
210 variant = of_device_get_match_data(dev->dev);
211 if (!variant)
212 return -EINVAL;
213
214 dev->capabilities = variant->capabilities;
215
216 irq_dec = platform_get_irq(dev->pdev, 0);
217 if (irq_dec <= 0)
218 return irq_dec;
219 ret = devm_request_irq(dev->dev, irq_dec, cedrus_irq,
220 0, dev_name(dev->dev), dev);
221 if (ret) {
222 dev_err(dev->dev, "Failed to request IRQ\n");
223
224 return ret;
225 }
226
227 ret = of_reserved_mem_device_init(dev->dev);
228 if (ret && ret != -ENODEV) {
229 dev_err(dev->dev, "Failed to reserve memory\n");
230
231 return ret;
232 }
233
234 ret = sunxi_sram_claim(dev->dev);
235 if (ret) {
236 dev_err(dev->dev, "Failed to claim SRAM\n");
237
238 goto err_mem;
239 }
240
241 dev->ahb_clk = devm_clk_get(dev->dev, "ahb");
242 if (IS_ERR(dev->ahb_clk)) {
243 dev_err(dev->dev, "Failed to get AHB clock\n");
244
245 ret = PTR_ERR(dev->ahb_clk);
246 goto err_sram;
247 }
248
249 dev->mod_clk = devm_clk_get(dev->dev, "mod");
250 if (IS_ERR(dev->mod_clk)) {
251 dev_err(dev->dev, "Failed to get MOD clock\n");
252
253 ret = PTR_ERR(dev->mod_clk);
254 goto err_sram;
255 }
256
257 dev->ram_clk = devm_clk_get(dev->dev, "ram");
258 if (IS_ERR(dev->ram_clk)) {
259 dev_err(dev->dev, "Failed to get RAM clock\n");
260
261 ret = PTR_ERR(dev->ram_clk);
262 goto err_sram;
263 }
264
265 dev->rstc = devm_reset_control_get(dev->dev, NULL);
266 if (IS_ERR(dev->rstc)) {
267 dev_err(dev->dev, "Failed to get reset control\n");
268
269 ret = PTR_ERR(dev->rstc);
270 goto err_sram;
271 }
272
273 dev->base = devm_platform_ioremap_resource(dev->pdev, 0);
274 if (IS_ERR(dev->base)) {
275 dev_err(dev->dev, "Failed to map registers\n");
276
277 ret = PTR_ERR(dev->base);
278 goto err_sram;
279 }
280
281 ret = clk_set_rate(dev->mod_clk, variant->mod_rate);
282 if (ret) {
283 dev_err(dev->dev, "Failed to set clock rate\n");
284
285 goto err_sram;
286 }
287
288 pm_runtime_enable(dev->dev);
289 if (!pm_runtime_enabled(dev->dev)) {
290 ret = cedrus_hw_resume(dev->dev);
291 if (ret)
292 goto err_pm;
293 }
294
295 return 0;
296
297 err_pm:
298 pm_runtime_disable(dev->dev);
299 err_sram:
300 sunxi_sram_release(dev->dev);
301 err_mem:
302 of_reserved_mem_device_release(dev->dev);
303
304 return ret;
305 }
306
cedrus_hw_remove(struct cedrus_dev * dev)307 void cedrus_hw_remove(struct cedrus_dev *dev)
308 {
309 pm_runtime_disable(dev->dev);
310 if (!pm_runtime_status_suspended(dev->dev))
311 cedrus_hw_suspend(dev->dev);
312
313 sunxi_sram_release(dev->dev);
314
315 of_reserved_mem_device_release(dev->dev);
316 }
317