1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Zoran zr36057/zr36067 PCI controller driver, for the
4 * Pinnacle/Miro DC10/DC10+/DC30/DC30+, Iomega Buz, Linux
5 * Media Labs LML33/LML33R10.
6 *
7 * This part handles device access (PCI/I2C/codec/...)
8 *
9 * Copyright (C) 2000 Serguei Miridonov <mirsev@cicese.mx>
10 */
11
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15
16 #include <linux/interrupt.h>
17 #include <linux/i2c.h>
18 #include <linux/i2c-algo-bit.h>
19 #include <linux/videodev2.h>
20 #include <media/v4l2-common.h>
21 #include <linux/spinlock.h>
22
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/wait.h>
26 #include <linux/dma-mapping.h>
27
28 #include <linux/io.h>
29
30 #include "videocodec.h"
31 #include "zoran.h"
32 #include "zoran_device.h"
33 #include "zoran_card.h"
34
35 #define IRQ_MASK (ZR36057_ISR_GIRQ0 | \
36 ZR36057_ISR_GIRQ1 | \
37 ZR36057_ISR_JPEG_REP_IRQ)
38
39 static bool lml33dpath; /* default = 0
40 * 1 will use digital path in capture
41 * mode instead of analog. It can be
42 * used for picture adjustments using
43 * tool like xawtv while watching image
44 * on TV monitor connected to the output.
45 * However, due to absence of 75 Ohm
46 * load on Bt819 input, there will be
47 * some image imperfections
48 */
49
50 module_param(lml33dpath, bool, 0644);
51 MODULE_PARM_DESC(lml33dpath, "Use digital path capture mode (on LML33 cards)");
52
53 int zr_set_buf(struct zoran *zr);
54 /*
55 * initialize video front end
56 */
zr36057_init_vfe(struct zoran * zr)57 static void zr36057_init_vfe(struct zoran *zr)
58 {
59 u32 reg;
60
61 reg = btread(ZR36057_VFESPFR);
62 reg |= ZR36057_VFESPFR_LITTLE_ENDIAN;
63 reg &= ~ZR36057_VFESPFR_VCLK_POL;
64 reg |= ZR36057_VFESPFR_EXT_FL;
65 reg |= ZR36057_VFESPFR_TOP_FIELD;
66 btwrite(reg, ZR36057_VFESPFR);
67 reg = btread(ZR36057_VDCR);
68 if (pci_pci_problems & PCIPCI_TRITON)
69 // || zr->revision < 1) // Revision 1 has also Triton support
70 reg &= ~ZR36057_VDCR_TRITON;
71 else
72 reg |= ZR36057_VDCR_TRITON;
73 btwrite(reg, ZR36057_VDCR);
74 }
75
76 /*
77 * General Purpose I/O and Guest bus access
78 */
79
80 /*
81 * This is a bit tricky. When a board lacks a GPIO function, the corresponding
82 * GPIO bit number in the card_info structure is set to 0.
83 */
84
GPIO(struct zoran * zr,int bit,unsigned int value)85 void GPIO(struct zoran *zr, int bit, unsigned int value)
86 {
87 u32 reg;
88 u32 mask;
89
90 /* Make sure the bit number is legal
91 * A bit number of -1 (lacking) gives a mask of 0,
92 * making it harmless
93 */
94 mask = (1 << (24 + bit)) & 0xff000000;
95 reg = btread(ZR36057_GPPGCR1) & ~mask;
96 if (value)
97 reg |= mask;
98
99 btwrite(reg, ZR36057_GPPGCR1);
100 udelay(1);
101 }
102
103 /*
104 * Wait til post office is no longer busy
105 */
106
post_office_wait(struct zoran * zr)107 int post_office_wait(struct zoran *zr)
108 {
109 u32 por;
110
111 // while (((por = btread(ZR36057_POR)) & (ZR36057_POR_PO_PEN | ZR36057_POR_PO_TIME)) == ZR36057_POR_PO_PEN) {
112 while ((por = btread(ZR36057_POR)) & ZR36057_POR_PO_PEN) {
113 /* wait for something to happen */
114 /* TODO add timeout */
115 }
116 if ((por & ZR36057_POR_PO_TIME) && !zr->card.gws_not_connected) {
117 /* In LML33/BUZ \GWS line is not connected, so it has always timeout set */
118 pci_info(zr->pci_dev, "pop timeout %08x\n", por);
119 return -1;
120 }
121
122 return 0;
123 }
124
post_office_write(struct zoran * zr,unsigned int guest,unsigned int reg,unsigned int value)125 int post_office_write(struct zoran *zr, unsigned int guest,
126 unsigned int reg, unsigned int value)
127 {
128 u32 por;
129
130 por =
131 ZR36057_POR_PO_DIR | ZR36057_POR_PO_TIME | ((guest & 7) << 20) |
132 ((reg & 7) << 16) | (value & 0xFF);
133 btwrite(por, ZR36057_POR);
134
135 return post_office_wait(zr);
136 }
137
post_office_read(struct zoran * zr,unsigned int guest,unsigned int reg)138 int post_office_read(struct zoran *zr, unsigned int guest, unsigned int reg)
139 {
140 u32 por;
141
142 por = ZR36057_POR_PO_TIME | ((guest & 7) << 20) | ((reg & 7) << 16);
143 btwrite(por, ZR36057_POR);
144 if (post_office_wait(zr) < 0)
145 return -1;
146
147 return btread(ZR36057_POR) & 0xFF;
148 }
149
150 /*
151 * detect guests
152 */
153
dump_guests(struct zoran * zr)154 static void dump_guests(struct zoran *zr)
155 {
156 if (zr36067_debug > 2) {
157 int i, guest[8];
158
159 /* do not print random data */
160 guest[0] = 0;
161
162 for (i = 1; i < 8; i++) /* Don't read jpeg codec here */
163 guest[i] = post_office_read(zr, i, 0);
164
165 pci_info(zr->pci_dev, "Guests: %*ph\n", 8, guest);
166 }
167 }
168
detect_guest_activity(struct zoran * zr)169 void detect_guest_activity(struct zoran *zr)
170 {
171 int timeout, i, j, res, guest[8], guest0[8], change[8][3];
172 ktime_t t0, t1;
173
174 /* do not print random data */
175 guest[0] = 0;
176 guest0[0] = 0;
177
178 dump_guests(zr);
179 pci_info(zr->pci_dev, "Detecting guests activity, please wait...\n");
180 for (i = 1; i < 8; i++) /* Don't read jpeg codec here */
181 guest0[i] = guest[i] = post_office_read(zr, i, 0);
182
183 timeout = 0;
184 j = 0;
185 t0 = ktime_get();
186 while (timeout < 10000) {
187 udelay(10);
188 timeout++;
189 for (i = 1; (i < 8) && (j < 8); i++) {
190 res = post_office_read(zr, i, 0);
191 if (res != guest[i]) {
192 t1 = ktime_get();
193 change[j][0] = ktime_to_us(ktime_sub(t1, t0));
194 t0 = t1;
195 change[j][1] = i;
196 change[j][2] = res;
197 j++;
198 guest[i] = res;
199 }
200 }
201 if (j >= 8)
202 break;
203 }
204
205 pci_info(zr->pci_dev, "Guests: %*ph\n", 8, guest0);
206
207 if (j == 0) {
208 pci_info(zr->pci_dev, "No activity detected.\n");
209 return;
210 }
211 for (i = 0; i < j; i++)
212 pci_info(zr->pci_dev, "%6d: %d => 0x%02x\n", change[i][0], change[i][1], change[i][2]);
213 }
214
215 /*
216 * JPEG Codec access
217 */
218
jpeg_codec_sleep(struct zoran * zr,int sleep)219 void jpeg_codec_sleep(struct zoran *zr, int sleep)
220 {
221 GPIO(zr, zr->card.gpio[ZR_GPIO_JPEG_SLEEP], !sleep);
222 if (!sleep) {
223 pci_dbg(zr->pci_dev, "%s() - wake GPIO=0x%08x\n", __func__, btread(ZR36057_GPPGCR1));
224 udelay(500);
225 } else {
226 pci_dbg(zr->pci_dev, "%s() - sleep GPIO=0x%08x\n", __func__, btread(ZR36057_GPPGCR1));
227 udelay(2);
228 }
229 }
230
jpeg_codec_reset(struct zoran * zr)231 int jpeg_codec_reset(struct zoran *zr)
232 {
233 /* Take the codec out of sleep */
234 jpeg_codec_sleep(zr, 0);
235
236 if (zr->card.gpcs[GPCS_JPEG_RESET] != 0xff) {
237 post_office_write(zr, zr->card.gpcs[GPCS_JPEG_RESET], 0,
238 0);
239 udelay(2);
240 } else {
241 GPIO(zr, zr->card.gpio[ZR_GPIO_JPEG_RESET], 0);
242 udelay(2);
243 GPIO(zr, zr->card.gpio[ZR_GPIO_JPEG_RESET], 1);
244 udelay(2);
245 }
246
247 return 0;
248 }
249
250 /*
251 * Set the registers for the size we have specified. Don't bother
252 * trying to understand this without the ZR36057 manual in front of
253 * you [AC].
254 */
zr36057_adjust_vfe(struct zoran * zr,enum zoran_codec_mode mode)255 static void zr36057_adjust_vfe(struct zoran *zr, enum zoran_codec_mode mode)
256 {
257 u32 reg;
258
259 switch (mode) {
260 case BUZ_MODE_MOTION_DECOMPRESS:
261 btand(~ZR36057_VFESPFR_EXT_FL, ZR36057_VFESPFR);
262 reg = btread(ZR36057_VFEHCR);
263 if ((reg & (1 << 10)) && zr->card.type != LML33R10)
264 reg += ((1 << 10) | 1);
265
266 btwrite(reg, ZR36057_VFEHCR);
267 break;
268 case BUZ_MODE_MOTION_COMPRESS:
269 case BUZ_MODE_IDLE:
270 default:
271 if ((zr->norm & V4L2_STD_NTSC) ||
272 (zr->card.type == LML33R10 &&
273 (zr->norm & V4L2_STD_PAL)))
274 btand(~ZR36057_VFESPFR_EXT_FL, ZR36057_VFESPFR);
275 else
276 btor(ZR36057_VFESPFR_EXT_FL, ZR36057_VFESPFR);
277 reg = btread(ZR36057_VFEHCR);
278 if (!(reg & (1 << 10)) && zr->card.type != LML33R10)
279 reg -= ((1 << 10) | 1);
280
281 btwrite(reg, ZR36057_VFEHCR);
282 break;
283 }
284 }
285
286 /*
287 * set geometry
288 */
289
zr36057_set_vfe(struct zoran * zr,int video_width,int video_height,const struct zoran_format * format)290 static void zr36057_set_vfe(struct zoran *zr, int video_width, int video_height,
291 const struct zoran_format *format)
292 {
293 const struct tvnorm *tvn;
294 unsigned int h_start, h_end, v_start, v_end;
295 unsigned int disp_mode;
296 unsigned int vid_win_wid, vid_win_ht;
297 unsigned int hcrop1, hcrop2, vcrop1, vcrop2;
298 unsigned int wa, we, ha, he;
299 unsigned int X, Y, hor_dcm, ver_dcm;
300 u32 reg;
301
302 tvn = zr->timing;
303
304 wa = tvn->wa;
305 ha = tvn->ha;
306
307 pci_info(zr->pci_dev, "set_vfe() - width = %d, height = %d\n", video_width, video_height);
308
309 if (video_width < BUZ_MIN_WIDTH ||
310 video_height < BUZ_MIN_HEIGHT ||
311 video_width > wa || video_height > ha) {
312 pci_err(zr->pci_dev, "set_vfe: w=%d h=%d not valid\n", video_width, video_height);
313 return;
314 }
315
316 /**** zr36057 ****/
317
318 /* horizontal */
319 vid_win_wid = video_width;
320 X = DIV_ROUND_UP(vid_win_wid * 64, tvn->wa);
321 we = (vid_win_wid * 64) / X;
322 hor_dcm = 64 - X;
323 hcrop1 = 2 * ((tvn->wa - we) / 4);
324 hcrop2 = tvn->wa - we - hcrop1;
325 h_start = tvn->h_start ? tvn->h_start : 1;
326 /* (Ronald) Original comment:
327 * "| 1 Doesn't have any effect, tested on both a DC10 and a DC10+"
328 * this is false. It inverses chroma values on the LML33R10 (so Cr
329 * suddenly is shown as Cb and reverse, really cool effect if you
330 * want to see blue faces, not useful otherwise). So don't use |1.
331 * However, the DC10 has '0' as h_start, but does need |1, so we
332 * use a dirty check...
333 */
334 h_end = h_start + tvn->wa - 1;
335 h_start += hcrop1;
336 h_end -= hcrop2;
337 reg = ((h_start & ZR36057_VFEHCR_HMASK) << ZR36057_VFEHCR_H_START)
338 | ((h_end & ZR36057_VFEHCR_HMASK) << ZR36057_VFEHCR_H_END);
339 if (zr->card.vfe_pol.hsync_pol)
340 reg |= ZR36057_VFEHCR_HS_POL;
341 btwrite(reg, ZR36057_VFEHCR);
342
343 /* Vertical */
344 disp_mode = !(video_height > BUZ_MAX_HEIGHT / 2);
345 vid_win_ht = disp_mode ? video_height : video_height / 2;
346 Y = DIV_ROUND_UP(vid_win_ht * 64 * 2, tvn->ha);
347 he = (vid_win_ht * 64) / Y;
348 ver_dcm = 64 - Y;
349 vcrop1 = (tvn->ha / 2 - he) / 2;
350 vcrop2 = tvn->ha / 2 - he - vcrop1;
351 v_start = tvn->v_start;
352 v_end = v_start + tvn->ha / 2; // - 1; FIXME SnapShot times out with -1 in 768*576 on the DC10 - LP
353 v_start += vcrop1;
354 v_end -= vcrop2;
355 reg = ((v_start & ZR36057_VFEVCR_VMASK) << ZR36057_VFEVCR_V_START)
356 | ((v_end & ZR36057_VFEVCR_VMASK) << ZR36057_VFEVCR_V_END);
357 if (zr->card.vfe_pol.vsync_pol)
358 reg |= ZR36057_VFEVCR_VS_POL;
359 btwrite(reg, ZR36057_VFEVCR);
360
361 /* scaler and pixel format */
362 reg = 0;
363 reg |= (hor_dcm << ZR36057_VFESPFR_HOR_DCM);
364 reg |= (ver_dcm << ZR36057_VFESPFR_VER_DCM);
365 reg |= (disp_mode << ZR36057_VFESPFR_DISP_MODE);
366 /* RJ: I don't know, why the following has to be the opposite
367 * of the corresponding ZR36060 setting, but only this way
368 * we get the correct colors when uncompressing to the screen */
369 //reg |= ZR36057_VFESPFR_VCLK_POL; /**/
370 /* RJ: Don't know if that is needed for NTSC also */
371 if (!(zr->norm & V4L2_STD_NTSC))
372 reg |= ZR36057_VFESPFR_EXT_FL; // NEEDED!!!!!!! Wolfgang
373 reg |= ZR36057_VFESPFR_TOP_FIELD;
374 if (hor_dcm >= 48)
375 reg |= 3 << ZR36057_VFESPFR_H_FILTER; /* 5 tap filter */
376 else if (hor_dcm >= 32)
377 reg |= 2 << ZR36057_VFESPFR_H_FILTER; /* 4 tap filter */
378 else if (hor_dcm >= 16)
379 reg |= 1 << ZR36057_VFESPFR_H_FILTER; /* 3 tap filter */
380
381 reg |= format->vfespfr;
382 btwrite(reg, ZR36057_VFESPFR);
383
384 /* display configuration */
385 reg = (16 << ZR36057_VDCR_MIN_PIX)
386 | (vid_win_ht << ZR36057_VDCR_VID_WIN_HT)
387 | (vid_win_wid << ZR36057_VDCR_VID_WIN_WID);
388 if (pci_pci_problems & PCIPCI_TRITON)
389 // || zr->revision < 1) // Revision 1 has also Triton support
390 reg &= ~ZR36057_VDCR_TRITON;
391 else
392 reg |= ZR36057_VDCR_TRITON;
393 btwrite(reg, ZR36057_VDCR);
394
395 zr36057_adjust_vfe(zr, zr->codec_mode);
396 }
397
398 /* Enable/Disable uncompressed memory grabbing of the 36057 */
zr36057_set_memgrab(struct zoran * zr,int mode)399 void zr36057_set_memgrab(struct zoran *zr, int mode)
400 {
401 if (mode) {
402 /* We only check SnapShot and not FrameGrab here. SnapShot==1
403 * means a capture is already in progress, but FrameGrab==1
404 * doesn't necessary mean that. It's more correct to say a 1
405 * to 0 transition indicates a capture completed. If a
406 * capture is pending when capturing is tuned off, FrameGrab
407 * will be stuck at 1 until capturing is turned back on.
408 */
409 if (btread(ZR36057_VSSFGR) & ZR36057_VSSFGR_SNAP_SHOT)
410 pci_warn(zr->pci_dev, "zr36057_set_memgrab(1) with SnapShot on!?\n");
411
412 /* switch on VSync interrupts */
413 btwrite(IRQ_MASK, ZR36057_ISR); // Clear Interrupts
414 btor(zr->card.vsync_int, ZR36057_ICR); // SW
415
416 /* enable SnapShot */
417 btor(ZR36057_VSSFGR_SNAP_SHOT, ZR36057_VSSFGR);
418
419 /* Set zr36057 video front end and enable video */
420 zr36057_set_vfe(zr, zr->v4l_settings.width,
421 zr->v4l_settings.height,
422 zr->v4l_settings.format);
423 } else {
424 /* switch off VSync interrupts */
425 btand(~zr->card.vsync_int, ZR36057_ICR); // SW
426
427 /* re-enable grabbing to screen if it was running */
428 btand(~ZR36057_VDCR_VID_EN, ZR36057_VDCR);
429 btand(~ZR36057_VSSFGR_SNAP_SHOT, ZR36057_VSSFGR);
430 }
431 }
432
433 /*****************************************************************************
434 * *
435 * Set up the Buz-specific MJPEG part *
436 * *
437 *****************************************************************************/
438
set_frame(struct zoran * zr,int val)439 static inline void set_frame(struct zoran *zr, int val)
440 {
441 GPIO(zr, zr->card.gpio[ZR_GPIO_JPEG_FRAME], val);
442 }
443
set_videobus_dir(struct zoran * zr,int val)444 static void set_videobus_dir(struct zoran *zr, int val)
445 {
446 switch (zr->card.type) {
447 case LML33:
448 case LML33R10:
449 if (!lml33dpath)
450 GPIO(zr, 5, val);
451 else
452 GPIO(zr, 5, 1);
453 break;
454 default:
455 GPIO(zr, zr->card.gpio[ZR_GPIO_VID_DIR],
456 zr->card.gpio_pol[ZR_GPIO_VID_DIR] ? !val : val);
457 break;
458 }
459 }
460
init_jpeg_queue(struct zoran * zr)461 static void init_jpeg_queue(struct zoran *zr)
462 {
463 int i;
464
465 /* re-initialize DMA ring stuff */
466 zr->jpg_que_head = 0;
467 zr->jpg_dma_head = 0;
468 zr->jpg_dma_tail = 0;
469 zr->jpg_que_tail = 0;
470 zr->jpg_seq_num = 0;
471 zr->jpeg_error = 0;
472 zr->num_errors = 0;
473 zr->jpg_err_seq = 0;
474 zr->jpg_err_shift = 0;
475 zr->jpg_queued_num = 0;
476 for (i = 0; i < BUZ_NUM_STAT_COM; i++)
477 zr->stat_com[i] = cpu_to_le32(1); /* mark as unavailable to zr36057 */
478 }
479
zr36057_set_jpg(struct zoran * zr,enum zoran_codec_mode mode)480 static void zr36057_set_jpg(struct zoran *zr, enum zoran_codec_mode mode)
481 {
482 const struct tvnorm *tvn;
483 u32 reg;
484
485 tvn = zr->timing;
486
487 /* assert P_Reset, disable code transfer, deassert Active */
488 btwrite(0, ZR36057_JPC);
489
490 /* MJPEG compression mode */
491 switch (mode) {
492 case BUZ_MODE_MOTION_COMPRESS:
493 default:
494 reg = ZR36057_JMC_MJPG_CMP_MODE;
495 break;
496
497 case BUZ_MODE_MOTION_DECOMPRESS:
498 reg = ZR36057_JMC_MJPG_EXP_MODE;
499 reg |= ZR36057_JMC_SYNC_MSTR;
500 /* RJ: The following is experimental - improves the output to screen */
501 //if(zr->jpg_settings.VFIFO_FB) reg |= ZR36057_JMC_VFIFO_FB; // No, it doesn't. SM
502 break;
503
504 case BUZ_MODE_STILL_COMPRESS:
505 reg = ZR36057_JMC_JPG_CMP_MODE;
506 break;
507
508 case BUZ_MODE_STILL_DECOMPRESS:
509 reg = ZR36057_JMC_JPG_EXP_MODE;
510 break;
511 }
512 reg |= ZR36057_JMC_JPG;
513 if (zr->jpg_settings.field_per_buff == 1)
514 reg |= ZR36057_JMC_FLD_PER_BUFF;
515 btwrite(reg, ZR36057_JMC);
516
517 /* vertical */
518 btor(ZR36057_VFEVCR_VS_POL, ZR36057_VFEVCR);
519 reg = (6 << ZR36057_VSP_VSYNC_SIZE) |
520 (tvn->ht << ZR36057_VSP_FRM_TOT);
521 btwrite(reg, ZR36057_VSP);
522 reg = ((zr->jpg_settings.img_y + tvn->v_start) << ZR36057_FVAP_NAY) |
523 (zr->jpg_settings.img_height << ZR36057_FVAP_PAY);
524 btwrite(reg, ZR36057_FVAP);
525
526 /* horizontal */
527 if (zr->card.vfe_pol.hsync_pol)
528 btor(ZR36057_VFEHCR_HS_POL, ZR36057_VFEHCR);
529 else
530 btand(~ZR36057_VFEHCR_HS_POL, ZR36057_VFEHCR);
531 reg = ((tvn->h_sync_start) << ZR36057_HSP_HSYNC_START) |
532 (tvn->wt << ZR36057_HSP_LINE_TOT);
533 btwrite(reg, ZR36057_HSP);
534 reg = ((zr->jpg_settings.img_x +
535 tvn->h_start + 4) << ZR36057_FHAP_NAX) |
536 (zr->jpg_settings.img_width << ZR36057_FHAP_PAX);
537 btwrite(reg, ZR36057_FHAP);
538
539 /* field process parameters */
540 if (zr->jpg_settings.odd_even)
541 reg = ZR36057_FPP_ODD_EVEN;
542 else
543 reg = 0;
544
545 btwrite(reg, ZR36057_FPP);
546
547 /* Set proper VCLK Polarity, else colors will be wrong during playback */
548 //btor(ZR36057_VFESPFR_VCLK_POL, ZR36057_VFESPFR);
549
550 /* code base address */
551 btwrite(zr->p_sc, ZR36057_JCBA);
552
553 /* FIFO threshold (FIFO is 160. double words) */
554 /* NOTE: decimal values here */
555 switch (mode) {
556 case BUZ_MODE_STILL_COMPRESS:
557 case BUZ_MODE_MOTION_COMPRESS:
558 if (zr->card.type != BUZ)
559 reg = 140;
560 else
561 reg = 60;
562 break;
563
564 case BUZ_MODE_STILL_DECOMPRESS:
565 case BUZ_MODE_MOTION_DECOMPRESS:
566 reg = 20;
567 break;
568
569 default:
570 reg = 80;
571 break;
572 }
573 btwrite(reg, ZR36057_JCFT);
574 zr36057_adjust_vfe(zr, mode);
575 }
576
clear_interrupt_counters(struct zoran * zr)577 void clear_interrupt_counters(struct zoran *zr)
578 {
579 zr->intr_counter_GIRQ1 = 0;
580 zr->intr_counter_GIRQ0 = 0;
581 zr->intr_counter_cod_rep_irq = 0;
582 zr->intr_counter_jpeg_rep_irq = 0;
583 zr->field_counter = 0;
584 zr->irq1_in = 0;
585 zr->irq1_out = 0;
586 zr->jpeg_in = 0;
587 zr->jpeg_out = 0;
588 zr->JPEG_0 = 0;
589 zr->JPEG_1 = 0;
590 zr->end_event_missed = 0;
591 zr->jpeg_missed = 0;
592 zr->jpeg_max_missed = 0;
593 zr->jpeg_min_missed = 0x7fffffff;
594 }
595
count_reset_interrupt(struct zoran * zr)596 static u32 count_reset_interrupt(struct zoran *zr)
597 {
598 u32 isr;
599
600 isr = btread(ZR36057_ISR) & 0x78000000;
601 if (isr) {
602 if (isr & ZR36057_ISR_GIRQ1) {
603 btwrite(ZR36057_ISR_GIRQ1, ZR36057_ISR);
604 zr->intr_counter_GIRQ1++;
605 }
606 if (isr & ZR36057_ISR_GIRQ0) {
607 btwrite(ZR36057_ISR_GIRQ0, ZR36057_ISR);
608 zr->intr_counter_GIRQ0++;
609 }
610 if (isr & ZR36057_ISR_COD_REP_IRQ) {
611 btwrite(ZR36057_ISR_COD_REP_IRQ, ZR36057_ISR);
612 zr->intr_counter_cod_rep_irq++;
613 }
614 if (isr & ZR36057_ISR_JPEG_REP_IRQ) {
615 btwrite(ZR36057_ISR_JPEG_REP_IRQ, ZR36057_ISR);
616 zr->intr_counter_jpeg_rep_irq++;
617 }
618 }
619 return isr;
620 }
621
jpeg_start(struct zoran * zr)622 void jpeg_start(struct zoran *zr)
623 {
624 int reg;
625
626 zr->frame_num = 0;
627
628 /* deassert P_reset, disable code transfer, deassert Active */
629 btwrite(ZR36057_JPC_P_RESET, ZR36057_JPC);
630 /* stop flushing the internal code buffer */
631 btand(~ZR36057_MCTCR_C_FLUSH, ZR36057_MCTCR);
632 /* enable code transfer */
633 btor(ZR36057_JPC_COD_TRNS_EN, ZR36057_JPC);
634
635 /* clear IRQs */
636 btwrite(IRQ_MASK, ZR36057_ISR);
637 /* enable the JPEG IRQs */
638 btwrite(zr->card.jpeg_int | ZR36057_ICR_JPEG_REP_IRQ | ZR36057_ICR_INT_PIN_EN,
639 ZR36057_ICR);
640
641 set_frame(zr, 0); // \FRAME
642
643 /* set the JPEG codec guest ID */
644 reg = (zr->card.gpcs[1] << ZR36057_JCGI_JPE_GUEST_ID) |
645 (0 << ZR36057_JCGI_JPE_GUEST_REG);
646 btwrite(reg, ZR36057_JCGI);
647
648 if (zr->card.video_vfe == CODEC_TYPE_ZR36016 &&
649 zr->card.video_codec == CODEC_TYPE_ZR36050) {
650 /* Enable processing on the ZR36016 */
651 if (zr->vfe)
652 zr36016_write(zr->vfe, 0, 1);
653
654 /* load the address of the GO register in the ZR36050 latch */
655 post_office_write(zr, 0, 0, 0);
656 }
657
658 /* assert Active */
659 btor(ZR36057_JPC_ACTIVE, ZR36057_JPC);
660
661 /* enable the Go generation */
662 btor(ZR36057_JMC_GO_EN, ZR36057_JMC);
663 udelay(30);
664
665 set_frame(zr, 1); // /FRAME
666
667 pci_dbg(zr->pci_dev, "jpeg_start\n");
668 }
669
zr36057_enable_jpg(struct zoran * zr,enum zoran_codec_mode mode)670 void zr36057_enable_jpg(struct zoran *zr, enum zoran_codec_mode mode)
671 {
672 struct vfe_settings cap;
673 int field_size = zr->buffer_size / zr->jpg_settings.field_per_buff;
674
675 zr->codec_mode = mode;
676
677 cap.x = zr->jpg_settings.img_x;
678 cap.y = zr->jpg_settings.img_y;
679 cap.width = zr->jpg_settings.img_width;
680 cap.height = zr->jpg_settings.img_height;
681 cap.decimation =
682 zr->jpg_settings.hor_dcm | (zr->jpg_settings.ver_dcm << 8);
683 cap.quality = zr->jpg_settings.jpg_comp.quality;
684
685 switch (mode) {
686 case BUZ_MODE_MOTION_COMPRESS: {
687 struct jpeg_app_marker app;
688 struct jpeg_com_marker com;
689
690 /* In motion compress mode, the decoder output must be enabled, and
691 * the video bus direction set to input.
692 */
693 set_videobus_dir(zr, 0);
694 decoder_call(zr, video, s_stream, 1);
695 encoder_call(zr, video, s_routing, 0, 0, 0);
696
697 /* Take the JPEG codec and the VFE out of sleep */
698 jpeg_codec_sleep(zr, 0);
699
700 /* set JPEG app/com marker */
701 app.appn = zr->jpg_settings.jpg_comp.APPn;
702 app.len = zr->jpg_settings.jpg_comp.APP_len;
703 memcpy(app.data, zr->jpg_settings.jpg_comp.APP_data, 60);
704 zr->codec->control(zr->codec, CODEC_S_JPEG_APP_DATA,
705 sizeof(struct jpeg_app_marker), &app);
706
707 com.len = zr->jpg_settings.jpg_comp.COM_len;
708 memcpy(com.data, zr->jpg_settings.jpg_comp.COM_data, 60);
709 zr->codec->control(zr->codec, CODEC_S_JPEG_COM_DATA,
710 sizeof(struct jpeg_com_marker), &com);
711
712 /* Setup the JPEG codec */
713 zr->codec->control(zr->codec, CODEC_S_JPEG_TDS_BYTE,
714 sizeof(int), &field_size);
715 zr->codec->set_video(zr->codec, zr->timing, &cap,
716 &zr->card.vfe_pol);
717 zr->codec->set_mode(zr->codec, CODEC_DO_COMPRESSION);
718
719 /* Setup the VFE */
720 if (zr->vfe) {
721 zr->vfe->control(zr->vfe, CODEC_S_JPEG_TDS_BYTE,
722 sizeof(int), &field_size);
723 zr->vfe->set_video(zr->vfe, zr->timing, &cap,
724 &zr->card.vfe_pol);
725 zr->vfe->set_mode(zr->vfe, CODEC_DO_COMPRESSION);
726 }
727
728 init_jpeg_queue(zr);
729 zr36057_set_jpg(zr, mode); // \P_Reset, ... Video param, FIFO
730
731 clear_interrupt_counters(zr);
732 pci_info(zr->pci_dev, "enable_jpg(MOTION_COMPRESS)\n");
733 break;
734 }
735
736 case BUZ_MODE_MOTION_DECOMPRESS:
737 /* In motion decompression mode, the decoder output must be disabled, and
738 * the video bus direction set to output.
739 */
740 decoder_call(zr, video, s_stream, 0);
741 set_videobus_dir(zr, 1);
742 encoder_call(zr, video, s_routing, 1, 0, 0);
743
744 /* Take the JPEG codec and the VFE out of sleep */
745 jpeg_codec_sleep(zr, 0);
746 /* Setup the VFE */
747 if (zr->vfe) {
748 zr->vfe->set_video(zr->vfe, zr->timing, &cap,
749 &zr->card.vfe_pol);
750 zr->vfe->set_mode(zr->vfe, CODEC_DO_EXPANSION);
751 }
752 /* Setup the JPEG codec */
753 zr->codec->set_video(zr->codec, zr->timing, &cap,
754 &zr->card.vfe_pol);
755 zr->codec->set_mode(zr->codec, CODEC_DO_EXPANSION);
756
757 init_jpeg_queue(zr);
758 zr36057_set_jpg(zr, mode); // \P_Reset, ... Video param, FIFO
759
760 clear_interrupt_counters(zr);
761 pci_info(zr->pci_dev, "enable_jpg(MOTION_DECOMPRESS)\n");
762 break;
763
764 case BUZ_MODE_IDLE:
765 default:
766 /* shut down processing */
767 btand(~(zr->card.jpeg_int | ZR36057_ICR_JPEG_REP_IRQ),
768 ZR36057_ICR);
769 btwrite(zr->card.jpeg_int | ZR36057_ICR_JPEG_REP_IRQ,
770 ZR36057_ISR);
771 btand(~ZR36057_JMC_GO_EN, ZR36057_JMC); // \Go_en
772
773 msleep(50);
774
775 set_videobus_dir(zr, 0);
776 set_frame(zr, 1); // /FRAME
777 btor(ZR36057_MCTCR_C_FLUSH, ZR36057_MCTCR); // /CFlush
778 btwrite(0, ZR36057_JPC); // \P_Reset,\CodTrnsEn,\Active
779 btand(~ZR36057_JMC_VFIFO_FB, ZR36057_JMC);
780 btand(~ZR36057_JMC_SYNC_MSTR, ZR36057_JMC);
781 jpeg_codec_reset(zr);
782 jpeg_codec_sleep(zr, 1);
783 zr36057_adjust_vfe(zr, mode);
784
785 decoder_call(zr, video, s_stream, 1);
786 encoder_call(zr, video, s_routing, 0, 0, 0);
787
788 pci_info(zr->pci_dev, "enable_jpg(IDLE)\n");
789 break;
790 }
791 }
792
793 /* when this is called the spinlock must be held */
zoran_feed_stat_com(struct zoran * zr)794 void zoran_feed_stat_com(struct zoran *zr)
795 {
796 /* move frames from pending queue to DMA */
797
798 int i, max_stat_com;
799 struct zr_buffer *buf;
800 struct vb2_v4l2_buffer *vbuf;
801 dma_addr_t phys_addr = 0;
802 unsigned long flags;
803 unsigned long payload;
804
805 max_stat_com =
806 (zr->jpg_settings.tmp_dcm ==
807 1) ? BUZ_NUM_STAT_COM : (BUZ_NUM_STAT_COM >> 1);
808
809 spin_lock_irqsave(&zr->queued_bufs_lock, flags);
810 while ((zr->jpg_dma_head - zr->jpg_dma_tail) < max_stat_com) {
811 buf = list_first_entry_or_null(&zr->queued_bufs, struct zr_buffer, queue);
812 if (!buf) {
813 pci_err(zr->pci_dev, "No buffer available to queue\n");
814 spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
815 return;
816 }
817 list_del(&buf->queue);
818 zr->buf_in_reserve--;
819 vbuf = &buf->vbuf;
820 vbuf->vb2_buf.state = VB2_BUF_STATE_ACTIVE;
821 phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
822 payload = vb2_get_plane_payload(&vbuf->vb2_buf, 0);
823 if (payload == 0)
824 payload = zr->buffer_size;
825 if (zr->jpg_settings.tmp_dcm == 1) {
826 /* fill 1 stat_com entry */
827 i = (zr->jpg_dma_head -
828 zr->jpg_err_shift) & BUZ_MASK_STAT_COM;
829 if (!(zr->stat_com[i] & cpu_to_le32(1)))
830 break;
831 zr->stat_comb[i * 2] = cpu_to_le32(phys_addr);
832 zr->stat_comb[i * 2 + 1] = cpu_to_le32((payload >> 1) | 1);
833 zr->inuse[i] = buf;
834 zr->stat_com[i] = cpu_to_le32(zr->p_scb + i * 2 * 4);
835 } else {
836 /* fill 2 stat_com entries */
837 i = ((zr->jpg_dma_head -
838 zr->jpg_err_shift) & 1) * 2;
839 if (!(zr->stat_com[i] & cpu_to_le32(1)))
840 break;
841 zr->stat_com[i] = cpu_to_le32(zr->p_scb + i * 2 * 4);
842 zr->stat_com[i + 1] = cpu_to_le32(zr->p_scb + i * 2 * 4);
843
844 zr->stat_comb[i * 2] = cpu_to_le32(phys_addr);
845 zr->stat_comb[i * 2 + 1] = cpu_to_le32((payload >> 1) | 1);
846
847 zr->inuse[i] = buf;
848 zr->inuse[i + 1] = NULL;
849 }
850 zr->jpg_dma_head++;
851 }
852 spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
853 if (zr->codec_mode == BUZ_MODE_MOTION_DECOMPRESS)
854 zr->jpg_queued_num++;
855 }
856
857 /* when this is called the spinlock must be held */
zoran_reap_stat_com(struct zoran * zr)858 static void zoran_reap_stat_com(struct zoran *zr)
859 {
860 /* move frames from DMA queue to done queue */
861
862 int i;
863 u32 stat_com;
864 unsigned int seq;
865 unsigned int dif;
866 unsigned long flags;
867 struct zr_buffer *buf;
868 unsigned int size = 0;
869 u32 fcnt;
870
871 /* In motion decompress we don't have a hardware frame counter,
872 * we just count the interrupts here */
873
874 if (zr->codec_mode == BUZ_MODE_MOTION_DECOMPRESS)
875 zr->jpg_seq_num++;
876
877 spin_lock_irqsave(&zr->queued_bufs_lock, flags);
878 while (zr->jpg_dma_tail < zr->jpg_dma_head) {
879 if (zr->jpg_settings.tmp_dcm == 1)
880 i = (zr->jpg_dma_tail - zr->jpg_err_shift) & BUZ_MASK_STAT_COM;
881 else
882 i = ((zr->jpg_dma_tail - zr->jpg_err_shift) & 1) * 2 + 1;
883
884 stat_com = le32_to_cpu(zr->stat_com[i]);
885 if ((stat_com & 1) == 0) {
886 spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
887 return;
888 }
889
890 fcnt = (stat_com & GENMASK(31, 24)) >> 24;
891 size = (stat_com & GENMASK(22, 1)) >> 1;
892
893 buf = zr->inuse[i];
894 buf->vbuf.vb2_buf.timestamp = ktime_get_ns();
895
896 if (zr->codec_mode == BUZ_MODE_MOTION_COMPRESS) {
897 vb2_set_plane_payload(&buf->vbuf.vb2_buf, 0, size);
898
899 /* update sequence number with the help of the counter in stat_com */
900 seq = (fcnt + zr->jpg_err_seq) & 0xff;
901 dif = (seq - zr->jpg_seq_num) & 0xff;
902 zr->jpg_seq_num += dif;
903 }
904 buf->vbuf.sequence = zr->jpg_settings.tmp_dcm ==
905 2 ? (zr->jpg_seq_num >> 1) : zr->jpg_seq_num;
906 zr->inuse[i] = NULL;
907 if (zr->jpg_settings.tmp_dcm != 1)
908 buf->vbuf.field = zr->jpg_settings.odd_even ?
909 V4L2_FIELD_TOP : V4L2_FIELD_BOTTOM;
910 else
911 buf->vbuf.field = zr->jpg_settings.odd_even ?
912 V4L2_FIELD_SEQ_TB : V4L2_FIELD_SEQ_BT;
913 vb2_buffer_done(&buf->vbuf.vb2_buf, VB2_BUF_STATE_DONE);
914
915 zr->jpg_dma_tail++;
916 }
917 spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
918 }
919
zoran_irq(int irq,void * dev_id)920 irqreturn_t zoran_irq(int irq, void *dev_id)
921 {
922 struct zoran *zr = dev_id;
923 u32 stat, astat;
924
925 stat = count_reset_interrupt(zr);
926 astat = stat & IRQ_MASK;
927 if (astat & zr->card.vsync_int) {
928 if (zr->running == ZORAN_MAP_MODE_RAW) {
929 if ((btread(ZR36057_VSSFGR) & ZR36057_VSSFGR_SNAP_SHOT) == 0)
930 pci_warn(zr->pci_dev, "BuzIRQ with SnapShot off ???\n");
931 if ((btread(ZR36057_VSSFGR) & ZR36057_VSSFGR_FRAME_GRAB) == 0)
932 zr_set_buf(zr);
933 return IRQ_HANDLED;
934 }
935 if (astat & ZR36057_ISR_JPEG_REP_IRQ) {
936 if (zr->codec_mode != BUZ_MODE_MOTION_DECOMPRESS &&
937 zr->codec_mode != BUZ_MODE_MOTION_COMPRESS) {
938 pci_err(zr->pci_dev, "JPG IRQ when not in good mode\n");
939 return IRQ_HANDLED;
940 }
941 zr->frame_num++;
942 zoran_reap_stat_com(zr);
943 zoran_feed_stat_com(zr);
944 return IRQ_HANDLED;
945 }
946 /* unused interrupts */
947 }
948 zr->ghost_int++;
949 return IRQ_HANDLED;
950 }
951
zoran_set_pci_master(struct zoran * zr,int set_master)952 void zoran_set_pci_master(struct zoran *zr, int set_master)
953 {
954 if (set_master) {
955 pci_set_master(zr->pci_dev);
956 } else {
957 u16 command;
958
959 pci_read_config_word(zr->pci_dev, PCI_COMMAND, &command);
960 command &= ~PCI_COMMAND_MASTER;
961 pci_write_config_word(zr->pci_dev, PCI_COMMAND, command);
962 }
963 }
964
zoran_init_hardware(struct zoran * zr)965 void zoran_init_hardware(struct zoran *zr)
966 {
967 /* Enable bus-mastering */
968 zoran_set_pci_master(zr, 1);
969
970 /* Initialize the board */
971 if (zr->card.init)
972 zr->card.init(zr);
973
974 decoder_call(zr, core, init, 0);
975 decoder_call(zr, video, s_std, zr->norm);
976 decoder_call(zr, video, s_routing,
977 zr->card.input[zr->input].muxsel, 0, 0);
978
979 encoder_call(zr, core, init, 0);
980 encoder_call(zr, video, s_std_output, zr->norm);
981 encoder_call(zr, video, s_routing, 0, 0, 0);
982
983 /* toggle JPEG codec sleep to sync PLL */
984 jpeg_codec_sleep(zr, 1);
985 jpeg_codec_sleep(zr, 0);
986
987 /*
988 * set individual interrupt enables (without GIRQ1)
989 * but don't global enable until zoran_open()
990 */
991 zr36057_init_vfe(zr);
992
993 zr36057_enable_jpg(zr, BUZ_MODE_IDLE);
994
995 btwrite(IRQ_MASK, ZR36057_ISR); // Clears interrupts
996 }
997
zr36057_restart(struct zoran * zr)998 void zr36057_restart(struct zoran *zr)
999 {
1000 btwrite(0, ZR36057_SPGPPCR);
1001 udelay(1000);
1002 btor(ZR36057_SPGPPCR_SOFT_RESET, ZR36057_SPGPPCR);
1003 udelay(1000);
1004
1005 /* assert P_Reset */
1006 btwrite(0, ZR36057_JPC);
1007 /* set up GPIO direction - all output */
1008 btwrite(ZR36057_SPGPPCR_SOFT_RESET | 0, ZR36057_SPGPPCR);
1009
1010 /* set up GPIO pins and guest bus timing */
1011 btwrite((0x81 << 24) | 0x8888, ZR36057_GPPGCR1);
1012 }
1013
1014