1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25 #ifndef __MSM_DRM_H__ 26 #define __MSM_DRM_H__ 27 28 #include "drm.h" 29 30 #if defined(__cplusplus) 31 extern "C" { 32 #endif 33 34 /* Please note that modifications to all structs defined here are 35 * subject to backwards-compatibility constraints: 36 * 1) Do not use pointers, use uint64_t instead for 32 bit / 64 bit 37 * user/kernel compatibility 38 * 2) Keep fields aligned to their size 39 * 3) Because of how drm_ioctl() works, we can add new fields at 40 * the end of an ioctl if some care is taken: drm_ioctl() will 41 * zero out the new fields at the tail of the ioctl, so a zero 42 * value should have a backwards compatible meaning. And for 43 * output params, userspace won't see the newly added output 44 * fields.. so that has to be somehow ok. 45 */ 46 47 #define MSM_PIPE_NONE 0x00 48 #define MSM_PIPE_2D0 0x01 49 #define MSM_PIPE_2D1 0x02 50 #define MSM_PIPE_3D0 0x10 51 52 /* The pipe-id just uses the lower bits, so can be OR'd with flags in 53 * the upper 16 bits (which could be extended further, if needed, maybe 54 * we extend/overload the pipe-id some day to deal with multiple rings, 55 * but even then I don't think we need the full lower 16 bits). 56 */ 57 #define MSM_PIPE_ID_MASK 0xffff 58 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 59 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 60 61 /* timeouts are specified in clock-monotonic absolute times (to simplify 62 * restarting interrupted ioctls). The following struct is logically the 63 * same as 'struct timespec' but 32/64b ABI safe. 64 */ 65 struct drm_msm_timespec { 66 int64_t tv_sec; /* seconds */ 67 int64_t tv_nsec; /* nanoseconds */ 68 }; 69 70 #define MSM_PARAM_GPU_ID 0x01 71 #define MSM_PARAM_GMEM_SIZE 0x02 72 #define MSM_PARAM_CHIP_ID 0x03 73 #define MSM_PARAM_MAX_FREQ 0x04 74 #define MSM_PARAM_TIMESTAMP 0x05 75 #define MSM_PARAM_GMEM_BASE 0x06 76 #define MSM_PARAM_NR_RINGS 0x07 77 #define MSM_PARAM_PP_PGTABLE 0x08 /* => 1 for per-process pagetables, else 0 */ 78 #define MSM_PARAM_FAULTS 0x09 79 #define MSM_PARAM_SUSPENDS 0x0a 80 81 struct drm_msm_param { 82 uint32_t pipe; /* in, MSM_PIPE_x */ 83 uint32_t param; /* in, MSM_PARAM_x */ 84 uint64_t value; /* out (get_param) or in (set_param) */ 85 }; 86 87 /* 88 * GEM buffers: 89 */ 90 91 #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */ 92 #define MSM_BO_GPU_READONLY 0x00000002 93 #define MSM_BO_CACHE_MASK 0x000f0000 94 /* cache modes */ 95 #define MSM_BO_CACHED 0x00010000 96 #define MSM_BO_WC 0x00020000 97 #define MSM_BO_UNCACHED 0x00040000 98 99 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ 100 MSM_BO_GPU_READONLY | \ 101 MSM_BO_CACHED | \ 102 MSM_BO_WC | \ 103 MSM_BO_UNCACHED) 104 105 struct drm_msm_gem_new { 106 uint64_t size; /* in */ 107 uint32_t flags; /* in, mask of MSM_BO_x */ 108 uint32_t handle; /* out */ 109 }; 110 111 /* Get or set GEM buffer info. The requested value can be passed 112 * directly in 'value', or for data larger than 64b 'value' is a 113 * pointer to userspace buffer, with 'len' specifying the number of 114 * bytes copied into that buffer. For info returned by pointer, 115 * calling the GEM_INFO ioctl with null 'value' will return the 116 * required buffer size in 'len' 117 */ 118 #define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */ 119 #define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */ 120 #define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */ 121 #define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */ 122 123 struct drm_msm_gem_info { 124 uint32_t handle; /* in */ 125 uint32_t info; /* in - one of MSM_INFO_* */ 126 uint64_t value; /* in or out */ 127 uint32_t len; /* in or out */ 128 uint32_t pad; 129 }; 130 131 #define MSM_PREP_READ 0x01 132 #define MSM_PREP_WRITE 0x02 133 #define MSM_PREP_NOSYNC 0x04 134 135 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 136 137 struct drm_msm_gem_cpu_prep { 138 uint32_t handle; /* in */ 139 uint32_t op; /* in, mask of MSM_PREP_x */ 140 struct drm_msm_timespec timeout; /* in */ 141 }; 142 143 struct drm_msm_gem_cpu_fini { 144 uint32_t handle; /* in */ 145 }; 146 147 /* 148 * Cmdstream Submission: 149 */ 150 151 /* The value written into the cmdstream is logically: 152 * 153 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or 154 * 155 * When we have GPU's w/ >32bit ptrs, it should be possible to deal 156 * with this by emit'ing two reloc entries with appropriate shift 157 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option. 158 * 159 * NOTE that reloc's must be sorted by order of increasing submit_offset, 160 * otherwise EINVAL. 161 */ 162 struct drm_msm_gem_submit_reloc { 163 uint32_t submit_offset; /* in, offset from submit_bo */ 164 uint32_t or; /* in, value OR'd with result */ 165 int32_t shift; /* in, amount of left shift (can be negative) */ 166 uint32_t reloc_idx; /* in, index of reloc_bo buffer */ 167 uint64_t reloc_offset; /* in, offset from start of reloc_bo */ 168 }; 169 170 /* submit-types: 171 * BUF - this cmd buffer is executed normally. 172 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are 173 * processed normally, but the kernel does not setup an IB to 174 * this buffer in the first-level ringbuffer 175 * CTX_RESTORE_BUF - only executed if there has been a GPU context 176 * switch since the last SUBMIT ioctl 177 */ 178 #define MSM_SUBMIT_CMD_BUF 0x0001 179 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 180 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 181 struct drm_msm_gem_submit_cmd { 182 uint32_t type; /* in, one of MSM_SUBMIT_CMD_x */ 183 uint32_t submit_idx; /* in, index of submit_bo cmdstream buffer */ 184 uint32_t submit_offset; /* in, offset into submit_bo */ 185 uint32_t size; /* in, cmdstream size */ 186 uint32_t pad; 187 uint32_t nr_relocs; /* in, number of submit_reloc's */ 188 uint64_t relocs; /* in, ptr to array of submit_reloc's */ 189 }; 190 191 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the 192 * cmdstream buffer(s) themselves or reloc entries) has one (and only 193 * one) entry in the submit->bos[] table. 194 * 195 * As a optimization, the current buffer (gpu virtual address) can be 196 * passed back through the 'presumed' field. If on a subsequent reloc, 197 * userspace passes back a 'presumed' address that is still valid, 198 * then patching the cmdstream for this entry is skipped. This can 199 * avoid kernel needing to map/access the cmdstream bo in the common 200 * case. 201 */ 202 #define MSM_SUBMIT_BO_READ 0x0001 203 #define MSM_SUBMIT_BO_WRITE 0x0002 204 #define MSM_SUBMIT_BO_DUMP 0x0004 205 206 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \ 207 MSM_SUBMIT_BO_WRITE | \ 208 MSM_SUBMIT_BO_DUMP) 209 210 struct drm_msm_gem_submit_bo { 211 uint32_t flags; /* in, mask of MSM_SUBMIT_BO_x */ 212 uint32_t handle; /* in, GEM handle */ 213 uint64_t presumed; /* in/out, presumed buffer address */ 214 }; 215 216 /* Valid submit ioctl flags: */ 217 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */ 218 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */ 219 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */ 220 #define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */ 221 #define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */ 222 #define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */ 223 #define MSM_SUBMIT_FLAGS ( \ 224 MSM_SUBMIT_NO_IMPLICIT | \ 225 MSM_SUBMIT_FENCE_FD_IN | \ 226 MSM_SUBMIT_FENCE_FD_OUT | \ 227 MSM_SUBMIT_SUDO | \ 228 MSM_SUBMIT_SYNCOBJ_IN | \ 229 MSM_SUBMIT_SYNCOBJ_OUT | \ 230 0) 231 232 #define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */ 233 #define MSM_SUBMIT_SYNCOBJ_FLAGS ( \ 234 MSM_SUBMIT_SYNCOBJ_RESET | \ 235 0) 236 237 struct drm_msm_gem_submit_syncobj { 238 uint32_t handle; /* in, syncobj handle. */ 239 uint32_t flags; /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */ 240 uint64_t point; /* in, timepoint for timeline syncobjs. */ 241 }; 242 243 /* Each cmdstream submit consists of a table of buffers involved, and 244 * one or more cmdstream buffers. This allows for conditional execution 245 * (context-restore), and IB buffers needed for per tile/bin draw cmds. 246 */ 247 struct drm_msm_gem_submit { 248 uint32_t flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ 249 uint32_t fence; /* out */ 250 uint32_t nr_bos; /* in, number of submit_bo's */ 251 uint32_t nr_cmds; /* in, number of submit_cmd's */ 252 uint64_t bos; /* in, ptr to array of submit_bo's */ 253 uint64_t cmds; /* in, ptr to array of submit_cmd's */ 254 int32_t fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ 255 uint32_t queueid; /* in, submitqueue id */ 256 uint64_t in_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */ 257 uint64_t out_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */ 258 uint32_t nr_in_syncobjs; /* in, number of entries in in_syncobj */ 259 uint32_t nr_out_syncobjs; /* in, number of entries in out_syncobj. */ 260 uint32_t syncobj_stride; /* in, stride of syncobj arrays. */ 261 uint32_t pad; /*in, reserved for future use, always 0. */ 262 263 }; 264 265 /* The normal way to synchronize with the GPU is just to CPU_PREP on 266 * a buffer if you need to access it from the CPU (other cmdstream 267 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all 268 * handle the required synchronization under the hood). This ioctl 269 * mainly just exists as a way to implement the gallium pipe_fence 270 * APIs without requiring a dummy bo to synchronize on. 271 */ 272 struct drm_msm_wait_fence { 273 uint32_t fence; /* in */ 274 uint32_t pad; 275 struct drm_msm_timespec timeout; /* in */ 276 uint32_t queueid; /* in, submitqueue id */ 277 }; 278 279 /* madvise provides a way to tell the kernel in case a buffers contents 280 * can be discarded under memory pressure, which is useful for userspace 281 * bo cache where we want to optimistically hold on to buffer allocate 282 * and potential mmap, but allow the pages to be discarded under memory 283 * pressure. 284 * 285 * Typical usage would involve madvise(DONTNEED) when buffer enters BO 286 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache. 287 * In the WILLNEED case, 'retained' indicates to userspace whether the 288 * backing pages still exist. 289 */ 290 #define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */ 291 #define MSM_MADV_DONTNEED 1 /* backing pages not needed */ 292 #define __MSM_MADV_PURGED 2 /* internal state */ 293 294 struct drm_msm_gem_madvise { 295 uint32_t handle; /* in, GEM handle */ 296 uint32_t madv; /* in, MSM_MADV_x */ 297 uint32_t retained; /* out, whether backing store still exists */ 298 }; 299 300 /* 301 * Draw queues allow the user to set specific submission parameter. Command 302 * submissions specify a specific submitqueue to use. ID 0 is reserved for 303 * backwards compatibility as a "default" submitqueue 304 */ 305 306 #define MSM_SUBMITQUEUE_FLAGS (0) 307 308 struct drm_msm_submitqueue { 309 uint32_t flags; /* in, MSM_SUBMITQUEUE_x */ 310 uint32_t prio; /* in, Priority level */ 311 uint32_t id; /* out, identifier */ 312 }; 313 314 #define MSM_SUBMITQUEUE_PARAM_FAULTS 0 315 316 struct drm_msm_submitqueue_query { 317 uint64_t data; 318 uint32_t id; 319 uint32_t param; 320 uint32_t len; 321 uint32_t pad; 322 }; 323 324 #define DRM_MSM_GET_PARAM 0x00 325 /* placeholder: 326 #define DRM_MSM_SET_PARAM 0x01 327 */ 328 #define DRM_MSM_GEM_NEW 0x02 329 #define DRM_MSM_GEM_INFO 0x03 330 #define DRM_MSM_GEM_CPU_PREP 0x04 331 #define DRM_MSM_GEM_CPU_FINI 0x05 332 #define DRM_MSM_GEM_SUBMIT 0x06 333 #define DRM_MSM_WAIT_FENCE 0x07 334 #define DRM_MSM_GEM_MADVISE 0x08 335 /* placeholder: 336 #define DRM_MSM_GEM_SVM_NEW 0x09 337 */ 338 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 339 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 340 #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C 341 342 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 343 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 344 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 345 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 346 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 347 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 348 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 349 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 350 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 351 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, uint32_t) 352 #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query) 353 354 #if defined(__cplusplus) 355 } 356 #endif 357 358 #endif /* __MSM_DRM_H__ */ 359