1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * cs35l35.c -- CS35L35 ALSA SoC audio driver
4 *
5 * Copyright 2017 Cirrus Logic, Inc.
6 *
7 * Author: Brian Austin <brian.austin@cirrus.com>
8 */
9
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/i2c.h>
16 #include <linux/slab.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/regmap.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <linux/gpio.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <sound/cs35l35.h>
32 #include <linux/of_irq.h>
33 #include <linux/completion.h>
34
35 #include "cs35l35.h"
36
37 /*
38 * Some fields take zero as a valid value so use a high bit flag that won't
39 * get written to the device to mark those.
40 */
41 #define CS35L35_VALID_PDATA 0x80000000
42
43 static const struct reg_default cs35l35_reg[] = {
44 {CS35L35_PWRCTL1, 0x01},
45 {CS35L35_PWRCTL2, 0x11},
46 {CS35L35_PWRCTL3, 0x00},
47 {CS35L35_CLK_CTL1, 0x04},
48 {CS35L35_CLK_CTL2, 0x12},
49 {CS35L35_CLK_CTL3, 0xCF},
50 {CS35L35_SP_FMT_CTL1, 0x20},
51 {CS35L35_SP_FMT_CTL2, 0x00},
52 {CS35L35_SP_FMT_CTL3, 0x02},
53 {CS35L35_MAG_COMP_CTL, 0x00},
54 {CS35L35_AMP_INP_DRV_CTL, 0x01},
55 {CS35L35_AMP_DIG_VOL_CTL, 0x12},
56 {CS35L35_AMP_DIG_VOL, 0x00},
57 {CS35L35_ADV_DIG_VOL, 0x00},
58 {CS35L35_PROTECT_CTL, 0x06},
59 {CS35L35_AMP_GAIN_AUD_CTL, 0x13},
60 {CS35L35_AMP_GAIN_PDM_CTL, 0x00},
61 {CS35L35_AMP_GAIN_ADV_CTL, 0x00},
62 {CS35L35_GPI_CTL, 0x00},
63 {CS35L35_BST_CVTR_V_CTL, 0x00},
64 {CS35L35_BST_PEAK_I, 0x07},
65 {CS35L35_BST_RAMP_CTL, 0x85},
66 {CS35L35_BST_CONV_COEF_1, 0x24},
67 {CS35L35_BST_CONV_COEF_2, 0x24},
68 {CS35L35_BST_CONV_SLOPE_COMP, 0x4E},
69 {CS35L35_BST_CONV_SW_FREQ, 0x04},
70 {CS35L35_CLASS_H_CTL, 0x0B},
71 {CS35L35_CLASS_H_HEADRM_CTL, 0x0B},
72 {CS35L35_CLASS_H_RELEASE_RATE, 0x08},
73 {CS35L35_CLASS_H_FET_DRIVE_CTL, 0x41},
74 {CS35L35_CLASS_H_VP_CTL, 0xC5},
75 {CS35L35_VPBR_CTL, 0x0A},
76 {CS35L35_VPBR_VOL_CTL, 0x90},
77 {CS35L35_VPBR_TIMING_CTL, 0x6A},
78 {CS35L35_VPBR_MODE_VOL_CTL, 0x00},
79 {CS35L35_SPKR_MON_CTL, 0xC0},
80 {CS35L35_IMON_SCALE_CTL, 0x30},
81 {CS35L35_AUDIN_RXLOC_CTL, 0x00},
82 {CS35L35_ADVIN_RXLOC_CTL, 0x80},
83 {CS35L35_VMON_TXLOC_CTL, 0x00},
84 {CS35L35_IMON_TXLOC_CTL, 0x80},
85 {CS35L35_VPMON_TXLOC_CTL, 0x04},
86 {CS35L35_VBSTMON_TXLOC_CTL, 0x84},
87 {CS35L35_VPBR_STATUS_TXLOC_CTL, 0x04},
88 {CS35L35_ZERO_FILL_LOC_CTL, 0x00},
89 {CS35L35_AUDIN_DEPTH_CTL, 0x0F},
90 {CS35L35_SPKMON_DEPTH_CTL, 0x0F},
91 {CS35L35_SUPMON_DEPTH_CTL, 0x0F},
92 {CS35L35_ZEROFILL_DEPTH_CTL, 0x00},
93 {CS35L35_MULT_DEV_SYNCH1, 0x02},
94 {CS35L35_MULT_DEV_SYNCH2, 0x80},
95 {CS35L35_PROT_RELEASE_CTL, 0x00},
96 {CS35L35_DIAG_MODE_REG_LOCK, 0x00},
97 {CS35L35_DIAG_MODE_CTL_1, 0x40},
98 {CS35L35_DIAG_MODE_CTL_2, 0x00},
99 {CS35L35_INT_MASK_1, 0xFF},
100 {CS35L35_INT_MASK_2, 0xFF},
101 {CS35L35_INT_MASK_3, 0xFF},
102 {CS35L35_INT_MASK_4, 0xFF},
103
104 };
105
cs35l35_volatile_register(struct device * dev,unsigned int reg)106 static bool cs35l35_volatile_register(struct device *dev, unsigned int reg)
107 {
108 switch (reg) {
109 case CS35L35_INT_STATUS_1:
110 case CS35L35_INT_STATUS_2:
111 case CS35L35_INT_STATUS_3:
112 case CS35L35_INT_STATUS_4:
113 case CS35L35_PLL_STATUS:
114 case CS35L35_OTP_TRIM_STATUS:
115 return true;
116 default:
117 return false;
118 }
119 }
120
cs35l35_readable_register(struct device * dev,unsigned int reg)121 static bool cs35l35_readable_register(struct device *dev, unsigned int reg)
122 {
123 switch (reg) {
124 case CS35L35_DEVID_AB ... CS35L35_PWRCTL3:
125 case CS35L35_CLK_CTL1 ... CS35L35_SP_FMT_CTL3:
126 case CS35L35_MAG_COMP_CTL ... CS35L35_AMP_GAIN_AUD_CTL:
127 case CS35L35_AMP_GAIN_PDM_CTL ... CS35L35_BST_PEAK_I:
128 case CS35L35_BST_RAMP_CTL ... CS35L35_BST_CONV_SW_FREQ:
129 case CS35L35_CLASS_H_CTL ... CS35L35_CLASS_H_VP_CTL:
130 case CS35L35_CLASS_H_STATUS:
131 case CS35L35_VPBR_CTL ... CS35L35_VPBR_MODE_VOL_CTL:
132 case CS35L35_VPBR_ATTEN_STATUS:
133 case CS35L35_SPKR_MON_CTL:
134 case CS35L35_IMON_SCALE_CTL ... CS35L35_ZEROFILL_DEPTH_CTL:
135 case CS35L35_MULT_DEV_SYNCH1 ... CS35L35_PROT_RELEASE_CTL:
136 case CS35L35_DIAG_MODE_REG_LOCK ... CS35L35_DIAG_MODE_CTL_2:
137 case CS35L35_INT_MASK_1 ... CS35L35_PLL_STATUS:
138 case CS35L35_OTP_TRIM_STATUS:
139 return true;
140 default:
141 return false;
142 }
143 }
144
cs35l35_precious_register(struct device * dev,unsigned int reg)145 static bool cs35l35_precious_register(struct device *dev, unsigned int reg)
146 {
147 switch (reg) {
148 case CS35L35_INT_STATUS_1:
149 case CS35L35_INT_STATUS_2:
150 case CS35L35_INT_STATUS_3:
151 case CS35L35_INT_STATUS_4:
152 case CS35L35_PLL_STATUS:
153 case CS35L35_OTP_TRIM_STATUS:
154 return true;
155 default:
156 return false;
157 }
158 }
159
cs35l35_reset(struct cs35l35_private * cs35l35)160 static void cs35l35_reset(struct cs35l35_private *cs35l35)
161 {
162 gpiod_set_value_cansleep(cs35l35->reset_gpio, 0);
163 usleep_range(2000, 2100);
164 gpiod_set_value_cansleep(cs35l35->reset_gpio, 1);
165 usleep_range(1000, 1100);
166 }
167
cs35l35_wait_for_pdn(struct cs35l35_private * cs35l35)168 static int cs35l35_wait_for_pdn(struct cs35l35_private *cs35l35)
169 {
170 int ret;
171
172 if (cs35l35->pdata.ext_bst) {
173 usleep_range(5000, 5500);
174 return 0;
175 }
176
177 reinit_completion(&cs35l35->pdn_done);
178
179 ret = wait_for_completion_timeout(&cs35l35->pdn_done,
180 msecs_to_jiffies(100));
181 if (ret == 0) {
182 dev_err(cs35l35->dev, "PDN_DONE did not complete\n");
183 return -ETIMEDOUT;
184 }
185
186 return 0;
187 }
188
cs35l35_sdin_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)189 static int cs35l35_sdin_event(struct snd_soc_dapm_widget *w,
190 struct snd_kcontrol *kcontrol, int event)
191 {
192 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
193 struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
194 int ret = 0;
195
196 switch (event) {
197 case SND_SOC_DAPM_PRE_PMU:
198 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
199 CS35L35_MCLK_DIS_MASK,
200 0 << CS35L35_MCLK_DIS_SHIFT);
201 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
202 CS35L35_DISCHG_FILT_MASK,
203 0 << CS35L35_DISCHG_FILT_SHIFT);
204 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
205 CS35L35_PDN_ALL_MASK, 0);
206 break;
207 case SND_SOC_DAPM_POST_PMD:
208 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
209 CS35L35_DISCHG_FILT_MASK,
210 1 << CS35L35_DISCHG_FILT_SHIFT);
211 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
212 CS35L35_PDN_ALL_MASK, 1);
213
214 /* Already muted, so disable volume ramp for faster shutdown */
215 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_DIG_VOL_CTL,
216 CS35L35_AMP_DIGSFT_MASK, 0);
217
218 ret = cs35l35_wait_for_pdn(cs35l35);
219
220 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
221 CS35L35_MCLK_DIS_MASK,
222 1 << CS35L35_MCLK_DIS_SHIFT);
223
224 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_DIG_VOL_CTL,
225 CS35L35_AMP_DIGSFT_MASK,
226 1 << CS35L35_AMP_DIGSFT_SHIFT);
227 break;
228 default:
229 dev_err(component->dev, "Invalid event = 0x%x\n", event);
230 ret = -EINVAL;
231 }
232 return ret;
233 }
234
cs35l35_main_amp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)235 static int cs35l35_main_amp_event(struct snd_soc_dapm_widget *w,
236 struct snd_kcontrol *kcontrol, int event)
237 {
238 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
239 struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
240 unsigned int reg[4];
241 int i;
242
243 switch (event) {
244 case SND_SOC_DAPM_PRE_PMU:
245 if (cs35l35->pdata.bst_pdn_fet_on)
246 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
247 CS35L35_PDN_BST_MASK,
248 0 << CS35L35_PDN_BST_FETON_SHIFT);
249 else
250 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
251 CS35L35_PDN_BST_MASK,
252 0 << CS35L35_PDN_BST_FETOFF_SHIFT);
253 break;
254 case SND_SOC_DAPM_POST_PMU:
255 usleep_range(5000, 5100);
256 /* If in PDM mode we must use VP for Voltage control */
257 if (cs35l35->pdm_mode)
258 regmap_update_bits(cs35l35->regmap,
259 CS35L35_BST_CVTR_V_CTL,
260 CS35L35_BST_CTL_MASK,
261 0 << CS35L35_BST_CTL_SHIFT);
262
263 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
264 CS35L35_AMP_MUTE_MASK, 0);
265
266 for (i = 0; i < 2; i++)
267 regmap_bulk_read(cs35l35->regmap, CS35L35_INT_STATUS_1,
268 ®, ARRAY_SIZE(reg));
269
270 break;
271 case SND_SOC_DAPM_PRE_PMD:
272 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
273 CS35L35_AMP_MUTE_MASK,
274 1 << CS35L35_AMP_MUTE_SHIFT);
275 if (cs35l35->pdata.bst_pdn_fet_on)
276 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
277 CS35L35_PDN_BST_MASK,
278 1 << CS35L35_PDN_BST_FETON_SHIFT);
279 else
280 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
281 CS35L35_PDN_BST_MASK,
282 1 << CS35L35_PDN_BST_FETOFF_SHIFT);
283 break;
284 case SND_SOC_DAPM_POST_PMD:
285 usleep_range(5000, 5100);
286 /*
287 * If PDM mode we should switch back to pdata value
288 * for Voltage control when we go down
289 */
290 if (cs35l35->pdm_mode)
291 regmap_update_bits(cs35l35->regmap,
292 CS35L35_BST_CVTR_V_CTL,
293 CS35L35_BST_CTL_MASK,
294 cs35l35->pdata.bst_vctl
295 << CS35L35_BST_CTL_SHIFT);
296
297 break;
298 default:
299 dev_err(component->dev, "Invalid event = 0x%x\n", event);
300 }
301 return 0;
302 }
303
304 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1);
305 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 50, 0);
306
307 static const struct snd_kcontrol_new cs35l35_aud_controls[] = {
308 SOC_SINGLE_SX_TLV("Digital Audio Volume", CS35L35_AMP_DIG_VOL,
309 0, 0x34, 0xE4, dig_vol_tlv),
310 SOC_SINGLE_TLV("Analog Audio Volume", CS35L35_AMP_GAIN_AUD_CTL, 0, 19, 0,
311 amp_gain_tlv),
312 SOC_SINGLE_TLV("PDM Volume", CS35L35_AMP_GAIN_PDM_CTL, 0, 19, 0,
313 amp_gain_tlv),
314 };
315
316 static const struct snd_kcontrol_new cs35l35_adv_controls[] = {
317 SOC_SINGLE_SX_TLV("Digital Advisory Volume", CS35L35_ADV_DIG_VOL,
318 0, 0x34, 0xE4, dig_vol_tlv),
319 SOC_SINGLE_TLV("Analog Advisory Volume", CS35L35_AMP_GAIN_ADV_CTL, 0, 19, 0,
320 amp_gain_tlv),
321 };
322
323 static const struct snd_soc_dapm_widget cs35l35_dapm_widgets[] = {
324 SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L35_PWRCTL3, 1, 1,
325 cs35l35_sdin_event, SND_SOC_DAPM_PRE_PMU |
326 SND_SOC_DAPM_POST_PMD),
327 SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L35_PWRCTL3, 2, 1),
328
329 SND_SOC_DAPM_OUTPUT("SPK"),
330
331 SND_SOC_DAPM_INPUT("VP"),
332 SND_SOC_DAPM_INPUT("VBST"),
333 SND_SOC_DAPM_INPUT("ISENSE"),
334 SND_SOC_DAPM_INPUT("VSENSE"),
335
336 SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L35_PWRCTL2, 7, 1),
337 SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L35_PWRCTL2, 6, 1),
338 SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L35_PWRCTL3, 3, 1),
339 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L35_PWRCTL3, 4, 1),
340 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L35_PWRCTL2, 5, 1),
341
342 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L35_PWRCTL2, 0, 1, NULL, 0,
343 cs35l35_main_amp_event, SND_SOC_DAPM_PRE_PMU |
344 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU |
345 SND_SOC_DAPM_PRE_PMD),
346 };
347
348 static const struct snd_soc_dapm_route cs35l35_audio_map[] = {
349 {"VPMON ADC", NULL, "VP"},
350 {"VBSTMON ADC", NULL, "VBST"},
351 {"IMON ADC", NULL, "ISENSE"},
352 {"VMON ADC", NULL, "VSENSE"},
353 {"SDOUT", NULL, "IMON ADC"},
354 {"SDOUT", NULL, "VMON ADC"},
355 {"SDOUT", NULL, "VBSTMON ADC"},
356 {"SDOUT", NULL, "VPMON ADC"},
357 {"AMP Capture", NULL, "SDOUT"},
358
359 {"SDIN", NULL, "AMP Playback"},
360 {"CLASS H", NULL, "SDIN"},
361 {"Main AMP", NULL, "CLASS H"},
362 {"SPK", NULL, "Main AMP"},
363 };
364
cs35l35_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)365 static int cs35l35_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
366 {
367 struct snd_soc_component *component = codec_dai->component;
368 struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
369
370 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
371 case SND_SOC_DAIFMT_CBM_CFM:
372 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
373 CS35L35_MS_MASK, 1 << CS35L35_MS_SHIFT);
374 cs35l35->slave_mode = false;
375 break;
376 case SND_SOC_DAIFMT_CBS_CFS:
377 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
378 CS35L35_MS_MASK, 0 << CS35L35_MS_SHIFT);
379 cs35l35->slave_mode = true;
380 break;
381 default:
382 return -EINVAL;
383 }
384
385 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
386 case SND_SOC_DAIFMT_I2S:
387 cs35l35->i2s_mode = true;
388 cs35l35->pdm_mode = false;
389 break;
390 case SND_SOC_DAIFMT_PDM:
391 cs35l35->pdm_mode = true;
392 cs35l35->i2s_mode = false;
393 break;
394 default:
395 return -EINVAL;
396 }
397
398 return 0;
399 }
400
401 struct cs35l35_sysclk_config {
402 int sysclk;
403 int srate;
404 u8 clk_cfg;
405 };
406
407 static struct cs35l35_sysclk_config cs35l35_clk_ctl[] = {
408
409 /* SYSCLK, Sample Rate, Serial Port Cfg */
410 {5644800, 44100, 0x00},
411 {5644800, 88200, 0x40},
412 {6144000, 48000, 0x10},
413 {6144000, 96000, 0x50},
414 {11289600, 44100, 0x01},
415 {11289600, 88200, 0x41},
416 {11289600, 176400, 0x81},
417 {12000000, 44100, 0x03},
418 {12000000, 48000, 0x13},
419 {12000000, 88200, 0x43},
420 {12000000, 96000, 0x53},
421 {12000000, 176400, 0x83},
422 {12000000, 192000, 0x93},
423 {12288000, 48000, 0x11},
424 {12288000, 96000, 0x51},
425 {12288000, 192000, 0x91},
426 {13000000, 44100, 0x07},
427 {13000000, 48000, 0x17},
428 {13000000, 88200, 0x47},
429 {13000000, 96000, 0x57},
430 {13000000, 176400, 0x87},
431 {13000000, 192000, 0x97},
432 {22579200, 44100, 0x02},
433 {22579200, 88200, 0x42},
434 {22579200, 176400, 0x82},
435 {24000000, 44100, 0x0B},
436 {24000000, 48000, 0x1B},
437 {24000000, 88200, 0x4B},
438 {24000000, 96000, 0x5B},
439 {24000000, 176400, 0x8B},
440 {24000000, 192000, 0x9B},
441 {24576000, 48000, 0x12},
442 {24576000, 96000, 0x52},
443 {24576000, 192000, 0x92},
444 {26000000, 44100, 0x0F},
445 {26000000, 48000, 0x1F},
446 {26000000, 88200, 0x4F},
447 {26000000, 96000, 0x5F},
448 {26000000, 176400, 0x8F},
449 {26000000, 192000, 0x9F},
450 };
451
cs35l35_get_clk_config(int sysclk,int srate)452 static int cs35l35_get_clk_config(int sysclk, int srate)
453 {
454 int i;
455
456 for (i = 0; i < ARRAY_SIZE(cs35l35_clk_ctl); i++) {
457 if (cs35l35_clk_ctl[i].sysclk == sysclk &&
458 cs35l35_clk_ctl[i].srate == srate)
459 return cs35l35_clk_ctl[i].clk_cfg;
460 }
461 return -EINVAL;
462 }
463
cs35l35_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)464 static int cs35l35_hw_params(struct snd_pcm_substream *substream,
465 struct snd_pcm_hw_params *params,
466 struct snd_soc_dai *dai)
467 {
468 struct snd_soc_component *component = dai->component;
469 struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
470 struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
471 int srate = params_rate(params);
472 int ret = 0;
473 u8 sp_sclks;
474 int audin_format;
475 int errata_chk;
476
477 int clk_ctl = cs35l35_get_clk_config(cs35l35->sysclk, srate);
478
479 if (clk_ctl < 0) {
480 dev_err(component->dev, "Invalid CLK:Rate %d:%d\n",
481 cs35l35->sysclk, srate);
482 return -EINVAL;
483 }
484
485 ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL2,
486 CS35L35_CLK_CTL2_MASK, clk_ctl);
487 if (ret != 0) {
488 dev_err(component->dev, "Failed to set port config %d\n", ret);
489 return ret;
490 }
491
492 /*
493 * Rev A0 Errata
494 * When configured for the weak-drive detection path (CH_WKFET_DIS = 0)
495 * the Class H algorithm does not enable weak-drive operation for
496 * nonzero values of CH_WKFET_DELAY if SP_RATE = 01 or 10
497 */
498 errata_chk = clk_ctl & CS35L35_SP_RATE_MASK;
499
500 if (classh->classh_wk_fet_disable == 0x00 &&
501 (errata_chk == 0x01 || errata_chk == 0x03)) {
502 ret = regmap_update_bits(cs35l35->regmap,
503 CS35L35_CLASS_H_FET_DRIVE_CTL,
504 CS35L35_CH_WKFET_DEL_MASK,
505 0 << CS35L35_CH_WKFET_DEL_SHIFT);
506 if (ret != 0) {
507 dev_err(component->dev, "Failed to set fet config %d\n",
508 ret);
509 return ret;
510 }
511 }
512
513 /*
514 * You can pull more Monitor data from the SDOUT pin than going to SDIN
515 * Just make sure your SCLK is fast enough to fill the frame
516 */
517 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
518 switch (params_width(params)) {
519 case 8:
520 audin_format = CS35L35_SDIN_DEPTH_8;
521 break;
522 case 16:
523 audin_format = CS35L35_SDIN_DEPTH_16;
524 break;
525 case 24:
526 audin_format = CS35L35_SDIN_DEPTH_24;
527 break;
528 default:
529 dev_err(component->dev, "Unsupported Width %d\n",
530 params_width(params));
531 return -EINVAL;
532 }
533 regmap_update_bits(cs35l35->regmap,
534 CS35L35_AUDIN_DEPTH_CTL,
535 CS35L35_AUDIN_DEPTH_MASK,
536 audin_format <<
537 CS35L35_AUDIN_DEPTH_SHIFT);
538 if (cs35l35->pdata.stereo) {
539 regmap_update_bits(cs35l35->regmap,
540 CS35L35_AUDIN_DEPTH_CTL,
541 CS35L35_ADVIN_DEPTH_MASK,
542 audin_format <<
543 CS35L35_ADVIN_DEPTH_SHIFT);
544 }
545 }
546
547 if (cs35l35->i2s_mode) {
548 /* We have to take the SCLK to derive num sclks
549 * to configure the CLOCK_CTL3 register correctly
550 */
551 if ((cs35l35->sclk / srate) % 4) {
552 dev_err(component->dev, "Unsupported sclk/fs ratio %d:%d\n",
553 cs35l35->sclk, srate);
554 return -EINVAL;
555 }
556 sp_sclks = ((cs35l35->sclk / srate) / 4) - 1;
557
558 /* Only certain ratios are supported in I2S Slave Mode */
559 if (cs35l35->slave_mode) {
560 switch (sp_sclks) {
561 case CS35L35_SP_SCLKS_32FS:
562 case CS35L35_SP_SCLKS_48FS:
563 case CS35L35_SP_SCLKS_64FS:
564 break;
565 default:
566 dev_err(component->dev, "ratio not supported\n");
567 return -EINVAL;
568 }
569 } else {
570 /* Only certain ratios supported in I2S MASTER Mode */
571 switch (sp_sclks) {
572 case CS35L35_SP_SCLKS_32FS:
573 case CS35L35_SP_SCLKS_64FS:
574 break;
575 default:
576 dev_err(component->dev, "ratio not supported\n");
577 return -EINVAL;
578 }
579 }
580 ret = regmap_update_bits(cs35l35->regmap,
581 CS35L35_CLK_CTL3,
582 CS35L35_SP_SCLKS_MASK, sp_sclks <<
583 CS35L35_SP_SCLKS_SHIFT);
584 if (ret != 0) {
585 dev_err(component->dev, "Failed to set fsclk %d\n", ret);
586 return ret;
587 }
588 }
589
590 return ret;
591 }
592
593 static const unsigned int cs35l35_src_rates[] = {
594 44100, 48000, 88200, 96000, 176400, 192000
595 };
596
597 static const struct snd_pcm_hw_constraint_list cs35l35_constraints = {
598 .count = ARRAY_SIZE(cs35l35_src_rates),
599 .list = cs35l35_src_rates,
600 };
601
cs35l35_pcm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)602 static int cs35l35_pcm_startup(struct snd_pcm_substream *substream,
603 struct snd_soc_dai *dai)
604 {
605 struct snd_soc_component *component = dai->component;
606 struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
607
608 if (!substream->runtime)
609 return 0;
610
611 snd_pcm_hw_constraint_list(substream->runtime, 0,
612 SNDRV_PCM_HW_PARAM_RATE, &cs35l35_constraints);
613
614 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
615 CS35L35_PDM_MODE_MASK,
616 0 << CS35L35_PDM_MODE_SHIFT);
617
618 return 0;
619 }
620
621 static const unsigned int cs35l35_pdm_rates[] = {
622 44100, 48000, 88200, 96000
623 };
624
625 static const struct snd_pcm_hw_constraint_list cs35l35_pdm_constraints = {
626 .count = ARRAY_SIZE(cs35l35_pdm_rates),
627 .list = cs35l35_pdm_rates,
628 };
629
cs35l35_pdm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)630 static int cs35l35_pdm_startup(struct snd_pcm_substream *substream,
631 struct snd_soc_dai *dai)
632 {
633 struct snd_soc_component *component = dai->component;
634 struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
635
636 if (!substream->runtime)
637 return 0;
638
639 snd_pcm_hw_constraint_list(substream->runtime, 0,
640 SNDRV_PCM_HW_PARAM_RATE,
641 &cs35l35_pdm_constraints);
642
643 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
644 CS35L35_PDM_MODE_MASK,
645 1 << CS35L35_PDM_MODE_SHIFT);
646
647 return 0;
648 }
649
cs35l35_dai_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)650 static int cs35l35_dai_set_sysclk(struct snd_soc_dai *dai,
651 int clk_id, unsigned int freq, int dir)
652 {
653 struct snd_soc_component *component = dai->component;
654 struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
655
656 /* Need the SCLK Frequency regardless of sysclk source for I2S */
657 cs35l35->sclk = freq;
658
659 return 0;
660 }
661
662 static const struct snd_soc_dai_ops cs35l35_ops = {
663 .startup = cs35l35_pcm_startup,
664 .set_fmt = cs35l35_set_dai_fmt,
665 .hw_params = cs35l35_hw_params,
666 .set_sysclk = cs35l35_dai_set_sysclk,
667 };
668
669 static const struct snd_soc_dai_ops cs35l35_pdm_ops = {
670 .startup = cs35l35_pdm_startup,
671 .set_fmt = cs35l35_set_dai_fmt,
672 .hw_params = cs35l35_hw_params,
673 };
674
675 static struct snd_soc_dai_driver cs35l35_dai[] = {
676 {
677 .name = "cs35l35-pcm",
678 .id = 0,
679 .playback = {
680 .stream_name = "AMP Playback",
681 .channels_min = 1,
682 .channels_max = 8,
683 .rates = SNDRV_PCM_RATE_KNOT,
684 .formats = CS35L35_FORMATS,
685 },
686 .capture = {
687 .stream_name = "AMP Capture",
688 .channels_min = 1,
689 .channels_max = 8,
690 .rates = SNDRV_PCM_RATE_KNOT,
691 .formats = CS35L35_FORMATS,
692 },
693 .ops = &cs35l35_ops,
694 .symmetric_rate = 1,
695 },
696 {
697 .name = "cs35l35-pdm",
698 .id = 1,
699 .playback = {
700 .stream_name = "PDM Playback",
701 .channels_min = 1,
702 .channels_max = 2,
703 .rates = SNDRV_PCM_RATE_KNOT,
704 .formats = CS35L35_FORMATS,
705 },
706 .ops = &cs35l35_pdm_ops,
707 },
708 };
709
cs35l35_component_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)710 static int cs35l35_component_set_sysclk(struct snd_soc_component *component,
711 int clk_id, int source, unsigned int freq,
712 int dir)
713 {
714 struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
715 int clksrc;
716 int ret = 0;
717
718 switch (clk_id) {
719 case 0:
720 clksrc = CS35L35_CLK_SOURCE_MCLK;
721 break;
722 case 1:
723 clksrc = CS35L35_CLK_SOURCE_SCLK;
724 break;
725 case 2:
726 clksrc = CS35L35_CLK_SOURCE_PDM;
727 break;
728 default:
729 dev_err(component->dev, "Invalid CLK Source\n");
730 return -EINVAL;
731 }
732
733 switch (freq) {
734 case 5644800:
735 case 6144000:
736 case 11289600:
737 case 12000000:
738 case 12288000:
739 case 13000000:
740 case 22579200:
741 case 24000000:
742 case 24576000:
743 case 26000000:
744 cs35l35->sysclk = freq;
745 break;
746 default:
747 dev_err(component->dev, "Invalid CLK Frequency Input : %d\n", freq);
748 return -EINVAL;
749 }
750
751 ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
752 CS35L35_CLK_SOURCE_MASK,
753 clksrc << CS35L35_CLK_SOURCE_SHIFT);
754 if (ret != 0) {
755 dev_err(component->dev, "Failed to set sysclk %d\n", ret);
756 return ret;
757 }
758
759 return ret;
760 }
761
cs35l35_boost_inductor(struct cs35l35_private * cs35l35,int inductor)762 static int cs35l35_boost_inductor(struct cs35l35_private *cs35l35,
763 int inductor)
764 {
765 struct regmap *regmap = cs35l35->regmap;
766 unsigned int bst_ipk = 0;
767
768 /*
769 * Digital Boost Converter Configuration for feedback,
770 * ramping, switching frequency, and estimation block seeding.
771 */
772
773 regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
774 CS35L35_BST_CONV_SWFREQ_MASK, 0x00);
775
776 regmap_read(regmap, CS35L35_BST_PEAK_I, &bst_ipk);
777 bst_ipk &= CS35L35_BST_IPK_MASK;
778
779 switch (inductor) {
780 case 1000: /* 1 uH */
781 regmap_write(regmap, CS35L35_BST_CONV_COEF_1, 0x24);
782 regmap_write(regmap, CS35L35_BST_CONV_COEF_2, 0x24);
783 regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
784 CS35L35_BST_CONV_LBST_MASK, 0x00);
785
786 if (bst_ipk < 0x04)
787 regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x1B);
788 else
789 regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x4E);
790 break;
791 case 1200: /* 1.2 uH */
792 regmap_write(regmap, CS35L35_BST_CONV_COEF_1, 0x20);
793 regmap_write(regmap, CS35L35_BST_CONV_COEF_2, 0x20);
794 regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
795 CS35L35_BST_CONV_LBST_MASK, 0x01);
796
797 if (bst_ipk < 0x04)
798 regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x1B);
799 else
800 regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x47);
801 break;
802 case 1500: /* 1.5uH */
803 regmap_write(regmap, CS35L35_BST_CONV_COEF_1, 0x20);
804 regmap_write(regmap, CS35L35_BST_CONV_COEF_2, 0x20);
805 regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
806 CS35L35_BST_CONV_LBST_MASK, 0x02);
807
808 if (bst_ipk < 0x04)
809 regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x1B);
810 else
811 regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x3C);
812 break;
813 case 2200: /* 2.2uH */
814 regmap_write(regmap, CS35L35_BST_CONV_COEF_1, 0x19);
815 regmap_write(regmap, CS35L35_BST_CONV_COEF_2, 0x25);
816 regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
817 CS35L35_BST_CONV_LBST_MASK, 0x03);
818
819 if (bst_ipk < 0x04)
820 regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x1B);
821 else
822 regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x23);
823 break;
824 default:
825 dev_err(cs35l35->dev, "Invalid Inductor Value %d uH\n",
826 inductor);
827 return -EINVAL;
828 }
829 return 0;
830 }
831
cs35l35_component_probe(struct snd_soc_component * component)832 static int cs35l35_component_probe(struct snd_soc_component *component)
833 {
834 struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
835 struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
836 struct monitor_cfg *monitor_config = &cs35l35->pdata.mon_cfg;
837 int ret;
838
839 /* Set Platform Data */
840 if (cs35l35->pdata.bst_vctl)
841 regmap_update_bits(cs35l35->regmap, CS35L35_BST_CVTR_V_CTL,
842 CS35L35_BST_CTL_MASK,
843 cs35l35->pdata.bst_vctl);
844
845 if (cs35l35->pdata.bst_ipk)
846 regmap_update_bits(cs35l35->regmap, CS35L35_BST_PEAK_I,
847 CS35L35_BST_IPK_MASK,
848 cs35l35->pdata.bst_ipk <<
849 CS35L35_BST_IPK_SHIFT);
850
851 ret = cs35l35_boost_inductor(cs35l35, cs35l35->pdata.boost_ind);
852 if (ret)
853 return ret;
854
855 if (cs35l35->pdata.gain_zc)
856 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
857 CS35L35_AMP_GAIN_ZC_MASK,
858 cs35l35->pdata.gain_zc <<
859 CS35L35_AMP_GAIN_ZC_SHIFT);
860
861 if (cs35l35->pdata.aud_channel)
862 regmap_update_bits(cs35l35->regmap,
863 CS35L35_AUDIN_RXLOC_CTL,
864 CS35L35_AUD_IN_LR_MASK,
865 cs35l35->pdata.aud_channel <<
866 CS35L35_AUD_IN_LR_SHIFT);
867
868 if (cs35l35->pdata.stereo) {
869 regmap_update_bits(cs35l35->regmap,
870 CS35L35_ADVIN_RXLOC_CTL,
871 CS35L35_ADV_IN_LR_MASK,
872 cs35l35->pdata.adv_channel <<
873 CS35L35_ADV_IN_LR_SHIFT);
874 if (cs35l35->pdata.shared_bst)
875 regmap_update_bits(cs35l35->regmap, CS35L35_CLASS_H_CTL,
876 CS35L35_CH_STEREO_MASK,
877 1 << CS35L35_CH_STEREO_SHIFT);
878 ret = snd_soc_add_component_controls(component, cs35l35_adv_controls,
879 ARRAY_SIZE(cs35l35_adv_controls));
880 if (ret)
881 return ret;
882 }
883
884 if (cs35l35->pdata.sp_drv_str)
885 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
886 CS35L35_SP_DRV_MASK,
887 cs35l35->pdata.sp_drv_str <<
888 CS35L35_SP_DRV_SHIFT);
889 if (cs35l35->pdata.sp_drv_unused)
890 regmap_update_bits(cs35l35->regmap, CS35L35_SP_FMT_CTL3,
891 CS35L35_SP_I2S_DRV_MASK,
892 cs35l35->pdata.sp_drv_unused <<
893 CS35L35_SP_I2S_DRV_SHIFT);
894
895 if (classh->classh_algo_enable) {
896 if (classh->classh_bst_override)
897 regmap_update_bits(cs35l35->regmap,
898 CS35L35_CLASS_H_CTL,
899 CS35L35_CH_BST_OVR_MASK,
900 classh->classh_bst_override <<
901 CS35L35_CH_BST_OVR_SHIFT);
902 if (classh->classh_bst_max_limit)
903 regmap_update_bits(cs35l35->regmap,
904 CS35L35_CLASS_H_CTL,
905 CS35L35_CH_BST_LIM_MASK,
906 classh->classh_bst_max_limit <<
907 CS35L35_CH_BST_LIM_SHIFT);
908 if (classh->classh_mem_depth)
909 regmap_update_bits(cs35l35->regmap,
910 CS35L35_CLASS_H_CTL,
911 CS35L35_CH_MEM_DEPTH_MASK,
912 classh->classh_mem_depth <<
913 CS35L35_CH_MEM_DEPTH_SHIFT);
914 if (classh->classh_headroom)
915 regmap_update_bits(cs35l35->regmap,
916 CS35L35_CLASS_H_HEADRM_CTL,
917 CS35L35_CH_HDRM_CTL_MASK,
918 classh->classh_headroom <<
919 CS35L35_CH_HDRM_CTL_SHIFT);
920 if (classh->classh_release_rate)
921 regmap_update_bits(cs35l35->regmap,
922 CS35L35_CLASS_H_RELEASE_RATE,
923 CS35L35_CH_REL_RATE_MASK,
924 classh->classh_release_rate <<
925 CS35L35_CH_REL_RATE_SHIFT);
926 if (classh->classh_wk_fet_disable)
927 regmap_update_bits(cs35l35->regmap,
928 CS35L35_CLASS_H_FET_DRIVE_CTL,
929 CS35L35_CH_WKFET_DIS_MASK,
930 classh->classh_wk_fet_disable <<
931 CS35L35_CH_WKFET_DIS_SHIFT);
932 if (classh->classh_wk_fet_delay)
933 regmap_update_bits(cs35l35->regmap,
934 CS35L35_CLASS_H_FET_DRIVE_CTL,
935 CS35L35_CH_WKFET_DEL_MASK,
936 classh->classh_wk_fet_delay <<
937 CS35L35_CH_WKFET_DEL_SHIFT);
938 if (classh->classh_wk_fet_thld)
939 regmap_update_bits(cs35l35->regmap,
940 CS35L35_CLASS_H_FET_DRIVE_CTL,
941 CS35L35_CH_WKFET_THLD_MASK,
942 classh->classh_wk_fet_thld <<
943 CS35L35_CH_WKFET_THLD_SHIFT);
944 if (classh->classh_vpch_auto)
945 regmap_update_bits(cs35l35->regmap,
946 CS35L35_CLASS_H_VP_CTL,
947 CS35L35_CH_VP_AUTO_MASK,
948 classh->classh_vpch_auto <<
949 CS35L35_CH_VP_AUTO_SHIFT);
950 if (classh->classh_vpch_rate)
951 regmap_update_bits(cs35l35->regmap,
952 CS35L35_CLASS_H_VP_CTL,
953 CS35L35_CH_VP_RATE_MASK,
954 classh->classh_vpch_rate <<
955 CS35L35_CH_VP_RATE_SHIFT);
956 if (classh->classh_vpch_man)
957 regmap_update_bits(cs35l35->regmap,
958 CS35L35_CLASS_H_VP_CTL,
959 CS35L35_CH_VP_MAN_MASK,
960 classh->classh_vpch_man <<
961 CS35L35_CH_VP_MAN_SHIFT);
962 }
963
964 if (monitor_config->is_present) {
965 if (monitor_config->vmon_specs) {
966 regmap_update_bits(cs35l35->regmap,
967 CS35L35_SPKMON_DEPTH_CTL,
968 CS35L35_VMON_DEPTH_MASK,
969 monitor_config->vmon_dpth <<
970 CS35L35_VMON_DEPTH_SHIFT);
971 regmap_update_bits(cs35l35->regmap,
972 CS35L35_VMON_TXLOC_CTL,
973 CS35L35_MON_TXLOC_MASK,
974 monitor_config->vmon_loc <<
975 CS35L35_MON_TXLOC_SHIFT);
976 regmap_update_bits(cs35l35->regmap,
977 CS35L35_VMON_TXLOC_CTL,
978 CS35L35_MON_FRM_MASK,
979 monitor_config->vmon_frm <<
980 CS35L35_MON_FRM_SHIFT);
981 }
982 if (monitor_config->imon_specs) {
983 regmap_update_bits(cs35l35->regmap,
984 CS35L35_SPKMON_DEPTH_CTL,
985 CS35L35_IMON_DEPTH_MASK,
986 monitor_config->imon_dpth <<
987 CS35L35_IMON_DEPTH_SHIFT);
988 regmap_update_bits(cs35l35->regmap,
989 CS35L35_IMON_TXLOC_CTL,
990 CS35L35_MON_TXLOC_MASK,
991 monitor_config->imon_loc <<
992 CS35L35_MON_TXLOC_SHIFT);
993 regmap_update_bits(cs35l35->regmap,
994 CS35L35_IMON_TXLOC_CTL,
995 CS35L35_MON_FRM_MASK,
996 monitor_config->imon_frm <<
997 CS35L35_MON_FRM_SHIFT);
998 regmap_update_bits(cs35l35->regmap,
999 CS35L35_IMON_SCALE_CTL,
1000 CS35L35_IMON_SCALE_MASK,
1001 monitor_config->imon_scale <<
1002 CS35L35_IMON_SCALE_SHIFT);
1003 }
1004 if (monitor_config->vpmon_specs) {
1005 regmap_update_bits(cs35l35->regmap,
1006 CS35L35_SUPMON_DEPTH_CTL,
1007 CS35L35_VPMON_DEPTH_MASK,
1008 monitor_config->vpmon_dpth <<
1009 CS35L35_VPMON_DEPTH_SHIFT);
1010 regmap_update_bits(cs35l35->regmap,
1011 CS35L35_VPMON_TXLOC_CTL,
1012 CS35L35_MON_TXLOC_MASK,
1013 monitor_config->vpmon_loc <<
1014 CS35L35_MON_TXLOC_SHIFT);
1015 regmap_update_bits(cs35l35->regmap,
1016 CS35L35_VPMON_TXLOC_CTL,
1017 CS35L35_MON_FRM_MASK,
1018 monitor_config->vpmon_frm <<
1019 CS35L35_MON_FRM_SHIFT);
1020 }
1021 if (monitor_config->vbstmon_specs) {
1022 regmap_update_bits(cs35l35->regmap,
1023 CS35L35_SUPMON_DEPTH_CTL,
1024 CS35L35_VBSTMON_DEPTH_MASK,
1025 monitor_config->vpmon_dpth <<
1026 CS35L35_VBSTMON_DEPTH_SHIFT);
1027 regmap_update_bits(cs35l35->regmap,
1028 CS35L35_VBSTMON_TXLOC_CTL,
1029 CS35L35_MON_TXLOC_MASK,
1030 monitor_config->vbstmon_loc <<
1031 CS35L35_MON_TXLOC_SHIFT);
1032 regmap_update_bits(cs35l35->regmap,
1033 CS35L35_VBSTMON_TXLOC_CTL,
1034 CS35L35_MON_FRM_MASK,
1035 monitor_config->vbstmon_frm <<
1036 CS35L35_MON_FRM_SHIFT);
1037 }
1038 if (monitor_config->vpbrstat_specs) {
1039 regmap_update_bits(cs35l35->regmap,
1040 CS35L35_SUPMON_DEPTH_CTL,
1041 CS35L35_VPBRSTAT_DEPTH_MASK,
1042 monitor_config->vpbrstat_dpth <<
1043 CS35L35_VPBRSTAT_DEPTH_SHIFT);
1044 regmap_update_bits(cs35l35->regmap,
1045 CS35L35_VPBR_STATUS_TXLOC_CTL,
1046 CS35L35_MON_TXLOC_MASK,
1047 monitor_config->vpbrstat_loc <<
1048 CS35L35_MON_TXLOC_SHIFT);
1049 regmap_update_bits(cs35l35->regmap,
1050 CS35L35_VPBR_STATUS_TXLOC_CTL,
1051 CS35L35_MON_FRM_MASK,
1052 monitor_config->vpbrstat_frm <<
1053 CS35L35_MON_FRM_SHIFT);
1054 }
1055 if (monitor_config->zerofill_specs) {
1056 regmap_update_bits(cs35l35->regmap,
1057 CS35L35_SUPMON_DEPTH_CTL,
1058 CS35L35_ZEROFILL_DEPTH_MASK,
1059 monitor_config->zerofill_dpth <<
1060 CS35L35_ZEROFILL_DEPTH_SHIFT);
1061 regmap_update_bits(cs35l35->regmap,
1062 CS35L35_ZERO_FILL_LOC_CTL,
1063 CS35L35_MON_TXLOC_MASK,
1064 monitor_config->zerofill_loc <<
1065 CS35L35_MON_TXLOC_SHIFT);
1066 regmap_update_bits(cs35l35->regmap,
1067 CS35L35_ZERO_FILL_LOC_CTL,
1068 CS35L35_MON_FRM_MASK,
1069 monitor_config->zerofill_frm <<
1070 CS35L35_MON_FRM_SHIFT);
1071 }
1072 }
1073
1074 return 0;
1075 }
1076
1077 static const struct snd_soc_component_driver soc_component_dev_cs35l35 = {
1078 .probe = cs35l35_component_probe,
1079 .set_sysclk = cs35l35_component_set_sysclk,
1080 .dapm_widgets = cs35l35_dapm_widgets,
1081 .num_dapm_widgets = ARRAY_SIZE(cs35l35_dapm_widgets),
1082 .dapm_routes = cs35l35_audio_map,
1083 .num_dapm_routes = ARRAY_SIZE(cs35l35_audio_map),
1084 .controls = cs35l35_aud_controls,
1085 .num_controls = ARRAY_SIZE(cs35l35_aud_controls),
1086 .idle_bias_on = 1,
1087 .use_pmdown_time = 1,
1088 .endianness = 1,
1089 .non_legacy_dai_naming = 1,
1090 };
1091
1092 static struct regmap_config cs35l35_regmap = {
1093 .reg_bits = 8,
1094 .val_bits = 8,
1095
1096 .max_register = CS35L35_MAX_REGISTER,
1097 .reg_defaults = cs35l35_reg,
1098 .num_reg_defaults = ARRAY_SIZE(cs35l35_reg),
1099 .volatile_reg = cs35l35_volatile_register,
1100 .readable_reg = cs35l35_readable_register,
1101 .precious_reg = cs35l35_precious_register,
1102 .cache_type = REGCACHE_RBTREE,
1103 .use_single_read = true,
1104 .use_single_write = true,
1105 };
1106
cs35l35_irq(int irq,void * data)1107 static irqreturn_t cs35l35_irq(int irq, void *data)
1108 {
1109 struct cs35l35_private *cs35l35 = data;
1110 unsigned int sticky1, sticky2, sticky3, sticky4;
1111 unsigned int mask1, mask2, mask3, mask4, current1;
1112
1113 /* ack the irq by reading all status registers */
1114 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_4, &sticky4);
1115 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_3, &sticky3);
1116 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_2, &sticky2);
1117 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, &sticky1);
1118
1119 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_4, &mask4);
1120 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_3, &mask3);
1121 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_2, &mask2);
1122 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_1, &mask1);
1123
1124 /* Check to see if unmasked bits are active */
1125 if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3)
1126 && !(sticky4 & ~mask4))
1127 return IRQ_NONE;
1128
1129 if (sticky2 & CS35L35_PDN_DONE)
1130 complete(&cs35l35->pdn_done);
1131
1132 /* read the current values */
1133 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, ¤t1);
1134
1135 /* handle the interrupts */
1136 if (sticky1 & CS35L35_CAL_ERR) {
1137 dev_crit(cs35l35->dev, "Calibration Error\n");
1138
1139 /* error is no longer asserted; safe to reset */
1140 if (!(current1 & CS35L35_CAL_ERR)) {
1141 pr_debug("%s : Cal error release\n", __func__);
1142 regmap_update_bits(cs35l35->regmap,
1143 CS35L35_PROT_RELEASE_CTL,
1144 CS35L35_CAL_ERR_RLS, 0);
1145 regmap_update_bits(cs35l35->regmap,
1146 CS35L35_PROT_RELEASE_CTL,
1147 CS35L35_CAL_ERR_RLS,
1148 CS35L35_CAL_ERR_RLS);
1149 regmap_update_bits(cs35l35->regmap,
1150 CS35L35_PROT_RELEASE_CTL,
1151 CS35L35_CAL_ERR_RLS, 0);
1152 }
1153 }
1154
1155 if (sticky1 & CS35L35_AMP_SHORT) {
1156 dev_crit(cs35l35->dev, "AMP Short Error\n");
1157 /* error is no longer asserted; safe to reset */
1158 if (!(current1 & CS35L35_AMP_SHORT)) {
1159 dev_dbg(cs35l35->dev, "Amp short error release\n");
1160 regmap_update_bits(cs35l35->regmap,
1161 CS35L35_PROT_RELEASE_CTL,
1162 CS35L35_SHORT_RLS, 0);
1163 regmap_update_bits(cs35l35->regmap,
1164 CS35L35_PROT_RELEASE_CTL,
1165 CS35L35_SHORT_RLS,
1166 CS35L35_SHORT_RLS);
1167 regmap_update_bits(cs35l35->regmap,
1168 CS35L35_PROT_RELEASE_CTL,
1169 CS35L35_SHORT_RLS, 0);
1170 }
1171 }
1172
1173 if (sticky1 & CS35L35_OTW) {
1174 dev_warn(cs35l35->dev, "Over temperature warning\n");
1175
1176 /* error is no longer asserted; safe to reset */
1177 if (!(current1 & CS35L35_OTW)) {
1178 dev_dbg(cs35l35->dev, "Over temperature warn release\n");
1179 regmap_update_bits(cs35l35->regmap,
1180 CS35L35_PROT_RELEASE_CTL,
1181 CS35L35_OTW_RLS, 0);
1182 regmap_update_bits(cs35l35->regmap,
1183 CS35L35_PROT_RELEASE_CTL,
1184 CS35L35_OTW_RLS,
1185 CS35L35_OTW_RLS);
1186 regmap_update_bits(cs35l35->regmap,
1187 CS35L35_PROT_RELEASE_CTL,
1188 CS35L35_OTW_RLS, 0);
1189 }
1190 }
1191
1192 if (sticky1 & CS35L35_OTE) {
1193 dev_crit(cs35l35->dev, "Over temperature error\n");
1194 /* error is no longer asserted; safe to reset */
1195 if (!(current1 & CS35L35_OTE)) {
1196 dev_dbg(cs35l35->dev, "Over temperature error release\n");
1197 regmap_update_bits(cs35l35->regmap,
1198 CS35L35_PROT_RELEASE_CTL,
1199 CS35L35_OTE_RLS, 0);
1200 regmap_update_bits(cs35l35->regmap,
1201 CS35L35_PROT_RELEASE_CTL,
1202 CS35L35_OTE_RLS,
1203 CS35L35_OTE_RLS);
1204 regmap_update_bits(cs35l35->regmap,
1205 CS35L35_PROT_RELEASE_CTL,
1206 CS35L35_OTE_RLS, 0);
1207 }
1208 }
1209
1210 if (sticky3 & CS35L35_BST_HIGH) {
1211 dev_crit(cs35l35->dev, "VBST error: powering off!\n");
1212 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1213 CS35L35_PDN_AMP, CS35L35_PDN_AMP);
1214 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
1215 CS35L35_PDN_ALL, CS35L35_PDN_ALL);
1216 }
1217
1218 if (sticky3 & CS35L35_LBST_SHORT) {
1219 dev_crit(cs35l35->dev, "LBST error: powering off!\n");
1220 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1221 CS35L35_PDN_AMP, CS35L35_PDN_AMP);
1222 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
1223 CS35L35_PDN_ALL, CS35L35_PDN_ALL);
1224 }
1225
1226 if (sticky2 & CS35L35_VPBR_ERR)
1227 dev_dbg(cs35l35->dev, "Error: Reactive Brownout\n");
1228
1229 if (sticky4 & CS35L35_VMON_OVFL)
1230 dev_dbg(cs35l35->dev, "Error: VMON overflow\n");
1231
1232 if (sticky4 & CS35L35_IMON_OVFL)
1233 dev_dbg(cs35l35->dev, "Error: IMON overflow\n");
1234
1235 return IRQ_HANDLED;
1236 }
1237
1238
cs35l35_handle_of_data(struct i2c_client * i2c_client,struct cs35l35_platform_data * pdata)1239 static int cs35l35_handle_of_data(struct i2c_client *i2c_client,
1240 struct cs35l35_platform_data *pdata)
1241 {
1242 struct device_node *np = i2c_client->dev.of_node;
1243 struct device_node *classh, *signal_format;
1244 struct classh_cfg *classh_config = &pdata->classh_algo;
1245 struct monitor_cfg *monitor_config = &pdata->mon_cfg;
1246 unsigned int val32 = 0;
1247 u8 monitor_array[4];
1248 const int imon_array_size = ARRAY_SIZE(monitor_array);
1249 const int mon_array_size = imon_array_size - 1;
1250 int ret = 0;
1251
1252 if (!np)
1253 return 0;
1254
1255 pdata->bst_pdn_fet_on = of_property_read_bool(np,
1256 "cirrus,boost-pdn-fet-on");
1257
1258 ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val32);
1259 if (ret >= 0) {
1260 if (val32 < 2600 || val32 > 9000) {
1261 dev_err(&i2c_client->dev,
1262 "Invalid Boost Voltage %d mV\n", val32);
1263 return -EINVAL;
1264 }
1265 pdata->bst_vctl = ((val32 - 2600) / 100) + 1;
1266 }
1267
1268 ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val32);
1269 if (ret >= 0) {
1270 if (val32 < 1680 || val32 > 4480) {
1271 dev_err(&i2c_client->dev,
1272 "Invalid Boost Peak Current %u mA\n", val32);
1273 return -EINVAL;
1274 }
1275
1276 pdata->bst_ipk = ((val32 - 1680) / 110) | CS35L35_VALID_PDATA;
1277 }
1278
1279 ret = of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val32);
1280 if (ret >= 0) {
1281 pdata->boost_ind = val32;
1282 } else {
1283 dev_err(&i2c_client->dev, "Inductor not specified.\n");
1284 return -EINVAL;
1285 }
1286
1287 if (of_property_read_u32(np, "cirrus,sp-drv-strength", &val32) >= 0)
1288 pdata->sp_drv_str = val32;
1289 if (of_property_read_u32(np, "cirrus,sp-drv-unused", &val32) >= 0)
1290 pdata->sp_drv_unused = val32 | CS35L35_VALID_PDATA;
1291
1292 pdata->stereo = of_property_read_bool(np, "cirrus,stereo-config");
1293
1294 if (pdata->stereo) {
1295 ret = of_property_read_u32(np, "cirrus,audio-channel", &val32);
1296 if (ret >= 0)
1297 pdata->aud_channel = val32;
1298
1299 ret = of_property_read_u32(np, "cirrus,advisory-channel",
1300 &val32);
1301 if (ret >= 0)
1302 pdata->adv_channel = val32;
1303
1304 pdata->shared_bst = of_property_read_bool(np,
1305 "cirrus,shared-boost");
1306 }
1307
1308 pdata->ext_bst = of_property_read_bool(np, "cirrus,external-boost");
1309
1310 pdata->gain_zc = of_property_read_bool(np, "cirrus,amp-gain-zc");
1311
1312 classh = of_get_child_by_name(np, "cirrus,classh-internal-algo");
1313 classh_config->classh_algo_enable = classh ? true : false;
1314
1315 if (classh_config->classh_algo_enable) {
1316 classh_config->classh_bst_override =
1317 of_property_read_bool(np, "cirrus,classh-bst-overide");
1318
1319 ret = of_property_read_u32(classh,
1320 "cirrus,classh-bst-max-limit",
1321 &val32);
1322 if (ret >= 0) {
1323 val32 |= CS35L35_VALID_PDATA;
1324 classh_config->classh_bst_max_limit = val32;
1325 }
1326
1327 ret = of_property_read_u32(classh,
1328 "cirrus,classh-bst-max-limit",
1329 &val32);
1330 if (ret >= 0) {
1331 val32 |= CS35L35_VALID_PDATA;
1332 classh_config->classh_bst_max_limit = val32;
1333 }
1334
1335 ret = of_property_read_u32(classh, "cirrus,classh-mem-depth",
1336 &val32);
1337 if (ret >= 0) {
1338 val32 |= CS35L35_VALID_PDATA;
1339 classh_config->classh_mem_depth = val32;
1340 }
1341
1342 ret = of_property_read_u32(classh, "cirrus,classh-release-rate",
1343 &val32);
1344 if (ret >= 0)
1345 classh_config->classh_release_rate = val32;
1346
1347 ret = of_property_read_u32(classh, "cirrus,classh-headroom",
1348 &val32);
1349 if (ret >= 0) {
1350 val32 |= CS35L35_VALID_PDATA;
1351 classh_config->classh_headroom = val32;
1352 }
1353
1354 ret = of_property_read_u32(classh,
1355 "cirrus,classh-wk-fet-disable",
1356 &val32);
1357 if (ret >= 0)
1358 classh_config->classh_wk_fet_disable = val32;
1359
1360 ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-delay",
1361 &val32);
1362 if (ret >= 0) {
1363 val32 |= CS35L35_VALID_PDATA;
1364 classh_config->classh_wk_fet_delay = val32;
1365 }
1366
1367 ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-thld",
1368 &val32);
1369 if (ret >= 0)
1370 classh_config->classh_wk_fet_thld = val32;
1371
1372 ret = of_property_read_u32(classh, "cirrus,classh-vpch-auto",
1373 &val32);
1374 if (ret >= 0) {
1375 val32 |= CS35L35_VALID_PDATA;
1376 classh_config->classh_vpch_auto = val32;
1377 }
1378
1379 ret = of_property_read_u32(classh, "cirrus,classh-vpch-rate",
1380 &val32);
1381 if (ret >= 0) {
1382 val32 |= CS35L35_VALID_PDATA;
1383 classh_config->classh_vpch_rate = val32;
1384 }
1385
1386 ret = of_property_read_u32(classh, "cirrus,classh-vpch-man",
1387 &val32);
1388 if (ret >= 0)
1389 classh_config->classh_vpch_man = val32;
1390 }
1391 of_node_put(classh);
1392
1393 /* frame depth location */
1394 signal_format = of_get_child_by_name(np, "cirrus,monitor-signal-format");
1395 monitor_config->is_present = signal_format ? true : false;
1396 if (monitor_config->is_present) {
1397 ret = of_property_read_u8_array(signal_format, "cirrus,imon",
1398 monitor_array, imon_array_size);
1399 if (!ret) {
1400 monitor_config->imon_specs = true;
1401 monitor_config->imon_dpth = monitor_array[0];
1402 monitor_config->imon_loc = monitor_array[1];
1403 monitor_config->imon_frm = monitor_array[2];
1404 monitor_config->imon_scale = monitor_array[3];
1405 }
1406 ret = of_property_read_u8_array(signal_format, "cirrus,vmon",
1407 monitor_array, mon_array_size);
1408 if (!ret) {
1409 monitor_config->vmon_specs = true;
1410 monitor_config->vmon_dpth = monitor_array[0];
1411 monitor_config->vmon_loc = monitor_array[1];
1412 monitor_config->vmon_frm = monitor_array[2];
1413 }
1414 ret = of_property_read_u8_array(signal_format, "cirrus,vpmon",
1415 monitor_array, mon_array_size);
1416 if (!ret) {
1417 monitor_config->vpmon_specs = true;
1418 monitor_config->vpmon_dpth = monitor_array[0];
1419 monitor_config->vpmon_loc = monitor_array[1];
1420 monitor_config->vpmon_frm = monitor_array[2];
1421 }
1422 ret = of_property_read_u8_array(signal_format, "cirrus,vbstmon",
1423 monitor_array, mon_array_size);
1424 if (!ret) {
1425 monitor_config->vbstmon_specs = true;
1426 monitor_config->vbstmon_dpth = monitor_array[0];
1427 monitor_config->vbstmon_loc = monitor_array[1];
1428 monitor_config->vbstmon_frm = monitor_array[2];
1429 }
1430 ret = of_property_read_u8_array(signal_format, "cirrus,vpbrstat",
1431 monitor_array, mon_array_size);
1432 if (!ret) {
1433 monitor_config->vpbrstat_specs = true;
1434 monitor_config->vpbrstat_dpth = monitor_array[0];
1435 monitor_config->vpbrstat_loc = monitor_array[1];
1436 monitor_config->vpbrstat_frm = monitor_array[2];
1437 }
1438 ret = of_property_read_u8_array(signal_format, "cirrus,zerofill",
1439 monitor_array, mon_array_size);
1440 if (!ret) {
1441 monitor_config->zerofill_specs = true;
1442 monitor_config->zerofill_dpth = monitor_array[0];
1443 monitor_config->zerofill_loc = monitor_array[1];
1444 monitor_config->zerofill_frm = monitor_array[2];
1445 }
1446 }
1447 of_node_put(signal_format);
1448
1449 return 0;
1450 }
1451
1452 /* Errata Rev A0 */
1453 static const struct reg_sequence cs35l35_errata_patch[] = {
1454
1455 { 0x7F, 0x99 },
1456 { 0x00, 0x99 },
1457 { 0x52, 0x22 },
1458 { 0x04, 0x14 },
1459 { 0x6D, 0x44 },
1460 { 0x24, 0x10 },
1461 { 0x58, 0xC4 },
1462 { 0x00, 0x98 },
1463 { 0x18, 0x08 },
1464 { 0x00, 0x00 },
1465 { 0x7F, 0x00 },
1466 };
1467
cs35l35_i2c_probe(struct i2c_client * i2c_client,const struct i2c_device_id * id)1468 static int cs35l35_i2c_probe(struct i2c_client *i2c_client,
1469 const struct i2c_device_id *id)
1470 {
1471 struct cs35l35_private *cs35l35;
1472 struct device *dev = &i2c_client->dev;
1473 struct cs35l35_platform_data *pdata = dev_get_platdata(dev);
1474 int i;
1475 int ret;
1476 unsigned int devid = 0;
1477 unsigned int reg;
1478
1479 cs35l35 = devm_kzalloc(dev, sizeof(struct cs35l35_private), GFP_KERNEL);
1480 if (!cs35l35)
1481 return -ENOMEM;
1482
1483 cs35l35->dev = dev;
1484
1485 i2c_set_clientdata(i2c_client, cs35l35);
1486 cs35l35->regmap = devm_regmap_init_i2c(i2c_client, &cs35l35_regmap);
1487 if (IS_ERR(cs35l35->regmap)) {
1488 ret = PTR_ERR(cs35l35->regmap);
1489 dev_err(dev, "regmap_init() failed: %d\n", ret);
1490 return ret;
1491 }
1492
1493 for (i = 0; i < ARRAY_SIZE(cs35l35_supplies); i++)
1494 cs35l35->supplies[i].supply = cs35l35_supplies[i];
1495
1496 cs35l35->num_supplies = ARRAY_SIZE(cs35l35_supplies);
1497
1498 ret = devm_regulator_bulk_get(dev, cs35l35->num_supplies,
1499 cs35l35->supplies);
1500 if (ret != 0) {
1501 dev_err(dev, "Failed to request core supplies: %d\n", ret);
1502 return ret;
1503 }
1504
1505 if (pdata) {
1506 cs35l35->pdata = *pdata;
1507 } else {
1508 pdata = devm_kzalloc(dev, sizeof(struct cs35l35_platform_data),
1509 GFP_KERNEL);
1510 if (!pdata)
1511 return -ENOMEM;
1512 if (i2c_client->dev.of_node) {
1513 ret = cs35l35_handle_of_data(i2c_client, pdata);
1514 if (ret != 0)
1515 return ret;
1516
1517 }
1518 cs35l35->pdata = *pdata;
1519 }
1520
1521 ret = regulator_bulk_enable(cs35l35->num_supplies,
1522 cs35l35->supplies);
1523 if (ret != 0) {
1524 dev_err(dev, "Failed to enable core supplies: %d\n", ret);
1525 return ret;
1526 }
1527
1528 /* returning NULL can be valid if in stereo mode */
1529 cs35l35->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1530 GPIOD_OUT_LOW);
1531 if (IS_ERR(cs35l35->reset_gpio)) {
1532 ret = PTR_ERR(cs35l35->reset_gpio);
1533 cs35l35->reset_gpio = NULL;
1534 if (ret == -EBUSY) {
1535 dev_info(dev,
1536 "Reset line busy, assuming shared reset\n");
1537 } else {
1538 dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
1539 goto err;
1540 }
1541 }
1542
1543 cs35l35_reset(cs35l35);
1544
1545 init_completion(&cs35l35->pdn_done);
1546
1547 ret = devm_request_threaded_irq(dev, i2c_client->irq, NULL, cs35l35_irq,
1548 IRQF_ONESHOT | IRQF_TRIGGER_LOW |
1549 IRQF_SHARED, "cs35l35", cs35l35);
1550 if (ret != 0) {
1551 dev_err(dev, "Failed to request IRQ: %d\n", ret);
1552 goto err;
1553 }
1554 /* initialize codec */
1555 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_AB, ®);
1556
1557 devid = (reg & 0xFF) << 12;
1558 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_CD, ®);
1559 devid |= (reg & 0xFF) << 4;
1560 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_E, ®);
1561 devid |= (reg & 0xF0) >> 4;
1562
1563 if (devid != CS35L35_CHIP_ID) {
1564 dev_err(dev, "CS35L35 Device ID (%X). Expected ID %X\n",
1565 devid, CS35L35_CHIP_ID);
1566 ret = -ENODEV;
1567 goto err;
1568 }
1569
1570 ret = regmap_read(cs35l35->regmap, CS35L35_REV_ID, ®);
1571 if (ret < 0) {
1572 dev_err(dev, "Get Revision ID failed: %d\n", ret);
1573 goto err;
1574 }
1575
1576 ret = regmap_register_patch(cs35l35->regmap, cs35l35_errata_patch,
1577 ARRAY_SIZE(cs35l35_errata_patch));
1578 if (ret < 0) {
1579 dev_err(dev, "Failed to apply errata patch: %d\n", ret);
1580 goto err;
1581 }
1582
1583 dev_info(dev, "Cirrus Logic CS35L35 (%x), Revision: %02X\n",
1584 devid, reg & 0xFF);
1585
1586 /* Set the INT Masks for critical errors */
1587 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_1,
1588 CS35L35_INT1_CRIT_MASK);
1589 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_2,
1590 CS35L35_INT2_CRIT_MASK);
1591 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_3,
1592 CS35L35_INT3_CRIT_MASK);
1593 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_4,
1594 CS35L35_INT4_CRIT_MASK);
1595
1596 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1597 CS35L35_PWR2_PDN_MASK,
1598 CS35L35_PWR2_PDN_MASK);
1599
1600 if (cs35l35->pdata.bst_pdn_fet_on)
1601 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1602 CS35L35_PDN_BST_MASK,
1603 1 << CS35L35_PDN_BST_FETON_SHIFT);
1604 else
1605 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1606 CS35L35_PDN_BST_MASK,
1607 1 << CS35L35_PDN_BST_FETOFF_SHIFT);
1608
1609 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL3,
1610 CS35L35_PWR3_PDN_MASK,
1611 CS35L35_PWR3_PDN_MASK);
1612
1613 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
1614 CS35L35_AMP_MUTE_MASK, 1 << CS35L35_AMP_MUTE_SHIFT);
1615
1616 ret = devm_snd_soc_register_component(dev, &soc_component_dev_cs35l35,
1617 cs35l35_dai, ARRAY_SIZE(cs35l35_dai));
1618 if (ret < 0) {
1619 dev_err(dev, "Failed to register component: %d\n", ret);
1620 goto err;
1621 }
1622
1623 return 0;
1624
1625 err:
1626 regulator_bulk_disable(cs35l35->num_supplies,
1627 cs35l35->supplies);
1628 gpiod_set_value_cansleep(cs35l35->reset_gpio, 0);
1629
1630 return ret;
1631 }
1632
cs35l35_i2c_remove(struct i2c_client * i2c_client)1633 static int cs35l35_i2c_remove(struct i2c_client *i2c_client)
1634 {
1635 struct cs35l35_private *cs35l35 = i2c_get_clientdata(i2c_client);
1636
1637 regulator_bulk_disable(cs35l35->num_supplies, cs35l35->supplies);
1638 gpiod_set_value_cansleep(cs35l35->reset_gpio, 0);
1639
1640 return 0;
1641 }
1642
1643 static const struct of_device_id cs35l35_of_match[] = {
1644 {.compatible = "cirrus,cs35l35"},
1645 {},
1646 };
1647 MODULE_DEVICE_TABLE(of, cs35l35_of_match);
1648
1649 static const struct i2c_device_id cs35l35_id[] = {
1650 {"cs35l35", 0},
1651 {}
1652 };
1653
1654 MODULE_DEVICE_TABLE(i2c, cs35l35_id);
1655
1656 static struct i2c_driver cs35l35_i2c_driver = {
1657 .driver = {
1658 .name = "cs35l35",
1659 .of_match_table = cs35l35_of_match,
1660 },
1661 .id_table = cs35l35_id,
1662 .probe = cs35l35_i2c_probe,
1663 .remove = cs35l35_i2c_remove,
1664 };
1665
1666 module_i2c_driver(cs35l35_i2c_driver);
1667
1668 MODULE_DESCRIPTION("ASoC CS35L35 driver");
1669 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1670 MODULE_LICENSE("GPL");
1671