1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // mt8192-afe-clk.c  --  Mediatek 8192 afe clock ctrl
4 //
5 // Copyright (c) 2020 MediaTek Inc.
6 // Author: Shane Chien <shane.chien@mediatek.com>
7 //
8 
9 #include <linux/arm-smccc.h>
10 #include <linux/clk.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/regmap.h>
13 
14 #include "mt8192-afe-clk.h"
15 #include "mt8192-afe-common.h"
16 
17 static const char *aud_clks[CLK_NUM] = {
18 	[CLK_AFE] = "aud_afe_clk",
19 	[CLK_TML] = "aud_tml_clk",
20 	[CLK_APLL22M] = "aud_apll22m_clk",
21 	[CLK_APLL24M] = "aud_apll24m_clk",
22 	[CLK_APLL1_TUNER] = "aud_apll1_tuner_clk",
23 	[CLK_APLL2_TUNER] = "aud_apll2_tuner_clk",
24 	[CLK_NLE] = "aud_nle",
25 	[CLK_INFRA_SYS_AUDIO] = "aud_infra_clk",
26 	[CLK_INFRA_AUDIO_26M] = "aud_infra_26m_clk",
27 	[CLK_MUX_AUDIO] = "top_mux_audio",
28 	[CLK_MUX_AUDIOINTBUS] = "top_mux_audio_int",
29 	[CLK_TOP_MAINPLL_D4_D4] = "top_mainpll_d4_d4",
30 	[CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
31 	[CLK_TOP_APLL1_CK] = "top_apll1_ck",
32 	[CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
33 	[CLK_TOP_APLL2_CK] = "top_apll2_ck",
34 	[CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1",
35 	[CLK_TOP_APLL1_D4] = "top_apll1_d4",
36 	[CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2",
37 	[CLK_TOP_APLL2_D4] = "top_apll2_d4",
38 	[CLK_TOP_MUX_AUDIO_H] = "top_mux_audio_h",
39 	[CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel",
40 	[CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel",
41 	[CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel",
42 	[CLK_TOP_I2S3_M_SEL] = "top_i2s3_m_sel",
43 	[CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel",
44 	[CLK_TOP_I2S5_M_SEL] = "top_i2s5_m_sel",
45 	[CLK_TOP_I2S6_M_SEL] = "top_i2s6_m_sel",
46 	[CLK_TOP_I2S7_M_SEL] = "top_i2s7_m_sel",
47 	[CLK_TOP_I2S8_M_SEL] = "top_i2s8_m_sel",
48 	[CLK_TOP_I2S9_M_SEL] = "top_i2s9_m_sel",
49 	[CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
50 	[CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
51 	[CLK_TOP_APLL12_DIV2] = "top_apll12_div2",
52 	[CLK_TOP_APLL12_DIV3] = "top_apll12_div3",
53 	[CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
54 	[CLK_TOP_APLL12_DIVB] = "top_apll12_divb",
55 	[CLK_TOP_APLL12_DIV5] = "top_apll12_div5",
56 	[CLK_TOP_APLL12_DIV6] = "top_apll12_div6",
57 	[CLK_TOP_APLL12_DIV7] = "top_apll12_div7",
58 	[CLK_TOP_APLL12_DIV8] = "top_apll12_div8",
59 	[CLK_TOP_APLL12_DIV9] = "top_apll12_div9",
60 	[CLK_CLK26M] = "top_clk26m_clk",
61 };
62 
mt8192_set_audio_int_bus_parent(struct mtk_base_afe * afe,int clk_id)63 int mt8192_set_audio_int_bus_parent(struct mtk_base_afe *afe,
64 				    int clk_id)
65 {
66 	struct mt8192_afe_private *afe_priv = afe->platform_priv;
67 	int ret;
68 
69 	ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
70 			     afe_priv->clk[clk_id]);
71 	if (ret) {
72 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
73 			__func__, aud_clks[CLK_MUX_AUDIOINTBUS],
74 			aud_clks[clk_id], ret);
75 	}
76 
77 	return ret;
78 }
79 
apll1_mux_setting(struct mtk_base_afe * afe,bool enable)80 static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
81 {
82 	struct mt8192_afe_private *afe_priv = afe->platform_priv;
83 	int ret;
84 
85 	if (enable) {
86 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
87 		if (ret) {
88 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
89 				__func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
90 			goto EXIT;
91 		}
92 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
93 				     afe_priv->clk[CLK_TOP_APLL1_CK]);
94 		if (ret) {
95 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
96 				__func__, aud_clks[CLK_TOP_MUX_AUD_1],
97 				aud_clks[CLK_TOP_APLL1_CK], ret);
98 			goto EXIT;
99 		}
100 
101 		/* 180.6336 / 4 = 45.1584MHz */
102 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
103 		if (ret) {
104 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
105 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
106 			goto EXIT;
107 		}
108 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
109 				     afe_priv->clk[CLK_TOP_APLL1_D4]);
110 		if (ret) {
111 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
112 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
113 				aud_clks[CLK_TOP_APLL1_D4], ret);
114 			goto EXIT;
115 		}
116 	} else {
117 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
118 				     afe_priv->clk[CLK_CLK26M]);
119 		if (ret) {
120 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
121 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
122 				aud_clks[CLK_CLK26M], ret);
123 			goto EXIT;
124 		}
125 		clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
126 
127 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
128 				     afe_priv->clk[CLK_CLK26M]);
129 		if (ret) {
130 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
131 				__func__, aud_clks[CLK_TOP_MUX_AUD_1],
132 				aud_clks[CLK_CLK26M], ret);
133 			goto EXIT;
134 		}
135 		clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
136 	}
137 
138 EXIT:
139 	return ret;
140 }
141 
apll2_mux_setting(struct mtk_base_afe * afe,bool enable)142 static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
143 {
144 	struct mt8192_afe_private *afe_priv = afe->platform_priv;
145 	int ret;
146 
147 	if (enable) {
148 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
149 		if (ret) {
150 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
151 				__func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
152 			goto EXIT;
153 		}
154 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
155 				     afe_priv->clk[CLK_TOP_APLL2_CK]);
156 		if (ret) {
157 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
158 				__func__, aud_clks[CLK_TOP_MUX_AUD_2],
159 				aud_clks[CLK_TOP_APLL2_CK], ret);
160 			goto EXIT;
161 		}
162 
163 		/* 196.608 / 4 = 49.152MHz */
164 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
165 		if (ret) {
166 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
167 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
168 			goto EXIT;
169 		}
170 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
171 				     afe_priv->clk[CLK_TOP_APLL2_D4]);
172 		if (ret) {
173 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
174 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
175 				aud_clks[CLK_TOP_APLL2_D4], ret);
176 			goto EXIT;
177 		}
178 	} else {
179 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
180 				     afe_priv->clk[CLK_CLK26M]);
181 		if (ret) {
182 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
183 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
184 				aud_clks[CLK_CLK26M], ret);
185 			goto EXIT;
186 		}
187 		clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
188 
189 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
190 				     afe_priv->clk[CLK_CLK26M]);
191 		if (ret) {
192 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
193 				__func__, aud_clks[CLK_TOP_MUX_AUD_2],
194 				aud_clks[CLK_CLK26M], ret);
195 			goto EXIT;
196 		}
197 		clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
198 	}
199 
200 EXIT:
201 	return ret;
202 }
203 
mt8192_afe_enable_clock(struct mtk_base_afe * afe)204 int mt8192_afe_enable_clock(struct mtk_base_afe *afe)
205 {
206 	struct mt8192_afe_private *afe_priv = afe->platform_priv;
207 	int ret;
208 
209 	dev_info(afe->dev, "%s()\n", __func__);
210 
211 	ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
212 	if (ret) {
213 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
214 			__func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
215 		goto EXIT;
216 	}
217 
218 	ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
219 	if (ret) {
220 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
221 			__func__, aud_clks[CLK_INFRA_AUDIO_26M], ret);
222 		goto EXIT;
223 	}
224 
225 	ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
226 	if (ret) {
227 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
228 			__func__, aud_clks[CLK_MUX_AUDIO], ret);
229 		goto EXIT;
230 	}
231 	ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
232 			     afe_priv->clk[CLK_CLK26M]);
233 	if (ret) {
234 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
235 			__func__, aud_clks[CLK_MUX_AUDIO],
236 			aud_clks[CLK_CLK26M], ret);
237 		goto EXIT;
238 	}
239 
240 	ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
241 	if (ret) {
242 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
243 			__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
244 		goto EXIT;
245 	}
246 
247 	ret = mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M);
248 	if (ret) {
249 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
250 			__func__, aud_clks[CLK_MUX_AUDIOINTBUS],
251 			aud_clks[CLK_CLK26M], ret);
252 		goto EXIT;
253 	}
254 
255 	ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H],
256 			     afe_priv->clk[CLK_TOP_APLL2_CK]);
257 	if (ret) {
258 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
259 			__func__, aud_clks[CLK_TOP_MUX_AUDIO_H],
260 			aud_clks[CLK_TOP_APLL2_CK], ret);
261 		goto EXIT;
262 	}
263 
264 	ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
265 	if (ret) {
266 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
267 			__func__, aud_clks[CLK_AFE], ret);
268 		goto EXIT;
269 	}
270 
271 EXIT:
272 	return ret;
273 }
274 
mt8192_afe_disable_clock(struct mtk_base_afe * afe)275 void mt8192_afe_disable_clock(struct mtk_base_afe *afe)
276 {
277 	struct mt8192_afe_private *afe_priv = afe->platform_priv;
278 
279 	dev_info(afe->dev, "%s()\n", __func__);
280 
281 	clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
282 	mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M);
283 	clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
284 	clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
285 	clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
286 	clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
287 }
288 
mt8192_apll1_enable(struct mtk_base_afe * afe)289 int mt8192_apll1_enable(struct mtk_base_afe *afe)
290 {
291 	struct mt8192_afe_private *afe_priv = afe->platform_priv;
292 	int ret;
293 
294 	/* setting for APLL */
295 	apll1_mux_setting(afe, true);
296 
297 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
298 	if (ret) {
299 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
300 			__func__, aud_clks[CLK_APLL22M], ret);
301 		goto EXIT;
302 	}
303 
304 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
305 	if (ret) {
306 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
307 			__func__, aud_clks[CLK_APLL1_TUNER], ret);
308 		goto EXIT;
309 	}
310 
311 	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
312 			   0x0000FFF7, 0x00000832);
313 	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);
314 
315 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
316 			   AFE_22M_ON_MASK_SFT,
317 			   0x1 << AFE_22M_ON_SFT);
318 
319 EXIT:
320 	return ret;
321 }
322 
mt8192_apll1_disable(struct mtk_base_afe * afe)323 void mt8192_apll1_disable(struct mtk_base_afe *afe)
324 {
325 	struct mt8192_afe_private *afe_priv = afe->platform_priv;
326 
327 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
328 			   AFE_22M_ON_MASK_SFT,
329 			   0x0 << AFE_22M_ON_SFT);
330 
331 	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0);
332 
333 	clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
334 	clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
335 
336 	apll1_mux_setting(afe, false);
337 }
338 
mt8192_apll2_enable(struct mtk_base_afe * afe)339 int mt8192_apll2_enable(struct mtk_base_afe *afe)
340 {
341 	struct mt8192_afe_private *afe_priv = afe->platform_priv;
342 	int ret;
343 
344 	/* setting for APLL */
345 	apll2_mux_setting(afe, true);
346 
347 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
348 	if (ret) {
349 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
350 			__func__, aud_clks[CLK_APLL24M], ret);
351 		goto EXIT;
352 	}
353 
354 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
355 	if (ret) {
356 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
357 			__func__, aud_clks[CLK_APLL2_TUNER], ret);
358 		goto EXIT;
359 	}
360 
361 	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
362 			   0x0000FFF7, 0x00000634);
363 	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);
364 
365 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
366 			   AFE_24M_ON_MASK_SFT,
367 			   0x1 << AFE_24M_ON_SFT);
368 
369 EXIT:
370 	return ret;
371 }
372 
mt8192_apll2_disable(struct mtk_base_afe * afe)373 void mt8192_apll2_disable(struct mtk_base_afe *afe)
374 {
375 	struct mt8192_afe_private *afe_priv = afe->platform_priv;
376 
377 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
378 			   AFE_24M_ON_MASK_SFT,
379 			   0x0 << AFE_24M_ON_SFT);
380 
381 	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0);
382 
383 	clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
384 	clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
385 
386 	apll2_mux_setting(afe, false);
387 }
388 
mt8192_get_apll_rate(struct mtk_base_afe * afe,int apll)389 int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll)
390 {
391 	return (apll == MT8192_APLL1) ? 180633600 : 196608000;
392 }
393 
mt8192_get_apll_by_rate(struct mtk_base_afe * afe,int rate)394 int mt8192_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
395 {
396 	return ((rate % 8000) == 0) ? MT8192_APLL2 : MT8192_APLL1;
397 }
398 
mt8192_get_apll_by_name(struct mtk_base_afe * afe,const char * name)399 int mt8192_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
400 {
401 	if (strcmp(name, APLL1_W_NAME) == 0)
402 		return MT8192_APLL1;
403 	else
404 		return MT8192_APLL2;
405 }
406 
407 /* mck */
408 struct mt8192_mck_div {
409 	int m_sel_id;
410 	int div_clk_id;
411 	/* below will be deprecated */
412 	int div_pdn_reg;
413 	int div_pdn_mask_sft;
414 	int div_reg;
415 	int div_mask_sft;
416 	int div_mask;
417 	int div_sft;
418 	int div_apll_sel_reg;
419 	int div_apll_sel_mask_sft;
420 	int div_apll_sel_sft;
421 };
422 
423 static const struct mt8192_mck_div mck_div[MT8192_MCK_NUM] = {
424 	[MT8192_I2S0_MCK] = {
425 		.m_sel_id = CLK_TOP_I2S0_M_SEL,
426 		.div_clk_id = CLK_TOP_APLL12_DIV0,
427 		.div_pdn_reg = CLK_AUDDIV_0,
428 		.div_pdn_mask_sft = APLL12_DIV0_PDN_MASK_SFT,
429 		.div_reg = CLK_AUDDIV_2,
430 		.div_mask_sft = APLL12_CK_DIV0_MASK_SFT,
431 		.div_mask = APLL12_CK_DIV0_MASK,
432 		.div_sft = APLL12_CK_DIV0_SFT,
433 		.div_apll_sel_reg = CLK_AUDDIV_0,
434 		.div_apll_sel_mask_sft = APLL_I2S0_MCK_SEL_MASK_SFT,
435 		.div_apll_sel_sft = APLL_I2S0_MCK_SEL_SFT,
436 	},
437 	[MT8192_I2S1_MCK] = {
438 		.m_sel_id = CLK_TOP_I2S1_M_SEL,
439 		.div_clk_id = CLK_TOP_APLL12_DIV1,
440 		.div_pdn_reg = CLK_AUDDIV_0,
441 		.div_pdn_mask_sft = APLL12_DIV1_PDN_MASK_SFT,
442 		.div_reg = CLK_AUDDIV_2,
443 		.div_mask_sft = APLL12_CK_DIV1_MASK_SFT,
444 		.div_mask = APLL12_CK_DIV1_MASK,
445 		.div_sft = APLL12_CK_DIV1_SFT,
446 		.div_apll_sel_reg = CLK_AUDDIV_0,
447 		.div_apll_sel_mask_sft = APLL_I2S1_MCK_SEL_MASK_SFT,
448 		.div_apll_sel_sft = APLL_I2S1_MCK_SEL_SFT,
449 	},
450 	[MT8192_I2S2_MCK] = {
451 		.m_sel_id = CLK_TOP_I2S2_M_SEL,
452 		.div_clk_id = CLK_TOP_APLL12_DIV2,
453 		.div_pdn_reg = CLK_AUDDIV_0,
454 		.div_pdn_mask_sft = APLL12_DIV2_PDN_MASK_SFT,
455 		.div_reg = CLK_AUDDIV_2,
456 		.div_mask_sft = APLL12_CK_DIV2_MASK_SFT,
457 		.div_mask = APLL12_CK_DIV2_MASK,
458 		.div_sft = APLL12_CK_DIV2_SFT,
459 		.div_apll_sel_reg = CLK_AUDDIV_0,
460 		.div_apll_sel_mask_sft = APLL_I2S2_MCK_SEL_MASK_SFT,
461 		.div_apll_sel_sft = APLL_I2S2_MCK_SEL_SFT,
462 	},
463 	[MT8192_I2S3_MCK] = {
464 		.m_sel_id = CLK_TOP_I2S3_M_SEL,
465 		.div_clk_id = CLK_TOP_APLL12_DIV3,
466 		.div_pdn_reg = CLK_AUDDIV_0,
467 		.div_pdn_mask_sft = APLL12_DIV3_PDN_MASK_SFT,
468 		.div_reg = CLK_AUDDIV_2,
469 		.div_mask_sft = APLL12_CK_DIV3_MASK_SFT,
470 		.div_mask = APLL12_CK_DIV3_MASK,
471 		.div_sft = APLL12_CK_DIV3_SFT,
472 		.div_apll_sel_reg = CLK_AUDDIV_0,
473 		.div_apll_sel_mask_sft = APLL_I2S3_MCK_SEL_MASK_SFT,
474 		.div_apll_sel_sft = APLL_I2S3_MCK_SEL_SFT,
475 	},
476 	[MT8192_I2S4_MCK] = {
477 		.m_sel_id = CLK_TOP_I2S4_M_SEL,
478 		.div_clk_id = CLK_TOP_APLL12_DIV4,
479 		.div_pdn_reg = CLK_AUDDIV_0,
480 		.div_pdn_mask_sft = APLL12_DIV4_PDN_MASK_SFT,
481 		.div_reg = CLK_AUDDIV_3,
482 		.div_mask_sft = APLL12_CK_DIV4_MASK_SFT,
483 		.div_mask = APLL12_CK_DIV4_MASK,
484 		.div_sft = APLL12_CK_DIV4_SFT,
485 		.div_apll_sel_reg = CLK_AUDDIV_0,
486 		.div_apll_sel_mask_sft = APLL_I2S4_MCK_SEL_MASK_SFT,
487 		.div_apll_sel_sft = APLL_I2S4_MCK_SEL_SFT,
488 	},
489 	[MT8192_I2S4_BCK] = {
490 		.m_sel_id = -1,
491 		.div_clk_id = CLK_TOP_APLL12_DIVB,
492 		.div_pdn_reg = CLK_AUDDIV_0,
493 		.div_pdn_mask_sft = APLL12_DIVB_PDN_MASK_SFT,
494 		.div_reg = CLK_AUDDIV_2,
495 		.div_mask_sft = APLL12_CK_DIVB_MASK_SFT,
496 		.div_mask = APLL12_CK_DIVB_MASK,
497 		.div_sft = APLL12_CK_DIVB_SFT,
498 	},
499 	[MT8192_I2S5_MCK] = {
500 		.m_sel_id = CLK_TOP_I2S5_M_SEL,
501 		.div_clk_id = CLK_TOP_APLL12_DIV5,
502 		.div_pdn_reg = CLK_AUDDIV_0,
503 		.div_pdn_mask_sft = APLL12_DIV5_PDN_MASK_SFT,
504 		.div_reg = CLK_AUDDIV_3,
505 		.div_mask_sft = APLL12_CK_DIV5_MASK_SFT,
506 		.div_mask = APLL12_CK_DIV5_MASK,
507 		.div_sft = APLL12_CK_DIV5_SFT,
508 		.div_apll_sel_reg = CLK_AUDDIV_0,
509 		.div_apll_sel_mask_sft = APLL_I2S5_MCK_SEL_MASK_SFT,
510 		.div_apll_sel_sft = APLL_I2S5_MCK_SEL_SFT,
511 	},
512 	[MT8192_I2S6_MCK] = {
513 		.m_sel_id = CLK_TOP_I2S6_M_SEL,
514 		.div_clk_id = CLK_TOP_APLL12_DIV6,
515 		.div_pdn_reg = CLK_AUDDIV_0,
516 		.div_pdn_mask_sft = APLL12_DIV6_PDN_MASK_SFT,
517 		.div_reg = CLK_AUDDIV_3,
518 		.div_mask_sft = APLL12_CK_DIV6_MASK_SFT,
519 		.div_mask = APLL12_CK_DIV6_MASK,
520 		.div_sft = APLL12_CK_DIV6_SFT,
521 		.div_apll_sel_reg = CLK_AUDDIV_0,
522 		.div_apll_sel_mask_sft = APLL_I2S6_MCK_SEL_MASK_SFT,
523 		.div_apll_sel_sft = APLL_I2S6_MCK_SEL_SFT,
524 	},
525 	[MT8192_I2S7_MCK] = {
526 		.m_sel_id = CLK_TOP_I2S7_M_SEL,
527 		.div_clk_id = CLK_TOP_APLL12_DIV7,
528 		.div_pdn_reg = CLK_AUDDIV_0,
529 		.div_pdn_mask_sft = APLL12_DIV7_PDN_MASK_SFT,
530 		.div_reg = CLK_AUDDIV_4,
531 		.div_mask_sft = APLL12_CK_DIV7_MASK_SFT,
532 		.div_mask = APLL12_CK_DIV7_MASK,
533 		.div_sft = APLL12_CK_DIV7_SFT,
534 		.div_apll_sel_reg = CLK_AUDDIV_0,
535 		.div_apll_sel_mask_sft = APLL_I2S7_MCK_SEL_MASK_SFT,
536 		.div_apll_sel_sft = APLL_I2S7_MCK_SEL_SFT,
537 	},
538 	[MT8192_I2S8_MCK] = {
539 		.m_sel_id = CLK_TOP_I2S8_M_SEL,
540 		.div_clk_id = CLK_TOP_APLL12_DIV8,
541 		.div_pdn_reg = CLK_AUDDIV_0,
542 		.div_pdn_mask_sft = APLL12_DIV8_PDN_MASK_SFT,
543 		.div_reg = CLK_AUDDIV_4,
544 		.div_mask_sft = APLL12_CK_DIV8_MASK_SFT,
545 		.div_mask = APLL12_CK_DIV8_MASK,
546 		.div_sft = APLL12_CK_DIV8_SFT,
547 		.div_apll_sel_reg = CLK_AUDDIV_0,
548 		.div_apll_sel_mask_sft = APLL_I2S8_MCK_SEL_MASK_SFT,
549 		.div_apll_sel_sft = APLL_I2S8_MCK_SEL_SFT,
550 	},
551 	[MT8192_I2S9_MCK] = {
552 		.m_sel_id = CLK_TOP_I2S9_M_SEL,
553 		.div_clk_id = CLK_TOP_APLL12_DIV9,
554 		.div_pdn_reg = CLK_AUDDIV_0,
555 		.div_pdn_mask_sft = APLL12_DIV9_PDN_MASK_SFT,
556 		.div_reg = CLK_AUDDIV_4,
557 		.div_mask_sft = APLL12_CK_DIV9_MASK_SFT,
558 		.div_mask = APLL12_CK_DIV9_MASK,
559 		.div_sft = APLL12_CK_DIV9_SFT,
560 		.div_apll_sel_reg = CLK_AUDDIV_0,
561 		.div_apll_sel_mask_sft = APLL_I2S9_MCK_SEL_MASK_SFT,
562 		.div_apll_sel_sft = APLL_I2S9_MCK_SEL_SFT,
563 	},
564 };
565 
mt8192_mck_enable(struct mtk_base_afe * afe,int mck_id,int rate)566 int mt8192_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
567 {
568 	struct mt8192_afe_private *afe_priv = afe->platform_priv;
569 	int apll = mt8192_get_apll_by_rate(afe, rate);
570 	int apll_clk_id = apll == MT8192_APLL1 ?
571 			  CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
572 	int m_sel_id = mck_div[mck_id].m_sel_id;
573 	int div_clk_id = mck_div[mck_id].div_clk_id;
574 	int ret;
575 
576 	/* select apll */
577 	if (m_sel_id >= 0) {
578 		ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
579 		if (ret) {
580 			dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
581 				__func__, aud_clks[m_sel_id], ret);
582 			return ret;
583 		}
584 		ret = clk_set_parent(afe_priv->clk[m_sel_id],
585 				     afe_priv->clk[apll_clk_id]);
586 		if (ret) {
587 			dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
588 				__func__, aud_clks[m_sel_id],
589 				aud_clks[apll_clk_id], ret);
590 			return ret;
591 		}
592 	}
593 
594 	/* enable div, set rate */
595 	ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
596 	if (ret) {
597 		dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
598 			__func__, aud_clks[div_clk_id], ret);
599 		return ret;
600 	}
601 	ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
602 	if (ret) {
603 		dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
604 			__func__, aud_clks[div_clk_id],
605 			rate, ret);
606 		return ret;
607 	}
608 
609 	return 0;
610 }
611 
mt8192_mck_disable(struct mtk_base_afe * afe,int mck_id)612 void mt8192_mck_disable(struct mtk_base_afe *afe, int mck_id)
613 {
614 	struct mt8192_afe_private *afe_priv = afe->platform_priv;
615 	int m_sel_id = mck_div[mck_id].m_sel_id;
616 	int div_clk_id = mck_div[mck_id].div_clk_id;
617 
618 	clk_disable_unprepare(afe_priv->clk[div_clk_id]);
619 	if (m_sel_id >= 0)
620 		clk_disable_unprepare(afe_priv->clk[m_sel_id]);
621 }
622 
mt8192_init_clock(struct mtk_base_afe * afe)623 int mt8192_init_clock(struct mtk_base_afe *afe)
624 {
625 	struct mt8192_afe_private *afe_priv = afe->platform_priv;
626 	struct device_node *of_node = afe->dev->of_node;
627 	int i = 0;
628 
629 	afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
630 				     GFP_KERNEL);
631 	if (!afe_priv->clk)
632 		return -ENOMEM;
633 
634 	for (i = 0; i < CLK_NUM; i++) {
635 		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
636 		if (IS_ERR(afe_priv->clk[i])) {
637 			dev_warn(afe->dev, "%s devm_clk_get %s fail, ret %ld\n",
638 				 __func__,
639 				 aud_clks[i], PTR_ERR(afe_priv->clk[i]));
640 			afe_priv->clk[i] = NULL;
641 		}
642 	}
643 
644 	afe_priv->apmixedsys = syscon_regmap_lookup_by_phandle(of_node,
645 							       "mediatek,apmixedsys");
646 	if (IS_ERR(afe_priv->apmixedsys)) {
647 		dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n",
648 			__func__, PTR_ERR(afe_priv->apmixedsys));
649 		return PTR_ERR(afe_priv->apmixedsys);
650 	}
651 
652 	afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node,
653 							     "mediatek,topckgen");
654 	if (IS_ERR(afe_priv->topckgen)) {
655 		dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n",
656 			__func__, PTR_ERR(afe_priv->topckgen));
657 		return PTR_ERR(afe_priv->topckgen);
658 	}
659 
660 	afe_priv->infracfg = syscon_regmap_lookup_by_phandle(of_node,
661 							     "mediatek,infracfg");
662 	if (IS_ERR(afe_priv->infracfg)) {
663 		dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n",
664 			__func__, PTR_ERR(afe_priv->infracfg));
665 		return PTR_ERR(afe_priv->infracfg);
666 	}
667 
668 	return 0;
669 }
670