1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Xiang, Haihao <haihao.xiang@intel.com>
26 *
27 */
28
29 #include <stdio.h>
30 #include <stdlib.h>
31 #include <stdbool.h>
32 #include <string.h>
33 #include <math.h>
34 #include <time.h>
35 #include <assert.h>
36
37 #include "intel_batchbuffer.h"
38 #include "intel_driver.h"
39
40 #include "i965_defines.h"
41 #include "i965_drv_video.h"
42 #include "i965_encoder.h"
43 #include "i965_gpe_utils.h"
44 #include "i965_encoder_vp8.h"
45 #include "vp8_probs.h"
46 #include "vpx_quant.h"
47
48 #define SCALE_FACTOR_4X 4
49 #define SCALE_FACTOR_16X 16
50
51 #define MAX_VP8_ENCODER_SURFACES 128
52
53 #define MAX_URB_SIZE 2048 /* In register */
54 #define NUM_KERNELS_PER_GPE_CONTEXT 1
55
56 #define VP8_BRC_KBPS 1000
57
58 #define BRC_KERNEL_CBR 0x0010
59 #define BRC_KERNEL_VBR 0x0020
60
61 struct i965_kernel vp8_kernels_brc_init_reset[NUM_VP8_BRC_RESET] = {
62 {
63 "VP8 BRC Init",
64 VP8_BRC_INIT,
65 NULL,
66 0,
67 NULL
68 },
69
70 {
71 "VP8 BRC Reset",
72 VP8_BRC_RESET,
73 NULL,
74 0,
75 NULL
76 },
77 };
78
79 struct i965_kernel vp8_kernels_scaling[NUM_VP8_SCALING] = {
80 {
81 "VP8 SCALE 4X",
82 VP8_SCALING_4X,
83 NULL,
84 0,
85 NULL
86 },
87
88 {
89 "VP8 SCALE 16",
90 VP8_SCALING_16X,
91 NULL,
92 0,
93 NULL
94 },
95 };
96
97 struct i965_kernel vp8_kernels_me[NUM_VP8_ME] = {
98 {
99 "VP8 ME 4X",
100 VP8_ME_4X,
101 NULL,
102 0,
103 NULL
104 },
105
106 {
107 "VP8 ME 16",
108 VP8_ME_16X,
109 NULL,
110 0,
111 NULL
112 },
113 };
114
115 struct i965_kernel vp8_kernels_mbenc[NUM_VP8_MBENC] = {
116 {
117 "VP8 MBEnc I Frame Dist",
118 VP8_MBENC_I_FRAME_DIST,
119 NULL,
120 0,
121 NULL
122 },
123
124 {
125 "VP8 MBEnc I Frame Luma",
126 VP8_MBENC_I_FRAME_LUMA,
127 NULL,
128 0,
129 NULL
130 },
131
132 {
133 "VP8 MBEnc I Frame Chroma",
134 VP8_MBENC_I_FRAME_CHROMA,
135 NULL,
136 0,
137 NULL
138 },
139
140 {
141 "VP8 MBEnc P Frame",
142 VP8_MBENC_P_FRAME,
143 NULL,
144 0,
145 NULL
146 },
147 };
148
149 struct i965_kernel vp8_kernels_mpu[NUM_VP8_MPU] = {
150 {
151 "VP8 MPU",
152 VP8_MPU,
153 NULL,
154 0,
155 NULL
156 },
157 };
158
159 struct i965_kernel vp8_kernels_tpu[NUM_VP8_TPU] = {
160 {
161 "VP8 TPU",
162 VP8_TPU,
163 NULL,
164 0,
165 NULL
166 },
167 };
168
169 struct i965_kernel vp8_kernels_brc_update[NUM_VP8_BRC_UPDATE] = {
170 {
171 "VP8 BRC Update",
172 VP8_BRC_UPDATE,
173 NULL,
174 0,
175 NULL
176 },
177 };
178
179 static const unsigned char
180 vp8_num_refs[8] = {
181 0, 1, 1, 2, 1, 2, 2, 3
182 };
183
184 static const unsigned int
185 vp8_search_path[8][16] = {
186 // MEMethod: 0
187 {
188 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
189 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
190 },
191 // MEMethod: 1
192 {
193 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
194 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
195 },
196 // MEMethod: 2
197 {
198 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
199 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
200 },
201 // MEMethod: 3
202 {
203 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101,
204 0x01010101, 0x11010101, 0x01010101, 0x00010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000
205 },
206 // MEMethod: 4
207 {
208 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
209 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
210 },
211 // MEMethod: 5
212 {
213 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
214 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
215 },
216 // MEMethod: 6
217 {
218 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
219 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
220 },
221 // MEMethod: 7
222 {
223 0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
224 0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
225 }
226 };
227
228 static const unsigned char
229 i_frame_vme_costs_vp8[NUM_QP_VP8][4] = {
230 {0x05, 0x1f, 0x02, 0x09},
231 {0x05, 0x1f, 0x02, 0x09},
232 {0x08, 0x2b, 0x03, 0x0e},
233 {0x08, 0x2b, 0x03, 0x0e},
234 {0x0a, 0x2f, 0x04, 0x12},
235 {0x0a, 0x2f, 0x04, 0x12},
236 {0x0d, 0x39, 0x05, 0x17},
237 {0x0d, 0x39, 0x05, 0x17},
238 {0x0d, 0x39, 0x05, 0x17},
239 {0x0f, 0x3b, 0x06, 0x1b},
240 {0x0f, 0x3b, 0x06, 0x1b},
241 {0x19, 0x3d, 0x07, 0x20},
242 {0x19, 0x3d, 0x07, 0x20},
243 {0x1a, 0x3f, 0x08, 0x24},
244 {0x1a, 0x3f, 0x08, 0x24},
245 {0x1a, 0x3f, 0x08, 0x24},
246 {0x1b, 0x48, 0x09, 0x29},
247 {0x1b, 0x48, 0x09, 0x29},
248 {0x1d, 0x49, 0x09, 0x2d},
249 {0x1d, 0x49, 0x09, 0x2d},
250 {0x1d, 0x49, 0x09, 0x2d},
251 {0x1d, 0x49, 0x09, 0x2d},
252 {0x1e, 0x4a, 0x0a, 0x32},
253 {0x1e, 0x4a, 0x0a, 0x32},
254 {0x1e, 0x4a, 0x0a, 0x32},
255 {0x1e, 0x4a, 0x0a, 0x32},
256 {0x1f, 0x4b, 0x0b, 0x36},
257 {0x1f, 0x4b, 0x0b, 0x36},
258 {0x1f, 0x4b, 0x0b, 0x36},
259 {0x28, 0x4c, 0x0c, 0x3b},
260 {0x28, 0x4c, 0x0c, 0x3b},
261 {0x29, 0x4d, 0x0d, 0x3f},
262 {0x29, 0x4d, 0x0d, 0x3f},
263 {0x29, 0x4e, 0x0e, 0x44},
264 {0x29, 0x4e, 0x0e, 0x44},
265 {0x2a, 0x4f, 0x0f, 0x48},
266 {0x2a, 0x4f, 0x0f, 0x48},
267 {0x2b, 0x58, 0x10, 0x4d},
268 {0x2b, 0x58, 0x10, 0x4d},
269 {0x2b, 0x58, 0x11, 0x51},
270 {0x2b, 0x58, 0x11, 0x51},
271 {0x2b, 0x58, 0x11, 0x51},
272 {0x2c, 0x58, 0x12, 0x56},
273 {0x2c, 0x58, 0x12, 0x56},
274 {0x2c, 0x59, 0x13, 0x5a},
275 {0x2c, 0x59, 0x13, 0x5a},
276 {0x2d, 0x59, 0x14, 0x5f},
277 {0x2d, 0x59, 0x14, 0x5f},
278 {0x2e, 0x5a, 0x15, 0x63},
279 {0x2e, 0x5a, 0x15, 0x63},
280 {0x2e, 0x5a, 0x16, 0x68},
281 {0x2e, 0x5a, 0x16, 0x68},
282 {0x2e, 0x5a, 0x16, 0x68},
283 {0x2f, 0x5b, 0x17, 0x6c},
284 {0x2f, 0x5b, 0x17, 0x6c},
285 {0x38, 0x5b, 0x18, 0x71},
286 {0x38, 0x5b, 0x18, 0x71},
287 {0x38, 0x5c, 0x19, 0x76},
288 {0x38, 0x5c, 0x19, 0x76},
289 {0x38, 0x5c, 0x1a, 0x7a},
290 {0x38, 0x5c, 0x1a, 0x7a},
291 {0x39, 0x5d, 0x1a, 0x7f},
292 {0x39, 0x5d, 0x1a, 0x7f},
293 {0x39, 0x5d, 0x1b, 0x83},
294 {0x39, 0x5d, 0x1b, 0x83},
295 {0x39, 0x5e, 0x1c, 0x88},
296 {0x39, 0x5e, 0x1c, 0x88},
297 {0x3a, 0x5e, 0x1d, 0x8c},
298 {0x3a, 0x5e, 0x1d, 0x8c},
299 {0x3a, 0x5f, 0x1e, 0x91},
300 {0x3a, 0x5f, 0x1e, 0x91},
301 {0x3a, 0x5f, 0x1f, 0x95},
302 {0x3a, 0x5f, 0x1f, 0x95},
303 {0x3a, 0x68, 0x20, 0x9a},
304 {0x3a, 0x68, 0x20, 0x9a},
305 {0x3b, 0x68, 0x21, 0x9e},
306 {0x3b, 0x68, 0x21, 0x9e},
307 {0x3b, 0x68, 0x22, 0xa3},
308 {0x3b, 0x68, 0x22, 0xa3},
309 {0x3b, 0x68, 0x23, 0xa7},
310 {0x3b, 0x68, 0x23, 0xa7},
311 {0x3c, 0x68, 0x24, 0xac},
312 {0x3c, 0x68, 0x24, 0xac},
313 {0x3c, 0x68, 0x24, 0xac},
314 {0x3c, 0x69, 0x25, 0xb0},
315 {0x3c, 0x69, 0x25, 0xb0},
316 {0x3c, 0x69, 0x26, 0xb5},
317 {0x3c, 0x69, 0x26, 0xb5},
318 {0x3d, 0x69, 0x27, 0xb9},
319 {0x3d, 0x69, 0x27, 0xb9},
320 {0x3d, 0x69, 0x28, 0xbe},
321 {0x3d, 0x69, 0x28, 0xbe},
322 {0x3d, 0x6a, 0x29, 0xc2},
323 {0x3d, 0x6a, 0x29, 0xc2},
324 {0x3e, 0x6a, 0x2a, 0xc7},
325 {0x3e, 0x6a, 0x2a, 0xc7},
326 {0x3e, 0x6a, 0x2b, 0xcb},
327 {0x3e, 0x6a, 0x2b, 0xd0},
328 {0x3f, 0x6b, 0x2c, 0xd4},
329 {0x3f, 0x6b, 0x2d, 0xd9},
330 {0x3f, 0x6b, 0x2e, 0xdd},
331 {0x48, 0x6b, 0x2f, 0xe2},
332 {0x48, 0x6b, 0x2f, 0xe2},
333 {0x48, 0x6c, 0x30, 0xe6},
334 {0x48, 0x6c, 0x31, 0xeb},
335 {0x48, 0x6c, 0x32, 0xf0},
336 {0x48, 0x6c, 0x33, 0xf4},
337 {0x48, 0x6c, 0x34, 0xf9},
338 {0x49, 0x6d, 0x35, 0xfd},
339 {0x49, 0x6d, 0x36, 0xff},
340 {0x49, 0x6d, 0x37, 0xff},
341 {0x49, 0x6d, 0x38, 0xff},
342 {0x49, 0x6e, 0x3a, 0xff},
343 {0x49, 0x6e, 0x3b, 0xff},
344 {0x4a, 0x6e, 0x3c, 0xff},
345 {0x4a, 0x6f, 0x3d, 0xff},
346 {0x4a, 0x6f, 0x3d, 0xff},
347 {0x4a, 0x6f, 0x3e, 0xff},
348 {0x4a, 0x6f, 0x3f, 0xff},
349 {0x4a, 0x6f, 0x40, 0xff},
350 {0x4b, 0x78, 0x41, 0xff},
351 {0x4b, 0x78, 0x42, 0xff},
352 {0x4b, 0x78, 0x43, 0xff},
353 {0x4b, 0x78, 0x44, 0xff},
354 {0x4b, 0x78, 0x46, 0xff},
355 {0x4c, 0x78, 0x47, 0xff},
356 {0x4c, 0x79, 0x49, 0xff},
357 {0x4c, 0x79, 0x4a, 0xff}
358 };
359
360 static const unsigned char
361 mainref_table_vp8[8] = {
362 0, 1, 2, 9, 3, 13, 14, 57
363 };
364
365 static const unsigned int
366 cost_table_vp8[NUM_QP_VP8][7] = {
367 {0x398f0500, 0x6f6f6f6f, 0x0000006f, 0x06040402, 0x1a0c0907, 0x08, 0x0e},
368 {0x3b8f0600, 0x6f6f6f6f, 0x0000006f, 0x06040402, 0x1a0c0907, 0x0a, 0x11},
369 {0x3e8f0700, 0x6f6f6f6f, 0x0000006f, 0x06040402, 0x1a0c0907, 0x0c, 0x14},
370 {0x488f0800, 0x6f6f6f6f, 0x0000006f, 0x06040402, 0x1a0c0907, 0x0f, 0x18},
371 {0x498f0a00, 0x6f6f6f6f, 0x0000006f, 0x0d080805, 0x291b190e, 0x11, 0x1b},
372 {0x4a8f0b00, 0x6f6f6f6f, 0x0000006f, 0x0d080805, 0x291b190e, 0x13, 0x1e},
373 {0x4b8f0c00, 0x6f6f6f6f, 0x0000006f, 0x0d080805, 0x291b190e, 0x15, 0x22},
374 {0x4b8f0c00, 0x6f6f6f6f, 0x0000006f, 0x0d080805, 0x291b190e, 0x15, 0x22},
375 {0x4d8f0d00, 0x6f6f6f6f, 0x0000006f, 0x0d080805, 0x291b190e, 0x17, 0x25},
376 {0x4e8f0e00, 0x6f6f6f6f, 0x0000006f, 0x190b0c07, 0x2e281e1a, 0x19, 0x29},
377 {0x4f8f0f00, 0x6f6f6f6f, 0x0000006f, 0x190b0c07, 0x2e281e1a, 0x1b, 0x2c},
378 {0x588f1800, 0x6f6f6f6f, 0x0000006f, 0x190b0c07, 0x2e281e1a, 0x1d, 0x2f},
379 {0x588f1900, 0x6f6f6f6f, 0x0000006f, 0x190b0c07, 0x2e281e1a, 0x1f, 0x33},
380 {0x598f1900, 0x6f6f6f6f, 0x0000006f, 0x1c0f0f0a, 0x392b291e, 0x21, 0x36},
381 {0x5a8f1a00, 0x6f6f6f6f, 0x0000006f, 0x1c0f0f0a, 0x392b291e, 0x23, 0x3a},
382 {0x5a8f1a00, 0x6f6f6f6f, 0x0000006f, 0x1c0f0f0a, 0x392b291e, 0x23, 0x3a},
383 {0x5a8f1a00, 0x6f6f6f6f, 0x0000006f, 0x1c0f0f0a, 0x392b291e, 0x25, 0x3d},
384 {0x5b8f1b00, 0x6f6f6f6f, 0x0000006f, 0x1c0f0f0a, 0x392b291e, 0x27, 0x40},
385 {0x5b8f1c00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x2a, 0x44},
386 {0x5b8f1c00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x2a, 0x44},
387 {0x5c8f1c00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x2c, 0x47},
388 {0x5c8f1c00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x2c, 0x47},
389 {0x5d8f1d00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x2e, 0x4a},
390 {0x5d8f1d00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x2e, 0x4a},
391 {0x5d8f1d00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x30, 0x4e},
392 {0x5d8f1d00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x30, 0x4e},
393 {0x5e8f1e00, 0x6f6f6f6f, 0x0000006f, 0x291b1b0f, 0x3e382e2a, 0x32, 0x51},
394 {0x5e8f1f00, 0x6f6f6f6f, 0x0000006f, 0x291b1b0f, 0x3e382e2a, 0x34, 0x55},
395 {0x5e8f1f00, 0x6f6f6f6f, 0x0000006f, 0x291b1b0f, 0x3e382e2a, 0x34, 0x55},
396 {0x5f8f1f00, 0x6f6f6f6f, 0x0000006f, 0x291b1b0f, 0x3e382e2a, 0x36, 0x58},
397 {0x688f2800, 0x6f6f6f6f, 0x0000006f, 0x291b1b0f, 0x3e382e2a, 0x38, 0x5b},
398 {0x688f2800, 0x6f6f6f6f, 0x0000006f, 0x2b1d1d18, 0x483a382c, 0x3a, 0x5f},
399 {0x688f2800, 0x6f6f6f6f, 0x0000006f, 0x2b1d1d18, 0x483a382c, 0x3c, 0x62},
400 {0x688f2900, 0x6f6f6f6f, 0x0000006f, 0x2b1d1d18, 0x483a382c, 0x3e, 0x65},
401 {0x698f2900, 0x6f6f6f6f, 0x0000006f, 0x2b1d1d18, 0x483a382c, 0x40, 0x69},
402 {0x698f2900, 0x6f6f6f6f, 0x0000006f, 0x2c1f1f19, 0x493b392e, 0x43, 0x6c},
403 {0x698f2900, 0x6f6f6f6f, 0x0000006f, 0x2c1f1f19, 0x493b392e, 0x45, 0x70},
404 {0x6a8f2a00, 0x6f6f6f6f, 0x0000006f, 0x2c1f1f19, 0x493b392e, 0x47, 0x73},
405 {0x6a8f2a00, 0x6f6f6f6f, 0x0000006f, 0x2c1f1f19, 0x493b392e, 0x49, 0x76},
406 {0x6a8f2a00, 0x6f6f6f6f, 0x0000006f, 0x2e28281b, 0x4b3d3a38, 0x4b, 0x7a},
407 {0x6b8f2b00, 0x6f6f6f6f, 0x0000006f, 0x2e28281b, 0x4b3d3a38, 0x4d, 0x7d},
408 {0x6b8f2b00, 0x6f6f6f6f, 0x0000006f, 0x2e28281b, 0x4b3d3a38, 0x4d, 0x7d},
409 {0x6b8f2b00, 0x6f6f6f6f, 0x0000006f, 0x2e28281b, 0x4b3d3a38, 0x4f, 0x81},
410 {0x6b8f2b00, 0x6f6f6f6f, 0x0000006f, 0x2e28281b, 0x4b3d3a38, 0x51, 0x84},
411 {0x6b8f2c00, 0x6f6f6f6f, 0x0000006f, 0x2f29291c, 0x4c3e3b38, 0x53, 0x87},
412 {0x6c8f2c00, 0x6f6f6f6f, 0x0000006f, 0x2f29291c, 0x4c3e3b38, 0x55, 0x8b},
413 {0x6c8f2c00, 0x6f6f6f6f, 0x0000006f, 0x2f29291c, 0x4c3e3b38, 0x57, 0x8e},
414 {0x6c8f2c00, 0x6f6f6f6f, 0x0000006f, 0x2f29291c, 0x4c3e3b38, 0x59, 0x91},
415 {0x6d8f2d00, 0x6f6f6f6f, 0x0000006f, 0x382a2a1d, 0x4d483c39, 0x5b, 0x95},
416 {0x6d8f2d00, 0x6f6f6f6f, 0x0000006f, 0x382a2a1d, 0x4d483c39, 0x5e, 0x98},
417 {0x6d8f2d00, 0x6f6f6f6f, 0x0000006f, 0x382a2a1d, 0x4d483c39, 0x60, 0x9c},
418 {0x6d8f2d00, 0x6f6f6f6f, 0x0000006f, 0x382a2a1d, 0x4d483c39, 0x60, 0x9c},
419 {0x6d8f2e00, 0x6f6f6f6f, 0x0000006f, 0x382a2a1d, 0x4d483c39, 0x62, 0x9f},
420 {0x6e8f2e00, 0x6f6f6f6f, 0x0000006f, 0x392b2b1e, 0x4e483e3a, 0x64, 0xa2},
421 {0x6e8f2e00, 0x6f6f6f6f, 0x0000006f, 0x392b2b1e, 0x4e483e3a, 0x66, 0xa6},
422 {0x6e8f2e00, 0x6f6f6f6f, 0x0000006f, 0x392b2b1e, 0x4e483e3a, 0x68, 0xa9},
423 {0x6f8f2f00, 0x6f6f6f6f, 0x0000006f, 0x392b2b1e, 0x4e483e3a, 0x6a, 0xad},
424 {0x6f8f2f00, 0x6f6f6f6f, 0x0000006f, 0x3a2c2c1f, 0x4f493f3b, 0x6c, 0xb0},
425 {0x6f8f2f00, 0x6f6f6f6f, 0x0000006f, 0x3a2c2c1f, 0x4f493f3b, 0x6e, 0xb3},
426 {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3a2c2c1f, 0x4f493f3b, 0x70, 0xb7},
427 {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3a2c2c1f, 0x4f493f3b, 0x72, 0xba},
428 {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3b2d2d28, 0x584a483c, 0x74, 0xbd},
429 {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3b2d2d28, 0x584a483c, 0x76, 0xc1},
430 {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3b2d2d28, 0x584a483c, 0x79, 0xc4},
431 {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3b2d2d28, 0x584a483c, 0x7b, 0xc8},
432 {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3b2e2e29, 0x594b483d, 0x7d, 0xcb},
433 {0x798f3900, 0x6f6f6f6f, 0x0000006f, 0x3b2e2e29, 0x594b483d, 0x7f, 0xce},
434 {0x798f3900, 0x6f6f6f6f, 0x0000006f, 0x3b2e2e29, 0x594b483d, 0x81, 0xd2},
435 {0x798f3900, 0x6f6f6f6f, 0x0000006f, 0x3b2e2e29, 0x594b483d, 0x83, 0xd5},
436 {0x798f3900, 0x6f6f6f6f, 0x0000006f, 0x3c2f2f29, 0x594b493e, 0x85, 0xd9},
437 {0x798f3900, 0x6f6f6f6f, 0x0000006f, 0x3c2f2f29, 0x594b493e, 0x87, 0xdc},
438 {0x798f3900, 0x6f6f6f6f, 0x0000006f, 0x3c2f2f29, 0x594b493e, 0x89, 0xdf},
439 {0x798f3a00, 0x6f6f6f6f, 0x0000006f, 0x3c2f2f29, 0x594b493e, 0x8b, 0xe3},
440 {0x7a8f3a00, 0x6f6f6f6f, 0x0000006f, 0x3d38382a, 0x5a4c493f, 0x8d, 0xe6},
441 {0x7a8f3a00, 0x6f6f6f6f, 0x0000006f, 0x3d38382a, 0x5a4c493f, 0x8f, 0xe9},
442 {0x7a8f3a00, 0x6f6f6f6f, 0x0000006f, 0x3d38382a, 0x5a4c493f, 0x91, 0xed},
443 {0x7a8f3a00, 0x6f6f6f6f, 0x0000006f, 0x3d38382a, 0x5a4c493f, 0x94, 0xf0},
444 {0x7a8f3a00, 0x6f6f6f6f, 0x0000006f, 0x3e38382b, 0x5b4d4a48, 0x96, 0xf4},
445 {0x7a8f3a00, 0x6f6f6f6f, 0x0000006f, 0x3e38382b, 0x5b4d4a48, 0x98, 0xf7},
446 {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3e38382b, 0x5b4d4a48, 0x9a, 0xfa},
447 {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3e38382b, 0x5b4d4a48, 0x9c, 0xfe},
448 {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3f38392b, 0x5b4d4b48, 0x9e, 0xff},
449 {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3f38392b, 0x5b4d4b48, 0x9e, 0xff},
450 {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3f38392b, 0x5b4d4b48, 0xa0, 0xff},
451 {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3f38392b, 0x5b4d4b48, 0xa2, 0xff},
452 {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3f38392b, 0x5b4d4b48, 0xa4, 0xff},
453 {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3f39392c, 0x5c4e4b48, 0xa6, 0xff},
454 {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x3f39392c, 0x5c4e4b48, 0xa8, 0xff},
455 {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x3f39392c, 0x5c4e4b48, 0xaa, 0xff},
456 {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x3f39392c, 0x5c4e4b48, 0xac, 0xff},
457 {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x48393a2c, 0x5c4f4c49, 0xaf, 0xff},
458 {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x48393a2c, 0x5c4f4c49, 0xb1, 0xff},
459 {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x48393a2c, 0x5c4f4c49, 0xb3, 0xff},
460 {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x48393a2c, 0x5c4f4c49, 0xb5, 0xff},
461 {0x7d8f3d00, 0x6f6f6f6f, 0x0000006f, 0x483a3a2d, 0x5d584c49, 0xb7, 0xff},
462 {0x7d8f3d00, 0x6f6f6f6f, 0x0000006f, 0x483a3a2d, 0x5d584c49, 0xb9, 0xff},
463 {0x7d8f3d00, 0x6f6f6f6f, 0x0000006f, 0x483a3a2d, 0x5d584c49, 0xbd, 0xff},
464 {0x7d8f3d00, 0x6f6f6f6f, 0x0000006f, 0x493a3b2e, 0x5e584d4a, 0xc1, 0xff},
465 {0x7e8f3e00, 0x6f6f6f6f, 0x0000006f, 0x493a3b2e, 0x5e584d4a, 0xc5, 0xff},
466 {0x7e8f3e00, 0x6f6f6f6f, 0x0000006f, 0x493b3b2e, 0x5e584e4a, 0xc8, 0xff},
467 {0x7e8f3e00, 0x6f6f6f6f, 0x0000006f, 0x493b3b2e, 0x5e584e4a, 0xcc, 0xff},
468 {0x7e8f3e00, 0x6f6f6f6f, 0x0000006f, 0x493b3c2f, 0x5f594e4b, 0xd0, 0xff},
469 {0x7f8f3f00, 0x6f6f6f6f, 0x0000006f, 0x493b3c2f, 0x5f594e4b, 0xd2, 0xff},
470 {0x7f8f3f00, 0x6f6f6f6f, 0x0000006f, 0x493b3c2f, 0x5f594e4b, 0xd4, 0xff},
471 {0x7f8f3f00, 0x6f6f6f6f, 0x0000006f, 0x4a3c3c2f, 0x5f594f4b, 0xd8, 0xff},
472 {0x7f8f3f00, 0x6f6f6f6f, 0x0000006f, 0x4a3c3c2f, 0x5f594f4b, 0xdc, 0xff},
473 {0x888f4800, 0x6f6f6f6f, 0x0000006f, 0x4a3c3d38, 0x68594f4c, 0xe0, 0xff},
474 {0x888f4800, 0x6f6f6f6f, 0x0000006f, 0x4a3c3d38, 0x68594f4c, 0xe5, 0xff},
475 {0x888f4800, 0x6f6f6f6f, 0x0000006f, 0x4b3d3d38, 0x685a584c, 0xe9, 0xff},
476 {0x888f4800, 0x6f6f6f6f, 0x0000006f, 0x4b3d3d38, 0x685a584c, 0xed, 0xff},
477 {0x888f4800, 0x6f6f6f6f, 0x0000006f, 0x4b3d3e38, 0x685a584c, 0xf1, 0xff},
478 {0x888f4800, 0x6f6f6f6f, 0x0000006f, 0x4b3d3e38, 0x685a584c, 0xf5, 0xff},
479 {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4b3e3e39, 0x695b584d, 0xfe, 0xff},
480 {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4c3e3e39, 0x695b594d, 0xff, 0xff},
481 {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4c3e3e39, 0x695b594d, 0xff, 0xff},
482 {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4c3f3f39, 0x695b594e, 0xff, 0xff},
483 {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4c3f3f39, 0x695b594e, 0xff, 0xff},
484 {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4d3f3f3a, 0x6a5c594e, 0xff, 0xff},
485 {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4d3f3f3a, 0x6a5c594e, 0xff, 0xff},
486 {0x8a8f4a00, 0x6f6f6f6f, 0x0000006f, 0x4d48483a, 0x6a5c594f, 0xff, 0xff},
487 {0x8a8f4a00, 0x6f6f6f6f, 0x0000006f, 0x4d48483a, 0x6a5c594f, 0xff, 0xff},
488 {0x8a8f4a00, 0x6f6f6f6f, 0x0000006f, 0x4d48483a, 0x6a5c5a4f, 0xff, 0xff},
489 {0x8a8f4a00, 0x6f6f6f6f, 0x0000006f, 0x4d48483a, 0x6a5c5a4f, 0xff, 0xff},
490 {0x8a8f4a00, 0x6f6f6f6f, 0x0000006f, 0x4e48483a, 0x6a5d5a58, 0xff, 0xff},
491 {0x8b8f4b00, 0x6f6f6f6f, 0x0000006f, 0x4e48483b, 0x6b5d5a58, 0xff, 0xff},
492 {0x8b8f4b00, 0x6f6f6f6f, 0x0000006f, 0x4e48483b, 0x6b5d5a58, 0xff, 0xff},
493 {0x8b8f4b00, 0x6f6f6f6f, 0x0000006f, 0x4f48493b, 0x6b5d5b58, 0xff, 0xff},
494 {0x8b8f4b00, 0x6f6f6f6f, 0x0000006f, 0x4f49493b, 0x6b5e5b58, 0xff, 0xff}
495 };
496
497 static const unsigned int single_su_vp8[56] = {
498 0x00000000, 0x00000000, 0x00000000, 0x00000000,
499 0x00000000, 0x00000000, 0x00000000, 0x00000000,
500 0x00000000, 0x00000000, 0x00000000, 0x00000000,
501 0x00000000, 0x00000000
502 };
503
504 static const unsigned char full_spiral_48x40_vp8[56] = {
505 // L -> U -> R -> D
506 0x0F,
507 0xF0,
508 0x01, 0x01,
509 0x10, 0x10,
510 0x0F, 0x0F, 0x0F,
511 0xF0, 0xF0, 0xF0,
512 0x01, 0x01, 0x01, 0x01,
513 0x10, 0x10, 0x10, 0x10,
514 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
515 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
516 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
517 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, // The last 0x10 steps outside the search window.
518 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, // These are outside the search window.
519 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0
520 };
521
522 static const unsigned char raster_scan_48x40_vp8[56] = {
523 0x11, 0x01, 0x01, 0x01,
524 0x11, 0x01, 0x01, 0x01,
525 0x11, 0x01, 0x01, 0x01,
526 0x11, 0x01, 0x01, 0x01,
527 0x11, 0x01, 0x01, 0x01,
528 0x01, 0x01, 0x01, 0x01,
529 0x00, 0x00, 0x00, 0x00,
530 0x00, 0x00, 0x00, 0x00,
531 0x00, 0x00, 0x00, 0x00,
532 0x00, 0x00, 0x00, 0x00,
533 0x00, 0x00, 0x00, 0x00,
534 0x00, 0x00, 0x00, 0x00,
535 0x00, 0x00, 0x00, 0x00,
536 0x00, 0x00, 0x00, 0x00
537 };
538
539 static const unsigned char diamond_vp8[56] = {
540 0x0F, 0xF1, 0x0F, 0x12,//5
541 0x0D, 0xE2, 0x22, 0x1E,//9
542 0x10, 0xFF, 0xE2, 0x20,//13
543 0xFC, 0x06, 0xDD,//16
544 0x2E, 0xF1, 0x3F, 0xD3, 0x11, 0x3D, 0xF3, 0x1F,//24
545 0xEB, 0xF1, 0xF1, 0xF1,//28
546 0x4E, 0x11, 0x12, 0xF2, 0xF1,//33
547 0xE0, 0xFF, 0xFF, 0x0D, 0x1F, 0x1F,//39
548 0x20, 0x11, 0xCF, 0xF1, 0x05, 0x11,//45
549 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,//51
550 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
551 };
552
553 static const unsigned short
554 mv_ref_cost_context_vp8[6][4][2] = {
555 { {1328, 10},
556 {2047, 1},
557 {2047, 1},
558 {214, 304},
559 },
560 { {1072, 21},
561 {979, 27},
562 {1072, 21},
563 {321, 201},
564 },
565 { {235, 278},
566 {511, 107},
567 {553, 93},
568 {488, 115},
569 },
570 { {534, 99},
571 {560, 92},
572 {255, 257},
573 {505, 109},
574 },
575 { {174, 361},
576 {238, 275},
577 {255, 257},
578 {744, 53},
579 },
580 { {32, 922},
581 {113, 494},
582 {255, 257},
583 {816, 43},
584 },
585 };
586
587 static const unsigned int
588 new_mv_skip_threshold_vp8[NUM_QP_VP8] = {
589 111, 120, 129, 137, 146, 155, 163, 172, 180, 189, 198, 206, 215, 224, 232, 241,
590 249, 258, 267, 275, 284, 293, 301, 310, 318, 327, 336, 344, 353, 362, 370, 379,
591 387, 396, 405, 413, 422, 431, 439, 448, 456, 465, 474, 482, 491, 500, 508, 517,
592 525, 534, 543, 551, 560, 569, 577, 586, 594, 603, 612, 620, 629, 638, 646, 655,
593 663, 672, 681, 689, 698, 707, 715, 724, 733, 741, 750, 758, 767, 776, 784, 793,
594 802, 810, 819, 827, 836, 845, 853, 862, 871, 879, 888, 896, 905, 914, 922, 931,
595 940, 948, 957, 965, 974, 983, 991, 1000, 1009, 1017, 1026, 1034, 1043, 1052, 1060, 1069,
596 1078, 1086, 1095, 1103, 1112, 1121, 1129, 1138, 1147, 1155, 1164, 1172, 1181, 1190, 1198, 1208
597 };
598
599 static const unsigned short
600 mb_mode_cost_luma_vp8[10] = {
601 657, 869, 915, 917, 208, 0, 0, 0, 0, 0
602 };
603
604
605 static const unsigned short
606 block_mode_cost_vp8[10][10][10] = {
607 {
608 {37, 1725, 1868, 1151, 1622, 2096, 2011, 1770, 2218, 2128 },
609 {139, 759, 1683, 911, 1455, 1846, 1570, 1295, 1792, 1648 },
610 {560, 1383, 408, 639, 1612, 1174, 1562, 1736, 847, 991 },
611 {191, 1293, 1299, 466, 1774, 1840, 1784, 1691, 1698, 1505 },
612 {211, 1624, 1294, 779, 714, 1622, 2222, 1554, 1706, 903 },
613 {297, 1259, 1098, 1062, 1583, 618, 1053, 1889, 851, 1127 },
614 {275, 703, 1356, 1111, 1597, 1075, 656, 1529, 1531, 1275 },
615 {150, 1046, 1760, 1039, 1353, 1981, 2174, 728, 1730, 1379 },
616 {516, 1414, 741, 1045, 1495, 738, 1288, 1619, 442, 1200 },
617 {424, 1365, 706, 825, 1197, 1453, 1191, 1462, 1186, 519 },
618 },
619 {
620 {393, 515, 1491, 549, 1598, 1524, 964, 1126, 1651, 2172 },
621 {693, 237, 1954, 641, 1525, 2073, 1183, 971, 1973, 2235 },
622 {560, 739, 855, 836, 1224, 1115, 966, 839, 1076, 767 },
623 {657, 368, 1406, 425, 1672, 1853, 1210, 1125, 1969, 1542 },
624 {321, 1056, 1776, 774, 803, 3311, 1265, 1177, 1366, 636 },
625 {693, 510, 949, 877, 1049, 658, 882, 1178, 1515, 1111 },
626 {744, 377, 1278, 958, 1576, 1168, 477, 1146, 1838, 1501 },
627 {488, 477, 1767, 973, 1107, 1511, 1773, 486, 1527, 1449 },
628 {744, 1004, 695, 1012, 1326, 834, 1215, 774, 724, 704 },
629 {522, 567, 1036, 1082, 1039, 1333, 873, 1135, 1189, 677 },
630 },
631 {
632 {103, 1441, 1000, 864, 1513, 1928, 1832, 1916, 1663, 1567 },
633 {304, 872, 1100, 515, 1416, 1417, 3463, 1051, 1305, 1227 },
634 {684, 2176, 242, 729, 1867, 1496, 2056, 1544, 1038, 930 },
635 {534, 1198, 669, 300, 1805, 1377, 2165, 1894, 1249, 1153 },
636 {346, 1602, 1178, 612, 997, 3381, 1335, 1328, 997, 646 },
637 {393, 1027, 649, 813, 1276, 945, 1545, 1278, 875, 1031 },
638 {528, 996, 930, 617, 1086, 1190, 621, 2760, 787, 1347 },
639 {216, 873, 1595, 738, 1339, 3896, 3898, 743, 1343, 1605 },
640 {675, 1580, 543, 749, 1859, 1245, 1589, 2377, 384, 1075 },
641 {594, 1163, 415, 684, 1474, 1080, 1491, 1478, 1077, 801 },
642 },
643 {
644 {238, 1131, 1483, 398, 1510, 1651, 1495, 1545, 1970, 2090 },
645 {499, 456, 1499, 449, 1558, 1691, 1272, 969, 2114, 2116 },
646 {675, 1386, 318, 645, 1449, 1588, 1666, 1925, 979, 859 },
647 {467, 957, 1223, 238, 1825, 1704, 1608, 1560, 1665, 1376 },
648 {331, 1460, 1238, 627, 787, 1882, 3928, 1544, 1897, 579 },
649 {457, 1038, 903, 784, 1158, 725, 955, 1517, 842, 1016 },
650 {505, 497, 1131, 812, 1508, 1206, 703, 1072, 1254, 1256 },
651 {397, 741, 1336, 642, 1506, 1852, 1340, 599, 1854, 1000 },
652 {625, 1212, 597, 750, 1291, 1057, 1401, 1401, 527, 954 },
653 {499, 1041, 654, 752, 1299, 1217, 1605, 1424, 1377, 505 },
654 },
655 {
656 {263, 1094, 1218, 602, 938, 1487, 1231, 1016, 1724, 1448 },
657 {452, 535, 1728, 562, 1008, 1471, 1473, 873, 3182, 1136 },
658 {553, 1570, 935, 1093, 826, 1339, 879, 1007, 1006, 476 },
659 {365, 900, 1050, 582, 866, 1398, 1236, 1123, 1608, 1039 },
660 {294, 2044, 1790, 1143, 430, 1642, 3688, 1549, 2080, 704 },
661 {703, 1210, 958, 815, 1211, 960, 623, 2455, 815, 559 },
662 {675, 574, 862, 1261, 866, 864, 761, 1267, 1014, 936 },
663 {342, 1254, 1857, 989, 612, 1856, 1858, 553, 1840, 1037 },
664 {553, 1316, 811, 1072, 1068, 728, 1328, 1317, 1064, 475 },
665 {288, 1303, 1167, 1167, 823, 1634, 1636, 2497, 1294, 491 },
666 },
667 {
668 {227, 1059, 1369, 1066, 1505, 740, 970, 1511, 972, 1775 },
669 {516, 587, 1033, 646, 1188, 748, 978, 1445, 1294, 1450 },
670 {684, 1048, 663, 747, 1126, 826, 1386, 1128, 635, 924 },
671 {494, 814, 933, 510, 1606, 951, 878, 1344, 1031, 1347 },
672 {553, 1071, 1327, 726, 809, 3376, 1330, 1324, 1062, 407 },
673 {625, 1120, 988, 1121, 1197, 347, 1064, 1308, 862, 1206 },
674 {633, 853, 1657, 1073, 1662, 634, 460, 1405, 811, 1155 },
675 {505, 621, 1394, 876, 1394, 876, 878, 795, 878, 1399 },
676 {684, 1302, 968, 1704, 1280, 561, 972, 1713, 387, 1104 },
677 {397, 1447, 1060, 867, 957, 1058, 749, 1475, 1210, 660 },
678 },
679 {
680 {331, 933, 1647, 761, 1647, 998, 513, 1402, 1461, 2219 },
681 {573, 485, 1968, 641, 1570, 1198, 588, 1086, 1382, 1982 },
682 {790, 942, 570, 790, 1607, 1005, 938, 1193, 714, 751 },
683 {511, 745, 1152, 492, 1878, 1206, 596, 1867, 1617, 1157 },
684 {452, 1308, 896, 896, 451, 1308, 3354, 1301, 1306, 794 },
685 {693, 670, 1072, 1020, 1687, 566, 488, 1432, 1096, 3142 },
686 {778, 566, 1993, 1283, 3139, 1251, 227, 1378, 1784, 1447 },
687 {393, 937, 1091, 934, 939, 1348, 1092, 579, 1351, 1095 },
688 {560, 1013, 1007, 1014, 1011, 644, 1165, 1155, 605, 1016 },
689 {567, 627, 997, 793, 2562, 998, 849, 1260, 922, 748 },
690 },
691 {
692 {338, 762, 1868, 717, 1247, 1757, 1263, 535, 1751, 2162 },
693 {488, 442, 3235, 756, 1658, 1814, 1264, 528, 1857, 2119 },
694 {522, 1087, 840, 1103, 843, 1354, 1098, 888, 946, 588 },
695 {483, 688, 1502, 651, 1213, 1446, 1397, 491, 1908, 1253 },
696 {452, 1386, 1910, 1175, 298, 1507, 3553, 930, 1904, 905 },
697 {713, 839, 716, 715, 932, 719, 931, 848, 3088, 1042 },
698 {516, 495, 1331, 1340, 1331, 1069, 665, 702, 1593, 1337 },
699 {401, 977, 2167, 1537, 1069, 1764, 3810, 259, 3624, 1578 },
700 {560, 1104, 601, 1371, 965, 658, 2704, 779, 967, 969 },
701 {547, 1057, 801, 1141, 1133, 1397, 937, 605, 1252, 631 },
702 },
703 {
704 {163, 1240, 925, 983, 1653, 1321, 1353, 1566, 946, 1601 },
705 {401, 726, 758, 836, 1241, 926, 1656, 795, 1394, 1396 },
706 {905, 1073, 366, 876, 1436, 1576, 1732, 2432, 459, 1019 },
707 {594, 922, 835, 417, 1387, 1124, 1098, 2042, 843, 1023 },
708 {415, 1262, 860, 1274, 758, 1272, 3318, 1010, 1276, 503 },
709 {641, 1018, 1020, 1095, 1619, 667, 1371, 2348, 397, 849 },
710 {560, 817, 903, 1014, 1420, 695, 756, 904, 821, 1421 },
711 {406, 596, 1001, 993, 1257, 1258, 1260, 746, 1002, 1264 },
712 {979, 1371, 780, 1188, 1693, 1024, 1286, 1699, 183, 1405 },
713 {733, 1292, 458, 884, 1554, 889, 1151, 1286, 738, 740 },
714 },
715 {
716 {109, 1377, 1177, 933, 1140, 1928, 1639, 1705, 1861, 1292 },
717 {342, 570, 1081, 638, 1154, 1231, 1339, 1342, 1750, 1494 },
718 {560, 1203, 345, 767, 1325, 1681, 1425, 1905, 1205, 786 },
719 {406, 1027, 1011, 410, 1306, 1901, 1389, 1636, 1493, 776 },
720 {206, 1329, 1337, 1037, 802, 1600, 3646, 1451, 1603, 693 },
721 {472, 1167, 758, 911, 1424, 703, 2749, 1428, 703, 764 },
722 {342, 780, 1139, 889, 1290, 1139, 781, 1544, 957, 1042 },
723 {227, 888, 1039, 929, 988, 3753, 1707, 818, 1710, 1306 },
724 {767, 1055, 627, 725, 1312, 980, 1065, 1324, 599, 811 },
725 {304, 1372, 888, 1173, 979, 1578, 1580, 1974, 1318, 482 },
726 }
727 };
728
729 static const unsigned char
730 brc_qpadjustment_distthreshold_maxframethreshold_distqpadjustment_ipb_vp8[576] = {
731 0x01, 0x03, 0x05, 0x07, 0x09, 0x01, 0x02, 0x03, 0x05, 0x07, 0x00, 0x00, 0x01, 0x02, 0x04, 0x00,
732 0x00, 0x00, 0x01, 0x02, 0xff, 0x00, 0x00, 0x00, 0x01, 0xfd, 0xfe, 0xff, 0x00, 0x00, 0xfb, 0xfc,
733 0xfe, 0xff, 0x00, 0xf9, 0xfa, 0xfc, 0xfe, 0xff, 0xf7, 0xf9, 0xfb, 0xfe, 0xff, 0x00, 0x04, 0x1e,
734 0x3c, 0x50, 0x78, 0x8c, 0xc8, 0xff, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00,
735 0x01, 0x02, 0x05, 0x08, 0x0a, 0x01, 0x02, 0x04, 0x06, 0x08, 0x00, 0x01, 0x02, 0x04, 0x06, 0x00,
736 0x00, 0x00, 0x01, 0x02, 0xff, 0x00, 0x00, 0x00, 0x01, 0xfe, 0xff, 0xff, 0x00, 0x00, 0xfd, 0xfe,
737 0xff, 0xff, 0x00, 0xfb, 0xfd, 0xfe, 0xff, 0x00, 0xf9, 0xfa, 0xfc, 0xfe, 0xff, 0x00, 0x04, 0x1e,
738 0x3c, 0x50, 0x78, 0x8c, 0xc8, 0xff, 0x04, 0x05, 0x06, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
739 0x01, 0x02, 0x05, 0x08, 0x0a, 0x01, 0x02, 0x04, 0x06, 0x08, 0x00, 0x01, 0x02, 0x04, 0x06, 0x00,
740 0x00, 0x00, 0x01, 0x02, 0xff, 0x00, 0x00, 0x00, 0x01, 0xfe, 0xff, 0xff, 0x00, 0x00, 0xfd, 0xfe,
741 0xff, 0xff, 0x00, 0xfb, 0xfd, 0xfe, 0xff, 0x00, 0xf9, 0xfa, 0xfc, 0xfe, 0xff, 0x00, 0x02, 0x14,
742 0x28, 0x46, 0x82, 0xa0, 0xc8, 0xff, 0x04, 0x05, 0x06, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
743 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x06, 0x08, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05,
744 0x07, 0x09, 0xff, 0x00, 0x00, 0x00, 0x00, 0x03, 0x04, 0x06, 0x07, 0xfe, 0xff, 0x00, 0x00, 0x00,
745 0x01, 0x02, 0x03, 0x05, 0xfd, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01, 0x03, 0x05, 0xfc, 0xfe, 0xff,
746 0x00, 0x00, 0x00, 0x01, 0x03, 0x05, 0xfb, 0xfd, 0xfe, 0xff, 0x00, 0x00, 0x01, 0x03, 0x05, 0xfa,
747 0xfc, 0xfe, 0xff, 0x00, 0x00, 0x01, 0x03, 0x05, 0xfa, 0xfc, 0xfe, 0xff, 0x00, 0x00, 0x01, 0x03,
748 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
749 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
750 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
751 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05, 0x07, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05,
752 0x06, 0x08, 0xff, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05, 0x07, 0x08, 0xfe, 0xff, 0x00, 0x00, 0x00,
753 0x02, 0x04, 0x05, 0x06, 0xfd, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01, 0x04, 0x05, 0xfc, 0xfe, 0xff,
754 0x00, 0x00, 0x00, 0x01, 0x04, 0x05, 0xfc, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x04, 0x05, 0xfc,
755 0xfd, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01, 0x05, 0xfb, 0xfc, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01,
756 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
757 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
758 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
759 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05, 0x07, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05,
760 0x06, 0x08, 0xff, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05, 0x07, 0x08, 0xfe, 0xff, 0x00, 0x00, 0x00,
761 0x02, 0x04, 0x05, 0x06, 0xfd, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01, 0x04, 0x05, 0xfc, 0xfe, 0xff,
762 0x00, 0x00, 0x00, 0x01, 0x04, 0x05, 0xfc, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x04, 0x05, 0xfc,
763 0xfd, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01, 0x05, 0xfb, 0xfc, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01,
764 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
765 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
766 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
767 };
768
769 static const unsigned char
770 brc_iframe_cost_vp8[128][4] = {
771 { 0x5, 0x5, 0x8, 0x8 },
772 { 0xa, 0xa, 0xd, 0xd },
773 { 0xd, 0xf, 0xf, 0x19 },
774 { 0x19, 0x1a, 0x1a, 0x1a },
775 { 0x1b, 0x1b, 0x1d, 0x1d },
776 { 0x1d, 0x1d, 0x1e, 0x1e },
777 { 0x1e, 0x1e, 0x1f, 0x1f },
778 { 0x1f, 0x28, 0x28, 0x29 },
779 { 0x29, 0x29, 0x29, 0x2a },
780 { 0x2a, 0x2b, 0x2b, 0x2b },
781 { 0x2b, 0x2b, 0x2c, 0x2c },
782 { 0x2c, 0x2c, 0x2d, 0x2d },
783 { 0x2e, 0x2e, 0x2e, 0x2e },
784 { 0x2e, 0x2f, 0x2f, 0x38 },
785 { 0x38, 0x38, 0x38, 0x38 },
786 { 0x38, 0x39, 0x39, 0x39 },
787 { 0x39, 0x39, 0x39, 0x3a },
788 { 0x3a, 0x3a, 0x3a, 0x3a },
789 { 0x3a, 0x3a, 0x3a, 0x3b },
790 { 0x3b, 0x3b, 0x3b, 0x3b },
791 { 0x3b, 0x3c, 0x3c, 0x3c },
792 { 0x3c, 0x3c, 0x3c, 0x3c },
793 { 0x3d, 0x3d, 0x3d, 0x3d },
794 { 0x3d, 0x3d, 0x3e, 0x3e },
795 { 0x3e, 0x3e, 0x3f, 0x3f },
796 { 0x3f, 0x48, 0x48, 0x48 },
797 { 0x48, 0x48, 0x48, 0x48 },
798 { 0x49, 0x49, 0x49, 0x49 },
799 { 0x49, 0x49, 0x4a, 0x4a },
800 { 0x4a, 0x4a, 0x4a, 0x4a },
801 { 0x4b, 0x4b, 0x4b, 0x4b },
802 { 0x4b, 0x4c, 0x4c, 0x4c },
803 { 0x1f, 0x1f, 0x2b, 0x2b },
804 { 0x2f, 0x2f, 0x39, 0x39 },
805 { 0x39, 0x3b, 0x3b, 0x3d },
806 { 0x3d, 0x3f, 0x3f, 0x3f },
807 { 0x48, 0x48, 0x49, 0x49 },
808 { 0x49, 0x49, 0x4a, 0x4a },
809 { 0x4a, 0x4a, 0x4b, 0x4b },
810 { 0x4b, 0x4c, 0x4c, 0x4d },
811 { 0x4d, 0x4e, 0x4e, 0x4f },
812 { 0x4f, 0x58, 0x58, 0x58 },
813 { 0x58, 0x58, 0x58, 0x58 },
814 { 0x59, 0x59, 0x59, 0x59 },
815 { 0x5a, 0x5a, 0x5a, 0x5a },
816 { 0x5a, 0x5b, 0x5b, 0x5b },
817 { 0x5b, 0x5c, 0x5c, 0x5c },
818 { 0x5c, 0x5d, 0x5d, 0x5d },
819 { 0x5d, 0x5e, 0x5e, 0x5e },
820 { 0x5e, 0x5f, 0x5f, 0x5f },
821 { 0x5f, 0x68, 0x68, 0x68 },
822 { 0x68, 0x68, 0x68, 0x68 },
823 { 0x68, 0x68, 0x68, 0x68 },
824 { 0x69, 0x69, 0x69, 0x69 },
825 { 0x69, 0x69, 0x69, 0x69 },
826 { 0x6a, 0x6a, 0x6a, 0x6a },
827 { 0x6a, 0x6a, 0x6b, 0x6b },
828 { 0x6b, 0x6b, 0x6b, 0x6c },
829 { 0x6c, 0x6c, 0x6c, 0x6c },
830 { 0x6d, 0x6d, 0x6d, 0x6d },
831 { 0x6e, 0x6e, 0x6e, 0x6f },
832 { 0x6f, 0x6f, 0x6f, 0x6f },
833 { 0x78, 0x78, 0x78, 0x78 },
834 { 0x78, 0x78, 0x79, 0x79 },
835 { 0x2, 0x2, 0x3, 0x3 },
836 { 0x4, 0x4, 0x5, 0x5 },
837 { 0x5, 0x6, 0x6, 0x7 },
838 { 0x7, 0x8, 0x8, 0x8 },
839 { 0x9, 0x9, 0x9, 0x9 },
840 { 0x9, 0x9, 0xa, 0xa },
841 { 0xa, 0xa, 0xb, 0xb },
842 { 0xb, 0xc, 0xc, 0xd },
843 { 0xd, 0xe, 0xe, 0xf },
844 { 0xf, 0x10, 0x10, 0x11 },
845 { 0x11, 0x11, 0x12, 0x12 },
846 { 0x13, 0x13, 0x14, 0x14 },
847 { 0x15, 0x15, 0x16, 0x16 },
848 { 0x16, 0x17, 0x17, 0x18 },
849 { 0x18, 0x19, 0x19, 0x1a },
850 { 0x1a, 0x1a, 0x1a, 0x1b },
851 { 0x1b, 0x1c, 0x1c, 0x1d },
852 { 0x1d, 0x1e, 0x1e, 0x1f },
853 { 0x1f, 0x20, 0x20, 0x21 },
854 { 0x21, 0x22, 0x22, 0x23 },
855 { 0x23, 0x24, 0x24, 0x24 },
856 { 0x25, 0x25, 0x26, 0x26 },
857 { 0x27, 0x27, 0x28, 0x28 },
858 { 0x29, 0x29, 0x2a, 0x2a },
859 { 0x2b, 0x2b, 0x2c, 0x2d },
860 { 0x2e, 0x2f, 0x2f, 0x30 },
861 { 0x31, 0x32, 0x33, 0x34 },
862 { 0x35, 0x36, 0x37, 0x38 },
863 { 0x3a, 0x3b, 0x3c, 0x3d },
864 { 0x3d, 0x3e, 0x3f, 0x40 },
865 { 0x41, 0x42, 0x43, 0x44 },
866 { 0x46, 0x47, 0x49, 0x4a },
867 { 0x9, 0x9, 0xe, 0xe },
868 { 0x12, 0x12, 0x17, 0x17 },
869 { 0x17, 0x1b, 0x1b, 0x20 },
870 { 0x20, 0x24, 0x24, 0x24 },
871 { 0x29, 0x29, 0x2d, 0x2d },
872 { 0x2d, 0x2d, 0x32, 0x32 },
873 { 0x32, 0x32, 0x36, 0x36 },
874 { 0x36, 0x3b, 0x3b, 0x3f },
875 { 0x3f, 0x44, 0x44, 0x48 },
876 { 0x48, 0x4d, 0x4d, 0x51 },
877 { 0x51, 0x51, 0x56, 0x56 },
878 { 0x5a, 0x5a, 0x5f, 0x5f },
879 { 0x63, 0x63, 0x68, 0x68 },
880 { 0x68, 0x6c, 0x6c, 0x71 },
881 { 0x71, 0x76, 0x76, 0x7a },
882 { 0x7a, 0x7f, 0x7f, 0x83 },
883 { 0x83, 0x88, 0x88, 0x8c },
884 { 0x8c, 0x91, 0x91, 0x95 },
885 { 0x95, 0x9a, 0x9a, 0x9e },
886 { 0x9e, 0xa3, 0xa3, 0xa7 },
887 { 0xa7, 0xac, 0xac, 0xac },
888 { 0xb0, 0xb0, 0xb5, 0xb5 },
889 { 0xb9, 0xb9, 0xbe, 0xbe },
890 { 0xc2, 0xc2, 0xc7, 0xc7 },
891 { 0xcb, 0xd0, 0xd4, 0xd9 },
892 { 0xdd, 0xe2, 0xe2, 0xe6 },
893 { 0xeb, 0xf0, 0xf4, 0xf9 },
894 { 0xfd, 0xff, 0xff, 0xff },
895 { 0xff, 0xff, 0xff, 0xff },
896 { 0xff, 0xff, 0xff, 0xff },
897 { 0xff, 0xff, 0xff, 0xff },
898 { 0xff, 0xff, 0xff, 0xff },
899 };
900
901 static const unsigned int
902 brc_pframe_cost_vp8[256] = {
903 0x06040402,
904 0x06040402,
905 0x06040402,
906 0x06040402,
907 0x0d080805,
908 0x0d080805,
909 0x0d080805,
910 0x0d080805,
911 0x0d080805,
912 0x190b0c07,
913 0x190b0c07,
914 0x190b0c07,
915 0x190b0c07,
916 0x1c0f0f0a,
917 0x1c0f0f0a,
918 0x1c0f0f0a,
919 0x1c0f0f0a,
920 0x1c0f0f0a,
921 0x2819190c,
922 0x2819190c,
923 0x2819190c,
924 0x2819190c,
925 0x2819190c,
926 0x2819190c,
927 0x2819190c,
928 0x2819190c,
929 0x291b1b0f,
930 0x291b1b0f,
931 0x291b1b0f,
932 0x291b1b0f,
933 0x291b1b0f,
934 0x2b1d1d18,
935 0x2b1d1d18,
936 0x2b1d1d18,
937 0x2b1d1d18,
938 0x2c1f1f19,
939 0x2c1f1f19,
940 0x2c1f1f19,
941 0x2c1f1f19,
942 0x2e28281b,
943 0x2e28281b,
944 0x2e28281b,
945 0x2e28281b,
946 0x2e28281b,
947 0x2f29291c,
948 0x2f29291c,
949 0x2f29291c,
950 0x2f29291c,
951 0x382a2a1d,
952 0x382a2a1d,
953 0x382a2a1d,
954 0x382a2a1d,
955 0x382a2a1d,
956 0x392b2b1e,
957 0x392b2b1e,
958 0x392b2b1e,
959 0x392b2b1e,
960 0x3a2c2c1f,
961 0x3a2c2c1f,
962 0x3a2c2c1f,
963 0x3a2c2c1f,
964 0x3b2d2d28,
965 0x3b2d2d28,
966 0x3b2d2d28,
967 0x3b2d2d28,
968 0x3b2e2e29,
969 0x3b2e2e29,
970 0x3b2e2e29,
971 0x3b2e2e29,
972 0x3c2f2f29,
973 0x3c2f2f29,
974 0x3c2f2f29,
975 0x3c2f2f29,
976 0x3d38382a,
977 0x3d38382a,
978 0x3d38382a,
979 0x3d38382a,
980 0x3e38382b,
981 0x3e38382b,
982 0x3e38382b,
983 0x3e38382b,
984 0x3f38392b,
985 0x3f38392b,
986 0x3f38392b,
987 0x3f38392b,
988 0x3f38392b,
989 0x3f39392c,
990 0x3f39392c,
991 0x3f39392c,
992 0x3f39392c,
993 0x48393a2c,
994 0x48393a2c,
995 0x48393a2c,
996 0x48393a2c,
997 0x483a3a2d,
998 0x483a3a2d,
999 0x483a3a2d,
1000 0x493a3b2e,
1001 0x493a3b2e,
1002 0x493b3b2e,
1003 0x493b3b2e,
1004 0x493b3c2f,
1005 0x493b3c2f,
1006 0x493b3c2f,
1007 0x4a3c3c2f,
1008 0x4a3c3c2f,
1009 0x4a3c3d38,
1010 0x4a3c3d38,
1011 0x4b3d3d38,
1012 0x4b3d3d38,
1013 0x4b3d3e38,
1014 0x4b3d3e38,
1015 0x4b3e3e39,
1016 0x4c3e3e39,
1017 0x4c3e3e39,
1018 0x4c3f3f39,
1019 0x4c3f3f39,
1020 0x4d3f3f3a,
1021 0x4d3f3f3a,
1022 0x4d48483a,
1023 0x4d48483a,
1024 0x4d48483a,
1025 0x4d48483a,
1026 0x4e48483a,
1027 0x4e48483b,
1028 0x4e48483b,
1029 0x4f48493b,
1030 0x4f49493b,
1031 0x1a0c0907,
1032 0x1a0c0907,
1033 0x1a0c0907,
1034 0x1a0c0907,
1035 0x291b190e,
1036 0x291b190e,
1037 0x291b190e,
1038 0x291b190e,
1039 0x291b190e,
1040 0x2e281e1a,
1041 0x2e281e1a,
1042 0x2e281e1a,
1043 0x2e281e1a,
1044 0x392b291e,
1045 0x392b291e,
1046 0x392b291e,
1047 0x392b291e,
1048 0x392b291e,
1049 0x3c2e2b29,
1050 0x3c2e2b29,
1051 0x3c2e2b29,
1052 0x3c2e2b29,
1053 0x3c2e2b29,
1054 0x3c2e2b29,
1055 0x3c2e2b29,
1056 0x3c2e2b29,
1057 0x3e382e2a,
1058 0x3e382e2a,
1059 0x3e382e2a,
1060 0x3e382e2a,
1061 0x3e382e2a,
1062 0x483a382c,
1063 0x483a382c,
1064 0x483a382c,
1065 0x483a382c,
1066 0x493b392e,
1067 0x493b392e,
1068 0x493b392e,
1069 0x493b392e,
1070 0x4b3d3a38,
1071 0x4b3d3a38,
1072 0x4b3d3a38,
1073 0x4b3d3a38,
1074 0x4b3d3a38,
1075 0x4c3e3b38,
1076 0x4c3e3b38,
1077 0x4c3e3b38,
1078 0x4c3e3b38,
1079 0x4d483c39,
1080 0x4d483c39,
1081 0x4d483c39,
1082 0x4d483c39,
1083 0x4d483c39,
1084 0x4e483e3a,
1085 0x4e483e3a,
1086 0x4e483e3a,
1087 0x4e483e3a,
1088 0x4f493f3b,
1089 0x4f493f3b,
1090 0x4f493f3b,
1091 0x4f493f3b,
1092 0x584a483c,
1093 0x584a483c,
1094 0x584a483c,
1095 0x584a483c,
1096 0x594b483d,
1097 0x594b483d,
1098 0x594b483d,
1099 0x594b483d,
1100 0x594b493e,
1101 0x594b493e,
1102 0x594b493e,
1103 0x594b493e,
1104 0x5a4c493f,
1105 0x5a4c493f,
1106 0x5a4c493f,
1107 0x5a4c493f,
1108 0x5b4d4a48,
1109 0x5b4d4a48,
1110 0x5b4d4a48,
1111 0x5b4d4a48,
1112 0x5b4d4b48,
1113 0x5b4d4b48,
1114 0x5b4d4b48,
1115 0x5b4d4b48,
1116 0x5b4d4b48,
1117 0x5c4e4b48,
1118 0x5c4e4b48,
1119 0x5c4e4b48,
1120 0x5c4e4b48,
1121 0x5c4f4c49,
1122 0x5c4f4c49,
1123 0x5c4f4c49,
1124 0x5c4f4c49,
1125 0x5d584c49,
1126 0x5d584c49,
1127 0x5d584c49,
1128 0x5e584d4a,
1129 0x5e584d4a,
1130 0x5e584e4a,
1131 0x5e584e4a,
1132 0x5f594e4b,
1133 0x5f594e4b,
1134 0x5f594e4b,
1135 0x5f594f4b,
1136 0x5f594f4b,
1137 0x68594f4c,
1138 0x68594f4c,
1139 0x685a584c,
1140 0x685a584c,
1141 0x685a584c,
1142 0x685a584c,
1143 0x695b584d,
1144 0x695b594d,
1145 0x695b594d,
1146 0x695b594e,
1147 0x695b594e,
1148 0x6a5c594e,
1149 0x6a5c594e,
1150 0x6a5c594f,
1151 0x6a5c594f,
1152 0x6a5c5a4f,
1153 0x6a5c5a4f,
1154 0x6a5d5a58,
1155 0x6b5d5a58,
1156 0x6b5d5a58,
1157 0x6b5d5b58,
1158 0x6b5e5b58,
1159 };
1160
1161 static const unsigned short
1162 brc_skip_mv_threshold_vp8[256] = {
1163 111, 120, 129, 137, 146, 155, 163, 172, 180, 189, 198, 206, 215, 224, 232, 241,
1164 249, 258, 267, 275, 284, 293, 301, 310, 318, 327, 336, 344, 353, 362, 370, 379,
1165 387, 396, 405, 413, 422, 431, 439, 448, 456, 465, 474, 482, 491, 500, 508, 517,
1166 525, 534, 543, 551, 560, 569, 577, 586, 594, 603, 612, 620, 629, 638, 646, 655,
1167 663, 672, 681, 689, 698, 707, 715, 724, 733, 741, 750, 758, 767, 776, 784, 793,
1168 802, 810, 819, 827, 836, 845, 853, 862, 871, 879, 888, 896, 905, 914, 922, 931,
1169 940, 948, 957, 965, 974, 983, 991, 1000, 1009, 1017, 1026, 1034, 1043, 1052, 1060, 1069,
1170 1078, 1086, 1095, 1103, 1112, 1121, 1129, 1138, 1147, 1155, 1164, 1172, 1181, 1190, 1198, 1208
1171 };
1172
1173 void
i965_encoder_vp8_check_motion_estimation(VADriverContextP ctx,struct intel_encoder_context * encoder_context)1174 i965_encoder_vp8_check_motion_estimation(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1175 {
1176 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1177
1178 if (vp8_context->down_scaled_width_4x < vp8_context->min_scaled_dimension ||
1179 vp8_context->down_scaled_width_in_mb4x < vp8_context->min_scaled_dimension_in_mbs ||
1180 vp8_context->down_scaled_height_4x < vp8_context->min_scaled_dimension ||
1181 vp8_context->down_scaled_height_in_mb4x < vp8_context->min_scaled_dimension_in_mbs) {
1182
1183 vp8_context->hme_16x_supported = 0;
1184
1185 if (vp8_context->down_scaled_width_4x < vp8_context->min_scaled_dimension ||
1186 vp8_context->down_scaled_width_in_mb4x < vp8_context->min_scaled_dimension_in_mbs) {
1187
1188 vp8_context->down_scaled_width_4x = vp8_context->min_scaled_dimension;
1189 vp8_context->down_scaled_width_in_mb4x = vp8_context->min_scaled_dimension_in_mbs;
1190 }
1191
1192 if (vp8_context->down_scaled_height_4x < vp8_context->min_scaled_dimension ||
1193 vp8_context->down_scaled_height_in_mb4x < vp8_context->min_scaled_dimension_in_mbs) {
1194
1195 vp8_context->down_scaled_height_4x = vp8_context->min_scaled_dimension;
1196 vp8_context->down_scaled_height_in_mb4x = vp8_context->min_scaled_dimension_in_mbs;
1197 }
1198 } else if (vp8_context->down_scaled_width_16x < vp8_context->min_scaled_dimension ||
1199 vp8_context->down_scaled_width_in_mb16x < vp8_context->min_scaled_dimension_in_mbs ||
1200 vp8_context->down_scaled_height_16x < vp8_context->min_scaled_dimension ||
1201 vp8_context->down_scaled_height_in_mb16x < vp8_context->min_scaled_dimension_in_mbs) {
1202
1203 if (vp8_context->down_scaled_width_16x < vp8_context->min_scaled_dimension ||
1204 vp8_context->down_scaled_width_in_mb16x < vp8_context->min_scaled_dimension_in_mbs) {
1205
1206 vp8_context->down_scaled_width_16x = vp8_context->min_scaled_dimension;
1207 vp8_context->down_scaled_width_in_mb16x = vp8_context->min_scaled_dimension_in_mbs;
1208 }
1209
1210 if (vp8_context->down_scaled_height_16x < vp8_context->min_scaled_dimension ||
1211 vp8_context->down_scaled_height_in_mb16x < vp8_context->min_scaled_dimension_in_mbs) {
1212
1213 vp8_context->down_scaled_height_16x = vp8_context->min_scaled_dimension;
1214 vp8_context->down_scaled_height_in_mb16x = vp8_context->min_scaled_dimension_in_mbs;
1215 }
1216 }
1217 }
1218
1219 static void
i965_encoder_vp8_free_surfaces(void ** data)1220 i965_encoder_vp8_free_surfaces(void **data)
1221 {
1222 struct i965_encoder_vp8_surface *vp8_surface;
1223
1224 if (!data || !(*data))
1225 return;
1226
1227 vp8_surface = *data;
1228
1229 if (vp8_surface->scaled_4x_surface_obj) {
1230 i965_DestroySurfaces(vp8_surface->ctx, &vp8_surface->scaled_4x_surface_id, 1);
1231 vp8_surface->scaled_4x_surface_id = VA_INVALID_SURFACE;
1232 vp8_surface->scaled_4x_surface_obj = NULL;
1233 }
1234
1235 if (vp8_surface->scaled_16x_surface_obj) {
1236 i965_DestroySurfaces(vp8_surface->ctx, &vp8_surface->scaled_16x_surface_id, 1);
1237 vp8_surface->scaled_16x_surface_id = VA_INVALID_SURFACE;
1238 vp8_surface->scaled_16x_surface_obj = NULL;
1239 }
1240
1241 free(vp8_surface);
1242 }
1243
1244 static void
i965_encoder_vp8_allocate_surfaces(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct object_surface * obj_surface,int forced_free)1245 i965_encoder_vp8_allocate_surfaces(VADriverContextP ctx,
1246 struct intel_encoder_context *encoder_context,
1247 struct object_surface *obj_surface,
1248 int forced_free)
1249 {
1250 struct i965_driver_data *i965 = i965_driver_data(ctx);
1251 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1252 struct i965_encoder_vp8_surface *vp8_surface;
1253 int down_scaled_width_4x, down_scaled_height_4x;
1254 int down_scaled_width_16x, down_scaled_height_16x;
1255
1256 if (!obj_surface)
1257 return;
1258
1259 if (obj_surface->private_data && obj_surface->free_private_data) {
1260 if (forced_free && obj_surface->free_private_data != i965_encoder_vp8_free_surfaces)
1261 obj_surface->free_private_data(obj_surface->private_data);
1262 else
1263 return;
1264 }
1265
1266 vp8_surface = calloc(1, sizeof(struct i965_encoder_vp8_surface));
1267
1268 if (!vp8_surface) {
1269 obj_surface->private_data = NULL;
1270 obj_surface->free_private_data = NULL;
1271
1272 return;
1273 }
1274
1275 vp8_surface->ctx = ctx;
1276
1277 down_scaled_width_4x = vp8_context->down_scaled_width_4x;
1278 down_scaled_height_4x = vp8_context->down_scaled_height_4x;
1279 i965_CreateSurfaces(ctx,
1280 down_scaled_width_4x,
1281 down_scaled_height_4x,
1282 VA_RT_FORMAT_YUV420,
1283 1,
1284 &vp8_surface->scaled_4x_surface_id);
1285 vp8_surface->scaled_4x_surface_obj = SURFACE(vp8_surface->scaled_4x_surface_id);
1286
1287 if (vp8_surface->scaled_4x_surface_obj)
1288 i965_check_alloc_surface_bo(ctx, vp8_surface->scaled_4x_surface_obj, 1,
1289 VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
1290
1291 down_scaled_width_16x = vp8_context->down_scaled_width_16x;
1292 down_scaled_height_16x = vp8_context->down_scaled_height_16x;
1293 i965_CreateSurfaces(ctx,
1294 down_scaled_width_16x,
1295 down_scaled_height_16x,
1296 VA_RT_FORMAT_YUV420,
1297 1,
1298 &vp8_surface->scaled_16x_surface_id);
1299 vp8_surface->scaled_16x_surface_obj = SURFACE(vp8_surface->scaled_16x_surface_id);
1300
1301 if (vp8_surface->scaled_16x_surface_obj)
1302 i965_check_alloc_surface_bo(ctx, vp8_surface->scaled_16x_surface_obj, 1,
1303 VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
1304
1305 obj_surface->private_data = vp8_surface;
1306 obj_surface->free_private_data = i965_encoder_vp8_free_surfaces;
1307 }
1308
1309 static void
i965_encoder_vp8_read_encode_status(VADriverContextP ctx,struct intel_encoder_context * encoder_context)1310 i965_encoder_vp8_read_encode_status(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1311 {
1312 struct intel_batchbuffer *batch = encoder_context->base.batch;
1313 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
1314 struct i965_encoder_vp8_encode_status_buffer *encode_status_buffer = &vp8_context->encode_status_buffer;
1315 struct i965_gpe_table *gpe = vp8_context->gpe_table;
1316 struct gpe_mi_store_register_mem_parameter mi_store_register_mem_param;
1317 struct gpe_mi_flush_dw_parameter mi_flush_dw_param;
1318 unsigned int base_offset;
1319
1320 base_offset = encode_status_buffer->base_offset;
1321
1322 memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
1323 gpe->mi_flush_dw(ctx, batch, &mi_flush_dw_param);
1324
1325 memset(&mi_store_register_mem_param, 0, sizeof(mi_store_register_mem_param));
1326 mi_store_register_mem_param.bo = encode_status_buffer->bo;
1327 mi_store_register_mem_param.offset = base_offset + encode_status_buffer->bitstream_byte_count_offset;
1328 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFC_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET;
1329 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1330
1331 mi_store_register_mem_param.offset = base_offset + encode_status_buffer->image_status_mask_offset;
1332 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFC_IMAGE_STATUS_MASK_REG_OFFSET;
1333 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1334
1335 mi_store_register_mem_param.offset = base_offset + encode_status_buffer->image_status_ctrl_offset;
1336 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFC_IMAGE_STATUS_CTRL_REG_OFFSET;
1337 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1338
1339 memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
1340 gpe->mi_flush_dw(ctx, batch, &mi_flush_dw_param);
1341 }
1342
1343 static void
i965_encoder_vp8_read_pak_statistics(VADriverContextP ctx,struct intel_encoder_context * encoder_context,int ipass)1344 i965_encoder_vp8_read_pak_statistics(VADriverContextP ctx,
1345 struct intel_encoder_context *encoder_context,
1346 int ipass)
1347 {
1348 struct intel_batchbuffer *batch = encoder_context->base.batch;
1349 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
1350 struct i965_gpe_table *gpe = vp8_context->gpe_table;
1351 struct gpe_mi_store_data_imm_parameter mi_store_data_imm_param;
1352 struct gpe_mi_store_register_mem_parameter mi_store_register_mem_param;
1353 struct gpe_mi_flush_dw_parameter mi_flush_dw_param;
1354
1355 memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
1356 gpe->mi_flush_dw(ctx, batch, &mi_flush_dw_param);
1357
1358 if (ipass < vp8_context->num_brc_pak_passes) {
1359 memset(&mi_store_data_imm_param, 0, sizeof(mi_store_data_imm_param));
1360 mi_store_data_imm_param.bo = vp8_context->brc_pak_statistics_buffer.bo;
1361 mi_store_data_imm_param.offset = sizeof(unsigned int) * 2;
1362 mi_store_data_imm_param.dw0 = (ipass + 1) << 8;
1363 gpe->mi_store_data_imm(ctx, batch, &mi_store_data_imm_param);
1364 }
1365
1366 memset(&mi_store_register_mem_param, 0, sizeof(mi_store_register_mem_param));
1367 mi_store_register_mem_param.bo = vp8_context->brc_pak_statistics_buffer.bo;
1368 mi_store_register_mem_param.offset = 0;
1369 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFC_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET;
1370 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1371
1372 mi_store_register_mem_param.offset = sizeof(unsigned int) * 5;
1373 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_DQ_INDEX_REG_OFFSET;
1374 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1375
1376 mi_store_register_mem_param.offset = sizeof(unsigned int) * 6;
1377 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_D_LOOP_FILTER_REG_OFFSET;
1378 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1379
1380 if (ipass == 0) {
1381 mi_store_register_mem_param.offset = sizeof(unsigned int) * 4;
1382 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET;
1383 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1384 }
1385
1386 mi_store_register_mem_param.offset = sizeof(unsigned int) * 9;
1387 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET;
1388 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1389
1390 mi_store_register_mem_param.offset = sizeof(unsigned int) * 10;
1391 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX23_REG_OFFSET;
1392 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1393
1394 mi_store_register_mem_param.offset = sizeof(unsigned int) * 11;
1395 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_D_LOOP_FILTER01_REG_OFFSET;
1396 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1397
1398 mi_store_register_mem_param.offset = sizeof(unsigned int) * 12;
1399 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_D_LOOP_FILTER23_REG_OFFSET;
1400 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1401
1402 mi_store_register_mem_param.offset = sizeof(unsigned int) * 13;
1403 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CONVERGENCE_STATUS_REG_OFFSET;
1404 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1405 }
1406
1407 static void
i965_encoder_vp8_gpe_context_init_once(VADriverContextP ctx,struct i965_gpe_context * gpe_context,struct vp8_encoder_kernel_parameters * kernel_params,unsigned int idrt_entry_size)1408 i965_encoder_vp8_gpe_context_init_once(VADriverContextP ctx,
1409 struct i965_gpe_context *gpe_context,
1410 struct vp8_encoder_kernel_parameters *kernel_params,
1411 unsigned int idrt_entry_size)
1412 {
1413 struct i965_driver_data *i965 = i965_driver_data(ctx);
1414
1415 gpe_context->curbe.length = kernel_params->curbe_size; // in bytes
1416
1417 gpe_context->sampler.entry_size = 0;
1418 gpe_context->sampler.max_entries = 0;
1419
1420 gpe_context->idrt.entry_size = idrt_entry_size;
1421 gpe_context->idrt.max_entries = NUM_KERNELS_PER_GPE_CONTEXT;
1422
1423 gpe_context->surface_state_binding_table.max_entries = MAX_VP8_ENCODER_SURFACES;
1424 gpe_context->surface_state_binding_table.binding_table_offset = 0;
1425 gpe_context->surface_state_binding_table.surface_state_offset = gpe_context->surface_state_binding_table.binding_table_offset +
1426 ALIGN(MAX_VP8_ENCODER_SURFACES * 4, 64);
1427 gpe_context->surface_state_binding_table.length = ALIGN(MAX_VP8_ENCODER_SURFACES * 4, 64) + ALIGN(MAX_VP8_ENCODER_SURFACES * SURFACE_STATE_PADDED_SIZE_GEN8, 64);
1428
1429 if (i965->intel.eu_total > 0)
1430 gpe_context->vfe_state.max_num_threads = 6 * i965->intel.eu_total;
1431 else
1432 gpe_context->vfe_state.max_num_threads = 112;
1433
1434 gpe_context->vfe_state.curbe_allocation_size = ALIGN(gpe_context->curbe.length, 32) >> 5; // in registers
1435 gpe_context->vfe_state.urb_entry_size = MAX(1, (ALIGN(kernel_params->inline_data_size, 32) +
1436 ALIGN(kernel_params->external_data_size, 32)) >> 5); // in registers
1437 gpe_context->vfe_state.num_urb_entries = (MAX_URB_SIZE -
1438 gpe_context->vfe_state.curbe_allocation_size -
1439 ((gpe_context->idrt.entry_size >> 5) *
1440 gpe_context->idrt.max_entries)) / gpe_context->vfe_state.urb_entry_size;
1441 gpe_context->vfe_state.num_urb_entries = CLAMP(gpe_context->vfe_state.num_urb_entries, 1, 64);
1442 gpe_context->vfe_state.gpgpu_mode = 0;
1443 }
1444
1445 static void
i965_encoder_vp8_gpe_context_vfe_scoreboard_init(struct i965_gpe_context * gpe_context,struct vp8_encoder_scoreboard_parameters * scoreboard_params)1446 i965_encoder_vp8_gpe_context_vfe_scoreboard_init(struct i965_gpe_context *gpe_context, struct vp8_encoder_scoreboard_parameters *scoreboard_params)
1447 {
1448 gpe_context->vfe_desc5.scoreboard0.mask = scoreboard_params->mask;
1449 gpe_context->vfe_desc5.scoreboard0.type = scoreboard_params->type;
1450 gpe_context->vfe_desc5.scoreboard0.enable = scoreboard_params->enable;
1451
1452 // Scoreboard 0
1453 gpe_context->vfe_desc6.scoreboard1.delta_x0 = -1;
1454 gpe_context->vfe_desc6.scoreboard1.delta_y0 = 0;
1455
1456 // Scoreboard 1
1457 gpe_context->vfe_desc6.scoreboard1.delta_x1 = 0;
1458 gpe_context->vfe_desc6.scoreboard1.delta_y1 = -1;
1459
1460 // Scoreboard 2
1461 gpe_context->vfe_desc6.scoreboard1.delta_x2 = 1;
1462 gpe_context->vfe_desc6.scoreboard1.delta_y2 = -1;
1463
1464 // Scoreboard 3
1465 gpe_context->vfe_desc6.scoreboard1.delta_x3 = -1;
1466 gpe_context->vfe_desc6.scoreboard1.delta_y3 = -1;
1467
1468 // Scoreboard 4
1469 gpe_context->vfe_desc7.scoreboard2.delta_x4 = -1;
1470 gpe_context->vfe_desc7.scoreboard2.delta_y4 = 1;
1471
1472 // Scoreboard 5
1473 gpe_context->vfe_desc7.scoreboard2.delta_x5 = 0;
1474 gpe_context->vfe_desc7.scoreboard2.delta_y5 = -2;
1475 // Scoreboard 6
1476 gpe_context->vfe_desc7.scoreboard2.delta_x6 = 1;
1477 gpe_context->vfe_desc7.scoreboard2.delta_y6 = -2;
1478 // Scoreboard 7
1479 gpe_context->vfe_desc7.scoreboard2.delta_x6 = -1;
1480 gpe_context->vfe_desc7.scoreboard2.delta_y6 = -2;
1481 }
1482
1483 static void
i965_add_dri_buffer_gpe_surface(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,dri_bo * bo,int is_raw_buffer,unsigned int size,unsigned int offset,int index)1484 i965_add_dri_buffer_gpe_surface(VADriverContextP ctx,
1485 struct intel_encoder_context *encoder_context,
1486 struct i965_gpe_context *gpe_context,
1487 dri_bo *bo,
1488 int is_raw_buffer,
1489 unsigned int size,
1490 unsigned int offset,
1491 int index)
1492 {
1493 struct i965_gpe_resource gpe_resource;
1494
1495 i965_dri_object_to_buffer_gpe_resource(&gpe_resource, bo);
1496 i965_add_buffer_gpe_surface(ctx,
1497 gpe_context,
1498 &gpe_resource,
1499 is_raw_buffer,
1500 size,
1501 offset,
1502 index);
1503
1504 i965_free_gpe_resource(&gpe_resource);
1505 }
1506
1507 static void
i965_add_dri_buffer_2d_gpe_surface(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,dri_bo * bo,unsigned int width,unsigned int height,unsigned int pitch,int is_media_block_rw,unsigned int format,int index)1508 i965_add_dri_buffer_2d_gpe_surface(VADriverContextP ctx,
1509 struct intel_encoder_context *encoder_context,
1510 struct i965_gpe_context *gpe_context,
1511 dri_bo *bo,
1512 unsigned int width,
1513 unsigned int height,
1514 unsigned int pitch,
1515 int is_media_block_rw,
1516 unsigned int format,
1517 int index)
1518 {
1519 struct i965_gpe_resource gpe_resource;
1520
1521 i965_dri_object_to_2d_gpe_resource(&gpe_resource, bo, width, height, pitch);
1522 i965_add_buffer_2d_gpe_surface(ctx,
1523 gpe_context,
1524 &gpe_resource,
1525 is_media_block_rw,
1526 format,
1527 index);
1528
1529 i965_free_gpe_resource(&gpe_resource);
1530 }
1531
1532 static void
i965_run_kernel_media_object(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,int media_function,struct gpe_media_object_parameter * param)1533 i965_run_kernel_media_object(VADriverContextP ctx,
1534 struct intel_encoder_context *encoder_context,
1535 struct i965_gpe_context *gpe_context,
1536 int media_function,
1537 struct gpe_media_object_parameter *param)
1538 {
1539 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1540 struct i965_gpe_table *gpe = vp8_context->gpe_table;
1541 struct intel_batchbuffer *batch = encoder_context->base.batch;
1542
1543 intel_batchbuffer_start_atomic(batch, 0x1000);
1544
1545 intel_batchbuffer_emit_mi_flush(batch);
1546 gpe->pipeline_setup(ctx, gpe_context, batch);
1547 gpe->media_object(ctx, gpe_context, batch, param);
1548 gpe->media_state_flush(ctx, gpe_context, batch);
1549 gpe->pipeline_end(ctx, gpe_context, batch);
1550
1551 intel_batchbuffer_end_atomic(batch);
1552
1553 intel_batchbuffer_flush(batch);
1554 }
1555
1556 static void
i965_init_media_object_walker_parameters(struct intel_encoder_context * encoder_context,struct vp8_encoder_kernel_walker_parameter * kernel_walker_param,struct gpe_media_object_walker_parameter * walker_param)1557 i965_init_media_object_walker_parameters(struct intel_encoder_context *encoder_context,
1558 struct vp8_encoder_kernel_walker_parameter *kernel_walker_param,
1559 struct gpe_media_object_walker_parameter *walker_param)
1560 {
1561 memset(walker_param, 0, sizeof(*walker_param));
1562
1563 walker_param->use_scoreboard = kernel_walker_param->use_scoreboard;
1564
1565 walker_param->block_resolution.x = kernel_walker_param->resolution_x;
1566 walker_param->block_resolution.y = kernel_walker_param->resolution_y;
1567
1568 walker_param->global_resolution.x = kernel_walker_param->resolution_x;
1569 walker_param->global_resolution.y = kernel_walker_param->resolution_y;
1570
1571 walker_param->global_outer_loop_stride.x = kernel_walker_param->resolution_x;
1572 walker_param->global_outer_loop_stride.y = 0;
1573
1574 walker_param->global_inner_loop_unit.x = 0;
1575 walker_param->global_inner_loop_unit.y = kernel_walker_param->resolution_y;
1576
1577 walker_param->local_loop_exec_count = 0xFFFF; //MAX VALUE
1578 walker_param->global_loop_exec_count = 0xFFFF; //MAX VALUE
1579
1580 if (kernel_walker_param->no_dependency) {
1581 walker_param->scoreboard_mask = 0;
1582
1583 // Raster scan walking pattern
1584 walker_param->local_outer_loop_stride.x = 0;
1585 walker_param->local_outer_loop_stride.y = 1;
1586 walker_param->local_inner_loop_unit.x = 1;
1587 walker_param->local_inner_loop_unit.y = 0;
1588 walker_param->local_end.x = kernel_walker_param->resolution_x - 1;
1589 walker_param->local_end.y = 0;
1590 } else {
1591 walker_param->local_end.x = 0;
1592 walker_param->local_end.y = 0;
1593
1594 if (kernel_walker_param->walker_degree == VP8_ENCODER_46_DEGREE) {
1595 // 46 degree
1596 walker_param->scoreboard_mask = kernel_walker_param->scoreboard_mask;
1597 walker_param->local_outer_loop_stride.x = 1;
1598 walker_param->local_outer_loop_stride.y = 0;
1599 walker_param->local_inner_loop_unit.x = -1;
1600 walker_param->local_inner_loop_unit.y = 1;
1601 } else if (kernel_walker_param->walker_degree == VP8_ENCODER_45Z_DEGREE) {
1602 // 45z degree
1603 walker_param->scoreboard_mask = 0x0F;
1604
1605 walker_param->global_loop_exec_count = 0x3FF;
1606 walker_param->local_loop_exec_count = 0x3FF;
1607
1608 walker_param->global_resolution.x = (unsigned int)(kernel_walker_param->resolution_x / 2.f) + 1;
1609 walker_param->global_resolution.y = 2 * kernel_walker_param->resolution_y;
1610
1611 walker_param->global_start.x = 0;
1612 walker_param->global_start.y = 0;
1613
1614 walker_param->global_outer_loop_stride.x = walker_param->global_resolution.x;
1615 walker_param->global_outer_loop_stride.y = 0;
1616
1617 walker_param->global_inner_loop_unit.x = 0;
1618 walker_param->global_inner_loop_unit.y = walker_param->global_resolution.y;
1619
1620 walker_param->block_resolution.x = walker_param->global_resolution.x;
1621 walker_param->block_resolution.y = walker_param->global_resolution.y;
1622
1623 walker_param->local_start.x = 0;
1624 walker_param->local_start.y = 0;
1625
1626 walker_param->local_outer_loop_stride.x = 1;
1627 walker_param->local_outer_loop_stride.y = 0;
1628
1629 walker_param->local_inner_loop_unit.x = -1;
1630 walker_param->local_inner_loop_unit.y = 4;
1631
1632 walker_param->middle_loop_extra_steps = 3;
1633 walker_param->mid_loop_unit_x = 0;
1634 walker_param->mid_loop_unit_y = 1;
1635 } else if (kernel_walker_param->walker_degree == VP8_ENCODER_45_DEGREE) {
1636 // 45 degree
1637 walker_param->scoreboard_mask = 0x03;
1638 walker_param->local_outer_loop_stride.x = 1;
1639 walker_param->local_outer_loop_stride.y = 0;
1640 walker_param->local_inner_loop_unit.x = -1;
1641 walker_param->local_inner_loop_unit.y = 1;
1642 } else {
1643 // 26 degree
1644 walker_param->scoreboard_mask = 0x0F;
1645 walker_param->local_outer_loop_stride.x = 1;
1646 walker_param->local_outer_loop_stride.y = 0;
1647 walker_param->local_inner_loop_unit.x = -2;
1648 walker_param->local_inner_loop_unit.y = 1;
1649 }
1650 }
1651 }
1652
1653 static void
i965_run_kernel_media_object_walker(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,int media_function,struct gpe_media_object_walker_parameter * param)1654 i965_run_kernel_media_object_walker(VADriverContextP ctx,
1655 struct intel_encoder_context *encoder_context,
1656 struct i965_gpe_context *gpe_context,
1657 int media_function,
1658 struct gpe_media_object_walker_parameter *param)
1659 {
1660 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1661 struct i965_gpe_table *gpe = vp8_context->gpe_table;
1662 struct intel_batchbuffer *batch = encoder_context->base.batch;
1663
1664 intel_batchbuffer_start_atomic(batch, 0x1000);
1665
1666 intel_batchbuffer_emit_mi_flush(batch);
1667 gpe->pipeline_setup(ctx, gpe_context, batch);
1668 gpe->media_object_walker(ctx, gpe_context, batch, param);
1669 gpe->media_state_flush(ctx, gpe_context, batch);
1670 gpe->pipeline_end(ctx, gpe_context, batch);
1671
1672 intel_batchbuffer_end_atomic(batch);
1673
1674 intel_batchbuffer_flush(batch);
1675 }
1676
1677 static void
i965_encoder_vp8_vme_init_mpu_tpu_buffer(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_encoder_vp8_context * vp8_context)1678 i965_encoder_vp8_vme_init_mpu_tpu_buffer(VADriverContextP ctx,
1679 struct intel_encoder_context *encoder_context,
1680 struct i965_encoder_vp8_context *vp8_context)
1681 {
1682 char *pbuffer = NULL;
1683
1684 i965_zero_gpe_resource(&vp8_context->pak_mpu_tpu_mode_probs_buffer);
1685 i965_zero_gpe_resource(&vp8_context->pak_mpu_tpu_ref_mode_probs_buffer);
1686
1687 pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer);
1688
1689 if (!pbuffer)
1690 return;
1691
1692 memcpy(pbuffer, vp8_default_coef_probs, sizeof(vp8_default_coef_probs));
1693 i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer);
1694
1695 pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_entropy_cost_table_buffer);
1696
1697 if (!pbuffer)
1698 return;
1699
1700 memcpy(pbuffer, vp8_prob_cost, sizeof(vp8_prob_cost));
1701 i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_entropy_cost_table_buffer);
1702
1703 pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_pak_token_update_flags_buffer);
1704
1705 if (!pbuffer)
1706 return;
1707
1708 memcpy(pbuffer, vp8_probs_update_flag, sizeof(vp8_probs_update_flag));
1709 i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_pak_token_update_flags_buffer);
1710
1711 pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_default_token_probability_buffer);
1712
1713 if (!pbuffer)
1714 return;
1715
1716 memcpy(pbuffer, vp8_coef_update_probs, sizeof(vp8_coef_update_probs));
1717 i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_default_token_probability_buffer);
1718
1719 pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer);
1720
1721 if (!pbuffer)
1722 return;
1723
1724 memcpy(pbuffer, vp8_default_coef_probs, sizeof(vp8_default_coef_probs));
1725 i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer);
1726
1727 pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_updated_token_probability_buffer);
1728
1729 if (!pbuffer)
1730 return;
1731
1732 memcpy(pbuffer, vp8_default_coef_probs, sizeof(vp8_default_coef_probs));
1733 i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_updated_token_probability_buffer);
1734 }
1735
1736 #define ALLOC_VP8_RESOURCE_BUFFER(buffer, bufsize, des) \
1737 do { \
1738 vp8_context->buffer.type = I965_GPE_RESOURCE_BUFFER; \
1739 vp8_context->buffer.width = (bufsize); \
1740 vp8_context->buffer.height = 1; \
1741 vp8_context->buffer.pitch = vp8_context->buffer.width; \
1742 vp8_context->buffer.size = vp8_context->buffer.pitch * \
1743 vp8_context->buffer.height; \
1744 vp8_context->buffer.tiling = I915_TILING_NONE; \
1745 i965_allocate_gpe_resource(i965->intel.bufmgr, \
1746 &vp8_context->buffer, \
1747 vp8_context->buffer.size, \
1748 (des)); \
1749 } while (0)
1750
1751 static void
i965_encoder_vp8_vme_allocate_resources(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_encoder_vp8_context * vp8_context)1752 i965_encoder_vp8_vme_allocate_resources(VADriverContextP ctx,
1753 struct intel_encoder_context *encoder_context,
1754 struct i965_encoder_vp8_context *vp8_context)
1755 {
1756 struct i965_driver_data *i965 = i965_driver_data(ctx);
1757 unsigned int frame_size_in_mbs = vp8_context->frame_width_in_mbs *
1758 vp8_context->frame_height_in_mbs;
1759
1760 vp8_context->mv_offset = ALIGN((frame_size_in_mbs * 16 * 4), 4096);
1761 vp8_context->mb_coded_buffer_size = vp8_context->mv_offset + (frame_size_in_mbs * 16 * sizeof(unsigned int));
1762
1763 ALLOC_VP8_RESOURCE_BUFFER(reference_frame_mb_count_buffer, 32, "Reference frame mb count buffer");
1764
1765 vp8_context->mb_mode_cost_luma_buffer.type = I965_GPE_RESOURCE_2D;
1766 vp8_context->mb_mode_cost_luma_buffer.width = ALIGN((sizeof(short) * 10), 64);
1767 vp8_context->mb_mode_cost_luma_buffer.height = 1;
1768 vp8_context->mb_mode_cost_luma_buffer.pitch = vp8_context->mb_mode_cost_luma_buffer.width;
1769 vp8_context->mb_mode_cost_luma_buffer.size = vp8_context->mb_mode_cost_luma_buffer.pitch *
1770 vp8_context->mb_mode_cost_luma_buffer.height;
1771 vp8_context->mb_mode_cost_luma_buffer.tiling = I915_TILING_NONE;
1772 i965_allocate_gpe_resource(i965->intel.bufmgr,
1773 &vp8_context->mb_mode_cost_luma_buffer,
1774 vp8_context->mb_mode_cost_luma_buffer.size,
1775 "MB mode cost luma buffer");
1776
1777 vp8_context->block_mode_cost_buffer.type = I965_GPE_RESOURCE_2D;
1778 vp8_context->block_mode_cost_buffer.width = ALIGN((sizeof(short) * 10 * 10 * 10), 64);
1779 vp8_context->block_mode_cost_buffer.height = 1;
1780 vp8_context->block_mode_cost_buffer.pitch = vp8_context->block_mode_cost_buffer.width;
1781 vp8_context->block_mode_cost_buffer.size = vp8_context->block_mode_cost_buffer.pitch *
1782 vp8_context->block_mode_cost_buffer.height;
1783 vp8_context->block_mode_cost_buffer.tiling = I915_TILING_NONE;
1784 i965_allocate_gpe_resource(i965->intel.bufmgr,
1785 &vp8_context->block_mode_cost_buffer,
1786 vp8_context->block_mode_cost_buffer.size,
1787 "Block mode cost luma buffer");
1788
1789 ALLOC_VP8_RESOURCE_BUFFER(chroma_recon_buffer, frame_size_in_mbs * 64, "Chroma recon buffer");
1790
1791 vp8_context->per_mb_quant_data_buffer.type = I965_GPE_RESOURCE_2D;
1792 vp8_context->per_mb_quant_data_buffer.width = ALIGN((vp8_context->frame_width_in_mbs * 4), 64);
1793 vp8_context->per_mb_quant_data_buffer.height = vp8_context->frame_height_in_mbs;
1794 vp8_context->per_mb_quant_data_buffer.pitch = vp8_context->per_mb_quant_data_buffer.width;
1795 vp8_context->per_mb_quant_data_buffer.size = vp8_context->per_mb_quant_data_buffer.pitch *
1796 vp8_context->per_mb_quant_data_buffer.height;
1797 vp8_context->per_mb_quant_data_buffer.tiling = I915_TILING_NONE;
1798 i965_allocate_gpe_resource(i965->intel.bufmgr,
1799 &vp8_context->per_mb_quant_data_buffer,
1800 vp8_context->per_mb_quant_data_buffer.size,
1801 "Per MB quant data buffer");
1802
1803 ALLOC_VP8_RESOURCE_BUFFER(pred_mv_data_buffer, frame_size_in_mbs * 4 * sizeof(unsigned int), "Pred mv data buffer");
1804 ALLOC_VP8_RESOURCE_BUFFER(mode_cost_update_buffer, 16 * sizeof(unsigned int), "Mode cost update buffer");
1805
1806 /*
1807 * BRC buffers
1808 */
1809 ALLOC_VP8_RESOURCE_BUFFER(brc_history_buffer, VP8_BRC_HISTORY_BUFFER_SIZE, "BRC history buffer");
1810 i965_zero_gpe_resource(&vp8_context->brc_history_buffer);
1811
1812 vp8_context->brc_segment_map_buffer.type = I965_GPE_RESOURCE_2D;
1813 vp8_context->brc_segment_map_buffer.width = vp8_context->frame_width_in_mbs;
1814 vp8_context->brc_segment_map_buffer.height = vp8_context->frame_height_in_mbs;
1815 vp8_context->brc_segment_map_buffer.pitch = vp8_context->brc_segment_map_buffer.width;
1816 vp8_context->brc_segment_map_buffer.size = vp8_context->brc_segment_map_buffer.pitch *
1817 vp8_context->brc_segment_map_buffer.height;
1818 vp8_context->brc_segment_map_buffer.tiling = I915_TILING_NONE;
1819 i965_allocate_gpe_resource(i965->intel.bufmgr,
1820 &vp8_context->brc_segment_map_buffer,
1821 vp8_context->brc_segment_map_buffer.size,
1822 "BRC segment map buffer");
1823
1824 vp8_context->brc_distortion_buffer.type = I965_GPE_RESOURCE_2D;
1825 vp8_context->brc_distortion_buffer.width = ALIGN((vp8_context->down_scaled_width_in_mb4x * 8), 64);
1826 vp8_context->brc_distortion_buffer.height = 2 * ALIGN((vp8_context->down_scaled_height_in_mb4x * 4), 8);
1827 vp8_context->brc_distortion_buffer.pitch = vp8_context->brc_distortion_buffer.width;
1828 vp8_context->brc_distortion_buffer.size = vp8_context->brc_distortion_buffer.pitch *
1829 vp8_context->brc_distortion_buffer.height;
1830 vp8_context->brc_distortion_buffer.tiling = I915_TILING_NONE;
1831 i965_allocate_gpe_resource(i965->intel.bufmgr,
1832 &vp8_context->brc_distortion_buffer,
1833 vp8_context->brc_distortion_buffer.size,
1834 "BRC distortion buffer");
1835 i965_zero_gpe_resource(&vp8_context->brc_distortion_buffer);
1836
1837 ALLOC_VP8_RESOURCE_BUFFER(brc_pak_statistics_buffer, sizeof(struct vp8_brc_pak_statistics), "BRC pak statistics buffer");
1838 i965_zero_gpe_resource(&vp8_context->brc_pak_statistics_buffer);
1839
1840 ALLOC_VP8_RESOURCE_BUFFER(brc_vp8_cfg_command_read_buffer, VP8_BRC_IMG_STATE_SIZE_PER_PASS * VP8_BRC_MAXIMUM_NUM_PASSES, "BRC VP8 configuration command read buffer");
1841 i965_zero_gpe_resource(&vp8_context->brc_vp8_cfg_command_read_buffer);
1842
1843 ALLOC_VP8_RESOURCE_BUFFER(brc_vp8_cfg_command_write_buffer, VP8_BRC_IMG_STATE_SIZE_PER_PASS * VP8_BRC_MAXIMUM_NUM_PASSES, "BRC VP8 configuration command write buffer");
1844 i965_zero_gpe_resource(&vp8_context->brc_vp8_cfg_command_write_buffer);
1845
1846 ALLOC_VP8_RESOURCE_BUFFER(brc_vp8_constant_data_buffer, VP8_BRC_CONSTANT_DATA_SIZE, "BRC VP8 constant data buffer");
1847 i965_zero_gpe_resource(&vp8_context->brc_vp8_constant_data_buffer);
1848
1849 ALLOC_VP8_RESOURCE_BUFFER(brc_pak_statistics_dump_buffer, vp8_context->num_brc_pak_passes * sizeof(unsigned int) * 12, "BRC pak statistics buffer");
1850 i965_zero_gpe_resource(&vp8_context->brc_pak_statistics_dump_buffer);
1851
1852 vp8_context->me_4x_mv_data_buffer.type = I965_GPE_RESOURCE_2D;
1853 vp8_context->me_4x_mv_data_buffer.width = vp8_context->down_scaled_width_in_mb4x * 32;
1854 vp8_context->me_4x_mv_data_buffer.height = vp8_context->down_scaled_height_in_mb4x * 4 * 4;
1855 vp8_context->me_4x_mv_data_buffer.pitch = ALIGN(vp8_context->me_4x_mv_data_buffer.width, 64);
1856 vp8_context->me_4x_mv_data_buffer.size = vp8_context->me_4x_mv_data_buffer.pitch *
1857 vp8_context->me_4x_mv_data_buffer.height;
1858 vp8_context->me_4x_mv_data_buffer.tiling = I915_TILING_NONE;
1859 i965_allocate_gpe_resource(i965->intel.bufmgr,
1860 &vp8_context->me_4x_mv_data_buffer,
1861 vp8_context->me_4x_mv_data_buffer.size,
1862 "ME 4x MV Data buffer");
1863
1864 vp8_context->me_4x_distortion_buffer.type = I965_GPE_RESOURCE_2D;
1865 vp8_context->me_4x_distortion_buffer.width = vp8_context->down_scaled_width_in_mb4x * 8;
1866 vp8_context->me_4x_distortion_buffer.height = vp8_context->down_scaled_height_in_mb4x * 4 * 4;
1867 vp8_context->me_4x_distortion_buffer.pitch = ALIGN(vp8_context->me_4x_distortion_buffer.width, 64);
1868 vp8_context->me_4x_distortion_buffer.size = vp8_context->me_4x_distortion_buffer.pitch *
1869 vp8_context->me_4x_distortion_buffer.height;
1870 vp8_context->me_4x_distortion_buffer.tiling = I915_TILING_NONE;
1871 i965_allocate_gpe_resource(i965->intel.bufmgr,
1872 &vp8_context->me_4x_distortion_buffer,
1873 vp8_context->me_4x_distortion_buffer.size,
1874 "ME 4x Distortion buffer");
1875
1876 vp8_context->me_16x_mv_data_buffer.type = I965_GPE_RESOURCE_2D;
1877 vp8_context->me_16x_mv_data_buffer.width = ALIGN((vp8_context->down_scaled_width_in_mb16x * 32), 64);
1878 vp8_context->me_16x_mv_data_buffer.height = vp8_context->down_scaled_height_in_mb16x * 4 * VP8_ME_MV_DATA_SIZE_MULTIPLIER;
1879 vp8_context->me_16x_mv_data_buffer.pitch = vp8_context->me_16x_mv_data_buffer.width;
1880 vp8_context->me_16x_mv_data_buffer.size = vp8_context->me_16x_mv_data_buffer.pitch *
1881 vp8_context->me_16x_mv_data_buffer.height;
1882 vp8_context->me_16x_mv_data_buffer.tiling = I915_TILING_NONE;
1883 i965_allocate_gpe_resource(i965->intel.bufmgr,
1884 &vp8_context->me_16x_mv_data_buffer,
1885 vp8_context->me_16x_mv_data_buffer.size,
1886 "ME 16x MV Data buffer");
1887
1888 ALLOC_VP8_RESOURCE_BUFFER(histogram_buffer, VP8_HISTOGRAM_SIZE, "Histogram buffer");
1889 ALLOC_VP8_RESOURCE_BUFFER(pak_intra_row_store_scratch_buffer, vp8_context->frame_width_in_mbs * 64, "Intra row store scratch buffer");
1890 ALLOC_VP8_RESOURCE_BUFFER(pak_deblocking_filter_row_store_scratch_buffer, vp8_context->frame_width_in_mbs * 4 * 64, "Deblocking filter row store scratch buffer");
1891 ALLOC_VP8_RESOURCE_BUFFER(pak_mpc_row_store_scratch_buffer, vp8_context->frame_width_in_mbs * 2 * 64, "MPC row store scratch buffer");
1892 ALLOC_VP8_RESOURCE_BUFFER(pak_stream_out_buffer, frame_size_in_mbs * 16, "stream out buffer");
1893 ALLOC_VP8_RESOURCE_BUFFER(pak_frame_header_buffer, VP8_FRAME_HEADER_SIZE, "Frame header buffer");
1894 ALLOC_VP8_RESOURCE_BUFFER(pak_intermediate_buffer, frame_size_in_mbs * 256 * 2 + frame_size_in_mbs * 64 + VP8_INTERMEDIATE_PARTITION0_SIZE, "Intermediate buffer");
1895 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_mode_probs_buffer, VP8_MODE_PROPABILITIES_SIZE, "Mode probs buffer");
1896 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_ref_mode_probs_buffer, VP8_MODE_PROPABILITIES_SIZE, "Ref mode probs buffer");
1897 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_coeff_probs_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Coeff probs buffer");
1898 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_ref_coeff_probs_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Ref coeff probs buffer");
1899 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_token_bits_data_buffer, VP8_TOKEN_BITS_DATA_SIZE, "Token bits data buffer");
1900 i965_zero_gpe_resource(&vp8_context->pak_mpu_tpu_token_bits_data_buffer);
1901 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_picture_state_buffer, VP8_PICTURE_STATE_SIZE, "Picture state buffer");
1902 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_mpu_bitstream_buffer, VP8_MPU_BITSTREAM_SIZE, "Mpu bitstream buffer");
1903 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_tpu_bitstream_buffer, VP8_TPU_BITSTREAM_SIZE, "Tpu bitstream buffer");
1904 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_entropy_cost_table_buffer, VP8_ENTROPY_COST_TABLE_SIZE, "Entropy cost buffer");
1905 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_pak_token_statistics_buffer, VP8_TOKEN_STATISTICS_SIZE, "Pak token statistics buffer");
1906 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_pak_token_update_flags_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Pak token update flags buffer");
1907 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_default_token_probability_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Default token probability buffer");
1908 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_key_frame_token_probability_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Key frame token probability buffer");
1909 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_updated_token_probability_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Updated token probability buffer");
1910 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_hw_token_probability_pak_pass_2_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Hw token probability pak pass 2 buffer");
1911 ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_repak_decision_buffer, VP8_REPAK_DECISION_BUF_SIZE, "Tpu repak decision buffer");
1912
1913 i965_encoder_vp8_vme_init_mpu_tpu_buffer(ctx, encoder_context, vp8_context);
1914
1915 ALLOC_VP8_RESOURCE_BUFFER(mb_coded_buffer, vp8_context->mb_coded_buffer_size, "MB coded buffer");
1916 }
1917
1918 #undef ALLOC_VP8_RESOURCE_BUFFER
1919
1920 static void
i965_encoder_vp8_vme_free_resources(struct i965_encoder_vp8_context * vp8_context)1921 i965_encoder_vp8_vme_free_resources(struct i965_encoder_vp8_context *vp8_context)
1922 {
1923 i965_free_gpe_resource(&vp8_context->reference_frame_mb_count_buffer);
1924 i965_free_gpe_resource(&vp8_context->mb_mode_cost_luma_buffer);
1925 i965_free_gpe_resource(&vp8_context->block_mode_cost_buffer);
1926 i965_free_gpe_resource(&vp8_context->chroma_recon_buffer);
1927 i965_free_gpe_resource(&vp8_context->per_mb_quant_data_buffer);
1928 i965_free_gpe_resource(&vp8_context->pred_mv_data_buffer);
1929 i965_free_gpe_resource(&vp8_context->mode_cost_update_buffer);
1930
1931 i965_free_gpe_resource(&vp8_context->brc_history_buffer);
1932 i965_free_gpe_resource(&vp8_context->brc_segment_map_buffer);
1933 i965_free_gpe_resource(&vp8_context->brc_distortion_buffer);
1934 i965_free_gpe_resource(&vp8_context->brc_pak_statistics_buffer);
1935 i965_free_gpe_resource(&vp8_context->brc_vp8_cfg_command_read_buffer);
1936 i965_free_gpe_resource(&vp8_context->brc_vp8_cfg_command_write_buffer);
1937 i965_free_gpe_resource(&vp8_context->brc_vp8_constant_data_buffer);
1938 i965_free_gpe_resource(&vp8_context->brc_pak_statistics_dump_buffer);
1939
1940 i965_free_gpe_resource(&vp8_context->me_4x_mv_data_buffer);
1941 i965_free_gpe_resource(&vp8_context->me_4x_distortion_buffer);
1942 i965_free_gpe_resource(&vp8_context->me_16x_mv_data_buffer);
1943
1944 i965_free_gpe_resource(&vp8_context->histogram_buffer);
1945
1946 i965_free_gpe_resource(&vp8_context->pak_intra_row_store_scratch_buffer);
1947 i965_free_gpe_resource(&vp8_context->pak_deblocking_filter_row_store_scratch_buffer);
1948 i965_free_gpe_resource(&vp8_context->pak_mpc_row_store_scratch_buffer);
1949 i965_free_gpe_resource(&vp8_context->pak_stream_out_buffer);
1950 i965_free_gpe_resource(&vp8_context->pak_frame_header_buffer);
1951 i965_free_gpe_resource(&vp8_context->pak_intermediate_buffer);
1952 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_mode_probs_buffer);
1953 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_ref_mode_probs_buffer);
1954 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_coeff_probs_buffer);
1955 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer);
1956 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_token_bits_data_buffer);
1957 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
1958 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_mpu_bitstream_buffer);
1959 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_tpu_bitstream_buffer);
1960 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_entropy_cost_table_buffer);
1961 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_pak_token_statistics_buffer);
1962 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_pak_token_update_flags_buffer);
1963 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_default_token_probability_buffer);
1964 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer);
1965 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_updated_token_probability_buffer);
1966 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_hw_token_probability_pak_pass_2_buffer);
1967 i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_repak_decision_buffer);
1968
1969 i965_free_gpe_resource(&vp8_context->mb_coded_buffer);
1970 }
1971
1972 static void
i965_encoder_vp8_update_internal_rc_mode(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)1973 i965_encoder_vp8_update_internal_rc_mode(VADriverContextP ctx,
1974 struct encode_state *encode_state,
1975 struct intel_encoder_context *encoder_context)
1976 {
1977 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1978
1979 if (encoder_context->rate_control_mode & VA_RC_CBR)
1980 vp8_context->internal_rate_mode = I965_BRC_CBR;
1981 else if (encoder_context->rate_control_mode & VA_RC_VBR)
1982 vp8_context->internal_rate_mode = I965_BRC_VBR;
1983 else
1984 vp8_context->internal_rate_mode = I965_BRC_CQP;
1985 }
1986
1987 static void
i965_encoder_vp8_get_sequence_parameter(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)1988 i965_encoder_vp8_get_sequence_parameter(VADriverContextP ctx,
1989 struct encode_state *encode_state,
1990 struct intel_encoder_context *encoder_context)
1991 {
1992 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1993
1994 /*
1995 * It is required to update frame width and height for each frame
1996 */
1997 if (encoder_context->frame_width_in_pixel != vp8_context->picture_width ||
1998 encoder_context->frame_height_in_pixel != vp8_context->picture_height) {
1999 vp8_context->picture_width = encoder_context->frame_width_in_pixel;
2000 vp8_context->picture_height = encoder_context->frame_height_in_pixel;
2001
2002 vp8_context->frame_width_in_mbs = WIDTH_IN_MACROBLOCKS(vp8_context->picture_width);
2003 vp8_context->frame_height_in_mbs = HEIGHT_IN_MACROBLOCKS(vp8_context->picture_height);
2004
2005 vp8_context->frame_width = vp8_context->frame_width_in_mbs * 16;
2006 vp8_context->frame_height = vp8_context->frame_height_in_mbs * 16;
2007
2008 vp8_context->down_scaled_width_in_mb4x = WIDTH_IN_MACROBLOCKS(vp8_context->frame_width / SCALE_FACTOR_4X);
2009 vp8_context->down_scaled_height_in_mb4x = HEIGHT_IN_MACROBLOCKS(vp8_context->frame_height / SCALE_FACTOR_4X);
2010 vp8_context->down_scaled_width_4x = vp8_context->down_scaled_width_in_mb4x * 16;
2011 vp8_context->down_scaled_height_4x = vp8_context->down_scaled_height_in_mb4x * 16;
2012
2013 vp8_context->down_scaled_width_in_mb16x = WIDTH_IN_MACROBLOCKS(vp8_context->frame_width / SCALE_FACTOR_16X);
2014 vp8_context->down_scaled_height_in_mb16x = HEIGHT_IN_MACROBLOCKS(vp8_context->frame_height / SCALE_FACTOR_16X);
2015 vp8_context->down_scaled_width_16x = vp8_context->down_scaled_width_in_mb16x * 16;
2016 vp8_context->down_scaled_height_16x = vp8_context->down_scaled_height_in_mb16x * 16;
2017
2018 i965_encoder_vp8_check_motion_estimation(ctx, encoder_context);
2019
2020 i965_encoder_vp8_vme_free_resources(vp8_context);
2021 i965_encoder_vp8_vme_allocate_resources(ctx, encoder_context, vp8_context);
2022 }
2023
2024 vp8_context->num_passes = 0;
2025 vp8_context->repak_pass_iter_val = 0;
2026 vp8_context->ref_ctrl_optimization_done = 0;
2027 }
2028
2029 static void
i965_encoder_vp8_get_picture_parameter(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)2030 i965_encoder_vp8_get_picture_parameter(VADriverContextP ctx,
2031 struct encode_state *encode_state,
2032 struct intel_encoder_context *encoder_context)
2033 {
2034 struct i965_driver_data *i965 = i965_driver_data(ctx);
2035 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2036 struct object_surface *obj_surface;
2037 VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
2038 VAQMatrixBufferVP8 *quant_params = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
2039 int is_intra, i;
2040 unsigned int average_qp = 0;
2041 unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
2042 vp8_context->internal_rate_mode == I965_BRC_VBR);
2043
2044 vp8_context->frame_type = pic_param->pic_flags.bits.frame_type ? MPEG_P_PICTURE : MPEG_I_PICTURE;
2045 is_intra = (vp8_context->frame_type == MPEG_I_PICTURE);
2046
2047 if (is_intra) {
2048 vp8_context->ref_frame_ctrl = 0;
2049 } else {
2050 vp8_context->ref_frame_ctrl =
2051 ((!pic_param->ref_flags.bits.no_ref_last) |
2052 (!pic_param->ref_flags.bits.no_ref_gf << 1) |
2053 (!pic_param->ref_flags.bits.no_ref_arf << 2));
2054 }
2055
2056 vp8_context->hme_enabled = (vp8_context->hme_supported && !is_intra && vp8_context->ref_frame_ctrl != 0);
2057 vp8_context->hme_16x_enabled = (vp8_context->hme_16x_supported && !is_intra);
2058
2059 if (pic_param->ref_last_frame != VA_INVALID_SURFACE) {
2060 obj_surface = SURFACE(pic_param->ref_last_frame);
2061
2062 if (obj_surface && obj_surface->bo)
2063 vp8_context->ref_last_frame = obj_surface;
2064 else
2065 vp8_context->ref_last_frame = NULL;
2066 } else {
2067 vp8_context->ref_last_frame = NULL;
2068 }
2069
2070 if (pic_param->ref_gf_frame != VA_INVALID_SURFACE) {
2071 obj_surface = SURFACE(pic_param->ref_gf_frame);
2072
2073 if (obj_surface && obj_surface->bo)
2074 vp8_context->ref_gf_frame = obj_surface;
2075 else
2076 vp8_context->ref_gf_frame = NULL;
2077 } else {
2078 vp8_context->ref_gf_frame = NULL;
2079 }
2080
2081 if (pic_param->ref_arf_frame != VA_INVALID_SURFACE) {
2082 obj_surface = SURFACE(pic_param->ref_arf_frame);
2083
2084 if (obj_surface && obj_surface->bo)
2085 vp8_context->ref_arf_frame = obj_surface;
2086 else
2087 vp8_context->ref_arf_frame = NULL;
2088 } else {
2089 vp8_context->ref_arf_frame = NULL;
2090 }
2091
2092 vp8_context->brc_distortion_buffer_need_reset = 0;
2093
2094 if (brc_enabled) {
2095 if (is_intra) {
2096 vp8_context->brc_distortion_buffer_need_reset = 1;
2097 } else {
2098 if (vp8_context->frame_num % vp8_context->gop_size == 1) {
2099 vp8_context->brc_distortion_buffer_need_reset = 1;
2100 }
2101 }
2102 }
2103
2104 if (pic_param->pic_flags.bits.segmentation_enabled) {
2105 for (i = 0; i < VP8_MAX_SEGMENTS; i++) {
2106 average_qp += quant_params->quantization_index[i] + quant_params->quantization_index_delta[i];
2107 }
2108
2109 average_qp = average_qp / VP8_MAX_SEGMENTS;
2110 } else {
2111 average_qp += quant_params->quantization_index[0] + quant_params->quantization_index_delta[0];
2112 }
2113
2114 if (is_intra) {
2115 vp8_context->average_i_frame_qp = average_qp;
2116 } else {
2117 vp8_context->average_p_frame_qp = average_qp;
2118 }
2119
2120 if (brc_enabled && vp8_context->multiple_pass_brc_supported)
2121 vp8_context->num_brc_pak_passes = VP8_BRC_MINIMUM_NUM_PASSES;
2122 else
2123 vp8_context->num_brc_pak_passes = VP8_BRC_SINGLE_PASS;
2124
2125 vp8_context->num_passes = 0;
2126 vp8_context->min_pak_passes = 1;
2127 vp8_context->repak_pass_iter_val = 0;
2128
2129 if (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY) {
2130 vp8_context->num_passes = 1;
2131 vp8_context->min_pak_passes = 2;
2132 } else if (encoder_context->quality_level == ENCODER_LOW_QUALITY) {
2133 vp8_context->num_passes = 0;
2134 vp8_context->min_pak_passes = 1;
2135 } else {
2136 vp8_context->num_passes = 0;
2137 vp8_context->min_pak_passes = 1;
2138 }
2139
2140 if (!vp8_context->repak_supported) {
2141 vp8_context->num_passes = 0;
2142 vp8_context->min_pak_passes = 1;
2143 }
2144
2145 if (brc_enabled)
2146 vp8_context->num_passes += (vp8_context->num_brc_pak_passes - 1);
2147
2148 if (vp8_context->repak_supported && vp8_context->min_pak_passes > 1)
2149 vp8_context->repak_pass_iter_val = vp8_context->num_passes;
2150 }
2151
2152 static void
i965_encoder_vp8_get_misc_parameters(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)2153 i965_encoder_vp8_get_misc_parameters(VADriverContextP ctx,
2154 struct encode_state *encode_state,
2155 struct intel_encoder_context *encoder_context)
2156 {
2157 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2158
2159 if (vp8_context->internal_rate_mode == I965_BRC_CQP) {
2160 vp8_context->init_vbv_buffer_fullness_in_bit = 0;
2161 vp8_context->vbv_buffer_size_in_bit = 0;
2162 vp8_context->target_bit_rate = 0;
2163 vp8_context->max_bit_rate = 0;
2164 vp8_context->min_bit_rate = 0;
2165 vp8_context->brc_need_reset = 0;
2166 } else {
2167 vp8_context->gop_size = encoder_context->brc.gop_size;
2168
2169 if (encoder_context->brc.need_reset) {
2170 vp8_context->framerate = encoder_context->brc.framerate[0];
2171 vp8_context->vbv_buffer_size_in_bit = encoder_context->brc.hrd_buffer_size;
2172 vp8_context->init_vbv_buffer_fullness_in_bit = encoder_context->brc.hrd_initial_buffer_fullness;
2173 vp8_context->max_bit_rate = encoder_context->brc.bits_per_second[0]; // currently only one layer is supported
2174 vp8_context->brc_need_reset = (vp8_context->brc_initted && encoder_context->brc.need_reset);
2175
2176 if (vp8_context->internal_rate_mode == I965_BRC_CBR) {
2177 vp8_context->min_bit_rate = vp8_context->max_bit_rate;
2178 vp8_context->target_bit_rate = vp8_context->max_bit_rate;
2179 } else {
2180 assert(vp8_context->internal_rate_mode == I965_BRC_VBR);
2181
2182 if (encoder_context->brc.target_percentage[0] <= 50)
2183 vp8_context->min_bit_rate = 0;
2184 else
2185 vp8_context->min_bit_rate = vp8_context->max_bit_rate * (2 * encoder_context->brc.target_percentage[0] - 100) / 100;
2186
2187 vp8_context->target_bit_rate = vp8_context->max_bit_rate * encoder_context->brc.target_percentage[0] / 100;
2188 }
2189 }
2190 }
2191
2192 if (encoder_context->quality_level == ENCODER_LOW_QUALITY)
2193 vp8_context->hme_16x_supported = 0;
2194 }
2195
2196 static VAStatus
i965_encoder_vp8_get_paramters(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)2197 i965_encoder_vp8_get_paramters(VADriverContextP ctx,
2198 struct encode_state *encode_state,
2199 struct intel_encoder_context *encoder_context)
2200 {
2201 VAQMatrixBufferVP8 *quant_params = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
2202 struct i965_encoder_vp8_surface *vp8_surface;
2203
2204 i965_encoder_vp8_update_internal_rc_mode(ctx, encode_state, encoder_context);
2205 i965_encoder_vp8_get_sequence_parameter(ctx, encode_state, encoder_context);
2206 i965_encoder_vp8_get_misc_parameters(ctx, encode_state, encoder_context);
2207 i965_encoder_vp8_get_picture_parameter(ctx, encode_state, encoder_context);
2208
2209 i965_encoder_vp8_allocate_surfaces(ctx, encoder_context, encode_state->reconstructed_object, 1);
2210 vp8_surface = encode_state->reconstructed_object->private_data;
2211 vp8_surface->qp_index = quant_params->quantization_index[0];
2212
2213 return VA_STATUS_SUCCESS;
2214 }
2215
2216 static VAStatus
i965_encoder_vp8_vme_gpe_kernel_init(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)2217 i965_encoder_vp8_vme_gpe_kernel_init(VADriverContextP ctx,
2218 struct encode_state *encode_state,
2219 struct intel_encoder_context *encoder_context)
2220 {
2221 struct i965_driver_data *i965 = i965_driver_data(ctx);
2222 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2223 struct i965_gpe_table *gpe = vp8_context->gpe_table;
2224 struct i965_encoder_vp8_mbenc_context *mbenc_context = &vp8_context->mbenc_context;
2225 struct i965_encoder_vp8_mpu_context *mpu_context = &vp8_context->mpu_context;
2226 struct i965_encoder_vp8_tpu_context *tpu_context = &vp8_context->tpu_context;
2227 struct gpe_dynamic_state_parameter ds_param;
2228 int i;
2229
2230 /*
2231 * BRC will update MBEnc curbe data buffer, so initialize GPE context for
2232 * MBEnc first
2233 */
2234 for (i = 0; i < NUM_VP8_MBENC; i++) {
2235 gpe->context_init(ctx, &mbenc_context->gpe_contexts[i]);
2236 }
2237
2238 /*
2239 * VP8_MBENC_I_FRAME_LUMA and VP8_MBENC_I_FRAME_CHROMA will use the same
2240 * the dynamic state buffer,
2241 */
2242 ds_param.bo_size = ALIGN(MAX(sizeof(struct vp8_mbenc_i_frame_curbe_data), sizeof(struct vp8_mbenc_p_frame_curbe_data)), 64) +
2243 vp8_context->idrt_entry_size * 2;
2244 mbenc_context->luma_chroma_dynamic_buffer = dri_bo_alloc(i965->intel.bufmgr,
2245 "IFrame Luma & CHROMA curbe buffer",
2246 ds_param.bo_size,
2247 0x1000);
2248
2249 /*
2250 * VP8_MBENC_I_FRAME_LUMA and VP8_MBENC_I_FRAME_CHROMA will share the same
2251 * the curbe data buffer
2252 */
2253 ds_param.bo = mbenc_context->luma_chroma_dynamic_buffer;
2254 ds_param.curbe_offset = 0;
2255 ds_param.idrt_offset = ALIGN(MAX(sizeof(struct vp8_mbenc_i_frame_curbe_data), sizeof(struct vp8_mbenc_p_frame_curbe_data)), 64);
2256 ds_param.sampler_offset = ds_param.bo_size;
2257 gpe->set_dynamic_buffer(ctx, &mbenc_context->gpe_contexts[VP8_MBENC_I_FRAME_LUMA], &ds_param);
2258
2259 ds_param.idrt_offset = ds_param.idrt_offset + vp8_context->idrt_entry_size;
2260 gpe->set_dynamic_buffer(ctx, &mbenc_context->gpe_contexts[VP8_MBENC_I_FRAME_CHROMA], &ds_param);
2261
2262 /*
2263 * BRC will update MPU curbe data buffer, so initialize GPE context for
2264 * MPU first
2265 */
2266 gpe->context_init(ctx, &mpu_context->gpe_contexts[0]);
2267 ds_param.bo_size = ALIGN(sizeof(struct vp8_mpu_curbe_data), 64) + vp8_context->idrt_entry_size;
2268 mpu_context->dynamic_buffer = dri_bo_alloc(i965->intel.bufmgr,
2269 "MPU dynamic buffer",
2270 ds_param.bo_size,
2271 0x1000);
2272
2273 ds_param.bo = mpu_context->dynamic_buffer;
2274 ds_param.curbe_offset = 0;
2275 ds_param.idrt_offset = ALIGN(sizeof(struct vp8_mpu_curbe_data), 64);
2276 ds_param.sampler_offset = ds_param.bo_size;
2277 gpe->set_dynamic_buffer(ctx, &mpu_context->gpe_contexts[0], &ds_param);
2278
2279 /*
2280 * BRC will update TPU curbe data buffer, so initialize GPE context for
2281 * TPU first
2282 */
2283 gpe->context_init(ctx, &tpu_context->gpe_contexts[0]);
2284 ds_param.bo_size = ALIGN(sizeof(struct vp8_tpu_curbe_data), 64) + vp8_context->idrt_entry_size;
2285 tpu_context->dynamic_buffer = dri_bo_alloc(i965->intel.bufmgr,
2286 "MPU dynamic buffer",
2287 ds_param.bo_size,
2288 0x1000);
2289
2290 ds_param.bo = tpu_context->dynamic_buffer;
2291 ds_param.curbe_offset = 0;
2292 ds_param.idrt_offset = ALIGN(sizeof(struct vp8_tpu_curbe_data), 64);
2293 ds_param.sampler_offset = ds_param.bo_size;
2294 gpe->set_dynamic_buffer(ctx, &tpu_context->gpe_contexts[0], &ds_param);
2295
2296 return VA_STATUS_SUCCESS;
2297 }
2298
2299 static void
i965_encoder_vp8_vme_brc_init_reset_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)2300 i965_encoder_vp8_vme_brc_init_reset_set_curbe(VADriverContextP ctx,
2301 struct encode_state *encode_state,
2302 struct intel_encoder_context *encoder_context,
2303 struct i965_gpe_context *gpe_context)
2304 {
2305 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2306 VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
2307 struct vp8_brc_init_reset_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
2308 double input_bits_per_frame, bps_ratio;
2309
2310 if (!pcmd)
2311 return;
2312
2313 memset(pcmd, 0, sizeof(*pcmd));
2314
2315 pcmd->dw0.profile_level_max_frame = vp8_context->frame_width * vp8_context->frame_height;
2316 pcmd->dw1.init_buf_full_in_bits = vp8_context->init_vbv_buffer_fullness_in_bit;
2317 pcmd->dw2.buf_size_in_bits = vp8_context->vbv_buffer_size_in_bit;
2318 pcmd->dw3.average_bitrate = (vp8_context->target_bit_rate + VP8_BRC_KBPS - 1) / VP8_BRC_KBPS * VP8_BRC_KBPS;
2319 pcmd->dw4.max_bitrate = (vp8_context->max_bit_rate + VP8_BRC_KBPS - 1) / VP8_BRC_KBPS * VP8_BRC_KBPS;
2320 pcmd->dw6.frame_rate_m = vp8_context->framerate.num;
2321 pcmd->dw7.frame_rate_d = vp8_context->framerate.den;
2322 pcmd->dw8.brc_flag = 0;
2323 pcmd->dw8.gop_minus1 = vp8_context->gop_size - 1;
2324
2325 if (vp8_context->internal_rate_mode == I965_BRC_CBR) {
2326 pcmd->dw4.max_bitrate = pcmd->dw3.average_bitrate;
2327
2328 pcmd->dw8.brc_flag = pcmd->dw8.brc_flag | BRC_KERNEL_CBR;
2329 } else if (vp8_context->internal_rate_mode == I965_BRC_VBR) {
2330 if (pcmd->dw4.max_bitrate < pcmd->dw3.average_bitrate) {
2331 pcmd->dw4.max_bitrate = 2 * pcmd->dw3.average_bitrate;
2332 }
2333
2334 pcmd->dw8.brc_flag = pcmd->dw8.brc_flag | BRC_KERNEL_VBR;
2335 }
2336
2337 input_bits_per_frame =
2338 ((double)(pcmd->dw4.max_bitrate) * (double)(pcmd->dw7.frame_rate_d) /
2339 (double)(pcmd->dw6.frame_rate_m));
2340
2341 if (pcmd->dw2.buf_size_in_bits < (unsigned int)input_bits_per_frame * 4) {
2342 pcmd->dw2.buf_size_in_bits = (unsigned int)input_bits_per_frame * 4;
2343 }
2344
2345 if (pcmd->dw1.init_buf_full_in_bits == 0) {
2346 pcmd->dw1.init_buf_full_in_bits = 7 * pcmd->dw2.buf_size_in_bits / 8;
2347 }
2348
2349 if (pcmd->dw1.init_buf_full_in_bits < (unsigned int)(input_bits_per_frame * 2)) {
2350 pcmd->dw1.init_buf_full_in_bits = (unsigned int)(input_bits_per_frame * 2);
2351 }
2352
2353 if (pcmd->dw1.init_buf_full_in_bits > pcmd->dw2.buf_size_in_bits) {
2354 pcmd->dw1.init_buf_full_in_bits = pcmd->dw2.buf_size_in_bits;
2355 }
2356
2357 bps_ratio = input_bits_per_frame / ((double)(pcmd->dw2.buf_size_in_bits) / 30);
2358 bps_ratio = (bps_ratio < 0.1) ? 0.1 : (bps_ratio > 3.5) ? 3.5 : bps_ratio;
2359
2360 pcmd->dw9.frame_width_in_bytes = vp8_context->picture_width;
2361 pcmd->dw10.frame_height_in_bytes = vp8_context->picture_height;
2362 pcmd->dw10.avbr_accuracy = 30;
2363 pcmd->dw11.avbr_convergence = 150;
2364 pcmd->dw11.min_qp = pic_param->clamp_qindex_low;
2365 pcmd->dw12.max_qp = pic_param->clamp_qindex_high;
2366 pcmd->dw12.level_qp = 60;
2367
2368 // DW13 default 100
2369 pcmd->dw13.max_section_pct = 100;
2370 pcmd->dw13.under_shoot_cbr_pct = 115;
2371
2372 // DW14 default 100
2373 pcmd->dw14.min_section_pct = 100;
2374 pcmd->dw14.vbr_bias_pct = 100;
2375 pcmd->dw15.instant_rate_threshold_0_for_p = 30;
2376 pcmd->dw15.instant_rate_threshold_1_for_p = 50;
2377 pcmd->dw15.instant_rate_threshold_2_for_p = 70;
2378 pcmd->dw15.instant_rate_threshold_3_for_p = 120;
2379
2380 pcmd->dw17.instant_rate_threshold_0_for_i = 30;
2381 pcmd->dw17.instant_rate_threshold_1_for_i = 50;
2382 pcmd->dw17.instant_rate_threshold_2_for_i = 90;
2383 pcmd->dw17.instant_rate_threshold_3_for_i = 115;
2384 pcmd->dw18.deviation_threshold_0_for_p = (unsigned int)(-50 * pow(0.9, bps_ratio));
2385 pcmd->dw18.deviation_threshold_1_for_p = (unsigned int)(-50 * pow(0.66, bps_ratio));
2386 pcmd->dw18.deviation_threshold_2_for_p = (unsigned int)(-50 * pow(0.46, bps_ratio));
2387 pcmd->dw18.deviation_threshold_3_for_p = (unsigned int)(-50 * pow(0.3, bps_ratio));
2388 pcmd->dw19.deviation_threshold_4_for_p = (unsigned int)(50 * pow(0.3, bps_ratio));
2389 pcmd->dw19.deviation_threshold_5_for_p = (unsigned int)(50 * pow(0.46, bps_ratio));
2390 pcmd->dw19.deviation_threshold_6_for_p = (unsigned int)(50 * pow(0.7, bps_ratio));
2391 pcmd->dw19.deviation_threshold_7_for_p = (unsigned int)(50 * pow(0.9, bps_ratio));
2392 pcmd->dw20.deviation_threshold_0_for_vbr = (unsigned int)(-50 * pow(0.9, bps_ratio));
2393 pcmd->dw20.deviation_threshold_1_for_vbr = (unsigned int)(-50 * pow(0.7, bps_ratio));
2394 pcmd->dw20.deviation_threshold_2_for_vbr = (unsigned int)(-50 * pow(0.5, bps_ratio));
2395 pcmd->dw20.deviation_threshold_3_for_vbr = (unsigned int)(-50 * pow(0.3, bps_ratio));
2396 pcmd->dw21.deviation_threshold_4_for_vbr = (unsigned int)(100 * pow(0.4, bps_ratio));
2397 pcmd->dw21.deviation_threshold_5_for_vbr = (unsigned int)(100 * pow(0.5, bps_ratio));
2398 pcmd->dw21.deviation_threshold_6_for_vbr = (unsigned int)(100 * pow(0.75, bps_ratio));
2399 pcmd->dw21.deviation_threshold_7_for_vbr = (unsigned int)(100 * pow(0.9, bps_ratio));
2400 pcmd->dw22.deviation_threshold_0_for_i = (unsigned int)(-50 * pow(0.8, bps_ratio));
2401 pcmd->dw22.deviation_threshold_1_for_i = (unsigned int)(-50 * pow(0.6, bps_ratio));
2402 pcmd->dw22.deviation_threshold_2_for_i = (unsigned int)(-50 * pow(0.34, bps_ratio));
2403 pcmd->dw22.deviation_threshold_3_for_i = (unsigned int)(-50 * pow(0.2, bps_ratio));
2404 pcmd->dw23.deviation_threshold_4_for_i = (unsigned int)(50 * pow(0.2, bps_ratio));
2405 pcmd->dw23.deviation_threshold_5_for_i = (unsigned int)(50 * pow(0.4, bps_ratio));
2406 pcmd->dw23.deviation_threshold_6_for_i = (unsigned int)(50 * pow(0.66, bps_ratio));
2407 pcmd->dw23.deviation_threshold_7_for_i = (unsigned int)(50 * pow(0.9, bps_ratio));
2408
2409 // Default: 1
2410 pcmd->dw24.num_t_levels = 1;
2411
2412 if (!vp8_context->brc_initted) {
2413 vp8_context->brc_init_current_target_buf_full_in_bits = pcmd->dw1.init_buf_full_in_bits;
2414 }
2415
2416 vp8_context->brc_init_reset_buf_size_in_bits = pcmd->dw2.buf_size_in_bits;
2417 vp8_context->brc_init_reset_input_bits_per_frame = input_bits_per_frame;
2418
2419 pcmd->dw26.history_buffer_bti = VP8_BTI_BRC_INIT_RESET_HISTORY;
2420 pcmd->dw27.distortion_buffer_bti = VP8_BTI_BRC_INIT_RESET_DISTORTION;
2421
2422 i965_gpe_context_unmap_curbe(gpe_context);
2423 }
2424
2425 static void
i965_encoder_vp8_vme_brc_init_reset_add_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)2426 i965_encoder_vp8_vme_brc_init_reset_add_surfaces(VADriverContextP ctx,
2427 struct encode_state *encode_state,
2428 struct intel_encoder_context *encoder_context,
2429 struct i965_gpe_context *gpe_context)
2430 {
2431 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2432
2433 i965_add_buffer_gpe_surface(ctx,
2434 gpe_context,
2435 &vp8_context->brc_history_buffer,
2436 0,
2437 vp8_context->brc_history_buffer.size,
2438 0,
2439 VP8_BTI_BRC_INIT_RESET_HISTORY);
2440
2441 i965_add_buffer_2d_gpe_surface(ctx,
2442 gpe_context,
2443 &vp8_context->brc_distortion_buffer,
2444 1,
2445 I965_SURFACEFORMAT_R8_UNORM,
2446 VP8_BTI_BRC_INIT_RESET_DISTORTION);
2447 }
2448
2449 static VAStatus
i965_encoder_vp8_vme_brc_init_reset(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)2450 i965_encoder_vp8_vme_brc_init_reset(VADriverContextP ctx,
2451 struct encode_state *encode_state,
2452 struct intel_encoder_context *encoder_context)
2453 {
2454 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2455 struct i965_encoder_vp8_brc_init_reset_context *init_reset_context = &vp8_context->brc_init_reset_context;
2456 struct i965_gpe_table *gpe = vp8_context->gpe_table;
2457 struct gpe_media_object_parameter media_object_param;
2458 struct i965_gpe_context *gpe_context;
2459 int gpe_index = VP8_BRC_INIT;
2460 int media_function = VP8_MEDIA_STATE_BRC_INIT_RESET;
2461
2462 if (vp8_context->brc_initted)
2463 gpe_index = VP8_BRC_RESET;
2464
2465 gpe_context = &init_reset_context->gpe_contexts[gpe_index];
2466
2467 gpe->context_init(ctx, gpe_context);
2468 gpe->reset_binding_table(ctx, gpe_context);
2469 i965_encoder_vp8_vme_brc_init_reset_set_curbe(ctx, encode_state, encoder_context, gpe_context);
2470 i965_encoder_vp8_vme_brc_init_reset_add_surfaces(ctx, encode_state, encoder_context, gpe_context);
2471 gpe->setup_interface_data(ctx, gpe_context);
2472
2473 memset(&media_object_param, 0, sizeof(media_object_param));
2474 i965_run_kernel_media_object(ctx, encoder_context, gpe_context, media_function, &media_object_param);
2475
2476 return VA_STATUS_SUCCESS;
2477 }
2478
2479 static void
i965_encoder_vp8_vme_scaling_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,struct scaling_curbe_parameters * params)2480 i965_encoder_vp8_vme_scaling_set_curbe(VADriverContextP ctx,
2481 struct encode_state *encode_state,
2482 struct intel_encoder_context *encoder_context,
2483 struct i965_gpe_context *gpe_context,
2484 struct scaling_curbe_parameters *params)
2485 {
2486 struct vp8_scaling_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
2487
2488 if (!pcmd)
2489 return;
2490
2491 memset(pcmd, 0, sizeof(*pcmd));
2492
2493 pcmd->dw0.input_picture_width = params->input_picture_width;
2494 pcmd->dw0.input_picture_height = params->input_picture_height;
2495
2496 if (!params->is_field_picture) {
2497 pcmd->dw1.input_y_bti_frame = VP8_BTI_SCALING_FRAME_SRC_Y;
2498 pcmd->dw2.output_y_bti_frame = VP8_BTI_SCALING_FRAME_DST_Y;
2499 } else {
2500 pcmd->dw1.input_y_bti_top_field = VP8_BTI_SCALING_FIELD_TOP_SRC_Y;
2501 pcmd->dw2.output_y_bti_top_field = VP8_BTI_SCALING_FIELD_TOP_DST_Y;
2502 pcmd->dw3.input_y_bti_bottom_field = VP8_BTI_SCALING_FIELD_BOT_SRC_Y;
2503 pcmd->dw4.output_y_bti_bottom_field = VP8_BTI_SCALING_FIELD_BOT_DST_Y;
2504 }
2505
2506 if (params->flatness_check_enabled) {
2507 pcmd->dw5.flatness_threshold = 128;
2508 pcmd->dw6.enable_mb_flatness_check = 1;
2509
2510 if (!params->is_field_picture) {
2511 pcmd->dw8.flatness_output_bti_frame = VP8_BTI_SCALING_FRAME_FLATNESS_DST;
2512 } else {
2513 pcmd->dw8.flatness_output_bti_top_field = VP8_BTI_SCALING_FIELD_TOP_FLATNESS_DST;
2514 pcmd->dw9.flatness_output_bti_bottom_field = VP8_BTI_SCALING_FIELD_BOT_FLATNESS_DST;
2515 }
2516 } else {
2517 pcmd->dw6.enable_mb_flatness_check = 0;
2518 }
2519
2520 pcmd->dw6.enable_mb_variance_output = params->mb_variance_output_enabled;
2521 pcmd->dw6.enable_mb_pixel_average_output = params->mb_pixel_average_output_enabled;
2522
2523 if (params->mb_variance_output_enabled || params->mb_pixel_average_output_enabled) {
2524 if (!params->is_field_picture) {
2525 pcmd->dw10.mbv_proc_stats_bti_frame = VP8_BTI_SCALING_FRAME_MBVPROCSTATS_DST;
2526 } else {
2527 pcmd->dw10.mbv_proc_stats_bti_top_field = VP8_BTI_SCALING_FIELD_TOP_MBVPROCSTATS_DST;
2528 pcmd->dw11.mbv_proc_stats_bti_bottom_field = VP8_BTI_SCALING_FIELD_BOT_MBVPROCSTATS_DST;
2529 }
2530 }
2531
2532 i965_gpe_context_unmap_curbe(gpe_context);
2533 }
2534
2535 static void
i965_encoder_vp8_vme_scaling_add_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,struct scaling_surface_parameters * params)2536 i965_encoder_vp8_vme_scaling_add_surfaces(VADriverContextP ctx,
2537 struct encode_state *encode_state,
2538 struct intel_encoder_context *encoder_context,
2539 struct i965_gpe_context *gpe_context,
2540 struct scaling_surface_parameters *params)
2541 {
2542 i965_add_2d_gpe_surface(ctx,
2543 gpe_context,
2544 params->input_obj_surface,
2545 0,
2546 1,
2547 I965_SURFACEFORMAT_R32_UNORM,
2548 VP8_BTI_SCALING_FRAME_SRC_Y);
2549 i965_add_2d_gpe_surface(ctx,
2550 gpe_context,
2551 params->output_obj_surface,
2552 0,
2553 1,
2554 I965_SURFACEFORMAT_R32_UNORM,
2555 VP8_BTI_SCALING_FRAME_DST_Y);
2556 }
2557
2558 static VAStatus
i965_encoder_vp8_vme_scaling(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,int scaling_16x_enabled)2559 i965_encoder_vp8_vme_scaling(VADriverContextP ctx,
2560 struct encode_state *encode_state,
2561 struct intel_encoder_context *encoder_context,
2562 int scaling_16x_enabled)
2563 {
2564 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2565 struct i965_encoder_vp8_scaling_context *scaling_context = &vp8_context->scaling_context;
2566 struct i965_gpe_table *gpe = vp8_context->gpe_table;
2567 struct gpe_media_object_walker_parameter media_object_walker_param;
2568 struct i965_gpe_context *gpe_context;
2569 struct scaling_curbe_parameters scaling_curbe_params;
2570 struct scaling_surface_parameters scaling_surface_params;
2571 struct vp8_encoder_kernel_walker_parameter kernel_walker_param;
2572 struct object_surface *input_obj_surface, *output_obj_surface;
2573 struct i965_encoder_vp8_surface *vp8_surface;
2574 unsigned int input_frame_width, input_frame_height, output_frame_width, output_frame_height;
2575 unsigned int down_scaled_width_in_mbs, down_scaled_height_in_mbs;
2576 int gpe_index, media_function;
2577
2578 vp8_surface = encode_state->reconstructed_object->private_data;
2579
2580 if (scaling_16x_enabled) {
2581 gpe_index = VP8_SCALING_16X;
2582 media_function = VP8_MEDIA_STATE_16X_SCALING;
2583
2584 down_scaled_width_in_mbs = vp8_context->down_scaled_width_in_mb16x;
2585 down_scaled_height_in_mbs = vp8_context->down_scaled_height_in_mb16x;
2586
2587 input_obj_surface = vp8_surface->scaled_4x_surface_obj;
2588 input_frame_width = vp8_context->down_scaled_width_4x;
2589 input_frame_height = vp8_context->down_scaled_height_4x;
2590
2591 output_obj_surface = vp8_surface->scaled_16x_surface_obj;
2592 output_frame_width = vp8_context->down_scaled_width_16x;
2593 output_frame_height = vp8_context->down_scaled_height_16x;
2594 } else {
2595 gpe_index = VP8_SCALING_4X;
2596 media_function = VP8_MEDIA_STATE_4X_SCALING;
2597
2598 down_scaled_width_in_mbs = vp8_context->down_scaled_width_in_mb4x;
2599 down_scaled_height_in_mbs = vp8_context->down_scaled_height_in_mb4x;
2600
2601 input_obj_surface = encode_state->input_yuv_object;
2602 input_frame_width = vp8_context->picture_width; /* the orignal width */
2603 input_frame_height = vp8_context->picture_height; /* the orignal height */
2604
2605 output_obj_surface = vp8_surface->scaled_4x_surface_obj;
2606 output_frame_width = vp8_context->down_scaled_width_4x;
2607 output_frame_height = vp8_context->down_scaled_height_4x;
2608 }
2609
2610 gpe_context = &scaling_context->gpe_contexts[gpe_index];
2611
2612 gpe->context_init(ctx, gpe_context);
2613 gpe->reset_binding_table(ctx, gpe_context);
2614
2615 memset(&scaling_curbe_params, 0, sizeof(scaling_curbe_params));
2616 scaling_curbe_params.input_picture_width = input_frame_width;
2617 scaling_curbe_params.input_picture_height = input_frame_height;
2618 scaling_curbe_params.is_field_picture = 0;
2619 scaling_curbe_params.flatness_check_enabled = 0;
2620 scaling_curbe_params.mb_variance_output_enabled = 0;
2621 scaling_curbe_params.mb_pixel_average_output_enabled = 0;
2622 i965_encoder_vp8_vme_scaling_set_curbe(ctx, encode_state, encoder_context, gpe_context, &scaling_curbe_params);
2623
2624 scaling_surface_params.input_obj_surface = input_obj_surface;
2625 scaling_surface_params.input_width = input_frame_width;
2626 scaling_surface_params.input_height = input_frame_height;
2627 scaling_surface_params.output_obj_surface = output_obj_surface;
2628 scaling_surface_params.output_width = output_frame_width;
2629 scaling_surface_params.output_height = output_frame_height;
2630 i965_encoder_vp8_vme_scaling_add_surfaces(ctx, encode_state, encoder_context, gpe_context, &scaling_surface_params);
2631
2632 gpe->setup_interface_data(ctx, gpe_context);
2633
2634 memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
2635 kernel_walker_param.resolution_x = down_scaled_width_in_mbs * 2; /* 8x8 level */
2636 kernel_walker_param.resolution_y = down_scaled_height_in_mbs * 2;
2637 kernel_walker_param.no_dependency = 1;
2638 i965_init_media_object_walker_parameters(encoder_context, &kernel_walker_param, &media_object_walker_param);
2639
2640 i965_run_kernel_media_object_walker(ctx, encoder_context, gpe_context, media_function, &media_object_walker_param);
2641
2642 return VA_STATUS_SUCCESS;
2643 }
2644
2645 static void
i965_encoder_vp8_vme_me_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,struct me_curbe_parameters * params)2646 i965_encoder_vp8_vme_me_set_curbe(VADriverContextP ctx,
2647 struct encode_state *encode_state,
2648 struct intel_encoder_context *encoder_context,
2649 struct i965_gpe_context *gpe_context,
2650 struct me_curbe_parameters *params)
2651 {
2652 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2653 struct vp8_me_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
2654 int me_mode, me_method;
2655
2656 if (!pcmd)
2657 return;
2658
2659 if (vp8_context->hme_16x_enabled) {
2660 if (params->use_16x_me)
2661 me_mode = VP8_ME_MODE_ME16X_BEFORE_ME4X;
2662 else
2663 me_mode = VP8_ME_MODE_ME4X_AFTER_ME16X;
2664 } else {
2665 me_mode = VP8_ME_MODE_ME4X_ONLY;
2666 }
2667
2668 memset(pcmd, 0, sizeof(*pcmd));
2669
2670 pcmd->dw1.max_num_mvs = 0x10;
2671 pcmd->dw1.bi_weight = 0;
2672
2673 pcmd->dw2.max_num_su = 57;
2674 pcmd->dw2.max_len_sp = 57;
2675
2676 pcmd->dw3.sub_mb_part_mask = 0x77;
2677 pcmd->dw3.inter_sad = 0;
2678 pcmd->dw3.intra_sad = 0;
2679 pcmd->dw3.bme_disable_fbr = 1;
2680 pcmd->dw3.sub_pel_mode = 3;
2681
2682 pcmd->dw4.picture_height_minus1 = params->down_scaled_height_in_mbs - 1;
2683 pcmd->dw4.picture_width = params->down_scaled_width_in_mbs;
2684
2685 if (pcmd->dw4.picture_height_minus1 < 2)
2686 pcmd->dw4.picture_height_minus1 = 2;
2687
2688 if (pcmd->dw4.picture_width < 3)
2689 pcmd->dw4.picture_width = 3;
2690
2691 pcmd->dw5.ref_height = 40;
2692 pcmd->dw5.ref_width = 48;
2693
2694 pcmd->dw6.me_mode = me_mode;
2695
2696 if (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY)
2697 pcmd->dw6.super_combine_dist = 5;
2698 else if (encoder_context->quality_level == ENCODER_LOW_QUALITY)
2699 pcmd->dw6.super_combine_dist = 0;
2700 else
2701 pcmd->dw6.super_combine_dist = 1;
2702
2703 pcmd->dw6.max_vmv_range = 0x7fc;
2704
2705 pcmd->dw13.num_ref_idx_l0_minus1 = vp8_num_refs[vp8_context->ref_frame_ctrl] - 1;
2706 pcmd->dw13.num_ref_idx_l1_minus1 = 0;
2707
2708 me_method = (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY) ? 6 : 4;
2709 memcpy(&pcmd->dw16, vp8_search_path[me_method], 14 * sizeof(pcmd->dw16));
2710
2711 pcmd->dw32.vp8_me_mv_output_data_bti = VP8_BTI_ME_MV_DATA;
2712 pcmd->dw33.vp8_me_mv_input_data_bti = VP8_BTI_16X_ME_MV_DATA;
2713 pcmd->dw34.vp8_me_distorion_bti = VP8_BTI_ME_DISTORTION;
2714 pcmd->dw35.vp8_me_min_dist_brc_bti = VP8_BTI_ME_MIN_DIST_BRC_DATA;
2715 pcmd->dw36.vp8_me_forward_ref_bti = VP8_BTI_VME_INTER_PRED;
2716
2717 i965_gpe_context_unmap_curbe(gpe_context);
2718 }
2719
2720 static void
i965_encoder_vp8_vme_me_add_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,struct me_surface_parameters * params)2721 i965_encoder_vp8_vme_me_add_surfaces(VADriverContextP ctx,
2722 struct encode_state *encode_state,
2723 struct intel_encoder_context *encoder_context,
2724 struct i965_gpe_context *gpe_context,
2725 struct me_surface_parameters *params)
2726 {
2727 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2728 struct i965_encoder_vp8_surface *vp8_surface;
2729 struct i965_gpe_resource *me_gpe_buffer, *me_brc_distortion_buffer;
2730 struct object_surface *obj_surface;
2731 unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
2732 vp8_context->internal_rate_mode == I965_BRC_VBR);
2733
2734 if (brc_enabled)
2735 me_brc_distortion_buffer = &vp8_context->brc_distortion_buffer;
2736 else
2737 me_brc_distortion_buffer = &vp8_context->me_4x_distortion_buffer;
2738
2739 if (params->use_16x_me) {
2740 me_gpe_buffer = &vp8_context->me_16x_mv_data_buffer;
2741 } else {
2742 me_gpe_buffer = &vp8_context->me_4x_mv_data_buffer;
2743 }
2744
2745 i965_add_buffer_2d_gpe_surface(ctx,
2746 gpe_context,
2747 me_gpe_buffer,
2748 1,
2749 I965_SURFACEFORMAT_R8_UNORM,
2750 VP8_BTI_ME_MV_DATA);
2751
2752 if (vp8_context->hme_16x_enabled) {
2753 me_gpe_buffer = &vp8_context->me_16x_mv_data_buffer;
2754 i965_add_buffer_2d_gpe_surface(ctx,
2755 gpe_context,
2756 me_gpe_buffer,
2757 1,
2758 I965_SURFACEFORMAT_R8_UNORM,
2759 VP8_BTI_16X_ME_MV_DATA);
2760 }
2761
2762 if (!params->use_16x_me) {
2763 me_gpe_buffer = &vp8_context->me_4x_distortion_buffer;
2764 i965_add_buffer_2d_gpe_surface(ctx,
2765 gpe_context,
2766 me_gpe_buffer,
2767 1,
2768 I965_SURFACEFORMAT_R8_UNORM,
2769 VP8_BTI_ME_DISTORTION);
2770
2771 me_gpe_buffer = me_brc_distortion_buffer;
2772 i965_add_buffer_2d_gpe_surface(ctx,
2773 gpe_context,
2774 me_gpe_buffer,
2775 1,
2776 I965_SURFACEFORMAT_R8_UNORM,
2777 VP8_BTI_ME_MIN_DIST_BRC_DATA);
2778 }
2779
2780 vp8_surface = encode_state->reconstructed_object->private_data;
2781 assert(vp8_surface);
2782
2783 if (params->use_16x_me) {
2784 obj_surface = vp8_surface->scaled_16x_surface_obj;
2785 } else {
2786 obj_surface = vp8_surface->scaled_4x_surface_obj;
2787 }
2788
2789 i965_add_adv_gpe_surface(ctx,
2790 gpe_context,
2791 obj_surface,
2792 VP8_BTI_VME_INTER_PRED);
2793
2794 if (vp8_context->ref_last_frame != NULL &&
2795 vp8_context->ref_last_frame->bo != NULL) {
2796 vp8_surface = vp8_context->ref_last_frame->private_data;
2797 obj_surface = NULL;
2798
2799 if (vp8_surface) {
2800 if (params->use_16x_me) {
2801 obj_surface = vp8_surface->scaled_16x_surface_obj;
2802 } else {
2803 obj_surface = vp8_surface->scaled_4x_surface_obj;
2804 }
2805 }
2806
2807 if (obj_surface) {
2808 i965_add_adv_gpe_surface(ctx,
2809 gpe_context,
2810 obj_surface,
2811 VP8_BTI_ME_REF1_PIC);
2812 }
2813 }
2814
2815 if (vp8_context->ref_gf_frame != NULL &&
2816 vp8_context->ref_gf_frame->bo != NULL) {
2817 vp8_surface = vp8_context->ref_gf_frame->private_data;
2818 obj_surface = NULL;
2819
2820 if (vp8_surface) {
2821 if (params->use_16x_me) {
2822 obj_surface = vp8_surface->scaled_16x_surface_obj;
2823 } else {
2824 obj_surface = vp8_surface->scaled_4x_surface_obj;
2825 }
2826 }
2827
2828 if (obj_surface) {
2829 switch (vp8_context->ref_frame_ctrl) {
2830 case 2:
2831 case 6:
2832 i965_add_adv_gpe_surface(ctx,
2833 gpe_context,
2834 obj_surface,
2835 VP8_BTI_ME_REF1_PIC);
2836 break;
2837
2838 case 3:
2839 case 7:
2840 i965_add_adv_gpe_surface(ctx,
2841 gpe_context,
2842 obj_surface,
2843 VP8_BTI_ME_REF2_PIC);
2844 break;
2845 }
2846 }
2847 }
2848
2849 if (vp8_context->ref_arf_frame != NULL &&
2850 vp8_context->ref_arf_frame->bo != NULL) {
2851 vp8_surface = vp8_context->ref_arf_frame->private_data;
2852 obj_surface = NULL;
2853
2854 if (vp8_surface) {
2855 if (params->use_16x_me) {
2856 obj_surface = vp8_surface->scaled_16x_surface_obj;
2857 } else {
2858 obj_surface = vp8_surface->scaled_4x_surface_obj;
2859 }
2860 }
2861
2862 if (obj_surface) {
2863 switch (vp8_context->ref_frame_ctrl) {
2864 case 4:
2865 i965_add_adv_gpe_surface(ctx,
2866 gpe_context,
2867 obj_surface,
2868 VP8_BTI_ME_REF1_PIC);
2869 break;
2870
2871 case 5:
2872 case 6:
2873 i965_add_adv_gpe_surface(ctx,
2874 gpe_context,
2875 obj_surface,
2876 VP8_BTI_ME_REF2_PIC);
2877 break;
2878
2879 case 7:
2880 i965_add_adv_gpe_surface(ctx,
2881 gpe_context,
2882 obj_surface,
2883 VP8_BTI_ME_REF3_PIC);
2884 break;
2885 }
2886 }
2887 }
2888 }
2889
2890 static void
i965_encoder_vp8_vme_init_brc_distorion_buffer(VADriverContextP ctx,struct intel_encoder_context * encoder_context)2891 i965_encoder_vp8_vme_init_brc_distorion_buffer(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
2892 {
2893 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2894
2895 i965_zero_gpe_resource(&vp8_context->brc_distortion_buffer);
2896 }
2897
2898 static VAStatus
i965_encoder_vp8_vme_me(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,int use_16x_me)2899 i965_encoder_vp8_vme_me(VADriverContextP ctx,
2900 struct encode_state *encode_state,
2901 struct intel_encoder_context *encoder_context,
2902 int use_16x_me)
2903 {
2904 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2905 struct i965_encoder_vp8_me_context *me_context = &vp8_context->me_context;
2906 struct i965_gpe_table *gpe = vp8_context->gpe_table;
2907 struct gpe_media_object_walker_parameter media_object_walker_param;
2908 struct vp8_encoder_kernel_walker_parameter kernel_walker_params;
2909 struct me_curbe_parameters me_curbe_params;
2910 struct i965_gpe_context *gpe_context;
2911 struct me_surface_parameters me_surface_params;
2912 VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
2913 unsigned int down_scaled_width_in_mbs, down_scaled_height_in_mbs;
2914 unsigned int ref_frame_flag_final, ref_frame_flag;
2915 int gpe_index, media_function;
2916
2917 if (vp8_context->frame_type == MPEG_P_PICTURE) {
2918 ref_frame_flag = VP8_REF_FLAG_ALL;
2919
2920 if (pic_param->ref_last_frame == pic_param->ref_gf_frame) {
2921 ref_frame_flag &= ~VP8_REF_FLAG_GOLDEN;
2922 }
2923
2924 if (pic_param->ref_last_frame == pic_param->ref_arf_frame) {
2925 ref_frame_flag &= ~VP8_REF_FLAG_ALT;
2926 }
2927
2928 if (pic_param->ref_gf_frame == pic_param->ref_arf_frame) {
2929 ref_frame_flag &= ~VP8_REF_FLAG_ALT;
2930 }
2931 } else {
2932 ref_frame_flag = VP8_REF_FLAG_LAST;
2933 }
2934
2935 switch (vp8_context->ref_frame_ctrl) {
2936 case 0:
2937 ref_frame_flag_final = VP8_REF_FLAG_NONE;
2938 break;
2939
2940 case 1:
2941 ref_frame_flag_final = VP8_REF_FLAG_LAST; // Last Ref only
2942 break;
2943
2944 case 2:
2945 ref_frame_flag_final = VP8_REF_FLAG_GOLDEN; // Gold Ref only
2946 break;
2947
2948 case 4:
2949 ref_frame_flag_final = VP8_REF_FLAG_ALT; // Alt Ref only
2950 break;
2951
2952 default:
2953 ref_frame_flag_final = ref_frame_flag;
2954 }
2955
2956 vp8_context->ref_frame_ctrl = ref_frame_flag_final;
2957 vp8_context->ref_ctrl_optimization_done = 1;
2958
2959 if (use_16x_me) {
2960 gpe_index = VP8_ME_16X;
2961 media_function = VP8_MEDIA_STATE_16X_ME;
2962 down_scaled_width_in_mbs = vp8_context->down_scaled_width_in_mb16x;
2963 down_scaled_height_in_mbs = vp8_context->down_scaled_height_in_mb16x;
2964 } else {
2965 gpe_index = VP8_ME_4X;
2966 media_function = VP8_MEDIA_STATE_4X_ME;
2967 down_scaled_width_in_mbs = vp8_context->down_scaled_width_in_mb4x;
2968 down_scaled_height_in_mbs = vp8_context->down_scaled_height_in_mb4x;
2969 }
2970
2971 gpe_context = &me_context->gpe_contexts[gpe_index];
2972
2973 gpe->context_init(ctx, gpe_context);
2974 gpe->reset_binding_table(ctx, gpe_context);
2975
2976 memset(&me_curbe_params, 0, sizeof(me_curbe_params));
2977 me_curbe_params.down_scaled_width_in_mbs = down_scaled_width_in_mbs;
2978 me_curbe_params.down_scaled_height_in_mbs = down_scaled_height_in_mbs;
2979 me_curbe_params.use_16x_me = use_16x_me;
2980 i965_encoder_vp8_vme_me_set_curbe(ctx, encode_state, encoder_context, gpe_context, &me_curbe_params);
2981
2982 if (vp8_context->brc_distortion_buffer_need_reset && !use_16x_me) {
2983 i965_encoder_vp8_vme_init_brc_distorion_buffer(ctx, encoder_context);
2984 }
2985
2986 memset(&me_surface_params, 0, sizeof(me_surface_params));
2987 me_surface_params.use_16x_me = use_16x_me;
2988 i965_encoder_vp8_vme_me_add_surfaces(ctx, encode_state, encoder_context, gpe_context, &me_surface_params);
2989
2990 gpe->setup_interface_data(ctx, gpe_context);
2991
2992 memset(&kernel_walker_params, 0, sizeof(kernel_walker_params));
2993 kernel_walker_params.resolution_x = down_scaled_width_in_mbs;
2994 kernel_walker_params.resolution_y = down_scaled_height_in_mbs;
2995 kernel_walker_params.no_dependency = 1;
2996 i965_init_media_object_walker_parameters(encoder_context, &kernel_walker_params, &media_object_walker_param);
2997
2998 i965_run_kernel_media_object_walker(ctx, encoder_context, gpe_context, media_function, &media_object_walker_param);
2999
3000 return VA_STATUS_SUCCESS;
3001 }
3002
3003 #define QUANT_INDEX(index, q_index, q_index_delta) \
3004 do { \
3005 index = quant_param->quantization_index[q_index] + quant_param->quantization_index_delta[q_index_delta]; \
3006 index = MIN(MAX_QP_VP8, index); \
3007 } while (0)
3008
3009 static void
i965_encoder_vp8_vme_mbenc_set_i_frame_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)3010 i965_encoder_vp8_vme_mbenc_set_i_frame_curbe(VADriverContextP ctx,
3011 struct encode_state *encode_state,
3012 struct intel_encoder_context *encoder_context,
3013 struct i965_gpe_context *gpe_context)
3014 {
3015 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3016 struct vp8_mbenc_i_frame_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
3017 VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
3018 VAQMatrixBufferVP8 *quant_param = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
3019 unsigned int segmentation_enabled = pic_param->pic_flags.bits.segmentation_enabled;
3020 unsigned short y_quanta_dc_idx, uv_quanta_dc_idx, uv_quanta_ac_idx;
3021
3022 if (!pcmd)
3023 return;
3024
3025 memset(pcmd, 0, sizeof(*pcmd));
3026
3027 pcmd->dw0.frame_width = vp8_context->frame_width;
3028 pcmd->dw0.frame_height = vp8_context->frame_height;
3029
3030 pcmd->dw1.frame_type = 0; /* key frame */
3031 pcmd->dw1.enable_segmentation = segmentation_enabled;
3032 pcmd->dw1.enable_hw_intra_prediction = (encoder_context->quality_level == ENCODER_LOW_QUALITY) ? 1 : 0;
3033 pcmd->dw1.enable_chroma_ip_enhancement = 1; /* Cannot be disabled */
3034 pcmd->dw1.enable_debug_dumps = 0;
3035 pcmd->dw1.enable_mpu_histogram_update = 1;
3036 pcmd->dw1.vme_distortion_measure = 2; /* HAAR transform */
3037 pcmd->dw1.vme_enable_tm_check = 0;
3038
3039 QUANT_INDEX(y_quanta_dc_idx, 0, 0);
3040 pcmd->dw2.lambda_seg_0 = (unsigned short)((quant_dc_vp8[y_quanta_dc_idx] * quant_dc_vp8[y_quanta_dc_idx]) / 4);
3041
3042 if (segmentation_enabled) {
3043 QUANT_INDEX(y_quanta_dc_idx, 1, 0);
3044 pcmd->dw2.lambda_seg_1 = (unsigned short)((quant_dc_vp8[y_quanta_dc_idx] * quant_dc_vp8[y_quanta_dc_idx]) / 4);
3045
3046 QUANT_INDEX(y_quanta_dc_idx, 2, 0);
3047 pcmd->dw3.lambda_seg_2 = (unsigned short)((quant_dc_vp8[y_quanta_dc_idx] * quant_dc_vp8[y_quanta_dc_idx]) / 4);
3048
3049 QUANT_INDEX(y_quanta_dc_idx, 3, 0);
3050 pcmd->dw3.lambda_seg_3 = (unsigned short)((quant_dc_vp8[y_quanta_dc_idx] * quant_dc_vp8[y_quanta_dc_idx]) / 4);
3051 }
3052
3053 pcmd->dw4.all_dc_bias_segment_0 = DC_BIAS_SEGMENT_DEFAULT_VAL_VP8;
3054
3055 if (segmentation_enabled) {
3056 pcmd->dw4.all_dc_bias_segment_1 = DC_BIAS_SEGMENT_DEFAULT_VAL_VP8;
3057 pcmd->dw5.all_dc_bias_segment_2 = DC_BIAS_SEGMENT_DEFAULT_VAL_VP8;
3058 pcmd->dw5.all_dc_bias_segment_3 = DC_BIAS_SEGMENT_DEFAULT_VAL_VP8;
3059 }
3060
3061 QUANT_INDEX(uv_quanta_dc_idx, 0, 1);
3062 pcmd->dw6.chroma_dc_de_quant_segment_0 = quant_dc_vp8[uv_quanta_dc_idx];
3063
3064 if (segmentation_enabled) {
3065 QUANT_INDEX(uv_quanta_dc_idx, 1, 1);
3066 pcmd->dw6.chroma_dc_de_quant_segment_1 = quant_dc_vp8[uv_quanta_dc_idx];
3067
3068 QUANT_INDEX(uv_quanta_dc_idx, 2, 1);
3069 pcmd->dw7.chroma_dc_de_quant_segment_2 = quant_dc_vp8[uv_quanta_dc_idx];
3070
3071 QUANT_INDEX(uv_quanta_dc_idx, 3, 1);
3072 pcmd->dw7.chroma_dc_de_quant_segment_3 = quant_dc_vp8[uv_quanta_dc_idx];
3073 }
3074
3075 QUANT_INDEX(uv_quanta_ac_idx, 0, 2);
3076 pcmd->dw8.chroma_ac_de_quant_segment0 = quant_ac_vp8[uv_quanta_ac_idx];
3077 pcmd->dw10.chroma_ac0_threshold0_segment0 = (unsigned short)((((((1) << 16) -
3078 1) * 1.0 / ((1 << 16) / quant_ac_vp8[uv_quanta_ac_idx]) -
3079 ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3080 (1 << 13) + 3400) / 2217.0);
3081 pcmd->dw10.chroma_ac0_threshold1_segment0 = (unsigned short)((((((2) << 16) -
3082 1) * 1.0 / ((1 << 16) / quant_ac_vp8[uv_quanta_ac_idx]) -
3083 ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3084 (1 << 13) + 3400) / 2217.0);
3085
3086 if (segmentation_enabled) {
3087 QUANT_INDEX(uv_quanta_ac_idx, 1, 2);
3088 pcmd->dw8.chroma_ac_de_quant_segment1 = quant_ac_vp8[uv_quanta_ac_idx];
3089 pcmd->dw10.chroma_ac0_threshold0_segment0 = (unsigned short)((((((1) << 16) -
3090 1) * 1.0 / ((1 << 16) /
3091 quant_ac_vp8[uv_quanta_ac_idx]) -
3092 ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3093 (1 << 13) + 3400) / 2217.0);
3094 pcmd->dw10.chroma_ac0_threshold1_segment0 = (unsigned short)((((((2) << 16) -
3095 1) * 1.0 / ((1 << 16) /
3096 quant_ac_vp8[uv_quanta_ac_idx]) -
3097 ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3098 (1 << 13) + 3400) / 2217.0);
3099
3100 QUANT_INDEX(uv_quanta_ac_idx, 2, 2);
3101 pcmd->dw9.chroma_ac_de_quant_segment2 = quant_ac_vp8[uv_quanta_ac_idx];
3102 pcmd->dw12.chroma_ac0_threshold0_segment2 = (unsigned short)((((((1) << 16) -
3103 1) * 1.0 / ((1 << 16) /
3104 quant_ac_vp8[uv_quanta_ac_idx]) -
3105 ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3106 (1 << 13) + 3400) / 2217.0);
3107 pcmd->dw12.chroma_ac0_threshold1_segment2 = (unsigned short)((((((2) << 16) -
3108 1) * 1.0 / ((1 << 16) /
3109 quant_ac_vp8[uv_quanta_ac_idx]) -
3110 ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3111 (1 << 13) + 3400) / 2217.0);
3112
3113 QUANT_INDEX(uv_quanta_ac_idx, 3, 2);
3114 pcmd->dw9.chroma_ac_de_quant_segment3 = quant_ac_vp8[uv_quanta_ac_idx];
3115 pcmd->dw13.chroma_ac0_threshold0_segment3 = (unsigned short)((((((1) << 16) -
3116 1) * 1.0 / ((1 << 16) /
3117 quant_ac_vp8[uv_quanta_ac_idx]) -
3118 ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3119 (1 << 13) + 3400) / 2217.0);
3120 pcmd->dw13.chroma_ac0_threshold1_segment3 = (unsigned short)((((((2) << 16) -
3121 1) * 1.0 / ((1 << 16) /
3122 quant_ac_vp8[uv_quanta_ac_idx]) -
3123 ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3124 (1 << 13) + 3400) / 2217.0);
3125 }
3126
3127 QUANT_INDEX(uv_quanta_dc_idx, 0, 1);
3128 pcmd->dw14.chroma_dc_threshold0_segment0 = (((1) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3129 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3130 pcmd->dw14.chroma_dc_threshold1_segment0 = (((2) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3131 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3132 pcmd->dw15.chroma_dc_threshold2_segment0 = (((3) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3133 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3134 pcmd->dw15.chroma_dc_threshold3_segment0 = (((4) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3135 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3136
3137 if (segmentation_enabled) {
3138 QUANT_INDEX(uv_quanta_dc_idx, 1, 1);
3139 pcmd->dw16.chroma_dc_threshold0_segment1 = (((1) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3140 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3141 pcmd->dw16.chroma_dc_threshold1_segment1 = (((2) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3142 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3143 pcmd->dw17.chroma_dc_threshold2_segment1 = (((3) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3144 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3145 pcmd->dw17.chroma_dc_threshold3_segment1 = (((4) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3146 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3147
3148 QUANT_INDEX(uv_quanta_dc_idx, 2, 1);
3149 pcmd->dw18.chroma_dc_threshold0_segment2 = (((1) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3150 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3151 pcmd->dw18.chroma_dc_threshold1_segment2 = (((2) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3152 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3153 pcmd->dw19.chroma_dc_threshold2_segment2 = (((3) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3154 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3155 pcmd->dw19.chroma_dc_threshold3_segment2 = (((4) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3156 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3157
3158 QUANT_INDEX(uv_quanta_dc_idx, 3, 1);
3159 pcmd->dw20.chroma_dc_threshold0_segment3 = (((1) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3160 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3161 pcmd->dw20.chroma_dc_threshold1_segment3 = (((2) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3162 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3163 pcmd->dw21.chroma_dc_threshold2_segment3 = (((3) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3164 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3165 pcmd->dw21.chroma_dc_threshold3_segment3 = (((4) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3166 ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3167 }
3168
3169 QUANT_INDEX(uv_quanta_ac_idx, 0, 2);
3170 pcmd->dw22.chroma_ac1_threshold_segment0 = ((1 << (16)) - 1) / ((1 << 16) / quant_ac_vp8[uv_quanta_ac_idx]) -
3171 ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7);
3172
3173 if (segmentation_enabled) {
3174 QUANT_INDEX(uv_quanta_ac_idx, 1, 2);
3175 pcmd->dw22.chroma_ac1_threshold_segment1 = ((1 << (16)) - 1) / ((1 << 16) / quant_ac_vp8[uv_quanta_ac_idx]) -
3176 ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7);
3177
3178 QUANT_INDEX(uv_quanta_ac_idx, 2, 2);
3179 pcmd->dw23.chroma_ac1_threshold_segment2 = ((1 << (16)) - 1) / ((1 << 16) / quant_ac_vp8[uv_quanta_ac_idx]) -
3180 ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7);
3181
3182 QUANT_INDEX(uv_quanta_ac_idx, 3, 2);
3183 pcmd->dw23.chroma_ac1_threshold_segment3 =
3184 ((1 << (16)) - 1) / ((1 << 16) / quant_ac_vp8[uv_quanta_ac_idx]) -
3185 ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7);
3186 }
3187
3188 QUANT_INDEX(uv_quanta_dc_idx, 0, 0);
3189 pcmd->dw24.vme_16x16_cost_segment0 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][0];
3190 pcmd->dw25.vme_4x4_cost_segment0 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][1];
3191 pcmd->dw26.vme_16x16_non_dc_penalty_segment0 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][2];
3192 pcmd->dw27.vme_4x4_non_dc_penalty_segment0 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][3];
3193
3194 if (segmentation_enabled) {
3195 QUANT_INDEX(uv_quanta_dc_idx, 1, 0);
3196 pcmd->dw24.vme_16x16_cost_segment1 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][0];
3197 pcmd->dw25.vme_4x4_cost_segment1 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][1];
3198 pcmd->dw26.vme_16x16_non_dc_penalty_segment1 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][2];
3199 pcmd->dw27.vme_4x4_non_dc_penalty_segment1 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][3];
3200
3201 QUANT_INDEX(uv_quanta_dc_idx, 2, 0);
3202 pcmd->dw24.vme_16x16_cost_segment2 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][0];
3203 pcmd->dw25.vme_4x4_cost_segment2 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][1];
3204 pcmd->dw26.vme_16x16_non_dc_penalty_segment2 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][2];
3205 pcmd->dw27.vme_4x4_non_dc_penalty_segment2 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][3];
3206
3207 QUANT_INDEX(uv_quanta_dc_idx, 3, 0);
3208 pcmd->dw24.vme_16x16_cost_segment3 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][0];
3209 pcmd->dw25.vme_4x4_cost_segment3 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][1];
3210 pcmd->dw26.vme_16x16_non_dc_penalty_segment3 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][2];
3211 pcmd->dw27.vme_4x4_non_dc_penalty_segment3 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][3];
3212 }
3213
3214 pcmd->dw32.mb_enc_per_mb_out_data_surf_bti = VP8_BTI_MBENC_PER_MB_OUT;
3215 pcmd->dw33.mb_enc_curr_y_bti = VP8_BTI_MBENC_CURR_Y;
3216 pcmd->dw34.mb_enc_curr_uv_bti = VP8_BTI_MBENC_CURR_Y;
3217 pcmd->dw35.mb_mode_cost_luma_bti = VP8_BTI_MBENC_MB_MODE_COST_LUMA;
3218 pcmd->dw36.mb_enc_block_mode_cost_bti = VP8_BTI_MBENC_BLOCK_MODE_COST;
3219 pcmd->dw37.chroma_recon_surf_bti = VP8_BTI_MBENC_CHROMA_RECON;
3220 pcmd->dw38.segmentation_map_bti = VP8_BTI_MBENC_SEGMENTATION_MAP;
3221 pcmd->dw39.histogram_bti = VP8_BTI_MBENC_HISTOGRAM;
3222 pcmd->dw40.mb_enc_vme_debug_stream_out_bti = VP8_BTI_MBENC_I_VME_DEBUG_STREAMOUT;
3223 pcmd->dw41.vme_bti = VP8_BTI_MBENC_VME;
3224 pcmd->dw42.idist_surface_bti = VP8_BTI_MBENC_IDIST;
3225 pcmd->dw43.curr_y_down_scaled_bti = VP8_BTI_MBENC_CURR_Y_DOWNSCALED;
3226 pcmd->dw44.vme_coarse_intra_bti = VP8_BTI_MBENC_VME_COARSE_INTRA;
3227
3228 i965_gpe_context_unmap_curbe(gpe_context);
3229 }
3230
3231 static void
i965_encoder_vp8_vme_mbenc_set_p_frame_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)3232 i965_encoder_vp8_vme_mbenc_set_p_frame_curbe(VADriverContextP ctx,
3233 struct encode_state *encode_state,
3234 struct intel_encoder_context *encoder_context,
3235 struct i965_gpe_context *gpe_context)
3236 {
3237 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3238 struct vp8_mbenc_p_frame_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
3239 VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
3240 VAQMatrixBufferVP8 *quant_param = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
3241 unsigned int segmentation_enabled = pic_param->pic_flags.bits.segmentation_enabled;
3242 unsigned short qp_seg0, qp_seg1, qp_seg2, qp_seg3;
3243 unsigned char me_method = (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY) ? 6 : 4;
3244
3245 if (!pcmd)
3246 return;
3247
3248 memset(pcmd, 0, sizeof(*pcmd));
3249
3250 QUANT_INDEX(qp_seg0, 0, 0);
3251 QUANT_INDEX(qp_seg1, 0, 0);
3252 QUANT_INDEX(qp_seg2, 0, 0);
3253 QUANT_INDEX(qp_seg3, 3, 0);
3254
3255 pcmd->dw0.frame_width = vp8_context->frame_width;
3256 pcmd->dw0.frame_height = vp8_context->frame_height;
3257
3258 pcmd->dw1.frame_type = 1; // P-frame
3259 pcmd->dw1.multiple_pred = (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY) ? 1 :
3260 ((encoder_context->quality_level == ENCODER_LOW_QUALITY) ? 0 : 2);
3261 pcmd->dw1.hme_enable = vp8_context->hme_enabled;
3262 pcmd->dw1.hme_combine_overlap = 1;
3263 pcmd->dw1.enable_temporal_scalability = 0;
3264 pcmd->dw1.ref_frame_flags = vp8_context->ref_frame_ctrl;
3265 pcmd->dw1.enable_segmentation = segmentation_enabled;
3266 pcmd->dw1.enable_segmentation_info_update = 1;
3267 pcmd->dw1.multi_reference_qp_check = 0;
3268 pcmd->dw1.mode_cost_enable_flag = 1;
3269 pcmd->dw1.main_ref = mainref_table_vp8[vp8_context->ref_frame_ctrl];
3270
3271 pcmd->dw2.lambda_intra_segment0 = quant_dc_vp8[qp_seg0];
3272 pcmd->dw2.lambda_inter_segment0 = (quant_dc_vp8[qp_seg0] >> 2);
3273
3274 pcmd->dw3.lambda_intra_segment1 = quant_dc_vp8[qp_seg1];
3275 pcmd->dw3.lambda_inter_segment1 = (quant_dc_vp8[qp_seg1] >> 2);
3276
3277 pcmd->dw4.lambda_intra_segment2 = quant_dc_vp8[qp_seg2];
3278 pcmd->dw4.lambda_inter_segment2 = (quant_dc_vp8[qp_seg2] >> 2);
3279
3280 pcmd->dw5.lambda_intra_segment3 = quant_dc_vp8[qp_seg3];
3281 pcmd->dw5.lambda_inter_segment3 = (quant_dc_vp8[qp_seg3] >> 2);
3282
3283 pcmd->dw6.reference_frame_sign_bias_3 = pic_param->pic_flags.bits.sign_bias_golden;
3284 pcmd->dw6.reference_frame_sign_bias_2 = pic_param->pic_flags.bits.sign_bias_alternate;
3285 pcmd->dw6.reference_frame_sign_bias_1 = pic_param->pic_flags.bits.sign_bias_golden ^ pic_param->pic_flags.bits.sign_bias_alternate;
3286 pcmd->dw6.reference_frame_sign_bias_0 = 0;
3287
3288 pcmd->dw7.raw_dist_threshold = (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY) ? 50 :
3289 ((encoder_context->quality_level == ENCODER_LOW_QUALITY) ? 0 : 100);
3290 pcmd->dw7.temporal_layer_id = 0;
3291
3292 pcmd->dw8.early_ime_successful_stop_threshold = 0;
3293 pcmd->dw8.adaptive_search_enable = (encoder_context->quality_level != ENCODER_LOW_QUALITY) ? 1 : 0;
3294 pcmd->dw8.skip_mode_enable = 1;
3295 pcmd->dw8.bidirectional_mix_disbale = 0;
3296 pcmd->dw8.transform8x8_flag_for_inter_enable = 0;
3297 pcmd->dw8.early_ime_success_enable = 0;
3298
3299 pcmd->dw9.ref_pixel_bias_enable = 0;
3300 pcmd->dw9.unidirection_mix_enable = 0;
3301 pcmd->dw9.bidirectional_weight = 0;
3302 pcmd->dw9.ref_id_polarity_bits = 0;
3303 pcmd->dw9.max_num_of_motion_vectors = 0;
3304
3305 pcmd->dw10.max_fixed_search_path_length = (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY) ? 25 :
3306 ((encoder_context->quality_level == ENCODER_LOW_QUALITY) ? 9 : 57);
3307 pcmd->dw10.maximum_search_path_length = 57;
3308
3309 pcmd->dw11.submacro_block_subPartition_mask = 0;
3310 pcmd->dw11.intra_sad_measure_adjustment = 2;
3311 pcmd->dw11.inter_sad_measure_adjustment = 2;
3312 pcmd->dw11.block_based_skip_enable = 0;
3313 pcmd->dw11.bme_disable_for_fbr_message = 0;
3314 pcmd->dw11.forward_trans_form_skip_check_enable = 0;
3315 pcmd->dw11.process_inter_chroma_pixels_mode = 0;
3316 pcmd->dw11.disable_field_cache_allocation = 0;
3317 pcmd->dw11.skip_mode_type = 0;
3318 pcmd->dw11.sub_pel_mode = 3;
3319 pcmd->dw11.dual_search_path_option = 0;
3320 pcmd->dw11.search_control = 0;
3321 pcmd->dw11.reference_access = 0;
3322 pcmd->dw11.source_access = 0;
3323 pcmd->dw11.inter_mb_type_road_map = 0;
3324 pcmd->dw11.source_block_size = 0;
3325
3326 pcmd->dw12.reference_search_windows_height = (encoder_context->quality_level != ENCODER_LOW_QUALITY) ? 40 : 28;
3327 pcmd->dw12.reference_search_windows_width = (encoder_context->quality_level != ENCODER_LOW_QUALITY) ? 48 : 28;
3328
3329 pcmd->dw13.mode_0_3_cost_seg0 = cost_table_vp8[qp_seg0][0];
3330 pcmd->dw14.mode_4_7_cost_seg0 = cost_table_vp8[qp_seg0][1];
3331 pcmd->dw15.mode_8_9_ref_id_chroma_cost_seg0 = cost_table_vp8[qp_seg0][2];
3332
3333 switch (me_method) {
3334 case 2:
3335 memcpy(&(pcmd->dw16), single_su_vp8, sizeof(single_su_vp8));
3336 break;
3337
3338 case 3:
3339 memcpy(&(pcmd->dw16), raster_scan_48x40_vp8, sizeof(raster_scan_48x40_vp8));
3340 break;
3341
3342 case 4:
3343 case 5:
3344 memcpy(&(pcmd->dw16), full_spiral_48x40_vp8, sizeof(full_spiral_48x40_vp8));
3345 break;
3346
3347 case 6:
3348 default:
3349 memcpy(&(pcmd->dw16), diamond_vp8, sizeof(diamond_vp8));
3350 break;
3351 }
3352
3353 pcmd->dw30.mv_0_3_cost_seg0 = cost_table_vp8[qp_seg0][3];
3354 pcmd->dw31.mv_4_7_cost_seg0 = cost_table_vp8[qp_seg0][4];
3355
3356 pcmd->dw32.bilinear_enable = 0;
3357 pcmd->dw32.intra_16x16_no_dc_penalty_segment0 = cost_table_vp8[qp_seg0][5];
3358 pcmd->dw32.intra_16x16_no_dc_penalty_segment1 = cost_table_vp8[qp_seg1][5];
3359
3360 pcmd->dw33.intra_16x16_no_dc_penalty_segment2 = cost_table_vp8[qp_seg2][5];
3361 pcmd->dw33.intra_16x16_no_dc_penalty_segment3 = cost_table_vp8[qp_seg3][5];
3362 pcmd->dw33.hme_combine_len = 8;
3363
3364 /* dw34 to dw 57 */
3365 memcpy(&(pcmd->dw34), mv_ref_cost_context_vp8, 24 * sizeof(unsigned int));
3366
3367 pcmd->dw58.enc_cost_16x16 = 0;
3368 pcmd->dw58.enc_cost_16x8 = 0x73c;
3369
3370 pcmd->dw59.enc_cost_8x8 = 0x365;
3371 pcmd->dw59.enc_cost_4x4 = 0xdc9;
3372
3373 pcmd->dw60.frame_count_probability_ref_frame_cost_0 = 0x0204;
3374 pcmd->dw60.frame_count_probability_ref_frame_cost_1 = 0x006a;
3375
3376 pcmd->dw61.frame_count_probability_ref_frame_cost_2 = 0x0967;
3377 pcmd->dw61.frame_count_probability_ref_frame_cost_3 = 0x0969;
3378
3379 switch (vp8_context->frame_num % vp8_context->gop_size) {
3380 case 1:
3381 pcmd->dw62.average_qp_of_last_ref_frame = quant_dc_vp8[vp8_context->average_i_frame_qp];
3382 pcmd->dw62.average_qp_of_gold_ref_frame = pcmd->dw62.average_qp_of_last_ref_frame;
3383 pcmd->dw62.average_qp_of_alt_ref_frame = pcmd->dw62.average_qp_of_last_ref_frame;
3384 break;
3385
3386 case 2:
3387 pcmd->dw62.average_qp_of_last_ref_frame = quant_dc_vp8[vp8_context->average_p_frame_qp];
3388 pcmd->dw62.average_qp_of_gold_ref_frame = quant_dc_vp8[vp8_context->average_i_frame_qp];
3389 pcmd->dw62.average_qp_of_alt_ref_frame = pcmd->dw62.average_qp_of_gold_ref_frame;
3390 break;
3391
3392 case 3:
3393 pcmd->dw62.average_qp_of_last_ref_frame = quant_dc_vp8[vp8_context->average_p_frame_qp];
3394 pcmd->dw62.average_qp_of_gold_ref_frame = quant_dc_vp8[vp8_context->average_p_frame_qp];
3395 pcmd->dw62.average_qp_of_alt_ref_frame = quant_dc_vp8[vp8_context->average_i_frame_qp];
3396 break;
3397
3398 default:
3399 pcmd->dw62.average_qp_of_last_ref_frame = quant_dc_vp8[vp8_context->average_p_frame_qp];
3400 pcmd->dw62.average_qp_of_gold_ref_frame = pcmd->dw62.average_qp_of_last_ref_frame;
3401 pcmd->dw62.average_qp_of_alt_ref_frame = pcmd->dw62.average_qp_of_last_ref_frame;
3402 break;
3403 }
3404
3405 pcmd->dw63.intra_4x4_no_dc_penalty_segment0 = cost_table_vp8[qp_seg0][6];
3406 pcmd->dw63.intra_4x4_no_dc_penalty_segment1 = cost_table_vp8[qp_seg1][6];
3407 pcmd->dw63.intra_4x4_no_dc_penalty_segment2 = cost_table_vp8[qp_seg2][6];
3408 pcmd->dw63.intra_4x4_no_dc_penalty_segment3 = cost_table_vp8[qp_seg3][6];
3409
3410 pcmd->dw64.mode_0_3_cost_seg1 = cost_table_vp8[qp_seg1][0];
3411 pcmd->dw65.mode_4_7_cost_seg1 = cost_table_vp8[qp_seg1][1];
3412 pcmd->dw66.mode_8_9_ref_id_chroma_cost_seg1 = cost_table_vp8[qp_seg1][2];
3413
3414 pcmd->dw67.mv_0_3_cost_seg1 = cost_table_vp8[qp_seg1][3];
3415 pcmd->dw68.mv_4_7_cost_seg1 = cost_table_vp8[qp_seg1][4];
3416
3417 pcmd->dw69.mode_0_3_cost_seg2 = cost_table_vp8[qp_seg2][0];
3418 pcmd->dw70.mode_4_7_cost_seg2 = cost_table_vp8[qp_seg2][1];
3419 pcmd->dw71.mode_8_9_ref_id_chroma_cost_seg2 = cost_table_vp8[qp_seg2][2];
3420
3421 pcmd->dw72.mv_0_3_cost_seg2 = cost_table_vp8[qp_seg2][3];
3422 pcmd->dw73.mv_4_7_cost_seg2 = cost_table_vp8[qp_seg2][4];
3423
3424 pcmd->dw74.mode_0_3_cost_seg3 = cost_table_vp8[qp_seg3][0];
3425 pcmd->dw75.mode_4_7_cost_seg3 = cost_table_vp8[qp_seg3][1];
3426 pcmd->dw76.mode_8_9_ref_id_chroma_cost_seg3 = cost_table_vp8[qp_seg3][2];
3427
3428 pcmd->dw77.mv_0_3_cost_seg3 = cost_table_vp8[qp_seg3][3];
3429 pcmd->dw78.mv_4_7_cost_seg3 = cost_table_vp8[qp_seg3][4];
3430
3431 pcmd->dw79.new_mv_skip_threshold_segment0 = new_mv_skip_threshold_vp8[qp_seg0];
3432 pcmd->dw79.new_mv_skip_threshold_segment1 = new_mv_skip_threshold_vp8[qp_seg1];
3433 pcmd->dw80.new_mv_skip_threshold_segment2 = new_mv_skip_threshold_vp8[qp_seg2];
3434 pcmd->dw80.new_mv_skip_threshold_segment3 = new_mv_skip_threshold_vp8[qp_seg3];
3435
3436 pcmd->dw81.per_mb_output_data_surface_bti = VP8_BTI_MBENC_PER_MB_OUT;
3437 pcmd->dw82.current_picture_y_surface_bti = VP8_BTI_MBENC_CURR_Y;
3438 pcmd->dw83.current_picture_interleaved_uv_surface_bti = VP8_BTI_MBENC_CURR_Y;
3439 pcmd->dw84.hme_mv_data_surface_bti = VP8_BTI_MBENC_MV_DATA_FROM_ME;
3440 pcmd->dw85.mv_data_surface_bti = VP8_BTI_MBENC_IND_MV_DATA;
3441 pcmd->dw86.mb_count_per_reference_frame_bti = VP8_BTI_MBENC_REF_MB_COUNT;
3442 pcmd->dw87.vme_inter_prediction_bti = VP8_BTI_MBENC_INTER_PRED;
3443 pcmd->dw88.active_ref1_bti = VP8_BTI_MBENC_REF1_PIC;
3444 pcmd->dw89.active_ref2_bti = VP8_BTI_MBENC_REF2_PIC;
3445 pcmd->dw90.active_ref3_bti = VP8_BTI_MBENC_REF3_PIC;
3446 pcmd->dw91.per_mb_quant_data_bti = VP8_BTI_MBENC_P_PER_MB_QUANT;
3447 pcmd->dw92.segment_map_bti = VP8_BTI_MBENC_SEGMENTATION_MAP;
3448 pcmd->dw93.inter_prediction_distortion_bti = VP8_BTI_MBENC_INTER_PRED_DISTORTION;
3449 pcmd->dw94.histogram_bti = VP8_BTI_MBENC_HISTOGRAM;
3450 pcmd->dw95.pred_mv_data_bti = VP8_BTI_MBENC_PRED_MV_DATA;
3451 pcmd->dw96.mode_cost_update_bti = VP8_BTI_MBENC_MODE_COST_UPDATE;
3452 pcmd->dw97.kernel_debug_dump_bti = VP8_BTI_MBENC_P_VME_DEBUG_STREAMOUT;
3453
3454 i965_gpe_context_unmap_curbe(gpe_context);
3455 }
3456
3457 #undef QUANT_INDEX
3458
3459 static void
i965_encoder_vp8_vme_mbenc_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)3460 i965_encoder_vp8_vme_mbenc_set_curbe(VADriverContextP ctx,
3461 struct encode_state *encode_state,
3462 struct intel_encoder_context *encoder_context,
3463 struct i965_gpe_context *gpe_context)
3464 {
3465 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3466
3467 if (vp8_context->frame_type == MPEG_I_PICTURE)
3468 i965_encoder_vp8_vme_mbenc_set_i_frame_curbe(ctx, encode_state, encoder_context, gpe_context);
3469 else
3470 i965_encoder_vp8_vme_mbenc_set_p_frame_curbe(ctx, encode_state, encoder_context, gpe_context);
3471 }
3472
3473 static void
i965_encoder_vp8_vme_mbenc_add_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,struct mbenc_surface_parameters * params)3474 i965_encoder_vp8_vme_mbenc_add_surfaces(VADriverContextP ctx,
3475 struct encode_state *encode_state,
3476 struct intel_encoder_context *encoder_context,
3477 struct i965_gpe_context *gpe_context,
3478 struct mbenc_surface_parameters *params)
3479 {
3480 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3481 struct i965_encoder_vp8_surface *vp8_surface;
3482 struct object_surface *obj_surface;
3483 VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
3484 unsigned int size = vp8_context->frame_width_in_mbs * vp8_context->frame_height_in_mbs * 16;
3485 unsigned int segmentation_enabled = pic_param->pic_flags.bits.segmentation_enabled;
3486
3487 /* Per MB output data buffer */
3488 i965_add_buffer_gpe_surface(ctx,
3489 gpe_context,
3490 &vp8_context->mb_coded_buffer,
3491 0,
3492 size,
3493 0,
3494 VP8_BTI_MBENC_PER_MB_OUT);
3495
3496 /* Current input surface Y & UV */
3497 i965_add_2d_gpe_surface(ctx,
3498 gpe_context,
3499 encode_state->input_yuv_object,
3500 0,
3501 1,
3502 I965_SURFACEFORMAT_R8_UNORM,
3503 VP8_BTI_MBENC_CURR_Y);
3504
3505 i965_add_2d_gpe_surface(ctx,
3506 gpe_context,
3507 encode_state->input_yuv_object,
3508 1,
3509 1,
3510 I965_SURFACEFORMAT_R8_UNORM,
3511 VP8_BTI_MBENC_CURR_UV);
3512
3513 /* Current surface for VME */
3514 i965_add_adv_gpe_surface(ctx,
3515 gpe_context,
3516 encode_state->input_yuv_object,
3517 VP8_BTI_MBENC_VME);
3518
3519 if (segmentation_enabled) {
3520 /* TODO check the internal segmetation buffer */
3521 dri_bo *bo = NULL;
3522
3523 if (encode_state->encmb_map)
3524 bo = encode_state->encmb_map->bo;
3525
3526 if (bo) {
3527 i965_add_dri_buffer_2d_gpe_surface(ctx,
3528 encoder_context,
3529 gpe_context,
3530 bo,
3531 vp8_context->frame_width_in_mbs,
3532 vp8_context->frame_height_in_mbs,
3533 vp8_context->frame_width_in_mbs,
3534 0,
3535 I965_SURFACEFORMAT_R8_UNORM,
3536 VP8_BTI_MBENC_SEGMENTATION_MAP);
3537 }
3538 }
3539
3540 /* Histogram buffer */
3541 size = VP8_HISTOGRAM_SIZE;
3542 i965_add_buffer_gpe_surface(ctx,
3543 gpe_context,
3544 &vp8_context->histogram_buffer,
3545 1,
3546 size,
3547 0,
3548 VP8_BTI_MBENC_HISTOGRAM);
3549
3550 if (vp8_context->frame_type == MPEG_I_PICTURE) {
3551 i965_add_buffer_2d_gpe_surface(ctx,
3552 gpe_context,
3553 &vp8_context->mb_mode_cost_luma_buffer,
3554 0,
3555 I965_SURFACEFORMAT_R8_UNORM,
3556 VP8_BTI_MBENC_MB_MODE_COST_LUMA);
3557
3558 i965_add_buffer_2d_gpe_surface(ctx,
3559 gpe_context,
3560 &vp8_context->block_mode_cost_buffer,
3561 0,
3562 I965_SURFACEFORMAT_R8_UNORM,
3563 VP8_BTI_MBENC_BLOCK_MODE_COST);
3564
3565 /* Chroma recon buffer */
3566 size = vp8_context->frame_width_in_mbs * vp8_context->frame_height_in_mbs * 64;
3567 i965_add_buffer_gpe_surface(ctx,
3568 gpe_context,
3569 &vp8_context->chroma_recon_buffer,
3570 0,
3571 size,
3572 0,
3573 VP8_BTI_MBENC_CHROMA_RECON);
3574
3575 if (params->i_frame_dist_in_use) {
3576 i965_add_buffer_2d_gpe_surface(ctx,
3577 gpe_context,
3578 params->me_brc_distortion_buffer,
3579 1,
3580 I965_SURFACEFORMAT_R8_UNORM,
3581 VP8_BTI_MBENC_IDIST);
3582
3583
3584 vp8_surface = encode_state->reconstructed_object->private_data;
3585 assert(vp8_surface);
3586
3587 if (vp8_surface && vp8_surface->scaled_4x_surface_obj) {
3588 obj_surface = vp8_surface->scaled_4x_surface_obj;
3589 } else
3590 obj_surface = NULL;
3591
3592 if (obj_surface) {
3593 i965_add_2d_gpe_surface(ctx,
3594 gpe_context,
3595 obj_surface,
3596 0,
3597 0,
3598 I965_SURFACEFORMAT_R8_UNORM,
3599 VP8_BTI_MBENC_CURR_Y_DOWNSCALED);
3600
3601 i965_add_adv_gpe_surface(ctx,
3602 gpe_context,
3603 obj_surface,
3604 VP8_BTI_MBENC_VME_COARSE_INTRA);
3605 }
3606 }
3607 } else {
3608 size = vp8_context->frame_width_in_mbs * vp8_context->frame_height_in_mbs * 64;
3609
3610 i965_add_buffer_gpe_surface(ctx,
3611 gpe_context,
3612 &vp8_context->mb_coded_buffer,
3613 1,
3614 size,
3615 vp8_context->mv_offset,
3616 VP8_BTI_MBENC_IND_MV_DATA);
3617
3618 if (vp8_context->hme_enabled) {
3619 i965_add_buffer_2d_gpe_surface(ctx,
3620 gpe_context,
3621 &vp8_context->me_4x_mv_data_buffer,
3622 1,
3623 I965_SURFACEFORMAT_R8_UNORM,
3624 VP8_BTI_MBENC_MV_DATA_FROM_ME);
3625 }
3626
3627 i965_add_buffer_gpe_surface(ctx,
3628 gpe_context,
3629 &vp8_context->reference_frame_mb_count_buffer,
3630 0,
3631 32, /* sizeof(unsigned int) * 8 */
3632 0,
3633 VP8_BTI_MBENC_REF_MB_COUNT);
3634
3635 i965_add_adv_gpe_surface(ctx,
3636 gpe_context,
3637 encode_state->input_yuv_object,
3638 VP8_BTI_MBENC_INTER_PRED);
3639
3640 if (vp8_context->ref_last_frame &&
3641 vp8_context->ref_last_frame->bo) {
3642 obj_surface = vp8_context->ref_last_frame;
3643
3644 switch (vp8_context->ref_frame_ctrl) {
3645 case 1:
3646 case 3:
3647 case 5:
3648 case 7:
3649 i965_add_adv_gpe_surface(ctx,
3650 gpe_context,
3651 obj_surface,
3652 VP8_BTI_MBENC_REF1_PIC);
3653 break;
3654 }
3655 }
3656
3657 if (vp8_context->ref_gf_frame &&
3658 vp8_context->ref_gf_frame->bo) {
3659 obj_surface = vp8_context->ref_gf_frame;
3660
3661 switch (vp8_context->ref_frame_ctrl) {
3662 case 2:
3663 case 6:
3664 i965_add_adv_gpe_surface(ctx,
3665 gpe_context,
3666 obj_surface,
3667 VP8_BTI_MBENC_REF1_PIC);
3668 break;
3669
3670 case 3:
3671 case 7:
3672 i965_add_adv_gpe_surface(ctx,
3673 gpe_context,
3674 obj_surface,
3675 VP8_BTI_MBENC_REF2_PIC);
3676 break;
3677 }
3678 }
3679
3680 if (vp8_context->ref_arf_frame &&
3681 vp8_context->ref_arf_frame->bo) {
3682 obj_surface = vp8_context->ref_arf_frame;
3683
3684 switch (vp8_context->ref_frame_ctrl) {
3685 case 4:
3686 i965_add_adv_gpe_surface(ctx,
3687 gpe_context,
3688 obj_surface,
3689 VP8_BTI_MBENC_REF1_PIC);
3690 break;
3691
3692 case 5:
3693 case 6:
3694 i965_add_adv_gpe_surface(ctx,
3695 gpe_context,
3696 obj_surface,
3697 VP8_BTI_MBENC_REF2_PIC);
3698 break;
3699
3700 case 7:
3701 i965_add_adv_gpe_surface(ctx,
3702 gpe_context,
3703 obj_surface,
3704 VP8_BTI_MBENC_REF3_PIC);
3705 break;
3706 }
3707 }
3708
3709 i965_add_buffer_2d_gpe_surface(ctx,
3710 gpe_context,
3711 &vp8_context->per_mb_quant_data_buffer,
3712 1,
3713 I965_SURFACEFORMAT_R8_UNORM,
3714 VP8_BTI_MBENC_P_PER_MB_QUANT);
3715
3716 i965_add_buffer_2d_gpe_surface(ctx,
3717 gpe_context,
3718 &vp8_context->me_4x_distortion_buffer,
3719 0,
3720 I965_SURFACEFORMAT_R8_UNORM,
3721 VP8_BTI_MBENC_INTER_PRED_DISTORTION);
3722
3723 size = vp8_context->frame_width_in_mbs * vp8_context->frame_height_in_mbs * 16;
3724 i965_add_buffer_gpe_surface(ctx,
3725 gpe_context,
3726 &vp8_context->pred_mv_data_buffer,
3727 0,
3728 size,
3729 0,
3730 VP8_BTI_MBENC_PRED_MV_DATA);
3731
3732 size = 16 * sizeof(unsigned int);
3733 i965_add_buffer_gpe_surface(ctx,
3734 gpe_context,
3735 &vp8_context->mode_cost_update_buffer,
3736 1,
3737 size,
3738 0,
3739 VP8_BTI_MBENC_MODE_COST_UPDATE);
3740 }
3741 }
3742
3743 static void
i965_encoder_vp8_vme_mbenc_init_constant_buffer(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)3744 i965_encoder_vp8_vme_mbenc_init_constant_buffer(VADriverContextP ctx,
3745 struct encode_state *encode_state,
3746 struct intel_encoder_context *encoder_context)
3747 {
3748 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3749 char *pbuffer = NULL;
3750
3751 i965_zero_gpe_resource(&vp8_context->mb_mode_cost_luma_buffer);
3752 i965_zero_gpe_resource(&vp8_context->block_mode_cost_buffer);
3753
3754 pbuffer = i965_map_gpe_resource(&vp8_context->mb_mode_cost_luma_buffer);
3755
3756 if (!pbuffer)
3757 return;
3758
3759 memcpy(pbuffer, mb_mode_cost_luma_vp8, sizeof(mb_mode_cost_luma_vp8));
3760 i965_unmap_gpe_resource(&vp8_context->mb_mode_cost_luma_buffer);
3761
3762 pbuffer = i965_map_gpe_resource(&vp8_context->block_mode_cost_buffer);
3763
3764 if (!pbuffer)
3765 return;
3766
3767 memcpy(pbuffer, block_mode_cost_vp8, sizeof(block_mode_cost_vp8));
3768 i965_unmap_gpe_resource(&vp8_context->block_mode_cost_buffer);
3769 }
3770
3771 static VAStatus
i965_encoder_vp8_vme_mbenc(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,int is_phase2,int is_iframe_dist)3772 i965_encoder_vp8_vme_mbenc(VADriverContextP ctx,
3773 struct encode_state *encode_state,
3774 struct intel_encoder_context *encoder_context,
3775 int is_phase2,
3776 int is_iframe_dist)
3777 {
3778 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3779 struct i965_encoder_vp8_mbenc_context *mbenc_context = &vp8_context->mbenc_context;
3780 struct i965_gpe_table *gpe = vp8_context->gpe_table;
3781 struct i965_gpe_context *gpe_context;
3782 struct mbenc_surface_parameters mbenc_surface_params;
3783 struct gpe_media_object_walker_parameter media_object_walker_param;
3784 struct vp8_encoder_kernel_walker_parameter kernel_walker_param;
3785 int is_intra = (vp8_context->frame_type == MPEG_I_PICTURE);
3786 int gpe_index, media_function;
3787
3788 if (is_iframe_dist) {
3789 gpe_index = VP8_MBENC_I_FRAME_DIST;
3790 media_function = VP8_MEDIA_STATE_ENC_I_FRAME_DIST;
3791 } else if (!is_phase2) {
3792 if (is_intra) {
3793 gpe_index = VP8_MBENC_I_FRAME_LUMA;
3794 media_function = VP8_MEDIA_STATE_ENC_I_FRAME_LUMA;
3795 } else {
3796 gpe_index = VP8_MBENC_P_FRAME;
3797 media_function = VP8_MEDIA_STATE_ENC_P_FRAME;
3798 }
3799 } else {
3800 gpe_index = VP8_MBENC_I_FRAME_CHROMA;
3801 media_function = VP8_MEDIA_STATE_ENC_I_FRAME_CHROMA;
3802 }
3803
3804 gpe_context = &mbenc_context->gpe_contexts[gpe_index];
3805
3806 if (!is_phase2 || (is_phase2 && vp8_context->brc_mbenc_phase1_ignored)) {
3807 if (!vp8_context->mbenc_curbe_updated_in_brc_update || is_iframe_dist) {
3808 VAEncPictureParameterBufferVP8 *pic_param =
3809 (VAEncPictureParameterBufferVP8 *) encode_state->pic_param_ext->buffer;
3810 unsigned int ref_frame_flag_final, ref_frame_flag;
3811
3812 if (!vp8_context->ref_ctrl_optimization_done) {
3813 if (!is_intra) {
3814 ref_frame_flag = VP8_REF_FLAG_ALL;
3815
3816 if (pic_param->ref_last_frame == pic_param->ref_gf_frame) {
3817 ref_frame_flag &= ~VP8_REF_FLAG_GOLDEN;
3818 }
3819
3820 if (pic_param->ref_last_frame == pic_param->ref_arf_frame) {
3821 ref_frame_flag &= ~VP8_REF_FLAG_ALT;
3822 }
3823
3824 if (pic_param->ref_gf_frame == pic_param->ref_arf_frame) {
3825 ref_frame_flag &= ~VP8_REF_FLAG_ALT;
3826 }
3827 } else {
3828 ref_frame_flag = VP8_REF_FLAG_LAST;
3829 }
3830
3831 switch (vp8_context->ref_frame_ctrl) {
3832 case 0:
3833 ref_frame_flag_final = VP8_REF_FLAG_NONE;
3834 break;
3835
3836 case 1:
3837 ref_frame_flag_final = VP8_REF_FLAG_LAST;
3838 break;
3839
3840 case 2:
3841 ref_frame_flag_final = VP8_REF_FLAG_GOLDEN;
3842 break;
3843
3844 case 4:
3845 ref_frame_flag_final = VP8_REF_FLAG_ALT;
3846 break;
3847
3848 default:
3849 ref_frame_flag_final = ref_frame_flag;
3850 }
3851
3852 vp8_context->ref_frame_ctrl = ref_frame_flag_final;
3853 }
3854
3855 i965_encoder_vp8_vme_mbenc_set_curbe(ctx, encode_state, encoder_context, gpe_context);
3856 }
3857
3858 if (is_intra) {
3859 i965_encoder_vp8_vme_mbenc_init_constant_buffer(ctx, encode_state, encoder_context);
3860 }
3861
3862 if (vp8_context->brc_distortion_buffer_need_reset && is_iframe_dist) {
3863 i965_encoder_vp8_vme_init_brc_distorion_buffer(ctx, encoder_context);
3864 }
3865 }
3866
3867 if (!is_phase2 || (is_phase2 && vp8_context->brc_mbenc_phase1_ignored)) {
3868 i965_zero_gpe_resource(&vp8_context->histogram_buffer);
3869 }
3870
3871 gpe->reset_binding_table(ctx, gpe_context);
3872
3873 memset(&mbenc_surface_params, 0, sizeof(mbenc_surface_params));
3874 mbenc_surface_params.i_frame_dist_in_use = is_iframe_dist;
3875
3876 if (is_iframe_dist)
3877 mbenc_surface_params.me_brc_distortion_buffer = &vp8_context->brc_distortion_buffer;
3878 else
3879 mbenc_surface_params.me_brc_distortion_buffer = &vp8_context->me_4x_distortion_buffer;
3880
3881 i965_encoder_vp8_vme_mbenc_add_surfaces(ctx, encode_state, encoder_context, gpe_context, &mbenc_surface_params);
3882
3883 gpe->setup_interface_data(ctx, gpe_context);
3884
3885 memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
3886
3887 kernel_walker_param.use_scoreboard = vp8_context->use_hw_scoreboard;
3888
3889 if (is_iframe_dist) {
3890 kernel_walker_param.resolution_x = vp8_context->down_scaled_width_in_mb4x;
3891 kernel_walker_param.resolution_y = vp8_context->down_scaled_height_in_mb4x;
3892 } else {
3893 kernel_walker_param.resolution_x = vp8_context->frame_width_in_mbs;
3894 kernel_walker_param.resolution_y = vp8_context->frame_height_in_mbs;
3895 }
3896
3897 if (is_intra && !is_phase2)
3898 kernel_walker_param.no_dependency = 1;
3899 else
3900 kernel_walker_param.walker_degree = VP8_ENCODER_45_DEGREE;
3901
3902 i965_init_media_object_walker_parameters(encoder_context, &kernel_walker_param, &media_object_walker_param);
3903
3904 i965_run_kernel_media_object_walker(ctx, encoder_context, gpe_context, media_function, &media_object_walker_param);
3905
3906 return VA_STATUS_SUCCESS;
3907 }
3908
3909 static void
i965_encoder_vp8_vme_brc_update_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)3910 i965_encoder_vp8_vme_brc_update_set_curbe(VADriverContextP ctx,
3911 struct encode_state *encode_state,
3912 struct intel_encoder_context *encoder_context,
3913 struct i965_gpe_context *gpe_context)
3914 {
3915 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3916 struct vp8_brc_update_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
3917 VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
3918 VAQMatrixBufferVP8 *quant_param = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
3919 int is_intra = (vp8_context->frame_type == MPEG_I_PICTURE);
3920
3921 if (!pcmd)
3922 return;
3923
3924 memset(pcmd, 0, sizeof(*pcmd));
3925
3926 pcmd->dw2.picture_header_size = 0;
3927
3928 pcmd->dw3.start_global_adjust_frame0 = 10;
3929 pcmd->dw3.start_global_adjust_frame1 = 50;
3930
3931 pcmd->dw4.start_global_adjust_frame2 = 100;
3932 pcmd->dw4.start_global_adjust_frame3 = 150;
3933
3934 pcmd->dw5.target_size_flag = 0;
3935
3936 if (vp8_context->brc_init_current_target_buf_full_in_bits > (double)vp8_context->brc_init_reset_buf_size_in_bits) {
3937 vp8_context->brc_init_current_target_buf_full_in_bits -= (double)vp8_context->brc_init_reset_buf_size_in_bits;
3938 pcmd->dw5.target_size_flag = 1;
3939 }
3940
3941 pcmd->dw0.target_size = (unsigned int)vp8_context->brc_init_current_target_buf_full_in_bits;
3942
3943 pcmd->dw5.curr_frame_type = is_intra ? 2 : 0;
3944 pcmd->dw5.brc_flag = 16 * vp8_context->internal_rate_mode;
3945 pcmd->dw5.max_num_paks = vp8_context->num_brc_pak_passes;
3946
3947 pcmd->dw6.tid = 0;
3948 pcmd->dw6.num_t_levels = 1;
3949
3950 pcmd->dw8.start_global_adjust_mult0 = 1;
3951 pcmd->dw8.start_global_adjust_mult1 = 1;
3952 pcmd->dw8.start_global_adjust_mult2 = 3;
3953 pcmd->dw8.start_global_adjust_mult3 = 2;
3954
3955 pcmd->dw9.start_global_adjust_div0 = 40;
3956 pcmd->dw9.start_global_adjust_div1 = 5;
3957 pcmd->dw9.start_global_adjust_div2 = 5;
3958 pcmd->dw9.start_global_adjust_mult4 = 1;
3959
3960 pcmd->dw10.start_global_adjust_div3 = 3;
3961 pcmd->dw10.start_global_adjust_div4 = 1;
3962 pcmd->dw10.qp_threshold0 = 20;
3963 pcmd->dw10.qp_threshold1 = 40;
3964
3965 pcmd->dw11.qp_threshold2 = 60;
3966 pcmd->dw11.qp_threshold3 = 90;
3967 pcmd->dw11.g_rate_ratio_threshold0 = 40;
3968 pcmd->dw11.g_rate_ratio_threshold1 = 75;
3969
3970 pcmd->dw12.g_rate_ratio_threshold2 = 97;
3971 pcmd->dw12.g_rate_ratio_threshold3 = 103;
3972 pcmd->dw12.g_rate_ratio_threshold4 = 125;
3973 pcmd->dw12.g_rate_ratio_threshold5 = 160;
3974
3975 pcmd->dw13.g_rate_ratio_threshold_qp0 = -3;
3976 pcmd->dw13.g_rate_ratio_threshold_qp1 = -2;
3977 pcmd->dw13.g_rate_ratio_threshold_qp2 = -1;
3978 pcmd->dw13.g_rate_ratio_threshold_qp3 = 0;
3979
3980 pcmd->dw14.g_rate_ratio_threshold_qp4 = 1;
3981 pcmd->dw14.g_rate_ratio_threshold_qp5 = 2;
3982 pcmd->dw14.g_rate_ratio_threshold_qp6 = 3;
3983 pcmd->dw14.index_of_previous_qp = 0;
3984
3985 pcmd->dw15.frame_width_in_mb = vp8_context->frame_width_in_mbs;
3986 pcmd->dw15.frame_height_in_mb = vp8_context->frame_height_in_mbs;
3987
3988 pcmd->dw16.p_frame_qp_seg0 = quant_param->quantization_index[0];
3989 pcmd->dw16.p_frame_qp_seg1 = quant_param->quantization_index[1];
3990 pcmd->dw16.p_frame_qp_seg2 = quant_param->quantization_index[2];
3991 pcmd->dw16.p_frame_qp_seg3 = quant_param->quantization_index[3];
3992
3993 pcmd->dw17.key_frame_qp_seg0 = quant_param->quantization_index[0];
3994 pcmd->dw17.key_frame_qp_seg1 = quant_param->quantization_index[1];
3995 pcmd->dw17.key_frame_qp_seg2 = quant_param->quantization_index[2];
3996 pcmd->dw17.key_frame_qp_seg3 = quant_param->quantization_index[3];
3997
3998 pcmd->dw18.qdelta_plane0 = 0;
3999 pcmd->dw18.qdelta_plane1 = 0;
4000 pcmd->dw18.qdelta_plane2 = 0;
4001 pcmd->dw18.qdelta_plane3 = 0;
4002
4003 pcmd->dw19.qdelta_plane4 = 0;
4004 pcmd->dw19.main_ref = is_intra ? 0 : mainref_table_vp8[vp8_context->ref_frame_ctrl];
4005 pcmd->dw19.ref_frame_flags = is_intra ? 0 : vp8_context->ref_frame_ctrl;
4006
4007 pcmd->dw20.seg_on = pic_param->pic_flags.bits.segmentation_enabled;
4008 pcmd->dw20.brc_method = vp8_context->internal_rate_mode;
4009 pcmd->dw20.mb_rc = 0;
4010
4011 pcmd->dw20.vme_intra_prediction = (encoder_context->quality_level == ENCODER_LOW_QUALITY) ? 1 : 0;
4012
4013 pcmd->dw22.historyt_buffer_bti = VP8_BTI_BRC_UPDATE_HISTORY;
4014 pcmd->dw23.pak_statistics_bti = VP8_BTI_BRC_UPDATE_PAK_STATISTICS_OUTPUT;
4015 pcmd->dw24.mfx_vp8_encoder_cfg_read_bti = VP8_BTI_BRC_UPDATE_MFX_ENCODER_CFG_READ;
4016 pcmd->dw25.mfx_vp8_encoder_cfg_write_bti = VP8_BTI_BRC_UPDATE_MFX_ENCODER_CFG_WRITE;
4017 pcmd->dw26.mbenc_curbe_read_bti = VP8_BTI_BRC_UPDATE_MBENC_CURBE_READ;
4018 pcmd->dw27.mbenc_curbe_write_bti = VP8_BTI_BRC_UPDATE_MBENC_CURBE_WRITE;
4019 pcmd->dw28.distortion_bti = VP8_BTI_BRC_UPDATE_DISTORTION_SURFACE;
4020 pcmd->dw29.constant_data_bti = VP8_BTI_BRC_UPDATE_CONSTANT_DATA;
4021 pcmd->dw30.segment_map_bti = VP8_BTI_BRC_UPDATE_SEGMENT_MAP;
4022 pcmd->dw31.mpu_curbe_read_bti = VP8_BTI_BRC_UPDATE_MPU_CURBE_READ;
4023 pcmd->dw32.mpu_curbe_write_bti = VP8_BTI_BRC_UPDATE_MPU_CURBE_WRITE;
4024 pcmd->dw33.tpu_curbe_read_bti = VP8_BTI_BRC_UPDATE_TPU_CURBE_READ;
4025 pcmd->dw34.tpu_curbe_write_bti = VP8_BTI_BRC_UPDATE_TPU_CURBE_WRITE;
4026
4027 vp8_context->brc_init_current_target_buf_full_in_bits += vp8_context->brc_init_reset_input_bits_per_frame;
4028
4029 i965_gpe_context_unmap_curbe(gpe_context);
4030 }
4031
4032 static void
4033 i965_encoder_vp8_vme_mpu_set_curbe(VADriverContextP ctx,
4034 struct encode_state *encode_state,
4035 struct intel_encoder_context *encoder_context,
4036 struct i965_gpe_context *gpe_context);
4037 static void
4038 i965_encoder_vp8_pak_tpu_set_curbe(VADriverContextP ctx,
4039 struct encode_state *encode_state,
4040 struct intel_encoder_context *encoder_context,
4041 struct i965_gpe_context *gpe_context);
4042
4043 static void
i965_encoder_vp8_vme_brc_update_add_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,struct brc_update_surface_parameters * params)4044 i965_encoder_vp8_vme_brc_update_add_surfaces(VADriverContextP ctx,
4045 struct encode_state *encode_state,
4046 struct intel_encoder_context *encoder_context,
4047 struct i965_gpe_context *gpe_context,
4048 struct brc_update_surface_parameters *params)
4049 {
4050 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4051 unsigned int size;
4052 int is_intra = (vp8_context->frame_type == MPEG_I_PICTURE);
4053
4054 /* BRC history buffer */
4055 size = VP8_BRC_HISTORY_BUFFER_SIZE;
4056 i965_add_buffer_gpe_surface(ctx,
4057 gpe_context,
4058 &vp8_context->brc_history_buffer,
4059 0,
4060 size,
4061 0,
4062 VP8_BTI_BRC_UPDATE_HISTORY);
4063
4064 /* PAK Statistics buffer */
4065 size = sizeof(struct vp8_brc_pak_statistics);
4066 i965_add_buffer_gpe_surface(ctx,
4067 gpe_context,
4068 &vp8_context->brc_pak_statistics_buffer,
4069 0,
4070 size,
4071 0,
4072 VP8_BTI_BRC_UPDATE_PAK_STATISTICS_OUTPUT);
4073
4074 /* Encoder CFG command surface - read only */
4075 size = VP8_BRC_IMG_STATE_SIZE_PER_PASS * VP8_BRC_MAXIMUM_NUM_PASSES;
4076 i965_add_buffer_gpe_surface(ctx,
4077 gpe_context,
4078 &vp8_context->brc_vp8_cfg_command_write_buffer,
4079 0,
4080 size,
4081 0,
4082 VP8_BTI_BRC_UPDATE_MFX_ENCODER_CFG_READ);
4083
4084 /* Encoder CFG command surface - write only */
4085 i965_add_buffer_gpe_surface(ctx,
4086 gpe_context,
4087 &vp8_context->brc_vp8_cfg_command_write_buffer,
4088 0,
4089 size,
4090 0,
4091 VP8_BTI_BRC_UPDATE_MFX_ENCODER_CFG_WRITE);
4092
4093 /* MBEnc CURBE Buffer - read only */
4094 size = ALIGN(params->mbenc_gpe_context->curbe.length, 64);
4095 i965_add_dri_buffer_gpe_surface(ctx,
4096 encoder_context,
4097 gpe_context,
4098 params->mbenc_gpe_context->curbe.bo,
4099 0,
4100 size,
4101 params->mbenc_gpe_context->curbe.offset,
4102 VP8_BTI_BRC_UPDATE_MBENC_CURBE_READ);
4103
4104 /* MBEnc CURBE Buffer - write only */
4105 i965_add_dri_buffer_gpe_surface(ctx,
4106 encoder_context,
4107 gpe_context,
4108 params->mbenc_gpe_context->curbe.bo,
4109 0,
4110 size,
4111 params->mbenc_gpe_context->curbe.offset,
4112 VP8_BTI_BRC_UPDATE_MBENC_CURBE_WRITE);
4113
4114 /* BRC Distortion data buffer - input/output */
4115 i965_add_buffer_2d_gpe_surface(ctx,
4116 gpe_context,
4117 is_intra ? &vp8_context->brc_distortion_buffer : &vp8_context->me_4x_distortion_buffer,
4118 1,
4119 I965_SURFACEFORMAT_R8_UNORM,
4120 VP8_BTI_BRC_UPDATE_DISTORTION_SURFACE);
4121
4122 /* Constant Data Surface */
4123 size = VP8_BRC_CONSTANT_DATA_SIZE;
4124 i965_add_buffer_gpe_surface(ctx,
4125 gpe_context,
4126 &vp8_context->brc_vp8_constant_data_buffer,
4127 0,
4128 size,
4129 0,
4130 VP8_BTI_BRC_UPDATE_CONSTANT_DATA);
4131
4132 /* Segmap surface */
4133 i965_add_buffer_2d_gpe_surface(ctx,
4134 gpe_context,
4135 &vp8_context->brc_segment_map_buffer,
4136 0,
4137 I965_SURFACEFORMAT_R8_UNORM,
4138 VP8_BTI_BRC_UPDATE_SEGMENT_MAP);
4139
4140 /* MPU CURBE Buffer - read only */
4141 size = ALIGN(params->mpu_gpe_context->curbe.length, 64);
4142 i965_add_dri_buffer_gpe_surface(ctx,
4143 encoder_context,
4144 gpe_context,
4145 params->mpu_gpe_context->curbe.bo,
4146 0,
4147 size,
4148 params->mpu_gpe_context->curbe.offset,
4149 VP8_BTI_BRC_UPDATE_MPU_CURBE_READ);
4150
4151 /* MPU CURBE Buffer - write only */
4152 size = ALIGN(params->mpu_gpe_context->curbe.length, 64);
4153 i965_add_dri_buffer_gpe_surface(ctx,
4154 encoder_context,
4155 gpe_context,
4156 params->mpu_gpe_context->curbe.bo,
4157 0,
4158 size,
4159 params->mpu_gpe_context->curbe.offset,
4160 VP8_BTI_BRC_UPDATE_MPU_CURBE_WRITE);
4161
4162 /* TPU CURBE Buffer - read only */
4163 size = ALIGN(params->tpu_gpe_context->curbe.length, 64);
4164 i965_add_dri_buffer_gpe_surface(ctx,
4165 encoder_context,
4166 gpe_context,
4167 params->tpu_gpe_context->curbe.bo,
4168 0,
4169 size,
4170 params->tpu_gpe_context->curbe.offset,
4171 VP8_BTI_BRC_UPDATE_TPU_CURBE_READ);
4172
4173 /* TPU CURBE Buffer - write only */
4174 size = ALIGN(params->tpu_gpe_context->curbe.length, 64);
4175 i965_add_dri_buffer_gpe_surface(ctx,
4176 encoder_context,
4177 gpe_context,
4178 params->tpu_gpe_context->curbe.bo,
4179 0,
4180 size,
4181 params->tpu_gpe_context->curbe.offset,
4182 VP8_BTI_BRC_UPDATE_TPU_CURBE_WRITE);
4183 }
4184
4185 static void
i965_encoder_vp8_vme_init_brc_update_constant_data(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)4186 i965_encoder_vp8_vme_init_brc_update_constant_data(VADriverContextP ctx,
4187 struct encode_state *encode_state,
4188 struct intel_encoder_context *encoder_context)
4189 {
4190 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4191 char *pbuffer;
4192
4193 pbuffer = i965_map_gpe_resource(&vp8_context->brc_vp8_constant_data_buffer);
4194
4195 if (!pbuffer)
4196 return;
4197
4198 memcpy(pbuffer,
4199 brc_qpadjustment_distthreshold_maxframethreshold_distqpadjustment_ipb_vp8,
4200 sizeof(brc_qpadjustment_distthreshold_maxframethreshold_distqpadjustment_ipb_vp8));
4201 pbuffer += sizeof(brc_qpadjustment_distthreshold_maxframethreshold_distqpadjustment_ipb_vp8);
4202
4203 memcpy(pbuffer, brc_iframe_cost_vp8, sizeof(brc_iframe_cost_vp8));
4204 pbuffer += sizeof(brc_iframe_cost_vp8);
4205
4206 memcpy(pbuffer, brc_pframe_cost_vp8, sizeof(brc_pframe_cost_vp8));
4207 pbuffer += sizeof(brc_pframe_cost_vp8);
4208
4209 memcpy(pbuffer, quant_dc_vp8, sizeof(quant_dc_vp8));
4210 pbuffer += sizeof(quant_dc_vp8);
4211
4212 memcpy(pbuffer, quant_ac_vp8, sizeof(quant_ac_vp8));
4213 pbuffer += sizeof(quant_ac_vp8);
4214
4215 memcpy(pbuffer, brc_skip_mv_threshold_vp8, sizeof(brc_skip_mv_threshold_vp8));
4216
4217 i965_unmap_gpe_resource(&vp8_context->brc_vp8_constant_data_buffer);
4218 }
4219
4220 static void
4221 i965_encoder_vp8_vme_init_mfx_config_command(VADriverContextP ctx,
4222 struct encode_state *encode_state,
4223 struct intel_encoder_context *encoder_context,
4224 struct vp8_mpu_encoder_config_parameters *params);
4225
4226 static VAStatus
i965_encoder_vp8_vme_brc_update(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)4227 i965_encoder_vp8_vme_brc_update(VADriverContextP ctx,
4228 struct encode_state *encode_state,
4229 struct intel_encoder_context *encoder_context)
4230 {
4231 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4232 struct i965_encoder_vp8_brc_update_context *brc_update_context = &vp8_context->brc_update_context;
4233 struct i965_encoder_vp8_mbenc_context *mbenc_context = &vp8_context->mbenc_context;
4234 struct i965_encoder_vp8_mpu_context *mpu_context = &vp8_context->mpu_context;
4235 struct i965_encoder_vp8_tpu_context *tpu_context = &vp8_context->tpu_context;
4236 struct i965_gpe_table *gpe = vp8_context->gpe_table;
4237 struct i965_gpe_context *gpe_context, *mbenc_gpe_context, *mpu_gpe_context, *tpu_gpe_context;
4238 struct brc_update_surface_parameters brc_update_surface_params;
4239 struct gpe_media_object_parameter media_object_param;
4240 struct vp8_mpu_encoder_config_parameters config_params;
4241 VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
4242 unsigned int ref_frame_flag_final, ref_frame_flag;
4243 int is_intra = (vp8_context->frame_type == MPEG_I_PICTURE);
4244 int media_function = VP8_MEDIA_STATE_BRC_UPDATE;
4245 int i;
4246
4247 gpe_context = &brc_update_context->gpe_contexts[0];
4248
4249 if (is_intra)
4250 mbenc_gpe_context = &mbenc_context->gpe_contexts[VP8_MBENC_I_FRAME_LUMA];
4251 else
4252 mbenc_gpe_context = &mbenc_context->gpe_contexts[VP8_MBENC_P_FRAME];
4253
4254 mpu_gpe_context = &mpu_context->gpe_contexts[0];
4255 tpu_gpe_context = &tpu_context->gpe_contexts[0];
4256
4257 if (!is_intra) {
4258 ref_frame_flag = VP8_REF_FLAG_ALL;
4259
4260 if (pic_param->ref_last_frame == pic_param->ref_gf_frame) {
4261 ref_frame_flag &= ~VP8_REF_FLAG_GOLDEN;
4262 }
4263
4264 if (pic_param->ref_last_frame == pic_param->ref_arf_frame) {
4265 ref_frame_flag &= ~VP8_REF_FLAG_ALT;
4266 }
4267
4268 if (pic_param->ref_gf_frame == pic_param->ref_arf_frame) {
4269 ref_frame_flag &= ~VP8_REF_FLAG_ALT;
4270 }
4271 } else {
4272 ref_frame_flag = VP8_REF_FLAG_LAST;
4273 }
4274
4275 switch (vp8_context->ref_frame_ctrl) {
4276 case 0:
4277 ref_frame_flag_final = VP8_REF_FLAG_NONE;
4278 break;
4279
4280 case 1:
4281 ref_frame_flag_final = VP8_REF_FLAG_LAST; // Last Ref only
4282 break;
4283
4284 case 2:
4285 ref_frame_flag_final = VP8_REF_FLAG_GOLDEN; // Gold Ref only
4286 break;
4287
4288 case 4:
4289 ref_frame_flag_final = VP8_REF_FLAG_ALT; // Alt Ref only
4290 break;
4291
4292 default:
4293 ref_frame_flag_final = ref_frame_flag;
4294 }
4295
4296 vp8_context->ref_frame_ctrl = ref_frame_flag_final;
4297 i965_encoder_vp8_vme_mbenc_set_curbe(ctx, encode_state, encoder_context, mbenc_gpe_context);
4298 vp8_context->mbenc_curbe_updated_in_brc_update = 1;
4299
4300 /* Set MPU & TPU curbe here */
4301 i965_encoder_vp8_vme_mpu_set_curbe(ctx, encode_state, encoder_context, mpu_gpe_context);
4302 vp8_context->mpu_curbe_updated_in_brc_update = 1;
4303
4304 i965_encoder_vp8_pak_tpu_set_curbe(ctx, encode_state, encoder_context, tpu_gpe_context);
4305 vp8_context->tpu_curbe_updated_in_brc_update = 1;
4306
4307 gpe->context_init(ctx, gpe_context);
4308 gpe->reset_binding_table(ctx, gpe_context);
4309
4310 i965_encoder_vp8_vme_brc_update_set_curbe(ctx, encode_state, encoder_context, gpe_context);
4311
4312 if (vp8_context->brc_constant_buffer_supported) {
4313 i965_encoder_vp8_vme_init_brc_update_constant_data(ctx, encode_state, encoder_context);
4314 }
4315
4316 memset(&config_params, 0, sizeof(config_params));
4317 config_params.buffer_size = VP8_HEADER_METADATA_SIZE;
4318 config_params.config_buffer = &vp8_context->brc_vp8_cfg_command_write_buffer;
4319
4320 for (i = 0; i < VP8_BRC_MAXIMUM_NUM_PASSES; i++) {
4321 config_params.is_first_pass = !i;
4322 config_params.command_offset = i * VP8_HEADER_METADATA_SIZE;
4323 i965_encoder_vp8_vme_init_mfx_config_command(ctx, encode_state, encoder_context, &config_params);
4324 }
4325
4326 vp8_context->mfx_encoder_config_command_initialized = 1;
4327
4328 memset(&brc_update_surface_params, 0, sizeof(brc_update_surface_params));
4329 brc_update_surface_params.mbenc_gpe_context = mbenc_gpe_context;
4330 brc_update_surface_params.mpu_gpe_context = mpu_gpe_context;
4331 brc_update_surface_params.tpu_gpe_context = tpu_gpe_context;
4332 i965_encoder_vp8_vme_brc_update_add_surfaces(ctx, encode_state, encoder_context, gpe_context, &brc_update_surface_params);
4333
4334 gpe->setup_interface_data(ctx, gpe_context);
4335
4336 memset(&media_object_param, 0, sizeof(media_object_param));
4337 i965_run_kernel_media_object(ctx, encoder_context, gpe_context, media_function, &media_object_param);
4338
4339 return VA_STATUS_SUCCESS;
4340 }
4341
4342 static void
i965_encoder_vp8_vme_mpu_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)4343 i965_encoder_vp8_vme_mpu_set_curbe(VADriverContextP ctx,
4344 struct encode_state *encode_state,
4345 struct intel_encoder_context *encoder_context,
4346 struct i965_gpe_context *gpe_context)
4347 {
4348 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4349 struct vp8_mpu_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
4350 VAEncSequenceParameterBufferVP8 *seq_param = (VAEncSequenceParameterBufferVP8 *)encode_state->seq_param_ext->buffer;
4351 VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
4352 VAQMatrixBufferVP8 *quant_param = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
4353
4354 if (!pcmd)
4355 return;
4356
4357 memset(pcmd, 0, sizeof(*pcmd));
4358
4359 pcmd->dw0.frame_width = vp8_context->frame_width;
4360 pcmd->dw0.frame_height = vp8_context->frame_height;
4361
4362 pcmd->dw1.frame_type = pic_param->pic_flags.bits.frame_type;
4363 pcmd->dw1.version = pic_param->pic_flags.bits.version;
4364 pcmd->dw1.show_frame = pic_param->pic_flags.bits.show_frame;
4365 pcmd->dw1.horizontal_scale_code = seq_param->frame_width_scale;
4366 pcmd->dw1.vertical_scale_code = seq_param->frame_height_scale;
4367 pcmd->dw1.color_space_type = pic_param->pic_flags.bits.color_space;
4368 pcmd->dw1.clamp_type = pic_param->pic_flags.bits.clamping_type;
4369 pcmd->dw1.partition_num_l2 = pic_param->pic_flags.bits.num_token_partitions;
4370 pcmd->dw1.enable_segmentation = pic_param->pic_flags.bits.segmentation_enabled;
4371 pcmd->dw1.seg_map_update = pic_param->pic_flags.bits.segmentation_enabled ? pic_param->pic_flags.bits.update_mb_segmentation_map : 0;
4372 pcmd->dw1.segmentation_feature_update = pic_param->pic_flags.bits.update_segment_feature_data;
4373 pcmd->dw1.segmentation_feature_mode = 1;
4374 pcmd->dw1.loop_filter_type = pic_param->pic_flags.bits.loop_filter_type;
4375 pcmd->dw1.sharpness_level = pic_param->sharpness_level;
4376 pcmd->dw1.loop_filter_adjustment_on = pic_param->pic_flags.bits.loop_filter_adj_enable;
4377 pcmd->dw1.mb_no_coeffiscient_skip = pic_param->pic_flags.bits.mb_no_coeff_skip;
4378 pcmd->dw1.golden_reference_copy_flag = ((pic_param->pic_flags.bits.refresh_golden_frame == 1) ? 3 : pic_param->pic_flags.bits.copy_buffer_to_golden);
4379 pcmd->dw1.alternate_reference_copy_flag = ((pic_param->pic_flags.bits.refresh_alternate_frame == 1) ? 3 : pic_param->pic_flags.bits.copy_buffer_to_alternate);
4380 pcmd->dw1.last_frame_update = pic_param->pic_flags.bits.refresh_last;
4381 pcmd->dw1.sign_bias_golden = pic_param->pic_flags.bits.sign_bias_golden;
4382 pcmd->dw1.sign_bias_alt_ref = pic_param->pic_flags.bits.sign_bias_alternate;
4383 pcmd->dw1.refresh_entropy_p = pic_param->pic_flags.bits.refresh_entropy_probs;
4384 pcmd->dw1.forced_lf_update_for_key_frame = pic_param->pic_flags.bits.forced_lf_adjustment;
4385
4386 pcmd->dw2.loop_filter_level = pic_param->loop_filter_level[0];
4387 pcmd->dw2.qindex = quant_param->quantization_index[0];
4388 pcmd->dw2.y1_dc_qindex = quant_param->quantization_index_delta[0];
4389 pcmd->dw2.y2_dc_qindex = quant_param->quantization_index_delta[3];
4390
4391 pcmd->dw3.y2_ac_qindex = quant_param->quantization_index_delta[4];
4392 pcmd->dw3.uv_dc_qindex = quant_param->quantization_index_delta[1];
4393 pcmd->dw3.uv_ac_qindex = quant_param->quantization_index_delta[2];
4394 pcmd->dw3.feature_data0_segment0 = quant_param->quantization_index[0];
4395
4396 pcmd->dw4.feature_data0_segment1 = quant_param->quantization_index[1];
4397 pcmd->dw4.feature_data0_segment2 = quant_param->quantization_index[2];
4398 pcmd->dw4.feature_data0_segment3 = quant_param->quantization_index[3];
4399 pcmd->dw4.feature_data1_segment0 = pic_param->loop_filter_level[0];
4400
4401 pcmd->dw5.feature_data1_segment1 = pic_param->loop_filter_level[1];
4402 pcmd->dw5.feature_data1_segment2 = pic_param->loop_filter_level[2];
4403 pcmd->dw5.feature_data1_segment3 = pic_param->loop_filter_level[3];
4404 pcmd->dw5.ref_lf_delta0 = pic_param->ref_lf_delta[0];
4405
4406 pcmd->dw6.ref_lf_delta1 = pic_param->ref_lf_delta[1];
4407 pcmd->dw6.ref_lf_delta2 = pic_param->ref_lf_delta[2];
4408 pcmd->dw6.ref_lf_delta3 = pic_param->ref_lf_delta[3];
4409 pcmd->dw6.mode_lf_delta0 = pic_param->mode_lf_delta[0];
4410
4411 pcmd->dw7.mode_lf_delta1 = pic_param->mode_lf_delta[1];
4412 pcmd->dw7.mode_lf_delta2 = pic_param->mode_lf_delta[2];
4413 pcmd->dw7.mode_lf_delta3 = pic_param->mode_lf_delta[3];
4414 pcmd->dw7.mc_filter_select = pic_param->pic_flags.bits.version > 0 ? 1 : 0;
4415 pcmd->dw7.chroma_full_pixel_mc_filter_mode = pic_param->pic_flags.bits.version < 3 ? 0 : 1;
4416 pcmd->dw7.max_num_pak_passes = vp8_context->num_brc_pak_passes;
4417 pcmd->dw7.forced_token_surface_read = 1;
4418 pcmd->dw7.mode_cost_enable_flag = 1;
4419
4420 pcmd->dw8.num_t_levels = 1;
4421 pcmd->dw8.temporal_layer_id = 0;
4422
4423 pcmd->dw12.histogram_bti = VP8_BTI_MPU_HISTOGRAM;
4424 pcmd->dw13.reference_mode_probability_bti = VP8_BTI_MPU_REF_MODE_PROBABILITY;
4425 pcmd->dw14.mode_probability_bti = VP8_BTI_MPU_CURR_MODE_PROBABILITY;
4426 pcmd->dw15.reference_token_probability_bti = VP8_BTI_MPU_REF_TOKEN_PROBABILITY;
4427 pcmd->dw16.token_probability_bti = VP8_BTI_MPU_CURR_TOKEN_PROBABILITY;
4428 pcmd->dw17.frame_header_bitstream_bti = VP8_BTI_MPU_HEADER_BITSTREAM;
4429 pcmd->dw18.header_meta_data_bti = VP8_BTI_MPU_HEADER_METADATA;
4430 pcmd->dw19.picture_state_bti = VP8_BTI_MPU_PICTURE_STATE;
4431 pcmd->dw20.mpu_bitstream_bti = VP8_BTI_MPU_MPU_BITSTREAM;
4432 pcmd->dw21.token_bits_data_bti = VP8_BTI_MPU_TOKEN_BITS_DATA_TABLE;
4433 pcmd->dw22.kernel_debug_dump_bti = VP8_BTI_MPU_VME_DEBUG_STREAMOUT;
4434 pcmd->dw23.entropy_cost_bti = VP8_BTI_MPU_ENTROPY_COST_TABLE;
4435 pcmd->dw24.mode_cost_update_bti = VP8_BTI_MPU_MODE_COST_UPDATE;
4436
4437 i965_gpe_context_unmap_curbe(gpe_context);
4438 }
4439
4440 static void
i965_encoder_vp8_vme_mpu_add_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)4441 i965_encoder_vp8_vme_mpu_add_surfaces(VADriverContextP ctx,
4442 struct encode_state *encode_state,
4443 struct intel_encoder_context *encoder_context,
4444 struct i965_gpe_context *gpe_context)
4445 {
4446 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4447 unsigned int size;
4448 unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
4449 vp8_context->internal_rate_mode == I965_BRC_VBR);
4450
4451 /* Histogram buffer */
4452 size = VP8_HISTOGRAM_SIZE;
4453 i965_add_buffer_gpe_surface(ctx,
4454 gpe_context,
4455 &vp8_context->histogram_buffer,
4456 1,
4457 size,
4458 0,
4459 VP8_BTI_MPU_HISTOGRAM);
4460
4461 // Reference mode probability
4462 size = VP8_MODE_PROPABILITIES_SIZE;
4463 i965_add_buffer_gpe_surface(ctx,
4464 gpe_context,
4465 &vp8_context->pak_mpu_tpu_ref_mode_probs_buffer,
4466 1,
4467 size,
4468 0,
4469 VP8_BTI_MPU_REF_MODE_PROBABILITY);
4470
4471 // Mode probability
4472 i965_add_buffer_gpe_surface(ctx,
4473 gpe_context,
4474 &vp8_context->pak_mpu_tpu_mode_probs_buffer,
4475 1,
4476 size,
4477 0,
4478 VP8_BTI_MPU_CURR_MODE_PROBABILITY);
4479
4480 // Reference Token probability
4481 size = VP8_COEFFS_PROPABILITIES_SIZE;
4482 i965_add_buffer_gpe_surface(ctx,
4483 gpe_context,
4484 &vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer,
4485 1,
4486 size,
4487 0,
4488 VP8_BTI_MPU_REF_TOKEN_PROBABILITY);
4489
4490 // Token probability
4491 i965_add_buffer_gpe_surface(ctx,
4492 gpe_context,
4493 &vp8_context->pak_mpu_tpu_coeff_probs_buffer,
4494 1,
4495 size,
4496 0,
4497 VP8_BTI_MPU_CURR_TOKEN_PROBABILITY);
4498
4499 // Frame header
4500 size = VP8_FRAME_HEADER_SIZE;
4501 i965_add_buffer_gpe_surface(ctx,
4502 gpe_context,
4503 &vp8_context->pak_frame_header_buffer,
4504 0,
4505 size,
4506 0,
4507 VP8_BTI_MPU_HEADER_BITSTREAM);
4508
4509 // Header Metadata
4510 size = VP8_HEADER_METADATA_SIZE;
4511
4512 if (brc_enabled) {
4513 i965_add_buffer_gpe_surface(ctx,
4514 gpe_context,
4515 &vp8_context->brc_vp8_cfg_command_write_buffer,
4516 0,
4517 size,
4518 0,
4519 VP8_BTI_MPU_HEADER_METADATA);
4520 } else {
4521 i965_add_buffer_gpe_surface(ctx,
4522 gpe_context,
4523 &vp8_context->pak_mpu_tpu_picture_state_buffer,
4524 0,
4525 size,
4526 VP8_HEADER_METADATA_OFFSET,
4527 VP8_BTI_MPU_HEADER_METADATA);
4528 }
4529
4530 // Picture state MFX_VP8_PIC_STATE
4531 size = 38 * sizeof(unsigned int);
4532 i965_add_buffer_gpe_surface(ctx,
4533 gpe_context,
4534 &vp8_context->pak_mpu_tpu_picture_state_buffer,
4535 0,
4536 size,
4537 0,
4538 VP8_BTI_MPU_PICTURE_STATE);
4539
4540 // Mpu Bitstream
4541 size = VP8_MPU_BITSTREAM_SIZE;
4542 i965_add_buffer_gpe_surface(ctx,
4543 gpe_context,
4544 &vp8_context->pak_mpu_tpu_mpu_bitstream_buffer,
4545 0,
4546 size,
4547 0,
4548 VP8_BTI_MPU_MPU_BITSTREAM);
4549
4550 // Token bits Data Surface
4551 size = VP8_TOKEN_BITS_DATA_SIZE;
4552 i965_add_buffer_gpe_surface(ctx,
4553 gpe_context,
4554 &vp8_context->pak_mpu_tpu_token_bits_data_buffer,
4555 1,
4556 size,
4557 0,
4558 VP8_BTI_MPU_TOKEN_BITS_DATA_TABLE);
4559
4560 // Entropy cost table
4561 size = VP8_ENTROPY_COST_TABLE_SIZE;
4562 i965_add_buffer_gpe_surface(ctx,
4563 gpe_context,
4564 &vp8_context->pak_mpu_tpu_entropy_cost_table_buffer,
4565 1,
4566 size,
4567 0,
4568 VP8_BTI_MPU_ENTROPY_COST_TABLE);
4569
4570 //Mode Cost Update Surface
4571 size = 16 * sizeof(unsigned int);
4572 i965_add_buffer_gpe_surface(ctx,
4573 gpe_context,
4574 &vp8_context->mode_cost_update_buffer,
4575 0,
4576 size,
4577 0,
4578 VP8_BTI_MPU_MODE_COST_UPDATE);
4579 }
4580
4581 static void
i965_encoder_vp8_vme_update_key_frame_mpu_tpu_buffer(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)4582 i965_encoder_vp8_vme_update_key_frame_mpu_tpu_buffer(VADriverContextP ctx,
4583 struct encode_state *encode_state,
4584 struct intel_encoder_context *encoder_context)
4585 {
4586 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4587 char *key_buffer, *pbuffer;
4588
4589 key_buffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer);
4590
4591 if (!key_buffer)
4592 return;
4593
4594 pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_coeff_probs_buffer);
4595
4596 if (!pbuffer) {
4597 i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer);
4598
4599 return;
4600 }
4601
4602 memcpy(pbuffer, key_buffer, VP8_COEFFS_PROPABILITIES_SIZE);
4603 i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_coeff_probs_buffer);
4604 i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer);
4605
4606 pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer);
4607
4608 if (!pbuffer)
4609 return;
4610
4611 memcpy(pbuffer, vp8_default_coef_probs, sizeof(vp8_default_coef_probs));
4612 i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer);
4613
4614 pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_hw_token_probability_pak_pass_2_buffer);
4615
4616 if (!pbuffer)
4617 return;
4618
4619 memcpy(pbuffer, vp8_default_coef_probs, sizeof(vp8_default_coef_probs));
4620 i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_hw_token_probability_pak_pass_2_buffer);
4621 }
4622
4623 static void
i965_encoder_vp8_vme_init_mfx_config_command(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct vp8_mpu_encoder_config_parameters * params)4624 i965_encoder_vp8_vme_init_mfx_config_command(VADriverContextP ctx,
4625 struct encode_state *encode_state,
4626 struct intel_encoder_context *encoder_context,
4627 struct vp8_mpu_encoder_config_parameters *params)
4628 {
4629 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4630 struct vp8_mfx_encoder_cfg_cmd *pcmd;
4631 VAEncSequenceParameterBufferVP8 *seq_param = (VAEncSequenceParameterBufferVP8 *)encode_state->seq_param_ext->buffer;
4632 VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
4633 VAQMatrixBufferVP8 *quant_param = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
4634 unsigned int segmentation_enabled = pic_param->pic_flags.bits.segmentation_enabled;
4635 int i;
4636 char *pbuffer;
4637 unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
4638 vp8_context->internal_rate_mode == I965_BRC_VBR);
4639
4640 pbuffer = i965_map_gpe_resource(params->config_buffer);
4641
4642 if (!pbuffer)
4643 return;
4644
4645 pbuffer += params->command_offset;
4646 memset(pbuffer, 0, params->buffer_size);
4647
4648 pcmd = (struct vp8_mfx_encoder_cfg_cmd *)pbuffer;
4649
4650 pcmd->dw0.value = (MFX_VP8_ENCODER_CFG | (sizeof(*pcmd) / 4 - 2));
4651
4652 pcmd->dw1.rate_control_initial_pass = params->is_first_pass ? 1 : 0;
4653 pcmd->dw1.per_segment_delta_qindex_loop_filter_disable = (params->is_first_pass || !brc_enabled);
4654 pcmd->dw1.token_statistics_output_enable = 1;
4655
4656 if (segmentation_enabled) {
4657 for (i = 1; i < 4; i++) {
4658 if ((quant_param->quantization_index[i] != quant_param->quantization_index[0]) ||
4659 (pic_param->loop_filter_level[i] != pic_param->loop_filter_level[0])) {
4660 pcmd->dw1.update_segment_feature_data_flag = 1;
4661 break;
4662 }
4663 }
4664 }
4665
4666 if (brc_enabled) {
4667 pcmd->dw2.max_frame_bit_count_rate_control_enable_mask = 1;
4668 pcmd->dw2.min_frame_bit_count_rate_control_enable_mask = 1;
4669 }
4670
4671 pcmd->dw22.show_frame = pic_param->pic_flags.bits.show_frame;
4672 pcmd->dw22.bitstream_format_version = pic_param->pic_flags.bits.version;
4673
4674 pcmd->dw23.horizontal_size_code = ((seq_param->frame_width_scale << 14) | seq_param->frame_width);
4675 pcmd->dw23.vertical_size_code = ((seq_param->frame_height_scale << 14) | seq_param->frame_height);
4676
4677 //Add batch buffer end command
4678 pbuffer += sizeof(*pcmd);
4679 *((unsigned int *)pbuffer) = MI_BATCH_BUFFER_END;
4680
4681 i965_unmap_gpe_resource(params->config_buffer);
4682 }
4683
4684 static VAStatus
i965_encoder_vp8_vme_mpu(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)4685 i965_encoder_vp8_vme_mpu(VADriverContextP ctx,
4686 struct encode_state *encode_state,
4687 struct intel_encoder_context *encoder_context)
4688 {
4689 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4690 struct i965_encoder_vp8_mpu_context *mpu_context = &vp8_context->mpu_context;
4691 struct i965_gpe_table *gpe = vp8_context->gpe_table;
4692 struct gpe_media_object_parameter media_object_param;
4693 struct i965_gpe_context *gpe_context;
4694 struct vp8_mpu_encoder_config_parameters config_params;
4695 int media_function = VP8_MEDIA_STATE_MPU;
4696
4697 gpe_context = &mpu_context->gpe_contexts[0];
4698 /* gpe->context_init(ctx, gpe_context); */
4699 gpe->reset_binding_table(ctx, gpe_context);
4700
4701 if (vp8_context->frame_type == MPEG_I_PICTURE)
4702 i965_encoder_vp8_vme_update_key_frame_mpu_tpu_buffer(ctx, encode_state, encoder_context);
4703
4704 if (!vp8_context->mfx_encoder_config_command_initialized) {
4705 memset(&config_params, 0, sizeof(config_params));
4706 config_params.is_first_pass = !vp8_context->curr_pass;
4707 config_params.command_offset = VP8_HEADER_METADATA_OFFSET;
4708 config_params.buffer_size = VP8_PICTURE_STATE_SIZE;
4709 config_params.config_buffer = &vp8_context->pak_mpu_tpu_picture_state_buffer;
4710 i965_encoder_vp8_vme_init_mfx_config_command(ctx, encode_state, encoder_context, &config_params);
4711 }
4712
4713 if (!vp8_context->mpu_curbe_updated_in_brc_update)
4714 i965_encoder_vp8_vme_mpu_set_curbe(ctx, encode_state, encoder_context, gpe_context);
4715
4716 i965_encoder_vp8_vme_mpu_add_surfaces(ctx, encode_state, encoder_context, gpe_context);
4717 gpe->setup_interface_data(ctx, gpe_context);
4718
4719 memset(&media_object_param, 0, sizeof(media_object_param));
4720 i965_run_kernel_media_object(ctx, encoder_context, gpe_context, media_function, &media_object_param);
4721
4722 return VA_STATUS_SUCCESS;
4723 }
4724
4725 static VAStatus
i965_encoder_vp8_vme_gpe_kernel_function(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)4726 i965_encoder_vp8_vme_gpe_kernel_function(VADriverContextP ctx,
4727 struct encode_state *encode_state,
4728 struct intel_encoder_context *encoder_context)
4729 {
4730 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4731 int is_intra = (vp8_context->frame_type == MPEG_I_PICTURE);
4732 unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
4733 vp8_context->internal_rate_mode == I965_BRC_VBR);
4734 unsigned char scaling_enabled = vp8_context->hme_supported;
4735 unsigned char scaling_16x_enabled = vp8_context->hme_16x_supported;
4736 unsigned char hme_enabled = vp8_context->hme_enabled;
4737 unsigned char hme_16x_enabled = vp8_context->hme_16x_enabled;
4738
4739 if (brc_enabled) {
4740 if (!vp8_context->brc_initted || vp8_context->brc_need_reset) {
4741 i965_encoder_vp8_vme_brc_init_reset(ctx, encode_state, encoder_context);
4742 }
4743 }
4744
4745 if (scaling_enabled) {
4746 i965_encoder_vp8_vme_scaling(ctx, encode_state, encoder_context, 0);
4747
4748 if (scaling_16x_enabled)
4749 i965_encoder_vp8_vme_scaling(ctx, encode_state, encoder_context, 1);
4750 }
4751
4752 if (hme_enabled) {
4753 if (hme_16x_enabled)
4754 i965_encoder_vp8_vme_me(ctx, encode_state, encoder_context, 1);
4755
4756 i965_encoder_vp8_vme_me(ctx, encode_state, encoder_context, 0);
4757 }
4758
4759 if (brc_enabled) {
4760 if (is_intra) {
4761 i965_encoder_vp8_vme_mbenc(ctx, encode_state, encoder_context, 0, 1);
4762 }
4763
4764 i965_encoder_vp8_vme_brc_update(ctx, encode_state, encoder_context);
4765 }
4766
4767 vp8_context->brc_initted = 1;
4768 vp8_context->brc_mbenc_phase1_ignored = 0;
4769
4770 if (is_intra && encoder_context->quality_level == ENCODER_LOW_QUALITY) {
4771 vp8_context->brc_mbenc_phase1_ignored = 1;
4772 } else {
4773 i965_encoder_vp8_vme_mbenc(ctx, encode_state, encoder_context, 0, 0);
4774 }
4775
4776 if (is_intra) {
4777 i965_encoder_vp8_vme_mbenc(ctx, encode_state, encoder_context, 1, 0);
4778 }
4779
4780 i965_encoder_vp8_vme_mpu(ctx, encode_state, encoder_context);
4781
4782 return VA_STATUS_SUCCESS;
4783 }
4784
4785 static VAStatus
i965_encoder_vp8_vme_gpe_kernel_final(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)4786 i965_encoder_vp8_vme_gpe_kernel_final(VADriverContextP ctx,
4787 struct encode_state *encode_state,
4788 struct intel_encoder_context *encoder_context)
4789 {
4790 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4791 struct i965_encoder_vp8_mbenc_context *mbenc_context = &vp8_context->mbenc_context;
4792 struct i965_encoder_vp8_mpu_context *mpu_context = &vp8_context->mpu_context;
4793
4794 dri_bo_unreference(mbenc_context->luma_chroma_dynamic_buffer);
4795 mbenc_context->luma_chroma_dynamic_buffer = NULL;
4796
4797 dri_bo_unreference(mpu_context->dynamic_buffer);
4798 mpu_context->dynamic_buffer = NULL;
4799
4800 return VA_STATUS_SUCCESS;
4801 }
4802
4803 static void
i965_encoder_vp8_vme_set_status_buffer(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)4804 i965_encoder_vp8_vme_set_status_buffer(VADriverContextP ctx,
4805 struct encode_state *encode_state,
4806 struct intel_encoder_context *encoder_context)
4807 {
4808 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4809 struct i965_encoder_vp8_encode_status_buffer *encode_status_buffer = &vp8_context->encode_status_buffer;
4810 struct vp8_encode_status *encode_status;
4811 char *pbuffer;
4812
4813 dri_bo_unreference(encode_status_buffer->bo);
4814 encode_status_buffer->bo = encode_state->coded_buf_object->buffer_store->bo;
4815 dri_bo_reference(encode_status_buffer->bo);
4816
4817 encode_status_buffer->base_offset = offsetof(struct i965_coded_buffer_segment, codec_private_data);
4818 encode_status_buffer->size = ALIGN(sizeof(struct vp8_encode_status), sizeof(unsigned int) * 2);
4819
4820 encode_status_buffer->bitstream_byte_count_offset = offsetof(struct vp8_encode_status, bitstream_byte_count_per_frame);
4821 encode_status_buffer->image_status_mask_offset = offsetof(struct vp8_encode_status, image_status_mask);
4822 encode_status_buffer->image_status_ctrl_offset = offsetof(struct vp8_encode_status, image_status_ctrl);
4823
4824 dri_bo_map(encode_status_buffer->bo, 1);
4825
4826 if (!encode_status_buffer->bo->virtual)
4827 return;
4828
4829 pbuffer = encode_status_buffer->bo->virtual;
4830 pbuffer += encode_status_buffer->base_offset;
4831 encode_status = (struct vp8_encode_status *)pbuffer;
4832 memset(encode_status, 0, sizeof(*encode_status));
4833
4834 dri_bo_unmap(encode_status_buffer->bo);
4835 }
4836
4837 static VAStatus
i965_encoder_vp8_vme_pipeline(VADriverContextP ctx,VAProfile profile,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)4838 i965_encoder_vp8_vme_pipeline(VADriverContextP ctx,
4839 VAProfile profile,
4840 struct encode_state *encode_state,
4841 struct intel_encoder_context *encoder_context)
4842 {
4843 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4844
4845 vp8_context->is_render_context = 1;
4846
4847 i965_encoder_vp8_vme_set_status_buffer(ctx, encode_state, encoder_context);
4848
4849 i965_encoder_vp8_get_paramters(ctx, encode_state, encoder_context);
4850
4851 i965_encoder_vp8_vme_gpe_kernel_init(ctx, encode_state, encoder_context);
4852 i965_encoder_vp8_vme_gpe_kernel_function(ctx, encode_state, encoder_context);
4853 i965_encoder_vp8_vme_gpe_kernel_final(ctx, encode_state, encoder_context);
4854
4855 vp8_context->frame_num++;
4856 vp8_context->brc_need_reset = 0;
4857
4858 vp8_context->mbenc_curbe_updated_in_brc_update = 0;
4859 vp8_context->mpu_curbe_updated_in_brc_update = 0;
4860 vp8_context->mfx_encoder_config_command_initialized = 0;
4861
4862 return VA_STATUS_SUCCESS;
4863 }
4864
4865 static void
i965_encoder_vp8_vme_kernel_context_destroy(struct i965_encoder_vp8_context * vp8_context)4866 i965_encoder_vp8_vme_kernel_context_destroy(struct i965_encoder_vp8_context *vp8_context)
4867 {
4868 struct i965_gpe_table *gpe = vp8_context->gpe_table;
4869 int i;
4870
4871 for (i = 0; i < NUM_VP8_BRC_RESET; i++)
4872 gpe->context_destroy(&vp8_context->brc_init_reset_context.gpe_contexts[i]);
4873
4874 for (i = 0; i < NUM_VP8_SCALING; i++)
4875 gpe->context_destroy(&vp8_context->scaling_context.gpe_contexts[i]);
4876
4877 for (i = 0; i < NUM_VP8_ME; i++)
4878 gpe->context_destroy(&vp8_context->me_context.gpe_contexts[i]);
4879
4880 for (i = 0; i < NUM_VP8_MBENC; i++)
4881 gpe->context_destroy(&vp8_context->mbenc_context.gpe_contexts[i]);
4882
4883 for (i = 0; i < NUM_VP8_BRC_UPDATE; i++)
4884 gpe->context_destroy(&vp8_context->brc_update_context.gpe_contexts[i]);
4885
4886 for (i = 0; i < NUM_VP8_MPU; i++)
4887 gpe->context_destroy(&vp8_context->mpu_context.gpe_contexts[i]);
4888
4889 i965_encoder_vp8_vme_free_resources(vp8_context);
4890 }
4891
4892 static void
i965_encoder_vp8_vme_context_destroy(void * context)4893 i965_encoder_vp8_vme_context_destroy(void *context)
4894 {
4895 struct i965_encoder_vp8_context *vp8_context = context;
4896 struct i965_encoder_vp8_encode_status_buffer *encode_status_buffer = &vp8_context->encode_status_buffer;
4897
4898 i965_encoder_vp8_vme_kernel_context_destroy(vp8_context);
4899
4900 dri_bo_unreference(encode_status_buffer->bo);
4901 encode_status_buffer->bo = NULL;
4902
4903 free(vp8_context);
4904 }
4905
4906 static void
i965_encoder_vp8_vme_brc_init_reset_context_init(VADriverContextP ctx,struct i965_encoder_vp8_context * vp8_context,struct i965_encoder_vp8_brc_init_reset_context * brc_init_reset_context)4907 i965_encoder_vp8_vme_brc_init_reset_context_init(VADriverContextP ctx,
4908 struct i965_encoder_vp8_context *vp8_context,
4909 struct i965_encoder_vp8_brc_init_reset_context *brc_init_reset_context)
4910 {
4911 struct i965_gpe_table *gpe = vp8_context->gpe_table;
4912 struct i965_gpe_context *gpe_context = NULL;
4913 struct vp8_encoder_kernel_parameters kernel_params;
4914 struct vp8_encoder_scoreboard_parameters scoreboard_params;
4915 int i;
4916
4917 kernel_params.curbe_size = sizeof(struct vp8_brc_init_reset_curbe_data);
4918 kernel_params.inline_data_size = 0;
4919 kernel_params.external_data_size = 0;
4920
4921 memset(&scoreboard_params, 0, sizeof(scoreboard_params));
4922 scoreboard_params.mask = 0xFF;
4923 scoreboard_params.enable = vp8_context->use_hw_scoreboard;
4924 scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
4925
4926 for (i = 0; i < NUM_VP8_BRC_RESET; i++) {
4927 gpe_context = &brc_init_reset_context->gpe_contexts[i];
4928 i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
4929 i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
4930 gpe->load_kernels(ctx,
4931 gpe_context,
4932 &vp8_kernels_brc_init_reset[i],
4933 1);
4934 }
4935 }
4936
4937 static void
i965_encoder_vp8_vme_scaling_context_init(VADriverContextP ctx,struct i965_encoder_vp8_context * vp8_context,struct i965_encoder_vp8_scaling_context * scaling_context)4938 i965_encoder_vp8_vme_scaling_context_init(VADriverContextP ctx,
4939 struct i965_encoder_vp8_context *vp8_context,
4940 struct i965_encoder_vp8_scaling_context *scaling_context)
4941 {
4942 struct i965_gpe_table *gpe = vp8_context->gpe_table;
4943 struct i965_gpe_context *gpe_context = NULL;
4944 struct vp8_encoder_kernel_parameters kernel_params;
4945 struct vp8_encoder_scoreboard_parameters scoreboard_params;
4946 int i;
4947
4948 kernel_params.curbe_size = sizeof(struct vp8_scaling_curbe_data);
4949 kernel_params.inline_data_size = 0;
4950 kernel_params.external_data_size = 0;
4951
4952 memset(&scoreboard_params, 0, sizeof(scoreboard_params));
4953 scoreboard_params.mask = 0xFF;
4954 scoreboard_params.enable = vp8_context->use_hw_scoreboard;
4955 scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
4956
4957 for (i = 0; i < NUM_VP8_SCALING; i++) {
4958 gpe_context = &scaling_context->gpe_contexts[i];
4959 i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
4960 i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
4961 gpe->load_kernels(ctx,
4962 gpe_context,
4963 &vp8_kernels_scaling[i],
4964 1);
4965 }
4966 }
4967
4968 static void
i965_encoder_vp8_vme_me_context_init(VADriverContextP ctx,struct i965_encoder_vp8_context * vp8_context,struct i965_encoder_vp8_me_context * me_context)4969 i965_encoder_vp8_vme_me_context_init(VADriverContextP ctx,
4970 struct i965_encoder_vp8_context *vp8_context,
4971 struct i965_encoder_vp8_me_context *me_context)
4972 {
4973 struct i965_gpe_table *gpe = vp8_context->gpe_table;
4974 struct i965_gpe_context *gpe_context = NULL;
4975 struct vp8_encoder_kernel_parameters kernel_params;
4976 struct vp8_encoder_scoreboard_parameters scoreboard_params;
4977 int i;
4978
4979 kernel_params.curbe_size = sizeof(struct vp8_me_curbe_data);
4980 kernel_params.inline_data_size = 0;
4981 kernel_params.external_data_size = 0;
4982
4983 memset(&scoreboard_params, 0, sizeof(scoreboard_params));
4984 scoreboard_params.mask = 0xFF;
4985 scoreboard_params.enable = vp8_context->use_hw_scoreboard;
4986 scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
4987
4988 for (i = 0; i < NUM_VP8_ME; i++) {
4989 gpe_context = &me_context->gpe_contexts[i];
4990 i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
4991 i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
4992 gpe->load_kernels(ctx,
4993 gpe_context,
4994 &vp8_kernels_me[i],
4995 1);
4996 }
4997 }
4998
4999 static void
i965_encoder_vp8_vme_mbenc_context_init(VADriverContextP ctx,struct i965_encoder_vp8_context * vp8_context,struct i965_encoder_vp8_mbenc_context * mbenc_context)5000 i965_encoder_vp8_vme_mbenc_context_init(VADriverContextP ctx,
5001 struct i965_encoder_vp8_context *vp8_context,
5002 struct i965_encoder_vp8_mbenc_context *mbenc_context)
5003 {
5004 struct i965_gpe_table *gpe = vp8_context->gpe_table;
5005 struct i965_gpe_context *gpe_context = NULL;
5006 struct vp8_encoder_kernel_parameters kernel_params;
5007 struct vp8_encoder_scoreboard_parameters scoreboard_params;
5008 int i;
5009
5010 kernel_params.curbe_size = MAX(sizeof(struct vp8_mbenc_i_frame_curbe_data), sizeof(struct vp8_mbenc_p_frame_curbe_data));
5011 kernel_params.inline_data_size = 0;
5012 kernel_params.external_data_size = 0;
5013
5014 memset(&scoreboard_params, 0, sizeof(scoreboard_params));
5015 scoreboard_params.mask = 0xFF;
5016 scoreboard_params.enable = vp8_context->use_hw_scoreboard;
5017 scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
5018
5019 for (i = 0; i < NUM_VP8_MBENC; i++) {
5020 gpe_context = &mbenc_context->gpe_contexts[i];
5021 i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
5022 i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
5023 gpe->load_kernels(ctx,
5024 gpe_context,
5025 &vp8_kernels_mbenc[i],
5026 1);
5027 }
5028 }
5029
5030 static void
i965_encoder_vp8_vme_brc_update_context_init(VADriverContextP ctx,struct i965_encoder_vp8_context * vp8_context,struct i965_encoder_vp8_brc_update_context * brc_update_context)5031 i965_encoder_vp8_vme_brc_update_context_init(VADriverContextP ctx,
5032 struct i965_encoder_vp8_context *vp8_context,
5033 struct i965_encoder_vp8_brc_update_context *brc_update_context)
5034 {
5035 struct i965_gpe_table *gpe = vp8_context->gpe_table;
5036 struct i965_gpe_context *gpe_context = NULL;
5037 struct vp8_encoder_kernel_parameters kernel_params;
5038 struct vp8_encoder_scoreboard_parameters scoreboard_params;
5039 int i;
5040
5041 kernel_params.curbe_size = sizeof(struct vp8_brc_update_curbe_data);
5042 kernel_params.inline_data_size = 0;
5043 kernel_params.external_data_size = 0;
5044
5045 memset(&scoreboard_params, 0, sizeof(scoreboard_params));
5046 scoreboard_params.mask = 0xFF;
5047 scoreboard_params.enable = vp8_context->use_hw_scoreboard;
5048 scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
5049
5050 for (i = 0; i < NUM_VP8_BRC_UPDATE; i++) {
5051 gpe_context = &brc_update_context->gpe_contexts[i];
5052 i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
5053 i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
5054 gpe->load_kernels(ctx,
5055 gpe_context,
5056 &vp8_kernels_brc_update[i],
5057 1);
5058 }
5059 }
5060
5061 static void
i965_encoder_vp8_vme_mpu_context_init(VADriverContextP ctx,struct i965_encoder_vp8_context * vp8_context,struct i965_encoder_vp8_mpu_context * mpu_context)5062 i965_encoder_vp8_vme_mpu_context_init(VADriverContextP ctx,
5063 struct i965_encoder_vp8_context *vp8_context,
5064 struct i965_encoder_vp8_mpu_context *mpu_context)
5065 {
5066 struct i965_gpe_table *gpe = vp8_context->gpe_table;
5067 struct i965_gpe_context *gpe_context = NULL;
5068 struct vp8_encoder_kernel_parameters kernel_params;
5069 struct vp8_encoder_scoreboard_parameters scoreboard_params;
5070 int i;
5071
5072 kernel_params.curbe_size = sizeof(struct vp8_mpu_curbe_data);
5073 kernel_params.inline_data_size = 0;
5074 kernel_params.external_data_size = 0;
5075
5076 memset(&scoreboard_params, 0, sizeof(scoreboard_params));
5077 scoreboard_params.mask = 0xFF;
5078 scoreboard_params.enable = vp8_context->use_hw_scoreboard;
5079 scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
5080
5081 for (i = 0; i < NUM_VP8_MPU; i++) {
5082 gpe_context = &mpu_context->gpe_contexts[i];
5083 i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
5084 i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
5085 gpe->load_kernels(ctx,
5086 gpe_context,
5087 &vp8_kernels_mpu[i],
5088 1);
5089 }
5090 }
5091
5092 static Bool
i965_encoder_vp8_vme_var_init(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_encoder_vp8_context * vp8_context)5093 i965_encoder_vp8_vme_var_init(VADriverContextP ctx,
5094 struct intel_encoder_context *encoder_context,
5095 struct i965_encoder_vp8_context *vp8_context)
5096 {
5097 struct i965_driver_data *i965 = i965_driver_data(ctx);
5098
5099 vp8_context->mocs = i965->intel.mocs_state;
5100
5101 vp8_context->gpe_table = &i965->gpe_table;
5102
5103 vp8_context->min_scaled_dimension = 48;
5104 vp8_context->min_scaled_dimension_in_mbs = WIDTH_IN_MACROBLOCKS(vp8_context->min_scaled_dimension);
5105
5106 vp8_context->vdbox_idc = BSD_RING0;
5107 vp8_context->vdbox_mmio_base = VDBOX0_MMIO_BASE;
5108
5109 /* TODO: This is a WA for VDBOX loading balance only, */
5110 if (i965->intel.has_bsd2) {
5111 srandom(time(NULL));
5112 vp8_context->vdbox_idc = (random() % 2 ? BSD_RING1 : BSD_RING0);
5113 }
5114
5115 if (vp8_context->vdbox_idc == BSD_RING1)
5116 vp8_context->vdbox_mmio_base = VDBOX1_MMIO_BASE;
5117
5118 vp8_context->frame_type = MPEG_I_PICTURE;
5119
5120 vp8_context->use_hw_scoreboard = 1;
5121 vp8_context->use_hw_non_stalling_scoreborad = 1; /* default: non-stalling */
5122 vp8_context->brc_distortion_buffer_supported = 1;
5123 vp8_context->brc_constant_buffer_supported = 1;
5124 vp8_context->repak_supported = 1;
5125 vp8_context->multiple_pass_brc_supported = 1;
5126 vp8_context->is_first_frame = 1;
5127 vp8_context->is_first_two_frame = 1;
5128 vp8_context->gop_size = 30;
5129 vp8_context->hme_supported = 1;
5130 vp8_context->hme_16x_supported = 1;
5131 vp8_context->hme_enabled = 0;
5132 vp8_context->hme_16x_enabled = 0;
5133 vp8_context->brc_initted = 0;
5134 vp8_context->frame_num = 0;
5135 vp8_context->framerate = (struct intel_fraction) {
5136 30, 1
5137 };
5138
5139 return True;
5140 }
5141
5142 static Bool
i965_encoder_vp8_vme_kernels_context_init(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_encoder_vp8_context * vp8_context)5143 i965_encoder_vp8_vme_kernels_context_init(VADriverContextP ctx,
5144 struct intel_encoder_context *encoder_context,
5145 struct i965_encoder_vp8_context *vp8_context)
5146 {
5147 i965_encoder_vp8_vme_brc_init_reset_context_init(ctx, vp8_context, &vp8_context->brc_init_reset_context);
5148 i965_encoder_vp8_vme_scaling_context_init(ctx, vp8_context, &vp8_context->scaling_context);
5149 i965_encoder_vp8_vme_me_context_init(ctx, vp8_context, &vp8_context->me_context);
5150 i965_encoder_vp8_vme_mbenc_context_init(ctx, vp8_context, &vp8_context->mbenc_context);
5151 i965_encoder_vp8_vme_brc_update_context_init(ctx, vp8_context, &vp8_context->brc_update_context);
5152 i965_encoder_vp8_vme_mpu_context_init(ctx, vp8_context, &vp8_context->mpu_context);
5153
5154 return True;
5155 }
5156
5157 extern Bool
5158 gen8_encoder_vp8_context_init(VADriverContextP, struct intel_encoder_context *, struct i965_encoder_vp8_context *);
5159
5160 extern Bool
5161 gen9_encoder_vp8_context_init(VADriverContextP, struct intel_encoder_context *, struct i965_encoder_vp8_context *);
5162
5163 extern Bool
5164 gen10_encoder_vp8_context_init(VADriverContextP, struct intel_encoder_context *, struct i965_encoder_vp8_context *);
5165
5166 Bool
i965_encoder_vp8_vme_context_init(VADriverContextP ctx,struct intel_encoder_context * encoder_context)5167 i965_encoder_vp8_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
5168 {
5169 struct i965_driver_data *i965 = i965_driver_data(ctx);
5170 struct i965_encoder_vp8_context *vp8_context = NULL;
5171
5172 vp8_context = calloc(1, sizeof(struct i965_encoder_vp8_context));
5173
5174 if (!vp8_context)
5175 return False;
5176
5177 i965_encoder_vp8_vme_var_init(ctx, encoder_context, vp8_context);
5178
5179 if (IS_CHERRYVIEW(i965->intel.device_info))
5180 gen8_encoder_vp8_context_init(ctx, encoder_context, vp8_context);
5181 else if (IS_GEN9(i965->intel.device_info)) {
5182 gen9_encoder_vp8_context_init(ctx, encoder_context, vp8_context);
5183 } else if (IS_GEN10(i965->intel.device_info)) {
5184 gen10_encoder_vp8_context_init(ctx, encoder_context, vp8_context);
5185 } else {
5186 free(vp8_context);
5187
5188 return False;
5189 }
5190
5191 i965_encoder_vp8_vme_kernels_context_init(ctx, encoder_context, vp8_context);
5192
5193 encoder_context->vme_context = vp8_context;
5194 encoder_context->vme_pipeline = i965_encoder_vp8_vme_pipeline;
5195 encoder_context->vme_context_destroy = i965_encoder_vp8_vme_context_destroy;
5196
5197 return True;
5198 }
5199
5200 /*
5201 * PAK part
5202 */
5203 static void
i965_encoder_vp8_pak_pre_pipeline(struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5204 i965_encoder_vp8_pak_pre_pipeline(struct encode_state *encode_state,
5205 struct intel_encoder_context *encoder_context)
5206 {
5207 /* No thing to do */
5208 }
5209
5210 static void
i965_encoder_vp8_pak_kernels_context_destroy(struct i965_encoder_vp8_context * vp8_context)5211 i965_encoder_vp8_pak_kernels_context_destroy(struct i965_encoder_vp8_context *vp8_context)
5212 {
5213 struct i965_gpe_table *gpe = vp8_context->gpe_table;
5214 int i;
5215
5216 for (i = 0; i < NUM_VP8_TPU; i++)
5217 gpe->context_destroy(&vp8_context->tpu_context.gpe_contexts[i]);
5218 }
5219
5220
5221 static void
i965_encoder_vp8_pak_context_destroy(void * context)5222 i965_encoder_vp8_pak_context_destroy(void *context)
5223 {
5224 struct i965_encoder_vp8_context *vp8_context = context;
5225 int i;
5226
5227 dri_bo_unreference(vp8_context->post_deblocking_output.bo);
5228 vp8_context->post_deblocking_output.bo = NULL;
5229
5230 dri_bo_unreference(vp8_context->pre_deblocking_output.bo);
5231 vp8_context->pre_deblocking_output.bo = NULL;
5232
5233 dri_bo_unreference(vp8_context->uncompressed_picture_source.bo);
5234 vp8_context->uncompressed_picture_source.bo = NULL;
5235
5236 dri_bo_unreference(vp8_context->indirect_pak_bse_object.bo);
5237 vp8_context->indirect_pak_bse_object.bo = NULL;
5238
5239 for (i = 0; i < MAX_MFX_REFERENCE_SURFACES; i++) {
5240 dri_bo_unreference(vp8_context->reference_surfaces[i].bo);
5241 vp8_context->reference_surfaces[i].bo = NULL;
5242 }
5243
5244 i965_encoder_vp8_pak_kernels_context_destroy(vp8_context);
5245
5246 /* vme & pak same the same structure, so don't free the context here */
5247 }
5248
5249 static void
i965_encoder_vp8_pak_pipe_mode_select(VADriverContextP ctx,struct intel_encoder_context * encoder_context)5250 i965_encoder_vp8_pak_pipe_mode_select(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
5251 {
5252 struct intel_batchbuffer *batch = encoder_context->base.batch;
5253 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5254
5255 BEGIN_BCS_BATCH(batch, 5);
5256
5257 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
5258 OUT_BCS_BATCH(batch,
5259 (MFX_LONG_MODE << 17) | /* Must be long format for encoder */
5260 (MFD_MODE_VLD << 15) | /* VLD mode */
5261 ((!!vp8_context->post_deblocking_output.bo) << 9) | /* Post Deblocking Output */
5262 ((!!vp8_context->pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */
5263 (1 << 4) | /* encoding mode */
5264 (MFX_FORMAT_VP8 << 0));
5265 OUT_BCS_BATCH(batch, 0);
5266 OUT_BCS_BATCH(batch, 0);
5267 OUT_BCS_BATCH(batch, 0);
5268
5269 ADVANCE_BCS_BATCH(batch);
5270 }
5271
5272 static void
i965_encoder_vp8_pak_surface_state(VADriverContextP ctx,struct object_surface * obj_surface,int id,struct intel_encoder_context * encoder_context)5273 i965_encoder_vp8_pak_surface_state(VADriverContextP ctx,
5274 struct object_surface *obj_surface,
5275 int id,
5276 struct intel_encoder_context *encoder_context)
5277 {
5278 struct intel_batchbuffer *batch = encoder_context->base.batch;
5279
5280 BEGIN_BCS_BATCH(batch, 6);
5281
5282 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
5283 OUT_BCS_BATCH(batch, id);
5284 OUT_BCS_BATCH(batch,
5285 ((obj_surface->orig_height - 1) << 18) |
5286 ((obj_surface->orig_width - 1) << 4));
5287 OUT_BCS_BATCH(batch,
5288 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
5289 (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
5290 ((obj_surface->width - 1) << 3) | /* pitch */
5291 (0 << 2) | /* must be 0 for interleave U/V */
5292 (1 << 1) | /* must be tiled */
5293 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
5294 OUT_BCS_BATCH(batch,
5295 (0 << 16) | /* must be 0 for interleave U/V */
5296 (obj_surface->height)); /* y offset for U(cb) */
5297 OUT_BCS_BATCH(batch, 0);
5298
5299 ADVANCE_BCS_BATCH(batch);
5300 }
5301
5302 #define PAK_OUT_BUFFER_2DW(buf_bo, is_target, delta) do { \
5303 if (buf_bo) { \
5304 OUT_BCS_RELOC64(batch, \
5305 buf_bo, \
5306 I915_GEM_DOMAIN_RENDER, \
5307 is_target ? I915_GEM_DOMAIN_RENDER : 0, \
5308 delta); \
5309 } else { \
5310 OUT_BCS_BATCH(batch, 0); \
5311 OUT_BCS_BATCH(batch, 0); \
5312 } \
5313 } while (0)
5314
5315 #define PAK_OUT_BUFFER_3DW(buf_bo, is_target, delta, attr) do { \
5316 PAK_OUT_BUFFER_2DW(buf_bo, is_target, delta); \
5317 OUT_BCS_BATCH(batch, attr); \
5318 } while (0)
5319
5320
5321
5322 static void
i965_encoder_vp8_pak_pipe_buf_addr_state(VADriverContextP ctx,struct intel_encoder_context * encoder_context)5323 i965_encoder_vp8_pak_pipe_buf_addr_state(VADriverContextP ctx,
5324 struct intel_encoder_context *encoder_context)
5325 {
5326 struct intel_batchbuffer *batch = encoder_context->base.batch;
5327 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5328 int i;
5329
5330 BEGIN_BCS_BATCH(batch, 61);
5331
5332 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
5333
5334 /* the DW1-3 is for pre_deblocking */
5335 PAK_OUT_BUFFER_3DW(vp8_context->pre_deblocking_output.bo, 1, 0, vp8_context->mocs);
5336
5337 /* the DW4-6 is for the post_deblocking */
5338 PAK_OUT_BUFFER_3DW(vp8_context->post_deblocking_output.bo, 1, 0, vp8_context->mocs);
5339
5340 /* the DW7-9 is for the uncompressed_picture */
5341 PAK_OUT_BUFFER_3DW(vp8_context->uncompressed_picture_source.bo, 0, 0, vp8_context->mocs);
5342
5343 /* the DW10-12 is for the mb status */
5344 PAK_OUT_BUFFER_3DW(vp8_context->pak_stream_out_buffer.bo, 1, 0, vp8_context->mocs);
5345
5346 /* the DW13-15 is for the intra_row_store_scratch */
5347 PAK_OUT_BUFFER_3DW(vp8_context->pak_intra_row_store_scratch_buffer.bo, 1, 0, vp8_context->mocs);
5348
5349 /* the DW16-18 is for the deblocking filter */
5350 PAK_OUT_BUFFER_3DW(vp8_context->pak_deblocking_filter_row_store_scratch_buffer.bo, 1, 0, vp8_context->mocs);
5351
5352 /* the DW 19-50 is for Reference pictures*/
5353 for (i = 0; i < ARRAY_ELEMS(vp8_context->reference_surfaces); i++) {
5354 PAK_OUT_BUFFER_2DW(vp8_context->reference_surfaces[i].bo, 0, 0);
5355 }
5356
5357 /* DW 51 */
5358 OUT_BCS_BATCH(batch, vp8_context->mocs);
5359
5360 /* The DW 52-54 is for the MB status buffer */
5361 PAK_OUT_BUFFER_3DW(NULL, 0, 0, 0);
5362
5363 /* the DW 55-57 is the ILDB buffer */
5364 PAK_OUT_BUFFER_3DW(NULL, 0, 0, 0);
5365
5366 /* the DW 58-60 is the second ILDB buffer */
5367 PAK_OUT_BUFFER_3DW(NULL, 0, 0, 0);
5368
5369 ADVANCE_BCS_BATCH(batch);
5370 }
5371
5372 static void
i965_encoder_vp8_pak_ind_obj_base_addr_state(VADriverContextP ctx,struct intel_encoder_context * encoder_context)5373 i965_encoder_vp8_pak_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
5374 {
5375 struct intel_batchbuffer *batch = encoder_context->base.batch;
5376 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5377 int vme_size = ALIGN((vp8_context->mb_coded_buffer_size - vp8_context->mv_offset), 0x1000);
5378
5379 BEGIN_BCS_BATCH(batch, 26);
5380
5381 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
5382
5383 /* the DW1-5 is for the MFX indirect bistream */
5384 PAK_OUT_BUFFER_3DW(vp8_context->indirect_pak_bse_object.bo, 1, vp8_context->indirect_pak_bse_object.offset, vp8_context->mocs);
5385 PAK_OUT_BUFFER_2DW(vp8_context->indirect_pak_bse_object.bo, 1, vp8_context->indirect_pak_bse_object.end_offset);
5386
5387 /* the DW6-10 is for MFX Indirect MV Object Base Address */
5388 PAK_OUT_BUFFER_3DW(vp8_context->mb_coded_buffer.bo, 0, vp8_context->mv_offset, vp8_context->mocs);
5389 PAK_OUT_BUFFER_2DW(vp8_context->mb_coded_buffer.bo, 0, (vp8_context->mv_offset + vme_size));
5390
5391 /* the DW11-15 is for MFX IT-COFF. Not used on encoder */
5392 PAK_OUT_BUFFER_3DW(NULL, 0, 0, 0);
5393 PAK_OUT_BUFFER_2DW(NULL, 0, 0);
5394
5395 /* the DW16-20 is for MFX indirect DBLK. Not used on encoder */
5396 PAK_OUT_BUFFER_3DW(NULL, 0, 0, 0);
5397 PAK_OUT_BUFFER_2DW(NULL, 0, 0);
5398
5399 /* the DW21-25 is for MFC Indirect PAK-BSE Object Base Address for Encoder*/
5400 PAK_OUT_BUFFER_3DW(vp8_context->indirect_pak_bse_object.bo, 1, vp8_context->indirect_pak_bse_object.offset, vp8_context->mocs);
5401 PAK_OUT_BUFFER_2DW(vp8_context->indirect_pak_bse_object.bo, 1, vp8_context->indirect_pak_bse_object.end_offset);
5402
5403 ADVANCE_BCS_BATCH(batch);
5404 }
5405
5406 static void
i965_encoder_vp8_pak_bsp_buf_base_addr_state(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5407 i965_encoder_vp8_pak_bsp_buf_base_addr_state(VADriverContextP ctx,
5408 struct encode_state *encode_state,
5409 struct intel_encoder_context *encoder_context)
5410 {
5411 struct intel_batchbuffer *batch = encoder_context->base.batch;
5412 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5413 VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
5414 int num_partitions = (1 << pic_param->pic_flags.bits.num_token_partitions);
5415 int offset;
5416 unsigned int token_size = vp8_context->frame_width * vp8_context->frame_height * 2;
5417 unsigned int part_size = token_size / num_partitions;
5418 unsigned int part0_size = (vp8_context->frame_width * vp8_context->frame_height) / 4 + VP8_INTERMEDIATE_PARTITION0_SIZE;
5419
5420 BEGIN_BCS_BATCH(batch, 32);
5421 OUT_BCS_BATCH(batch, MFX_VP8_BSP_BUF_BASE_ADDR_STATE | (32 - 2));
5422
5423 /* The 4th parameter in PAK_OUT_BUFFER_3DW() is not a MOCS index for this command per doc */
5424 /* DW1-3 */
5425 PAK_OUT_BUFFER_3DW(vp8_context->pak_frame_header_buffer.bo, 1, 0, 0);
5426 /* DW4-6 */
5427 PAK_OUT_BUFFER_3DW(vp8_context->pak_intermediate_buffer.bo, 1, 0, 0);
5428
5429 /* DW7-DW14 */
5430 offset = ALIGN(part0_size, 64);
5431 OUT_BCS_BATCH(batch, offset);
5432 offset = ALIGN(offset + part_size, 64);
5433 OUT_BCS_BATCH(batch, offset);
5434 offset = ALIGN(offset + part_size, 64);
5435 OUT_BCS_BATCH(batch, offset);
5436 offset = ALIGN(offset + part_size, 64);
5437 OUT_BCS_BATCH(batch, offset);
5438 offset = ALIGN(offset + part_size, 64);
5439 OUT_BCS_BATCH(batch, offset);
5440 offset = ALIGN(offset + part_size, 64);
5441 OUT_BCS_BATCH(batch, offset);
5442 offset = ALIGN(offset + part_size, 64);
5443 OUT_BCS_BATCH(batch, offset);
5444 offset = ALIGN(offset + part_size, 64);
5445 OUT_BCS_BATCH(batch, offset);
5446
5447 /* DW15 */
5448 OUT_BCS_BATCH(batch, token_size + part0_size);
5449
5450 /* DW16-18 */
5451 PAK_OUT_BUFFER_3DW(vp8_context->indirect_pak_bse_object.bo, 1, vp8_context->indirect_pak_bse_object.offset, 0);
5452
5453 /* DW19 */
5454 OUT_BCS_BATCH(batch, 0);
5455
5456 /* DW20-22 */
5457 PAK_OUT_BUFFER_3DW(NULL, 0, 0, 0);
5458
5459 /* DW23-25 */
5460 if (vp8_context->repak_pass_iter_val > 0 &&
5461 vp8_context->frame_type == MPEG_I_PICTURE &&
5462 vp8_context->repak_pass_iter_val == vp8_context->curr_pass)
5463 PAK_OUT_BUFFER_3DW(vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer.bo, 1, 0, 0);
5464 else
5465 PAK_OUT_BUFFER_3DW(vp8_context->pak_mpu_tpu_coeff_probs_buffer.bo, 1, 0, 0);
5466
5467 /* DW26-28 */
5468 PAK_OUT_BUFFER_3DW(vp8_context->pak_mpu_tpu_pak_token_statistics_buffer.bo, 1, 0, 0);
5469
5470 /* DW29-31 */
5471 PAK_OUT_BUFFER_3DW(vp8_context->pak_mpc_row_store_scratch_buffer.bo, 1, 0, 0);
5472
5473 ADVANCE_BCS_BATCH(batch);
5474 }
5475
5476 static void
i965_encoder_vp8_pak_insert_batch_buffers(VADriverContextP ctx,struct intel_encoder_context * encoder_context)5477 i965_encoder_vp8_pak_insert_batch_buffers(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
5478 {
5479 struct intel_batchbuffer *batch = encoder_context->base.batch;
5480 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5481 struct i965_gpe_table *gpe = vp8_context->gpe_table;
5482 struct gpe_mi_batch_buffer_start_parameter batch_param;
5483 unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
5484 vp8_context->internal_rate_mode == I965_BRC_VBR);
5485
5486 memset(&batch_param, 0, sizeof(batch_param));
5487 batch_param.bo = vp8_context->pak_mpu_tpu_picture_state_buffer.bo;
5488 batch_param.is_second_level = 1; /* Must be the second batch buffer */
5489 gpe->mi_batch_buffer_start(ctx, batch, &batch_param);
5490
5491 if (brc_enabled) {
5492 batch_param.bo = vp8_context->brc_vp8_cfg_command_write_buffer.bo;
5493
5494 if (vp8_context->repak_pass_iter_val == 0) {
5495 batch_param.offset = vp8_context->curr_pass * VP8_BRC_IMG_STATE_SIZE_PER_PASS;
5496 } else {
5497
5498 if (vp8_context->repak_pass_iter_val == vp8_context->curr_pass)
5499 batch_param.offset = 0;
5500 else
5501 batch_param.offset = vp8_context->curr_pass * VP8_BRC_IMG_STATE_SIZE_PER_PASS;
5502 }
5503
5504 gpe->mi_batch_buffer_start(ctx, batch, &batch_param);
5505 }
5506
5507 batch_param.bo = vp8_context->mb_coded_buffer.bo;
5508 batch_param.offset = 0;
5509 gpe->mi_batch_buffer_start(ctx, batch, &batch_param);
5510 }
5511
5512 static void
i965_encoder_vp8_pak_picture_level(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5513 i965_encoder_vp8_pak_picture_level(VADriverContextP ctx,
5514 struct encode_state *encode_state,
5515 struct intel_encoder_context *encoder_context)
5516 {
5517 struct intel_batchbuffer *batch = encoder_context->base.batch;
5518 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5519 struct i965_encoder_vp8_encode_status_buffer *encode_status_buffer = &vp8_context->encode_status_buffer;
5520 struct i965_gpe_table *gpe = vp8_context->gpe_table;
5521 struct gpe_mi_conditional_batch_buffer_end_parameter mi_param;
5522 unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
5523 vp8_context->internal_rate_mode == I965_BRC_VBR);
5524
5525 if (brc_enabled &&
5526 vp8_context->curr_pass > 0 &&
5527 (vp8_context->curr_pass < vp8_context->repak_pass_iter_val ||
5528 vp8_context->repak_pass_iter_val == 0)) {
5529 memset(&mi_param, 0, sizeof(mi_param));
5530 mi_param.bo = encode_status_buffer->bo;
5531 mi_param.offset = (encode_status_buffer->base_offset +
5532 encode_status_buffer->image_status_mask_offset);
5533 gpe->mi_conditional_batch_buffer_end(ctx, batch, &mi_param);
5534 }
5535
5536 if ((vp8_context->repak_pass_iter_val > 0) && (vp8_context->curr_pass == vp8_context->repak_pass_iter_val)) {
5537 memset(&mi_param, 0, sizeof(mi_param));
5538 mi_param.bo = vp8_context->pak_mpu_tpu_repak_decision_buffer.bo;
5539 mi_param.offset = 0;
5540 gpe->mi_conditional_batch_buffer_end(ctx, batch, &mi_param);
5541 }
5542
5543 i965_encoder_vp8_pak_pipe_mode_select(ctx, encoder_context);
5544 i965_encoder_vp8_pak_surface_state(ctx, encode_state->reconstructed_object, 0, encoder_context);
5545 i965_encoder_vp8_pak_surface_state(ctx, encode_state->input_yuv_object, 4, encoder_context);
5546 i965_encoder_vp8_pak_pipe_buf_addr_state(ctx, encoder_context);
5547 i965_encoder_vp8_pak_ind_obj_base_addr_state(ctx, encoder_context);
5548 i965_encoder_vp8_pak_bsp_buf_base_addr_state(ctx, encode_state, encoder_context);
5549 i965_encoder_vp8_pak_insert_batch_buffers(ctx, encoder_context);
5550 }
5551
5552 static void
i965_encoder_vp8_pak_set_pak_status_in_tpu_curbe(VADriverContextP ctx,struct intel_encoder_context * encoder_context,int ipass)5553 i965_encoder_vp8_pak_set_pak_status_in_tpu_curbe(VADriverContextP ctx,
5554 struct intel_encoder_context *encoder_context,
5555 int ipass)
5556 {
5557 struct intel_batchbuffer *batch = encoder_context->base.batch;
5558 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5559 struct i965_encoder_vp8_tpu_context *tpu_context = &vp8_context->tpu_context;
5560 struct i965_gpe_table *gpe = vp8_context->gpe_table;
5561 struct i965_gpe_context *tpu_gpe_context;
5562 struct gpe_mi_store_data_imm_parameter mi_store_data_imm_param;
5563 struct gpe_mi_store_register_mem_parameter mi_store_register_mem_param;
5564
5565 tpu_gpe_context = &tpu_context->gpe_contexts[0];
5566
5567 memset(&mi_store_data_imm_param, 0, sizeof(mi_store_data_imm_param));
5568 mi_store_data_imm_param.bo = tpu_gpe_context->curbe.bo;
5569 mi_store_data_imm_param.offset = tpu_gpe_context->curbe.offset + sizeof(unsigned int) * 6;
5570 mi_store_data_imm_param.dw0 = (vp8_context->curr_pass + 1) << 8;
5571
5572 gpe->mi_store_data_imm(ctx, batch, &mi_store_data_imm_param);
5573
5574 if (ipass == 0) {
5575 memset(&mi_store_register_mem_param, 0, sizeof(mi_store_register_mem_param));
5576 mi_store_register_mem_param.bo = tpu_gpe_context->curbe.bo;
5577 mi_store_register_mem_param.offset = tpu_gpe_context->curbe.offset + sizeof(unsigned int) * 8;
5578 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET;
5579 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
5580
5581 mi_store_register_mem_param.offset = tpu_gpe_context->curbe.offset + sizeof(unsigned int) * 9;
5582 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX23_REG_OFFSET;
5583 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
5584
5585 mi_store_register_mem_param.offset = tpu_gpe_context->curbe.offset + sizeof(unsigned int) * 10;
5586 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_D_LOOP_FILTER01_REG_OFFSET;
5587 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
5588
5589 mi_store_register_mem_param.offset = tpu_gpe_context->curbe.offset + sizeof(unsigned int) * 11;
5590 mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_D_LOOP_FILTER23_REG_OFFSET;
5591 gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
5592 }
5593 }
5594
5595 static void
i965_encoder_vp8_pak_slice_level_brc(VADriverContextP ctx,struct intel_encoder_context * encoder_context,int ipass)5596 i965_encoder_vp8_pak_slice_level_brc(VADriverContextP ctx,
5597 struct intel_encoder_context *encoder_context,
5598 int ipass)
5599 {
5600 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5601 unsigned int *pbuffer;
5602
5603 i965_encoder_vp8_read_pak_statistics(ctx, encoder_context, ipass);
5604
5605 pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
5606
5607 if (!pbuffer)
5608 return;
5609
5610 pbuffer += 38;
5611 *pbuffer = 0x05000000;
5612 i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
5613
5614 i965_encoder_vp8_pak_set_pak_status_in_tpu_curbe(ctx, encoder_context, ipass);
5615 }
5616
5617 static void
i965_encoder_vp8_pak_slice_level(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5618 i965_encoder_vp8_pak_slice_level(VADriverContextP ctx,
5619 struct encode_state *encode_state,
5620 struct intel_encoder_context *encoder_context)
5621 {
5622 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5623 unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
5624 vp8_context->internal_rate_mode == I965_BRC_VBR);
5625 unsigned int *pbuffer;
5626
5627 i965_encoder_vp8_read_encode_status(ctx, encoder_context);
5628
5629 if (vp8_context->num_brc_pak_passes == VP8_BRC_SINGLE_PASS) {
5630 if (brc_enabled) {
5631 i965_encoder_vp8_read_pak_statistics(ctx, encoder_context, vp8_context->curr_pass);
5632
5633 /* Workaround: */
5634 pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
5635
5636 if (!pbuffer)
5637 return;
5638
5639 pbuffer += 38;
5640 *pbuffer = 0x05000000;
5641 i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
5642 }
5643
5644 vp8_context->submit_batchbuffer = 1;
5645 } else {
5646 if ((brc_enabled) &&
5647 ((vp8_context->curr_pass < vp8_context->num_passes && vp8_context->repak_pass_iter_val > 0) ||
5648 (vp8_context->curr_pass <= vp8_context->num_passes && vp8_context->repak_pass_iter_val == 0))) {
5649 i965_encoder_vp8_pak_slice_level_brc(ctx, encoder_context, vp8_context->curr_pass);
5650
5651 if (vp8_context->tpu_required)
5652 vp8_context->submit_batchbuffer = 1;
5653 else
5654 vp8_context->submit_batchbuffer = 0;
5655 } else {
5656 if (brc_enabled) {
5657 i965_encoder_vp8_read_pak_statistics(ctx, encoder_context, vp8_context->curr_pass);
5658 }
5659
5660 pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
5661
5662 if (!pbuffer)
5663 return;
5664
5665 pbuffer += 38;
5666 *pbuffer = 0x05000000;
5667 i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
5668
5669 vp8_context->submit_batchbuffer = 1;
5670 }
5671 }
5672 }
5673
5674 static void
i965_encoder_vp8_pak_tpu_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)5675 i965_encoder_vp8_pak_tpu_set_curbe(VADriverContextP ctx,
5676 struct encode_state *encode_state,
5677 struct intel_encoder_context *encoder_context,
5678 struct i965_gpe_context *gpe_context)
5679 {
5680 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5681 struct vp8_tpu_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
5682 VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
5683 VAQMatrixBufferVP8 *quant_param = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
5684
5685 if (!pcmd)
5686 return;
5687
5688 memset(pcmd, 0, sizeof(*pcmd));
5689
5690 pcmd->dw0.mbs_in_frame = vp8_context->frame_width_in_mbs * vp8_context->frame_height_in_mbs;
5691
5692 pcmd->dw1.frame_type = pic_param->pic_flags.bits.frame_type;
5693 pcmd->dw1.enable_segmentation = pic_param->pic_flags.bits.segmentation_enabled;
5694 pcmd->dw1.rebinarization_frame_hdr = (vp8_context->repak_pass_iter_val ? 1 : 0);
5695
5696 pcmd->dw1.refresh_entropy_p = pic_param->pic_flags.bits.refresh_entropy_probs;
5697 pcmd->dw1.mb_no_coeffiscient_skip = pic_param->pic_flags.bits.mb_no_coeff_skip;
5698
5699 pcmd->dw3.max_qp = pic_param->clamp_qindex_high;
5700 pcmd->dw3.min_qp = pic_param->clamp_qindex_low;
5701
5702 pcmd->dw4.loop_filter_level_segment0 = pic_param->loop_filter_level[0];
5703 pcmd->dw4.loop_filter_level_segment1 = pic_param->loop_filter_level[1];
5704 pcmd->dw4.loop_filter_level_segment2 = pic_param->loop_filter_level[2];
5705 pcmd->dw4.loop_filter_level_segment3 = pic_param->loop_filter_level[3];
5706
5707 pcmd->dw5.quantization_index_segment0 = quant_param->quantization_index[0];
5708 pcmd->dw5.quantization_index_segment1 = quant_param->quantization_index[1];
5709 pcmd->dw5.quantization_index_segment2 = quant_param->quantization_index[2];
5710 pcmd->dw5.quantization_index_segment3 = quant_param->quantization_index[3];
5711
5712 pcmd->dw6.pak_pass_num = (vp8_context->internal_rate_mode > 0 ? vp8_context->num_brc_pak_passes : 0) << 8;
5713
5714 if (vp8_context->repak_pass_iter_val > 0) { // TODO: more check
5715 pcmd->dw7.skip_cost_delta_threshold = 100;
5716 pcmd->dw7.token_cost_delta_threshold = 50;
5717 } else {
5718 pcmd->dw7.skip_cost_delta_threshold = 0;
5719 pcmd->dw7.token_cost_delta_threshold = 0;
5720 }
5721
5722 pcmd->dw12.pak_token_statistics_bti = VP8_BTI_TPU_PAK_TOKEN_STATISTICS;
5723 pcmd->dw13.token_update_flags_bti = VP8_BTI_TPU_TOKEN_UPDATE_FLAGS;
5724 pcmd->dw14.entropy_cost_table_bti = VP8_BTI_TPU_ENTROPY_COST_TABLE;
5725 pcmd->dw15.frame_header_bitstream_bti = VP8_BTI_TPU_HEADER_BITSTREAM;
5726 pcmd->dw16.default_token_probability_bti = VP8_BTI_TPU_DEFAULT_TOKEN_PROBABILITY;
5727 pcmd->dw17.picture_state_bti = VP8_BTI_TPU_PICTURE_STATE;
5728 pcmd->dw18.mpu_curbe_data_bti = VP8_BTI_TPU_MPU_CURBE_DATA;
5729 pcmd->dw19.header_meta_data_bti = VP8_BTI_TPU_HEADER_METADATA;
5730 pcmd->dw20.token_probability_bti = VP8_BTI_TPU_TOKEN_PROBABILITY;
5731 pcmd->dw21.pak_hardware_token_probability_pass1_bti = VP8_BTI_TPU_PAK_HW_PASS1_PROBABILITY;
5732 pcmd->dw22.key_frame_token_probability_bti = VP8_BTI_TPU_KEY_TOKEN_PROBABILITY;
5733 pcmd->dw23.updated_token_probability_bti = VP8_BTI_TPU_UPDATED_TOKEN_PROBABILITY;
5734 pcmd->dw24.pak_hardware_token_probability_pass2_bti = VP8_BTI_TPU_PAK_HW_PASS2_PROBABILITY;
5735 pcmd->dw25.kernel_debug_dump_bti = VP8_BTI_TPU_VME_DEBUG_STREAMOUT;
5736 pcmd->dw26.repak_decision_surface_bti = VP8_BTI_TPU_REPAK_DECISION;
5737
5738 i965_gpe_context_unmap_curbe(gpe_context);
5739 }
5740
5741 static void
i965_encoder_vp8_tpu_add_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)5742 i965_encoder_vp8_tpu_add_surfaces(VADriverContextP ctx,
5743 struct encode_state *encode_state,
5744 struct intel_encoder_context *encoder_context,
5745 struct i965_gpe_context *gpe_context)
5746 {
5747 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5748 unsigned int size;
5749 unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
5750 vp8_context->internal_rate_mode == I965_BRC_VBR);
5751
5752 // Pak token statistics
5753 size = VP8_TOKEN_STATISTICS_SIZE;
5754 i965_add_buffer_gpe_surface(ctx,
5755 gpe_context,
5756 &vp8_context->pak_mpu_tpu_pak_token_statistics_buffer,
5757 1,
5758 size,
5759 0,
5760 VP8_BTI_TPU_PAK_TOKEN_STATISTICS);
5761
5762 // Pak token Update flags
5763 size = VP8_COEFFS_PROPABILITIES_SIZE;
5764 i965_add_buffer_gpe_surface(ctx,
5765 gpe_context,
5766 &vp8_context->pak_mpu_tpu_pak_token_update_flags_buffer,
5767 0,
5768 size,
5769 0,
5770 VP8_BTI_TPU_TOKEN_UPDATE_FLAGS);
5771
5772 // Entropy cost
5773 size = VP8_ENTROPY_COST_TABLE_SIZE;
5774 i965_add_buffer_gpe_surface(ctx,
5775 gpe_context,
5776 &vp8_context->pak_mpu_tpu_entropy_cost_table_buffer,
5777 1,
5778 size,
5779 0,
5780 VP8_BTI_TPU_ENTROPY_COST_TABLE);
5781
5782 // Frame header
5783 size = VP8_FRAME_HEADER_SIZE;
5784 i965_add_buffer_gpe_surface(ctx,
5785 gpe_context,
5786 &vp8_context->pak_frame_header_buffer,
5787 0,
5788 size,
5789 0,
5790 VP8_BTI_TPU_HEADER_BITSTREAM);
5791
5792 // Default token token probability
5793 size = VP8_COEFFS_PROPABILITIES_SIZE;
5794 i965_add_buffer_gpe_surface(ctx,
5795 gpe_context,
5796 &vp8_context->pak_mpu_tpu_default_token_probability_buffer,
5797 0,
5798 size,
5799 0,
5800 VP8_BTI_TPU_DEFAULT_TOKEN_PROBABILITY);
5801
5802 // Picture state surface
5803 size = VP8_PICTURE_STATE_SIZE;
5804 i965_add_buffer_gpe_surface(ctx,
5805 gpe_context,
5806 &vp8_context->pak_mpu_tpu_picture_state_buffer,
5807 0,
5808 size,
5809 0,
5810 VP8_BTI_TPU_PICTURE_STATE);
5811
5812 // MPU Curbe info from TPU
5813 size = VP8_TOKEN_BITS_DATA_SIZE;
5814 i965_add_buffer_gpe_surface(ctx,
5815 gpe_context,
5816 &vp8_context->pak_mpu_tpu_token_bits_data_buffer,
5817 0,
5818 size,
5819 0,
5820 VP8_BTI_TPU_MPU_CURBE_DATA);
5821
5822 // Encoder CFG command surface
5823 size = VP8_HEADER_METADATA_SIZE;
5824
5825 if (brc_enabled) {
5826 i965_add_buffer_gpe_surface(ctx,
5827 gpe_context,
5828 &vp8_context->brc_vp8_cfg_command_write_buffer,
5829 0,
5830 size,
5831 0,
5832 VP8_BTI_TPU_HEADER_METADATA);
5833 } else {
5834 i965_add_buffer_gpe_surface(ctx,
5835 gpe_context,
5836 &vp8_context->pak_mpu_tpu_picture_state_buffer,
5837 0,
5838 size,
5839 VP8_HEADER_METADATA_OFFSET,
5840 VP8_BTI_TPU_HEADER_METADATA);
5841 }
5842
5843 // Current frame token probability
5844 size = VP8_COEFFS_PROPABILITIES_SIZE;
5845 i965_add_buffer_gpe_surface(ctx,
5846 gpe_context,
5847 &vp8_context->pak_mpu_tpu_coeff_probs_buffer,
5848 0,
5849 size,
5850 0,
5851 VP8_BTI_TPU_TOKEN_PROBABILITY);
5852
5853 // Hardware token probability pass 1
5854 i965_add_buffer_gpe_surface(ctx,
5855 gpe_context,
5856 &vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer,
5857 0,
5858 size,
5859 0,
5860 VP8_BTI_TPU_PAK_HW_PASS1_PROBABILITY);
5861
5862 // key frame token probability
5863 i965_add_buffer_gpe_surface(ctx,
5864 gpe_context,
5865 &vp8_context->pak_mpu_tpu_updated_token_probability_buffer,
5866 0,
5867 size,
5868 0,
5869 VP8_BTI_TPU_UPDATED_TOKEN_PROBABILITY);
5870
5871 // update token probability
5872 i965_add_buffer_gpe_surface(ctx,
5873 gpe_context,
5874 &vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer,
5875 0,
5876 size,
5877 0,
5878 VP8_BTI_TPU_KEY_TOKEN_PROBABILITY);
5879
5880 // Hardware token probability pass 2
5881 i965_add_buffer_gpe_surface(ctx,
5882 gpe_context,
5883 &vp8_context->pak_mpu_tpu_hw_token_probability_pak_pass_2_buffer,
5884 0,
5885 size,
5886 0,
5887 VP8_BTI_TPU_PAK_HW_PASS2_PROBABILITY);
5888
5889 // Repak Decision
5890 i965_add_buffer_gpe_surface(ctx,
5891 gpe_context,
5892 &vp8_context->pak_mpu_tpu_repak_decision_buffer,
5893 0,
5894 size,
5895 0,
5896 VP8_BTI_TPU_REPAK_DECISION);
5897 }
5898
5899 static void
i965_encoder_vp8_pak_tpu(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5900 i965_encoder_vp8_pak_tpu(VADriverContextP ctx,
5901 struct encode_state *encode_state,
5902 struct intel_encoder_context *encoder_context)
5903 {
5904 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5905 struct i965_encoder_vp8_tpu_context *tpu_context = &vp8_context->tpu_context;
5906 struct i965_gpe_table *gpe = vp8_context->gpe_table;
5907 struct gpe_media_object_parameter media_object_param;
5908 struct i965_gpe_context *gpe_context;
5909 int media_function = VP8_MEDIA_STATE_TPU;
5910
5911 gpe_context = &tpu_context->gpe_contexts[0];
5912 /* gpe->context_init(ctx, gpe_context); */
5913 gpe->reset_binding_table(ctx, gpe_context);
5914
5915 if (!vp8_context->tpu_curbe_updated_in_brc_update)
5916 i965_encoder_vp8_pak_tpu_set_curbe(ctx, encode_state, encoder_context, gpe_context);
5917
5918 i965_encoder_vp8_tpu_add_surfaces(ctx, encode_state, encoder_context, gpe_context);
5919 gpe->setup_interface_data(ctx, gpe_context);
5920
5921 memset(&media_object_param, 0, sizeof(media_object_param));
5922 i965_run_kernel_media_object(ctx, encoder_context, gpe_context, media_function, &media_object_param);
5923 }
5924
5925 #define PAK_REFERENCE_BO(dst_bo, src_bo, is_ref_bo) \
5926 do { \
5927 dri_bo_unreference(dst_bo); \
5928 dst_bo = src_bo; \
5929 if (is_ref_bo) \
5930 dri_bo_reference(dst_bo); \
5931 } while (0)
5932
5933 static void
i965_encoder_vp8_pak_pipeline_prepare(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5934 i965_encoder_vp8_pak_pipeline_prepare(VADriverContextP ctx,
5935 struct encode_state *encode_state,
5936 struct intel_encoder_context *encoder_context)
5937 {
5938 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5939 struct object_surface *obj_surface;
5940 struct object_buffer *obj_buffer;
5941 struct i965_coded_buffer_segment *coded_buffer_segment;
5942 dri_bo *bo;
5943 int i;
5944
5945 /* reconstructed surface */
5946 obj_surface = encode_state->reconstructed_object;
5947 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
5948
5949 PAK_REFERENCE_BO(vp8_context->pre_deblocking_output.bo, obj_surface->bo, 1);
5950 PAK_REFERENCE_BO(vp8_context->post_deblocking_output.bo, obj_surface->bo, 1);
5951
5952 /* set vp8 reference frames */
5953 for (i = 0; i < ARRAY_ELEMS(vp8_context->reference_surfaces); i++) {
5954 obj_surface = encode_state->reference_objects[i];
5955
5956 if (obj_surface && obj_surface->bo) {
5957 PAK_REFERENCE_BO(vp8_context->reference_surfaces[i].bo, obj_surface->bo, 1);
5958 } else {
5959 PAK_REFERENCE_BO(vp8_context->reference_surfaces[i].bo, NULL, 0);
5960 }
5961 }
5962
5963 /* input YUV surface */
5964 obj_surface = encode_state->input_yuv_object;
5965 PAK_REFERENCE_BO(vp8_context->uncompressed_picture_source.bo, obj_surface->bo, 1);
5966
5967 /* coded buffer */
5968 obj_buffer = encode_state->coded_buf_object;
5969 bo = obj_buffer->buffer_store->bo;
5970 vp8_context->indirect_pak_bse_object.offset = I965_CODEDBUFFER_HEADER_SIZE;
5971 vp8_context->indirect_pak_bse_object.end_offset = ALIGN((obj_buffer->size_element - 0x1000), 0x1000);
5972 PAK_REFERENCE_BO(vp8_context->indirect_pak_bse_object.bo, bo, 1);
5973
5974 /* set the internal flag to 0 to indicate the coded size is unknown */
5975 dri_bo_map(bo, 1);
5976
5977 if (!bo->virtual)
5978 return;
5979
5980 coded_buffer_segment = (struct i965_coded_buffer_segment *)bo->virtual;
5981 coded_buffer_segment->mapped = 0;
5982 coded_buffer_segment->codec = encoder_context->codec;
5983 coded_buffer_segment->status_support = 1;
5984 dri_bo_unmap(bo);
5985 }
5986
5987 static VAStatus
i965_encoder_vp8_pak_pipeline_final(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5988 i965_encoder_vp8_pak_pipeline_final(VADriverContextP ctx,
5989 struct encode_state *encode_state,
5990 struct intel_encoder_context *encoder_context)
5991 {
5992 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5993 struct i965_encoder_vp8_tpu_context *tpu_context = &vp8_context->tpu_context;
5994
5995 dri_bo_unreference(tpu_context->dynamic_buffer);
5996 tpu_context->dynamic_buffer = NULL;
5997
5998 return VA_STATUS_SUCCESS;
5999 }
6000
6001 #undef PAK_REFERENCE_BO
6002
6003 static VAStatus
i965_encoder_vp8_pak_pipeline(VADriverContextP ctx,VAProfile profile,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)6004 i965_encoder_vp8_pak_pipeline(VADriverContextP ctx,
6005 VAProfile profile,
6006 struct encode_state *encode_state,
6007 struct intel_encoder_context *encoder_context)
6008 {
6009 struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
6010 struct intel_batchbuffer *batch = encoder_context->base.batch;
6011
6012 i965_encoder_vp8_pak_pipeline_prepare(ctx, encode_state, encoder_context);
6013
6014 vp8_context->is_render_context = 0;
6015 vp8_context->submit_batchbuffer = 1;
6016
6017 for (vp8_context->curr_pass = 0; vp8_context->curr_pass <= vp8_context->num_passes; vp8_context->curr_pass++) {
6018 vp8_context->tpu_required = ((vp8_context->curr_pass == (vp8_context->num_passes - 1) &&
6019 vp8_context->repak_pass_iter_val > 0) ||
6020 (vp8_context->curr_pass == vp8_context->num_passes &&
6021 vp8_context->repak_pass_iter_val == 0));
6022
6023 if (vp8_context->submit_batchbuffer)
6024 intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, vp8_context->vdbox_idc);
6025
6026 intel_batchbuffer_emit_mi_flush(batch);
6027 i965_encoder_vp8_pak_picture_level(ctx, encode_state, encoder_context);
6028 i965_encoder_vp8_pak_slice_level(ctx, encode_state, encoder_context);
6029
6030 if (vp8_context->submit_batchbuffer) {
6031 intel_batchbuffer_end_atomic(batch);
6032 intel_batchbuffer_flush(batch);
6033 }
6034
6035 if (vp8_context->tpu_required) {
6036 assert(vp8_context->submit_batchbuffer);
6037 i965_encoder_vp8_pak_tpu(ctx, encode_state, encoder_context);
6038 }
6039 }
6040
6041 if (!vp8_context->is_first_frame && vp8_context->is_first_two_frame)
6042 vp8_context->is_first_two_frame = 0;
6043
6044 vp8_context->is_first_frame = 0;
6045 vp8_context->tpu_curbe_updated_in_brc_update = 0;
6046
6047 i965_encoder_vp8_pak_pipeline_final(ctx, encode_state, encoder_context);
6048
6049 return VA_STATUS_SUCCESS;
6050 }
6051
6052 static void
i965_encoder_vp8_pak_tpu_context_init(VADriverContextP ctx,struct i965_encoder_vp8_context * vp8_context,struct i965_encoder_vp8_tpu_context * tpu_context)6053 i965_encoder_vp8_pak_tpu_context_init(VADriverContextP ctx,
6054 struct i965_encoder_vp8_context *vp8_context,
6055 struct i965_encoder_vp8_tpu_context *tpu_context)
6056 {
6057 struct i965_gpe_table *gpe = vp8_context->gpe_table;
6058 struct i965_gpe_context *gpe_context = NULL;
6059 struct vp8_encoder_kernel_parameters kernel_params;
6060 struct vp8_encoder_scoreboard_parameters scoreboard_params;
6061 int i;
6062
6063 kernel_params.curbe_size = sizeof(struct vp8_tpu_curbe_data);
6064 kernel_params.inline_data_size = 0;
6065 kernel_params.external_data_size = 0;
6066
6067 memset(&scoreboard_params, 0, sizeof(scoreboard_params));
6068 scoreboard_params.mask = 0xFF;
6069 scoreboard_params.enable = vp8_context->use_hw_scoreboard;
6070 scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
6071
6072 for (i = 0; i < NUM_VP8_TPU; i++) {
6073 gpe_context = &tpu_context->gpe_contexts[i];
6074 i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
6075 i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
6076 gpe->load_kernels(ctx,
6077 gpe_context,
6078 &vp8_kernels_tpu[i],
6079 1);
6080 }
6081 }
6082
6083 static void
i965_encoder_vp8_pak_kernels_context_init(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_encoder_vp8_context * vp8_context)6084 i965_encoder_vp8_pak_kernels_context_init(VADriverContextP ctx,
6085 struct intel_encoder_context *encoder_context,
6086 struct i965_encoder_vp8_context *vp8_context)
6087 {
6088 i965_encoder_vp8_pak_tpu_context_init(ctx, vp8_context, &vp8_context->tpu_context);
6089 }
6090
6091 static VAStatus
i965_encoder_vp8_get_status(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_coded_buffer_segment * coded_buffer_segment)6092 i965_encoder_vp8_get_status(VADriverContextP ctx,
6093 struct intel_encoder_context *encoder_context,
6094 struct i965_coded_buffer_segment *coded_buffer_segment)
6095 {
6096 struct vp8_encode_status *encode_state = (struct vp8_encode_status *)coded_buffer_segment->codec_private_data;
6097
6098 coded_buffer_segment->base.size = encode_state->bitstream_byte_count_per_frame;
6099
6100 return VA_STATUS_SUCCESS;
6101 }
6102
6103 Bool
i965_encoder_vp8_pak_context_init(VADriverContextP ctx,struct intel_encoder_context * encoder_context)6104 i965_encoder_vp8_pak_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
6105 {
6106 /* VME & PAK share the same context */
6107 struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
6108
6109 assert(vp8_context);
6110 i965_encoder_vp8_pak_kernels_context_init(ctx, encoder_context, vp8_context);
6111
6112 encoder_context->mfc_context = vp8_context;
6113 encoder_context->mfc_context_destroy = i965_encoder_vp8_pak_context_destroy;
6114 encoder_context->mfc_pipeline = i965_encoder_vp8_pak_pipeline;
6115 encoder_context->mfc_brc_prepare = i965_encoder_vp8_pak_pre_pipeline;
6116 encoder_context->get_status = i965_encoder_vp8_get_status;
6117
6118 return True;
6119 }
6120