1/* 2 * Copyright © <2010>, Intel Corporation. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25// Modual name: ME_header.inc 26// 27// Global symbols define 28// 29 30/* 31 * Constant 32 */ 33define(`VME_MESSAGE_TYPE_INTER', `1') 34define(`VME_MESSAGE_TYPE_INTRA', `2') 35define(`VME_MESSAGE_TYPE_MIXED', `3') 36 37define(`BLOCK_32X1', `0x0000001F') 38define(`BLOCK_4X16', `0x000F0003') 39 40define(`LUMA_INTRA_16x16_DISABLE', `0x1') 41define(`LUMA_INTRA_8x8_DISABLE', `0x2') 42define(`LUMA_INTRA_4x4_DISABLE', `0x4') 43 44define(`INTRA_PRED_AVAIL_FLAG_AE', `0x60') 45define(`INTRA_PRED_AVAIL_FLAG_B', `0x10') 46define(`INTRA_PRED_AVAIL_FLAG_C', `0x8') 47define(`INTRA_PRED_AVAIL_FLAG_D', `0x4') 48 49define(`BIND_IDX_VME', `0') 50define(`BIND_IDX_VME_REF0', `1') 51define(`BIND_IDX_VME_REF1', `2') 52define(`BIND_IDX_OUTPUT', `3') 53define(`BIND_IDX_INEP', `4') 54 55define(`SUB_PEL_MODE_INTEGER', `0x00000000') 56define(`SUB_PEL_MODE_HALF', `0x00001000') 57define(`SUB_PEL_MODE_QUARTER', `0x00003000') 58 59define(`INTER_SAD_NONE', `0x00000000') 60define(`INTER_SAD_HAAR', `0x00200000') 61 62define(`INTRA_SAD_NONE', `0x00000000') 63define(`INTRA_SAD_HAAR', `0x00800000') 64 65define(`INTER_PART_MASK', `0x00000000') 66 67define(`SEARCH_CTRL_SINGLE', `0x00000000') 68define(`SEARCH_CTRL_DUAL_START', `0x00000100') 69define(`SEARCH_CTRL_DUAL_RECORD', `0x00000300') 70define(`SEARCH_CTRL_DUAL_REFERENCE', `0x00000700') 71 72define(`REF_REGION_SIZE', `0x2830:UW') 73define(`MIN_REF_REGION_SIZE', `0x2020:UW') 74define(`DREF_REGION_SIZE', `0x2020:UW') 75 76define(`BI_SUB_MB_PART_MASK', `0x0c000000') 77define(`MAX_NUM_MV', `0x00000020') 78define(`FB_PRUNING_ENABLE', `0x40000000') 79define(`FB_PRUNING_DISABLE', `0x00000000') 80 81define(`SEARCH_PATH_LEN', `0x00003030') 82define(`START_CENTER', `0x30000000') 83 84define(`ADAPTIVE_SEARCH_ENABLE', `0x00000002') 85define(`INTRA_PREDICTORE_MODE', `0x11111111:UD') 86 87define(`INTER_VME_OUTPUT_IN_OWS', `10') 88define(`INTER_VME_OUTPUT_MV_IN_OWS', `8') 89 90define(`INTRAMBFLAG_MASK', `0x00002000') 91define(`MVSIZE_UW_BASE', `0x0040') 92define(`MFC_MV32_BIT_SHIFT', `5') 93define(`CBP_DC_YUV_UW', `0x000E') 94 95define(`DC_HARR_ENABLE', `0x0000') 96define(`DC_HARR_DISABLE', `0x0020') 97 98define(`MV32_BIT_MASK', `0x0020') 99define(`MV32_BIT_SHIFT', `5') 100 101define(`OBW_CACHE_TYPE', `10') 102 103 104define(`OBW_MESSAGE_TYPE', `8') 105 106define(`OBW_BIND_IDX', `BIND_IDX_OUTPUT') 107 108define(`OBW_CONTROL_0', `0') /* 1 OWord, low 128 bits */ 109define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */ 110define(`OBW_CONTROL_2', `2') /* 2 OWords */ 111define(`OBW_CONTROL_3', `3') /* 4 OWords */ 112define(`OBW_CONTROL_8', `4') /* 8 OWords */ 113 114define(`FME_REPART_ENABLE', `0x80000000') 115define(`FME_REPART_DISABLE', `0x00000000') 116define(`FME_SINGLE_PARTION', `0x00000000') 117define(`FME_MUL_PARTION', `0x00000008') 118 119 120define(`OBW_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ 121 122 123define(`OBW_HEADER_PRESENT', `1') 124 125/* GRF registers 126 * r0 header 127 * r1~r4 constant buffer (reserved) 128 * r5 inline data 129 * r6~r11 reserved 130 * r12 write back of VME message 131 * r13 write back of Oword Block Write 132 */ 133/* 134 * GRF 0 -- header 135 */ 136define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ 137 138/* 139 * GRF 1~4 -- Constant Buffer (reserved) 140 */ 141 142/* 143 * GRF 5 -- inline data 144 */ 145define(`inline_reg0', `r5') 146define(`w_in_mb_uw', `inline_reg0.2') 147define(`orig_xy_ub', `inline_reg0.0') 148define(`orig_x_ub', `inline_reg0.0') /* in macroblock */ 149define(`orig_y_ub', `inline_reg0.1') 150define(`transform_8x8_ub', `inline_reg0.4') 151define(`input_mb_intra_ub', `inline_reg0.5') 152define(`num_macroblocks', `inline_reg0.6') 153define(`quality_level_ub', `inline_reg0.7') 154 155define(`qp_ub', `inline_reg0.8') 156/* 157 * GRF 6~11 -- reserved 158 */ 159 160/* 161 * GRF 12~15 -- write back for VME message 162 */ 163define(`vme_wb', `r12') 164define(`vme_wb0', `r12') 165define(`vme_wb1', `r13') 166define(`vme_wb2', `r14') 167define(`vme_wb3', `r15') 168define(`vme_wb4', `r16') 169define(`vme_wb5', `r17') 170define(`vme_wb6', `r18') 171 172 173/* 174 * GRF 24 -- write for VME output message 175 */ 176define(`obw_wb', `null<1>:W') 177define(`obw_wb_length', `0') 178 179 180/* 181 * GRF 28~30 -- Intra Neighbor Edge Pixels 182 */ 183define(`INEP_ROW', `r28') 184define(`INEP_COL0', `r29') 185define(`INEP_COL1', `r30') 186 187/* 188 * temporary registers 189 */ 190define(`tmp_reg0', `r32') 191define(`read0_header', `tmp_reg0') 192define(`tmp_reg1', `r33') 193define(`read1_header', `tmp_reg1') 194define(`tmp_reg2', `r34') 195define(`vme_m0', `tmp_reg2') 196define(`tmp_reg3', `r35') 197define(`vme_m1', `tmp_reg3') 198define(`intra_flag', `vme_m1.28') 199define(`intra_part_mask_ub', `vme_m1.28') 200define(`mb_intra_struct_ub', `vme_m1.29') 201define(`tmp_reg4', `r36') 202define(`obw_m0', `tmp_reg4') 203define(`tmp_reg5', `r37') 204define(`obw_m1', `tmp_reg5') 205define(`tmp_reg6', `r38') 206define(`obw_m2', `tmp_reg6') 207define(`tmp_reg7', `r39') 208define(`obw_m3', `tmp_reg7') 209define(`tmp_reg8', `r40') 210define(`obw_m4', `tmp_reg8') 211define(`tmp_reg9', `r41') 212define(`tmp_x_w', `tmp_reg9.0') 213define(`tmp_rega', `r42') 214define(`tmp_ud0', `tmp_rega.0') 215define(`tmp_ud1', `tmp_rega.4') 216define(`tmp_ud2', `tmp_rega.8') 217define(`tmp_ud3', `tmp_rega.12') 218define(`tmp_uw0', `tmp_rega.0') 219define(`tmp_uw1', `tmp_rega.2') 220define(`tmp_uw2', `tmp_rega.4') 221define(`tmp_uw3', `tmp_rega.6') 222define(`tmp_uw4', `tmp_rega.8') 223define(`tmp_uw5', `tmp_rega.10') 224define(`tmp_uw6', `tmp_rega.12') 225define(`tmp_uw7', `tmp_rega.14') 226 227define(`vme_m2', `r43') 228/* 229 * MRF registers 230 */ 231 232define(`msg_ind', `64') 233define(`msg_reg0', `r64') 234define(`msg_reg1', `r65') 235define(`msg_reg2', `r66') 236define(`msg_reg3', `r67') 237define(`msg_reg4', `r68') 238define(`msg_reg5', `r69') 239define(`msg_reg6', `r70') 240define(`msg_reg7', `r71') 241define(`msg_reg8', `r72') 242define(`msg_reg9', `r73') 243 244define(`ts_msg_ind', `112') 245define(`ts_msg_reg0', `r112') 246/* 247 * VME message payload 248 */ 249 250define(`vme_msg_length', `5') 251define(`vme_inter_wb_length', `6') 252define(`vme_intra_wb_length', `1') 253 254define(`vme_msg_ind', `msg_ind') 255define(`vme_msg_0', `msg_reg0') 256define(`vme_msg_1', `msg_reg1') 257define(`vme_msg_2', `msg_reg2') 258 259define(`vme_msg_3', `msg_reg3') 260define(`vme_msg_4', `msg_reg4') 261 262 263define(`vme_msg_5', `msg_reg5') 264define(`vme_msg_6', `msg_reg6') 265define(`vme_msg_7', `msg_reg7') 266define(`vme_msg_8', `msg_reg8') 267define(`vme_msg_9', `msg_reg9') 268 269define(`RETURN_REG', `r127.0') 270define(`RET_ARG', `r127.4') 271 272/* Now at most two registers are used for input parameter */ 273define(`INPUT_ARG0', `r125') 274define(`INPUT_ARG1', `r126') 275 276/* Two temporal registers are used in the function */ 277define(`TEMP_VAR0', `r123') 278define(`TEMP_VAR1', `r124') 279 280 281define(`OBR_MESSAGE_TYPE', `0') 282define(`OBR_CACHE_TYPE', `10') 283define(`OBR_BIND_IDX', `BIND_IDX_OUTPUT') 284 285define(`OBR_CONTROL_0', `0') /* 1 OWord, low 128 bits */ 286define(`OBR_CONTROL_1', `1') /* 1 OWord, high 128 bits */ 287define(`OBR_CONTROL_2', `2') /* 2 OWords */ 288define(`OBR_CONTROL_4', `3') /* 4 OWords */ 289define(`OBR_CONTROL_8', `4') /* 8 OWords */ 290define(`OBR_WRITE_COMMIT_CATEGORY', `0') /* category on SNB+ for Data port */ 291define(`OBR_HEADER_PRESENT', `1') 292 293define(`mb_hwdep', `r5.6') 294define(`MB_AVAIL', `1:d') 295define(`MB_PRED_FLAG', `1:w') 296 297define(`mb_pred_mode', `r85') 298define(`mb_mvp_ref', `r86') 299define(`mba_result', `r87') 300define(`mbb_result', `r88') 301define(`mbc_result', `r89') 302define(`mb_ind', `90') 303define(`mb_msg0', `r90') 304define(`mb_msg_tmp', `r91') 305define(`mb_wb', `r92') 306define(`mb_mode_wb', `r92') 307define(`mb_mv0', `r93') 308define(`mb_mv1', `r94') 309define(`mb_mv2', `r95') 310define(`mb_mv3', `r96') 311define(`mb_ref', `r97') 312define(`mb_ref_win', `r84') 313 314define(`PRED_L0', `0x0':uw) 315define(`PRED_L1', `0x1':uw) 316define(`PRED_BI', `0x2':uw) 317define(`PRED_DIRECT', `0x3':uw) 318define(`PRED_MASK', `0x3':uw) 319 320/* The MAX search len per reference is 16 */ 321define(`DSEARCH_PATH_LEN', `0x00001212') 322define(`BI_WEIGHT', `0x20':uw) 323define(`DSTART_CENTER', `0x00000000') 324define(`INTER_MASK', `0x03') 325define(`INTER_16X16MODE', `0x0') 326define(`INTER_16X8MODE', `0x01') 327define(`INTER_8X16MODE', `0x02') 328define(`INTER_8X8MODE', `0x03') 329define(`INTER_BLOCK0', `0x0') 330define(`INTER_BLOCK1', `0x1') 331define(`INTER_BLOCK2', `0x2') 332define(`INTER_BLOCK3', `0x3') 333define(`INTER_16X8MODE', `0x01') 334define(`INTER_8X16MODE', `0x02') 335 336define(`OBR_MESSAGE_FENCE', `7') 337define(`OBR_MF_NOCOMMIT', `0') 338define(`OBR_MF_COMMIT', `0x20') 339 340define(`DEFAULT_QUALITY_LEVEL', `0x01') 341define(`HIGH_QUALITY_LEVEL', `DEFAULT_QUALITY_LEVEL') 342define(`LOW_QUALITY_LEVEL', `0x02') 343