1 /*===================== begin_copyright_notice ================================== 2 3 # Copyright (c) 2021, Intel Corporation 4 5 # Permission is hereby granted, free of charge, to any person obtaining a 6 # copy of this software and associated documentation files (the "Software"), 7 # to deal in the Software without restriction, including without limitation 8 # the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 # and/or sell copies of the Software, and to permit persons to whom the 10 # Software is furnished to do so, subject to the following conditions: 11 12 # The above copyright notice and this permission notice shall be included 13 # in all copies or substantial portions of the Software. 14 15 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 # OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_vdbox_hcp_hwcmd_xe_xpm_plus.h 26 //! \brief Auto-generated constructors for MHW and states. 27 //! \details This file may not be included outside of xe_xpm_plus as other components 28 //! should use MHW interface to interact with MHW commands and states. 29 //! 30 31 // DO NOT EDIT 32 33 #ifndef __MHW_VDBOX_HCP_HWCMD_XE_XPM_PLUS_H__ 34 #define __MHW_VDBOX_HCP_HWCMD_XE_XPM_PLUS_H__ 35 36 #include "mhw_hwcmd.h" 37 38 #pragma once 39 #pragma pack(1) 40 41 #include <cstdint> 42 #include <cstddef> 43 44 namespace mhw 45 { 46 namespace vdbox 47 { 48 namespace hcp 49 { 50 namespace xe_xpm_plus_base 51 { 52 namespace xe_xpm_plus 53 { 54 class Cmd 55 { 56 public: 57 GetOpLength(uint32_t uiLength)58 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 59 60 //! 61 //! \brief MEMORYADDRESSATTRIBUTES 62 //! \details 63 //! This field controls the priority of arbitration used in the GAC/GAM 64 //! pipeline for this surface. It defines the attributes for VDBOX addresses 65 //! on BDW+. 66 //! 67 struct MEMORYADDRESSATTRIBUTES_CMD 68 { 69 union 70 { 71 struct 72 { 73 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 74 uint32_t BaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Base Address - Index to Memory Object Control State (MOCS) Tables 75 uint32_t BaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Base Address - Arbitration Priority Control 76 uint32_t BaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Base Address - Memory Compression Enable 77 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< COMPRESSION_TYPE 78 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 79 uint32_t BaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 80 uint32_t TileMode : __CODEGEN_BITFIELD(13, 14) ; //!< TILE_MODE 81 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 82 }; 83 uint32_t Value; 84 } DW0; 85 86 //! \name Local enumerations 87 88 //! \brief COMPRESSION_TYPE 89 //! \details 90 //! Indicates if buffer is render/media compressed. 91 enum COMPRESSION_TYPE 92 { 93 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLE = 0, //!< No additional details 94 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLE = 1, //!< No additional details 95 }; 96 97 //! \brief BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 98 //! \details 99 //! This field controls if the Row Store is going to store inside Media 100 //! Cache (rowstore cache) or to LLC. 101 enum BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 102 { 103 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 104 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 105 }; 106 107 //! \brief BASE_ADDRESS_TILED_RESOURCE_MODE 108 //! \details 109 //! <b>For Media Surfaces:</b> This field specifies the tiled resource mode. 110 enum BASE_ADDRESS_TILED_RESOURCE_MODE 111 { 112 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< TileY resources 113 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 114 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 115 }; 116 117 //! \name Initializations 118 119 //! \brief Explicit member initialization function MEMORYADDRESSATTRIBUTES_CMDMEMORYADDRESSATTRIBUTES_CMD120 MEMORYADDRESSATTRIBUTES_CMD() 121 { 122 DW0.Value = 0x00000000; 123 //DW0.CompressionType = COMPRESSION_TYPE_MEDIACOMPRESSIONENABLE; 124 //DW0.BaseAddressRowStoreScratchBufferCacheSelect = BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0; 125 //DW0.BaseAddressTiledResourceMode = BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODENONE; 126 } 127 128 static const size_t dwSize = 1; 129 static const size_t byteSize = 4; 130 }; 131 132 //! 133 //! \brief SPLITBASEADDRESS64BYTEALIGNED 134 //! \details 135 //! Specifies a 64-bit (48-bit canonical) 64-byte aligned memory base 136 //! address. 137 //! 138 struct SPLITBASEADDRESS64BYTEALIGNED_CMD 139 { 140 union 141 { 142 struct 143 { 144 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 145 uint64_t BaseAddress : __CODEGEN_BITFIELD( 6, 56) ; //!< Base Address 146 uint64_t Reserved57 : __CODEGEN_BITFIELD(57, 63) ; //!< Reserved 147 }; 148 uint32_t Value[2]; 149 } DW0_1; 150 151 //! \name Local enumerations 152 153 //! \name Initializations 154 155 //! \brief Explicit member initialization function SPLITBASEADDRESS64BYTEALIGNED_CMDSPLITBASEADDRESS64BYTEALIGNED_CMD156 SPLITBASEADDRESS64BYTEALIGNED_CMD() 157 { 158 DW0_1.Value[0] = DW0_1.Value[1] = 0x00000000; 159 } 160 161 static const size_t dwSize = 2; 162 static const size_t byteSize = 8; 163 }; 164 165 //! 166 //! \brief SPLITBASEADDRESS4KBYTEALIGNED 167 //! \details 168 //! Specifies a 64-bit (48-bit canonical) 4K-byte aligned memory base 169 //! address. GraphicsAddress is a 64-bit value [63:0], but only a portion of 170 //! it is used by hardware. The upper reserved bits are ignored and MBZ. 171 //! 172 struct SPLITBASEADDRESS4KBYTEALIGNED_CMD 173 { 174 union 175 { 176 struct 177 { 178 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 179 uint64_t Graphicsaddress4712 : __CODEGEN_BITFIELD(12, 47) ; //!< GraphicsAddress47-12 180 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 181 }; 182 uint32_t Value[2]; 183 } DW0_1; 184 185 //! \name Local enumerations 186 187 //! \name Initializations 188 189 //! \brief Explicit member initialization function SPLITBASEADDRESS4KBYTEALIGNED_CMDSPLITBASEADDRESS4KBYTEALIGNED_CMD190 SPLITBASEADDRESS4KBYTEALIGNED_CMD() 191 { 192 DW0_1.Value[0] = DW0_1.Value[1] = 0x00000000; 193 } 194 195 static const size_t dwSize = 2; 196 static const size_t byteSize = 8; 197 }; 198 199 //! 200 //! \brief HCP_PIPE_MODE_SELECT 201 //! \details 202 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 203 //! Commands. Each HCP command has assigned a media instruction command as 204 //! defined in DWord 0, BitField 22:16. 205 //! 206 //! The workload for the HCP is based upon a single frame decode. There are 207 //! no states saved between frame decodes in the HCP. Once the bit stream 208 //! DMA is configured with the HCP_BSD_OBJECT command, and the bit stream is 209 //! presented to the HCP, the frame decode will begin. The 210 //! HCP_PIPE_MODE_SELECT command is responsible for general pipeline level 211 //! configuration that would normally be set once for a single stream encode 212 //! or decode and would not be modified on a frame workload basis. This is a 213 //! picture level state command and is shared by both encoding and decoding 214 //! processes. 215 //! 216 struct HCP_PIPE_MODE_SELECT_CMD 217 { 218 union 219 { 220 struct 221 { 222 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 223 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 224 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 225 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 226 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 227 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 228 }; 229 uint32_t Value; 230 } DW0; 231 union 232 { 233 struct 234 { 235 uint32_t CodecSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< CODEC_SELECT 236 uint32_t DeblockerStreamoutEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< DEBLOCKER_STREAMOUT_ENABLE 237 uint32_t PakPipelineStreamoutEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< PAK_PIPELINE_STREAMOUT_ENABLE 238 uint32_t PicStatusErrorReportEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< PIC_STATUSERROR_REPORT_ENABLE 239 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 240 uint32_t CodecStandardSelect : __CODEGEN_BITFIELD( 5, 7) ; //!< CODEC_STANDARD_SELECT 241 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 8) ; //!< Reserved 242 uint32_t AdvancedRateControlEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Advanced Rate Control Enable 243 uint32_t VdencMode : __CODEGEN_BITFIELD(10, 10) ; //!< VDEnc_Mode 244 uint32_t RdoqEnabledFlag : __CODEGEN_BITFIELD(11, 11) ; //!< RDOQ_ENABLED_FLAG 245 uint32_t PakFrameLevelStreamoutEnable : __CODEGEN_BITFIELD(12, 12) ; //!< PAK Frame Level StreamOut enable 246 uint32_t MultiEngineMode : __CODEGEN_BITFIELD(13, 14) ; //!< MULTI_ENGINE_MODE 247 uint32_t PipeWorkingMode : __CODEGEN_BITFIELD(15, 16) ; //!< PIPE_WORKING_MODE 248 uint32_t TileBasedEngine : __CODEGEN_BITFIELD(17, 17) ; //!< Tile Based Engine 249 uint32_t PrefetchDisable : __CODEGEN_BITFIELD(18, 18) ; //!< Prefetch Disable 250 uint32_t Vp9DynamicScalingEnable : __CODEGEN_BITFIELD(19, 19) ; //!< VP9 Dynamic scaling enable 251 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 22) ; //!< Reserved 252 uint32_t MotionCompMemoryTrackerCounterEnable : __CODEGEN_BITFIELD(23, 23) ; //!< Motion Comp Memory Tracker Counter Enable 253 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved56 254 }; 255 uint32_t Value; 256 } DW1; 257 union 258 { 259 struct 260 { 261 uint32_t MediaSoftResetCounterPer1000Clocks ; //!< MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 262 }; 263 uint32_t Value; 264 } DW2; 265 union 266 { 267 struct 268 { 269 uint32_t PicStatusErrorReportId ; //!< PIC_STATUSERROR_REPORT_ID 270 }; 271 uint32_t Value; 272 } DW3; 273 union 274 { 275 struct 276 { 277 uint32_t Reserved128 ; //!< Reserved 278 }; 279 uint32_t Value; 280 } DW4; 281 union 282 { 283 struct 284 { 285 uint32_t Reserved160 ; //!< Reserved 286 }; 287 uint32_t Value; 288 } DW5; 289 union 290 { 291 struct 292 { 293 uint32_t PhaseIndicator : __CODEGEN_BITFIELD( 0, 1) ; //!< PHASE_INDICATOR 294 uint32_t HevcSeparateTileProgramming : __CODEGEN_BITFIELD( 2, 2) ; //!< HEVC Separate Tile Programming 295 uint32_t FrameReconstructionDisable : __CODEGEN_BITFIELD( 3, 3) ; //!< Frame reconstruction disable 296 uint32_t Reserved196 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 297 }; 298 uint32_t Value; 299 } DW6; 300 301 //! \name Local enumerations 302 303 enum MEDIA_INSTRUCTION_COMMAND 304 { 305 MEDIA_INSTRUCTION_COMMAND_HCPPIPEMODESELECT = 0, //!< No additional details 306 }; 307 308 //! \brief MEDIA_INSTRUCTION_OPCODE 309 //! \details 310 //! Codec/Engine Name = HCP = 7h 311 enum MEDIA_INSTRUCTION_OPCODE 312 { 313 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 314 }; 315 316 enum PIPELINE_TYPE 317 { 318 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 319 }; 320 321 enum COMMAND_TYPE 322 { 323 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 324 }; 325 326 enum CODEC_SELECT 327 { 328 CODEC_SELECT_DECODE = 0, //!< No additional details 329 CODEC_SELECT_ENCODE = 1, //!< No additional details 330 }; 331 332 //! \brief DEBLOCKER_STREAMOUT_ENABLE 333 //! \details 334 //! Deblocker Streamout Enable not currently supported for Encode or Decode 335 enum DEBLOCKER_STREAMOUT_ENABLE 336 { 337 DEBLOCKER_STREAMOUT_ENABLE_DISABLE = 0, //!< Disable deblocker-only parameter streamout 338 DEBLOCKER_STREAMOUT_ENABLE_ENABLE = 1, //!< Enable deblocker-only parameter streamout 339 }; 340 341 //! \brief PAK_PIPELINE_STREAMOUT_ENABLE 342 //! \details 343 //! Pipeline Streamout Enable is only defined for encode. It is ignored for 344 //! decode. 345 enum PAK_PIPELINE_STREAMOUT_ENABLE 346 { 347 PAK_PIPELINE_STREAMOUT_ENABLE_DISABLEPIPELINESTATESANDPARAMETERSSTREAMOUT = 0, //!< No additional details 348 PAK_PIPELINE_STREAMOUT_ENABLE_ENABLEPIPELINESTATESANDPARAMETERSSTREAMOUT = 1, //!< No additional details 349 }; 350 351 enum PIC_STATUSERROR_REPORT_ENABLE 352 { 353 PIC_STATUSERROR_REPORT_ENABLE_DISABLE = 0, //!< Disable status/error reporting 354 PIC_STATUSERROR_REPORT_ENABLE_ENABLE = 1, //!< Status/Error reporting is written out once per picture. The Pic Status/Error Report ID in DWord3along with the status/error status bits are packed into one cache line and written to theStatus/Error Buffer address in the HCP_PIPE_BUF_ADDR_STATE command. Must be zero for encoder mode. 355 }; 356 357 enum CODEC_STANDARD_SELECT 358 { 359 CODEC_STANDARD_SELECT_HEVC = 0, //!< No additional details 360 CODEC_STANDARD_SELECT_VP9 = 1, //!< No additional details 361 }; 362 363 enum RDOQ_ENABLED_FLAG 364 { 365 RDOQ_ENABLED_FLAG_DISABLED = 0, //!< No additional details 366 RDOQ_ENABLED_FLAG_ENABLED = 1, //!< No additional details 367 }; 368 369 //! \brief MULTI_ENGINE_MODE 370 //! \details 371 //! <p>This indicates the current pipe is in single pipe mode or if in 372 //! scalable mode is in left/right/middle pipe in multi-engine mode.</p> 373 enum MULTI_ENGINE_MODE 374 { 375 MULTI_ENGINE_MODE_SINGLEENGINEMODEORCABACFEONLYDECODEMODE = 0, //!< This is for single engine mode (legacy) OR CABAC FE only decode mode During HEVC Decoder Scalability Real Tile Mode, for the last phase, it is possible to have single tile column left. In this case, it should be programmed with pipe as a single engine mode (using this value).For example, for 9 tile column running on 4 pipes. The first two phases will use all 4 pipes and finish 8 tile column. The remaining one column will be processed as last third phase as single tile column. 376 MULTI_ENGINE_MODE_PIPEISTHELEFTENGINEINAMULTI_ENGINEMODE = 1, //!< Current pipe is the most left engine while running in scalable multi-engine mode 377 MULTI_ENGINE_MODE_PIPEISTHERIGHTENGINEINAMULTI_ENGINEMODE = 2, //!< Current pipe is the most right engine while running in scalable multi-engine mode 378 MULTI_ENGINE_MODE_PIPEISONEOFTHEMIDDLEENGINEINAMULTI_ENGINEMODE = 3, //!< Current pipe is in one of the middle engine while running in scalable multi-engine mode 379 }; 380 381 //! \brief PIPE_WORKING_MODE 382 //! \details 383 //! <p>This programs the working mode for HCP pipe.</p> 384 enum PIPE_WORKING_MODE 385 { 386 PIPE_WORKING_MODE_LEGACYDECODERENCODERMODE_SINGLEPIPE = 0, //!< This is for single pipe mode non-scalable mode. It is used by both decoder and encoder. 387 PIPE_WORKING_MODE_CABACFEONLYDECODEMODE_SINGLECABACPIPE = 1, //!< This is for the single CABAC FE only in decoder mode. This will be only run CABAC and streamout syntax element. 388 PIPE_WORKING_MODE_DECODERBEONLYORENCODERMODE_SCALABLEMULTI_PIPE = 2, //!< This is for multiple-pipe scalable mode. In decoder, it is only on BE reconstruction. In ecoder, it is for PAK. 389 PIPE_WORKING_MODE_DECODERSCALABLEMODEWITHCABACINREALTILES_SCALABLEMULTI_PIPE = 3, //!< This is for multiple-pipe scalable mode decoder mode in real tiles. CABAC and reconstruction will run together. Each pipes will run in real tiles vertically. 390 }; 391 392 //! \brief MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 393 //! \details 394 //! In decoder modes, this counter value specifies the number of clocks (per 395 //! 1000) of GAC inactivity 396 //! before a media soft-reset is applied to the HCP and HuC. If counter 397 //! value is set to 0, the media 398 //! soft-reset feature is disabled and no reset will occur. 399 //! <p>In encoder modes, this counter must be set to 0 to disable media 400 //! soft reset. This feature is not 401 //! supported for the encoder.</p> 402 enum MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 403 { 404 MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE = 0, //!< No additional details 405 }; 406 407 //! \brief PIC_STATUSERROR_REPORT_ID 408 //! \details 409 //! The Pic Status/Error Report ID is a unique 32-bit unsigned integer 410 //! assigned to each picture 411 //! status/error output. Must be zero for encoder mode. 412 enum PIC_STATUSERROR_REPORT_ID 413 { 414 PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED = 0, //!< Unique ID Number 415 }; 416 417 //! \brief PHASE_INDICATOR 418 //! \details 419 //! <p>This is used to indicate whether this is first, middle or last phase 420 //! of programming during Real-Tile Decoder Mode. Since HEVC can have upto 421 //! 20 tile columns, maximum 10 phases are possible during 2 VDbox scalable 422 //! mode. This is used by hardware to know if the current programming is 423 //! first or last phases.</p> 424 //! <p>This field is ignored (programmed to 0) for other modes other than 425 //! HEVC Real-Tile Decoder Mode.</p> 426 enum PHASE_INDICATOR 427 { 428 PHASE_INDICATOR_FIRSTPHASE = 0, //!< No additional details 429 PHASE_INDICATOR_MIDDLEPHASE = 1, //!< No additional details 430 PHASE_INDICATOR_LASTPHASE = 2, //!< No additional details 431 }; 432 433 //! \name Initializations 434 435 //! \brief Explicit member initialization function HCP_PIPE_MODE_SELECT_CMDHCP_PIPE_MODE_SELECT_CMD436 HCP_PIPE_MODE_SELECT_CMD() 437 { 438 DW0.Value = 0x73800005; 439 //DW0.DwordLength = GetOpLength(dwSize); 440 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPIPEMODESELECT; 441 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 442 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 443 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 444 445 DW1.Value = 0x00000000; 446 //DW1.CodecSelect = CODEC_SELECT_DECODE; 447 //DW1.DeblockerStreamoutEnable = DEBLOCKER_STREAMOUT_ENABLE_DISABLE; 448 //DW1.PakPipelineStreamoutEnable = PAK_PIPELINE_STREAMOUT_ENABLE_DISABLEPIPELINESTATESANDPARAMETERSSTREAMOUT; 449 //DW1.PicStatusErrorReportEnable = PIC_STATUSERROR_REPORT_ENABLE_DISABLE; 450 //DW1.CodecStandardSelect = CODEC_STANDARD_SELECT_HEVC; 451 //DW1.RdoqEnabledFlag = RDOQ_ENABLED_FLAG_DISABLED; 452 //DW1.MultiEngineMode = MULTI_ENGINE_MODE_SINGLEENGINEMODEORCABACFEONLYDECODEMODE; 453 //DW1.PipeWorkingMode = PIPE_WORKING_MODE_LEGACYDECODERENCODERMODE_SINGLEPIPE; 454 455 DW2.Value = 0x00000000; 456 //DW2.MediaSoftResetCounterPer1000Clocks = MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE; 457 458 DW3.Value = 0x00000000; 459 //DW3.PicStatusErrorReportId = PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED; 460 461 DW4.Value = 0x00000000; 462 463 DW5.Value = 0x00000000; 464 465 DW6.Value = 0x00000000; 466 //DW6.PhaseIndicator = PHASE_INDICATOR_FIRSTPHASE; 467 } 468 469 static const size_t dwSize = 7; 470 static const size_t byteSize = 28; 471 }; 472 473 //! 474 //! \brief HCP_SURFACE_STATE 475 //! \details 476 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 477 //! Commands. Each HCP command has assigned a media instruction command as 478 //! defined in DWord 0, BitField 22:16. 479 //! 480 //! The HCP_SURFACE_STATE command is responsible for defining the frame 481 //! buffer pitch and the offset of the chroma component. This is a picture 482 //! level state command and is shared by both encoding and decoding 483 //! processes. Note : Only NV12 and Tile Y are being supported for HEVC. 484 //! Hence full pitch and interleaved UV is always in use. U and V Xoffset 485 //! must be set to 0; U and V Yoffset must be 16-pixel aligned. This Surface 486 //! State is not the same as that of the 3D engine and of the MFX pipeline. 487 //! 488 struct HCP_SURFACE_STATE_CMD 489 { 490 union 491 { 492 struct 493 { 494 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 495 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 496 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 497 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 498 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 499 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 500 }; 501 uint32_t Value; 502 } DW0; 503 union 504 { 505 struct 506 { 507 uint32_t SurfacePitchMinus1 : __CODEGEN_BITFIELD( 0, 16) ; //!< Surface Pitch Minus1 508 uint32_t Reserved49 : __CODEGEN_BITFIELD(17, 27) ; //!< Reserved 509 uint32_t SurfaceId : __CODEGEN_BITFIELD(28, 31) ; //!< SURFACE_ID 510 }; 511 uint32_t Value; 512 } DW1; 513 union 514 { 515 struct 516 { 517 uint32_t YOffsetForUCbInPixel : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) in pixel 518 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 26) ; //!< Reserved 519 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 520 }; 521 uint32_t Value; 522 } DW2; 523 union 524 { 525 struct 526 { 527 uint32_t DefaultAlphaValue : __CODEGEN_BITFIELD( 0, 15) ; //!< Default Alpha Value 528 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD(16, 31) ; //!< Y Offset for V(Cr) 529 }; 530 uint32_t Value; 531 } DW3; 532 union 533 { 534 struct 535 { 536 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD( 0, 7) ; //!< MEMORY_COMPRESSION_ENABLE 537 uint32_t CompressionType : __CODEGEN_BITFIELD( 8, 15) ; //!< COMPRESSION_TYPE 538 uint32_t CompressionFormat : __CODEGEN_BITFIELD(16, 20) ; //!< COMPRESSION_FORMAT 539 uint32_t Reserved149 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 540 }; 541 uint32_t Value; 542 } DW4; 543 544 //! \name Local enumerations 545 546 enum MEDIA_INSTRUCTION_COMMAND 547 { 548 MEDIA_INSTRUCTION_COMMAND_HCPSURFACESTATE = 1, //!< No additional details 549 }; 550 551 //! \brief MEDIA_INSTRUCTION_OPCODE 552 //! \details 553 //! Codec/Engine Name = HCP = 7h 554 enum MEDIA_INSTRUCTION_OPCODE 555 { 556 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 557 }; 558 559 enum PIPELINE_TYPE 560 { 561 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 562 }; 563 564 enum COMMAND_TYPE 565 { 566 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 567 }; 568 569 enum SURFACE_ID 570 { 571 SURFACE_ID_HEVCFORCURRENTDECODEDPICTURE = 0, //!< 8-bit uncompressed data 572 SURFACE_ID_SOURCEINPUTPICTURE_ENCODER = 1, //!< 8-bit uncompressed data 573 SURFACE_ID_PREVREFERENCEPICTURE = 2, //!< (VP9 only) Previous Reference 574 SURFACE_ID_GOLDENREFERENCEPICTURE = 3, //!< (VP9 only) Golden Reference 575 SURFACE_ID_ALTREFREFERENCEPICTURE = 4, //!< (VP9 only) AltRef Reference 576 SURFACE_ID_HEVCREFERENCEPICTURES = 5, //!< (HEVC only) Reference. Also, this will have separate compressible bits per reference surfaces for HEVC 577 }; 578 579 //! \brief SURFACE_FORMAT 580 //! \details 581 //! <p>Specifies the format of the surface.</p> 582 enum SURFACE_FORMAT 583 { 584 SURFACE_FORMAT_YUY2FORMAT = 0, //!< No additional details 585 SURFACE_FORMAT_RGB8FORMAT = 1, //!< No additional details 586 SURFACE_FORMAT_AYUV4444FORMAT = 2, //!< No additional details 587 SURFACE_FORMAT_P010VARIANT = 3, //!< No additional details 588 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details 589 SURFACE_FORMAT_YCRCBSWAPYFORMAT = 5, //!< No additional details 590 SURFACE_FORMAT_YCRCBSWAPUVFORMAT = 6, //!< No additional details 591 SURFACE_FORMAT_YCRCBSWAPUVYFORMAT = 7, //!< No additional details 592 SURFACE_FORMAT_Y216Y210FORMAT = 8, //!< Same value is used to represent Y216 and Y210 593 SURFACE_FORMAT_RGB10FORMAT = 9, //!< No additional details 594 SURFACE_FORMAT_Y410FORMAT = 10, //!< No additional details 595 SURFACE_FORMAT_NV21PLANAR4208FORMAT = 11, //!< No additional details 596 SURFACE_FORMAT_Y416FORMAT = 12, //!< No additional details 597 SURFACE_FORMAT_P010 = 13, //!< No additional details 598 SURFACE_FORMAT_P016 = 14, //!< No additional details 599 SURFACE_FORMAT_Y8FORMAT = 15, //!< No additional details 600 SURFACE_FORMAT_Y16FORMAT = 16, //!< No additional details 601 SURFACE_FORMAT_Y216VARIANT = 17, //!< Y216Variant is the modifed Y210/Y216 format, 8 bit planar 422 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The chroma is UV interleaved with identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 602 SURFACE_FORMAT_Y416VARIANT = 18, //!< Y416Variant is the modifed Y410/Y412/Y416 format,8 bit planar 444 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The U channel is below the luma, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma The V channel is below the U, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 603 SURFACE_FORMAT_YUY2VARIANT = 19, //!< YUY2Variant is the modifed YUY2 format, 8 bit planar 422. The chroma is UV interleaved and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 604 SURFACE_FORMAT_AYUV4444VARIANT = 20, //!< AYUV4444Variant is the modifed AYUV4444 format, 8 bit planar 444 format. The U channel is below the luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. The V channel is below the and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 605 }; 606 607 //! \brief MEMORY_COMPRESSION_ENABLE 608 //! \details 609 //! <p>In HEVC mode, each bit is used for 1 reference starting with Bit 0 610 //! for Ref 0 in the ref list and Bit 1 for Ref 1 and so on.</p> 611 //! <p>In VP9 mode, Bit 0 is for Previous Reference; Bit 1 is for Golden 612 //! Reference and Bit 2 is for Alterante Reference; Bits 3-7 are unused and 613 //! should be programmed to 0.</p> 614 enum MEMORY_COMPRESSION_ENABLE 615 { 616 MEMORY_COMPRESSION_ENABLE_MEMORYCOMPRESSIONDISABLE = 0, //!< No additional details 617 MEMORY_COMPRESSION_ENABLE_MEMORYCOMPRESSIONENABLE = 1, //!< No additional details 618 }; 619 620 //! \brief COMPRESSION_TYPE 621 //! \details 622 //! <p>This field indicates if the compression type for the reference 623 //! surface is media or render compressed.</p> 624 //! <p>In HEVC mode, each bit is used for 1 reference starting with Bit 8for 625 //! Ref 0 in the ref list and Bit 9for Ref 1 and so on.</p> 626 //! <p>In VP9 mode, Bit 8is for Previous Reference; Bit 9is for Golden 627 //! Reference and Bit 10is for Alterante Reference; Bits11-15are unused and 628 //! should be programmed to 0</p> 629 enum COMPRESSION_TYPE 630 { 631 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLED = 0, //!< No additional details 632 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLED = 1, //!< No additional details 633 }; 634 635 //! \name Initializations 636 637 //! \brief Explicit member initialization function HCP_SURFACE_STATE_CMDHCP_SURFACE_STATE_CMD638 HCP_SURFACE_STATE_CMD() 639 { 640 DW0.Value = 0x73810003; 641 //DW0.DwordLength = GetOpLength(dwSize); 642 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPSURFACESTATE; 643 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 644 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 645 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 646 647 DW1.Value = 0x00000000; 648 //DW1.SurfaceId = SURFACE_ID_HEVCFORCURRENTDECODEDPICTURE; 649 650 DW2.Value = 0x00000000; 651 //DW2.SurfaceFormat = SURFACE_FORMAT_YUY2FORMAT; 652 653 DW3.Value = 0x00000000; 654 655 DW4.Value = 0x00000000; 656 //DW4.MemoryCompressionEnable = MEMORY_COMPRESSION_ENABLE_MEMORYCOMPRESSIONDISABLE; 657 //DW4.CompressionType = COMPRESSION_TYPE_MEDIACOMPRESSIONENABLED; 658 //DW4.CompressionFormat = GMM_E2ECOMP_FORMAT_INVALID; 659 } 660 661 static const size_t dwSize = 5; 662 static const size_t byteSize = 20; 663 }; 664 665 //! 666 //! \brief HCP_PIPE_BUF_ADDR_STATE 667 //! \details 668 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 669 //! Commands. Each HCP command has assigned a media instruction command as 670 //! defined in DWord 0, BitField 22:16. 671 //! 672 //! This state command provides the memory base addresses for the row store 673 //! buffer and reconstructed picture output buffers required by the HCP. 674 //! This is a picture level state command and is shared by both encoding and 675 //! decoding processes. 676 //! 677 //! All pixel surface addresses must be 4K byte aligned. There is a max of 8 678 //! Reference Picture Buffer Addresses, and all share the same third address 679 //! DW in specifying 48-bit address. 680 //! 681 struct HCP_PIPE_BUF_ADDR_STATE_CMD 682 { 683 union 684 { 685 struct 686 { 687 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 688 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 689 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 690 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 691 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 692 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 693 }; 694 uint32_t Value; 695 } DW0; 696 SPLITBASEADDRESS4KBYTEALIGNED_CMD DecodedPicture; //!< DW1..2, Decoded Picture 697 MEMORYADDRESSATTRIBUTES_CMD DecodedPictureMemoryAddressAttributes; //!< DW3, Decoded Picture Memory Address Attributes 698 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterLineBuffer; //!< DW4..5, Deblocking Filter Line Buffer 699 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterLineBufferMemoryAddressAttributes; //!< DW6, Deblocking Filter Line Buffer Memory Address Attributes 700 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterTileLineBuffer; //!< DW7..8, Deblocking Filter Tile Line Buffer 701 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterTileLineBufferMemoryAddressAttributes; //!< DW9, Deblocking Filter Tile Line Buffer Memory Address Attributes 702 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterTileColumnBuffer; //!< DW10..11, Deblocking Filter Tile Column Buffer 703 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterTileColumnBufferMemoryAddressAttributes; //!< DW12, Deblocking Filter Tile Column Buffer Memory Address Attributes 704 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataLineBuffer; //!< DW13..14, Metadata Line Buffer 705 MEMORYADDRESSATTRIBUTES_CMD MetadataLineBufferMemoryAddressAttributes; //!< DW15, Metadata Line Buffer Memory Address Attributes 706 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataTileLineBuffer; //!< DW16..17, Metadata Tile Line Buffer 707 MEMORYADDRESSATTRIBUTES_CMD MetadataTileLineBufferMemoryAddressAttributes; //!< DW18, Metadata Tile Line Buffer Memory Address Attributes 708 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataTileColumnBuffer; //!< DW19..20, Metadata Tile Column Buffer 709 MEMORYADDRESSATTRIBUTES_CMD MetadataTileColumnBufferMemoryAddressAttributes; //!< DW21, Metadata Tile Column Buffer Memory Address Attributes 710 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoLineBuffer; //!< DW22..23, SAO Line Buffer 711 MEMORYADDRESSATTRIBUTES_CMD SaoLineBufferMemoryAddressAttributes; //!< DW24, SAO Line Buffer Memory Address Attributes 712 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoTileLineBuffer; //!< DW25..26, SAO Tile Line Buffer 713 MEMORYADDRESSATTRIBUTES_CMD SaoTileLineBufferMemoryAddressAttributes; //!< DW27, SAO Tile Line Buffer Memory Address Attributes 714 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoTileColumnBuffer; //!< DW28..29, SAO Tile Column Buffer 715 MEMORYADDRESSATTRIBUTES_CMD SaoTileColumnBufferMemoryAddressAttributes; //!< DW30, SAO Tile Column Buffer Memory Address Attributes 716 SPLITBASEADDRESS64BYTEALIGNED_CMD CurrentMotionVectorTemporalBuffer; //!< DW31..32, Current Motion Vector Temporal Buffer 717 MEMORYADDRESSATTRIBUTES_CMD CurrentMotionVectorTemporalBufferMemoryAddressAttributes; //!< DW33, Current Motion Vector Temporal Buffer Memory Address Attributes 718 union 719 { 720 struct 721 { 722 uint64_t Reserved1088 ; //!< Reserved 723 }; 724 uint32_t Value[2]; 725 } DW34_35; 726 union 727 { 728 struct 729 { 730 uint32_t Reserved1152 ; //!< Reserved 731 }; 732 uint32_t Value; 733 } DW36; 734 SPLITBASEADDRESS64BYTEALIGNED_CMD ReferencePictureBaseAddressRefaddr07[8]; //!< DW37..52, Reference Picture Base Address (RefAddr[0-7]) 735 MEMORYADDRESSATTRIBUTES_CMD ReferencePictureBaseAddressMemoryAddressAttributes; //!< DW53, Reference Picture Base Address Memory Address Attributes 736 SPLITBASEADDRESS64BYTEALIGNED_CMD OriginalUncompressedPictureSource; //!< DW54..55, Original Uncompressed Picture Source 737 MEMORYADDRESSATTRIBUTES_CMD OriginalUncompressedPictureSourceMemoryAddressAttributes; //!< DW56, Original Uncompressed Picture Source Memory Address Attributes 738 SPLITBASEADDRESS64BYTEALIGNED_CMD StreamoutDataDestination; //!< DW57..58, Streamout Data Destination 739 MEMORYADDRESSATTRIBUTES_CMD StreamoutDataDestinationMemoryAddressAttributes; //!< DW59, Streamout Data Destination Memory Address Attributes, Decoder Only 740 SPLITBASEADDRESS64BYTEALIGNED_CMD DecodedPictureStatusErrorBufferBaseAddressOrEncodedSliceSizeStreamoutBaseAddress;//!< DW60..61, Decoded Picture Status/Error Buffer Base Address or Encoded slice size streamout Base Address 741 MEMORYADDRESSATTRIBUTES_CMD DecodedPictureStatusErrorBufferBaseAddressMemoryAddressAttributes; //!< DW62, Decoded Picture Status/Error Buffer Base Address Memory Address Attributes 742 SPLITBASEADDRESS64BYTEALIGNED_CMD LcuIldbStreamoutBuffer; //!< DW63..64, LCU ILDB Streamout Buffer 743 MEMORYADDRESSATTRIBUTES_CMD LcuIldbStreamoutBufferMemoryAddressAttributes; //!< DW65, LCU ILDB Streamout Buffer Memory Address Attributes 744 SPLITBASEADDRESS64BYTEALIGNED_CMD CollocatedMotionVectorTemporalBuffer07[8]; //!< DW66..81, Collocated Motion Vector Temporal Buffer[0-7] 745 MEMORYADDRESSATTRIBUTES_CMD CollocatedMotionVectorTemporalBuffer07MemoryAddressAttributes; //!< DW82, Collocated Motion Vector Temporal Buffer[0-7] Memory Address Attributes 746 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9ProbabilityBufferReadWrite; //!< DW83..84, VP9 Probability Buffer Read/Write 747 MEMORYADDRESSATTRIBUTES_CMD Vp9ProbabilityBufferReadWriteMemoryAddressAttributes; //!< DW85, VP9 Probability Buffer Read/Write Memory Address Attributes 748 union 749 { 750 struct 751 { 752 uint64_t Vp9SegmentIdBufferReadWrite ; //!< VP9 Segment ID Buffer Read/Write 753 }; 754 uint32_t Value[2]; 755 } DW86_87; 756 MEMORYADDRESSATTRIBUTES_CMD Vp9SegmentIdBufferReadWriteMemoryAddressAttributes; //!< DW88, VP9 Segment ID buffer Read/Write Memory Address Attributes 757 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9HvdLineRowstoreBufferReadWrite; //!< DW89..90, VP9 HVD Line Rowstore Buffer Read/Write 758 MEMORYADDRESSATTRIBUTES_CMD Vp9HvdLineRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW91, VP9 HVD Line Rowstore buffer Read/Write Memory Address Attributes 759 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9HvdTileRowstoreBufferReadWrite; //!< DW92..93, VP9 HVD Tile Rowstore Buffer Read/Write 760 MEMORYADDRESSATTRIBUTES_CMD Vp9HvdTileRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW94, VP9 HVD Tile Rowstore buffer Read/Write Memory Address Attributes 761 union 762 { 763 struct 764 { 765 uint64_t SaoRowstoreBufferBaseAddress ; //!< SAO Rowstore Buffer Base Address 766 }; 767 uint32_t Value[2]; 768 } DW95_96; 769 MEMORYADDRESSATTRIBUTES_CMD SaoRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW97, SAO Rowstore Buffer Read/Write Memory Address Attributes 770 SPLITBASEADDRESS64BYTEALIGNED_CMD FrameStatisticsStreamoutDataDestinationBufferBaseAddress; //!< DW98..99, Frame Statistics Streamout Data Destination Buffer Base Address 771 MEMORYADDRESSATTRIBUTES_CMD FrameStatisticsStreamoutDataDestinationBufferAttributesReadWrite; //!< DW100, Frame Statistics Streamout Data Destination buffer (attributes) Read/Write 772 SPLITBASEADDRESS64BYTEALIGNED_CMD SseSourcePixelRowstoreBufferBaseAddress; //!< DW101..102, SSE Source Pixel RowStore Buffer Base Address 773 MEMORYADDRESSATTRIBUTES_CMD SseSourcePixelRowstoreBufferAttributesReadWrite; //!< DW103, SSE Source Pixel RowStore buffer (attributes) Read/Write 774 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilitySliceStateBufferBaseAddress; //!< DW104..105, HCP Scalability Slice State Buffer Base Address 775 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilitySliceStateBufferAttributesReadWrite; //!< DW106, HCP Scalability Slice State Buffer (attributes) Read/Write 776 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferBaseAddress; //!< DW107..108, HCP Scalability CABAC Decoded Syntax Elements Buffer Base Address 777 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferAttributesReadWrite; //!< DW109, HCP Scalability CABAC Decoded Syntax Elements Buffer (attributes) Read/Write 778 SPLITBASEADDRESS64BYTEALIGNED_CMD MotionVectorUpperRightColumnStoreBufferBaseAddress; //!< DW110..111, Motion Vector Upper Right Column Store Buffer Base Address 779 MEMORYADDRESSATTRIBUTES_CMD MotionVectorUpperRightColumnStoreBufferAttributesReadWrite; //!< DW112, Motion Vector Upper Right Column Store Buffer (attributes) Read/Write 780 SPLITBASEADDRESS64BYTEALIGNED_CMD IntraPredictionUpperRightColumnStoreBufferBaseAddress; //!< DW113..114, Intra Prediction Upper Right Column Store Buffer Base Address 781 MEMORYADDRESSATTRIBUTES_CMD IntraPredictionUpperRightColumnStoreBufferAttributesReadWrite; //!< DW115, Intra Prediction Upper Right Column Store Buffer (attributes) Read/Write 782 SPLITBASEADDRESS64BYTEALIGNED_CMD IntraPredictionLeftReconColumnStoreBufferBaseAddress; //!< DW116..117, Intra Prediction Left Recon Column Store Buffer Base Address 783 MEMORYADDRESSATTRIBUTES_CMD IntraPredictionLeftReconColumnStoreBufferAttributesReadWrite; //!< DW118, Intra Prediction Left Recon Column Store Buffer (attributes) Read/Write 784 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferMaxAddress; //!< DW119..120, HCP Scalability CABAC Decoded Syntax Elements Buffer Max Address 785 786 //! \name Local enumerations 787 788 enum MEDIA_INSTRUCTION_COMMAND 789 { 790 MEDIA_INSTRUCTION_COMMAND_HCPPIPEBUFADDRSTATE = 2, //!< No additional details 791 }; 792 793 //! \brief MEDIA_INSTRUCTION_OPCODE 794 //! \details 795 //! Codec/Engine Name = HCP = 7h 796 enum MEDIA_INSTRUCTION_OPCODE 797 { 798 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 799 }; 800 801 enum PIPELINE_TYPE 802 { 803 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 804 }; 805 806 enum COMMAND_TYPE 807 { 808 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 809 }; 810 811 //! \name Initializations 812 813 //! \brief Explicit member initialization function HCP_PIPE_BUF_ADDR_STATE_CMDHCP_PIPE_BUF_ADDR_STATE_CMD814 HCP_PIPE_BUF_ADDR_STATE_CMD() 815 { 816 DW0.Value = 0x73820077; 817 //DW0.DwordLength = GetOpLength(dwSize); 818 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPIPEBUFADDRSTATE; 819 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 820 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 821 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 822 823 DW34_35.Value[0] = DW34_35.Value[1] = 0x00000000; 824 825 DW36.Value = 0x00000000; 826 827 DW86_87.Value[0] = DW86_87.Value[1] = 0x00000000; 828 829 DW95_96.Value[0] = DW95_96.Value[1] = 0x00000000; 830 } 831 832 static const size_t dwSize = 121; 833 static const size_t byteSize = 484; 834 }; 835 836 //! 837 //! \brief HCP_IND_OBJ_BASE_ADDR_STATE 838 //! \details 839 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 840 //! Commands. Each HCP command has assigned a media instruction command as 841 //! defined in DWord 0, BitField 22:16. 842 //! 843 //! The HCP_IND_OBJ_BASE_ADDR_STATE command is used to define the indirect 844 //! object base address of the stream in graphics memory. This is a frame 845 //! level command. (Is it frame or picture level?) 846 //! This is a picture level state command and is issued in both encoding and 847 //! decoding processes. 848 //! 849 //! Compressed Header Format 850 //! 851 //! 852 //! 853 struct HCP_IND_OBJ_BASE_ADDR_STATE_CMD 854 { 855 union 856 { 857 struct 858 { 859 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 860 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 861 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 862 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 863 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 864 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 865 }; 866 uint32_t Value; 867 } DW0; 868 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpIndirectBitstreamObjectBaseAddress; //!< DW1..2, HCP Indirect Bitstream Object Base Address 869 MEMORYADDRESSATTRIBUTES_CMD HcpIndirectBitstreamObjectMemoryAddressAttributes; //!< DW3, HCP Indirect Bitstream Object Memory Address Attributes 870 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpIndirectBitstreamObjectAccessUpperBound; //!< DW4..5, HCP Indirect Bitstream Object Access Upper Bound 871 union 872 { 873 struct 874 { 875 uint64_t HcpIndirectCuObjectBaseAddress ; //!< HCP Indirect CU Object Base Address 876 }; 877 uint32_t Value[2]; 878 } DW6_7; 879 MEMORYADDRESSATTRIBUTES_CMD HcpIndirectCuObjectObjectMemoryAddressAttributes; //!< DW8, HCP Indirect CU Object Object Memory Address Attributes 880 union 881 { 882 struct 883 { 884 uint64_t HcpPakBseObjectBaseAddress ; //!< HCP PAK-BSE Object Base Address 885 }; 886 uint32_t Value[2]; 887 } DW9_10; 888 MEMORYADDRESSATTRIBUTES_CMD HcpPakBseObjectAddressMemoryAddressAttributes; //!< DW11, HCP PAK-BSE Object Address Memory Address Attributes 889 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpPakBseObjectAccessUpperBound; //!< DW12..13, HCP PAK-BSE Object Access Upper Bound 890 union 891 { 892 struct 893 { 894 uint64_t HcpVp9PakCompressedHeaderSyntaxStreaminBaseAddress ; //!< HCP VP9 PAK Compressed Header Syntax Streamin- Base Address 895 }; 896 uint32_t Value[2]; 897 } DW14_15; 898 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakCompressedHeaderSyntaxStreaminMemoryAddressAttributes; //!< DW16, HCP VP9 PAK Compressed Header Syntax StreamIn Memory Address Attributes 899 union 900 { 901 struct 902 { 903 uint64_t HcpVp9PakProbabilityCounterStreamoutBaseAddress ; //!< HCP VP9 PAK Probability Counter StreamOut- Base Address 904 }; 905 uint32_t Value[2]; 906 } DW17_18; 907 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakProbabilityCounterStreamoutMemoryAddressAttributes; //!< DW19, HCP VP9 PAK Probability Counter StreamOut Memory Address Attributes 908 union 909 { 910 struct 911 { 912 uint64_t HcpVp9PakProbabilityDeltasStreaminBaseAddress ; //!< HCP VP9 PAK Probability Deltas StreamIn- Base Address 913 }; 914 uint32_t Value[2]; 915 } DW20_21; 916 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakProbabilityDeltasStreaminMemoryAddressAttributes; //!< DW22, HCP VP9 PAK Probability Deltas StreamIn Memory Address Attributes 917 union 918 { 919 struct 920 { 921 uint64_t HcpVp9PakTileRecordStreamoutBaseAddress ; //!< HCP VP9 PAK Tile Record StreamOut- Base Address 922 }; 923 uint32_t Value[2]; 924 } DW23_24; 925 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakTileRecordStreamoutMemoryAddressAttributes; //!< DW25, HCP VP9 PAK Tile Record StreamOut Memory Address Attributes 926 union 927 { 928 struct 929 { 930 uint64_t HcpVp9PakCuLevelStatisticStreamoutBaseAddress ; //!< HCP VP9 PAK CU Level Statistic StreamOut- Base Address 931 }; 932 uint32_t Value[2]; 933 } DW26_27; 934 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakCuLevelStatisticStreamoutMemoryAddressAttributes; //!< DW28, HCP VP9 PAK CU Level Statistic StreamOut Memory Address Attributes 935 936 //! \name Local enumerations 937 938 enum MEDIA_INSTRUCTION_COMMAND 939 { 940 MEDIA_INSTRUCTION_COMMAND_HCPINDOBJBASEADDRSTATE = 3, //!< No additional details 941 }; 942 943 //! \brief MEDIA_INSTRUCTION_OPCODE 944 //! \details 945 //! Codec/Engine Name = HCP = 7h 946 enum MEDIA_INSTRUCTION_OPCODE 947 { 948 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 949 }; 950 951 enum PIPELINE_TYPE 952 { 953 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 954 }; 955 956 enum COMMAND_TYPE 957 { 958 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 959 }; 960 961 //! \name Initializations 962 963 //! \brief Explicit member initialization function HCP_IND_OBJ_BASE_ADDR_STATE_CMDHCP_IND_OBJ_BASE_ADDR_STATE_CMD964 HCP_IND_OBJ_BASE_ADDR_STATE_CMD() 965 { 966 DW0.Value = 0x7383001b; 967 //DW0.DwordLength = GetOpLength(dwSize); 968 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPINDOBJBASEADDRSTATE; 969 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 970 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 971 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 972 973 DW6_7.Value[0] = DW6_7.Value[1] = 0x00000000; 974 975 DW9_10.Value[0] = DW9_10.Value[1] = 0x00000000; 976 977 DW14_15.Value[0] = DW14_15.Value[1] = 0x00000000; 978 979 DW17_18.Value[0] = DW17_18.Value[1] = 0x00000000; 980 981 DW20_21.Value[0] = DW20_21.Value[1] = 0x00000000; 982 983 DW23_24.Value[0] = DW23_24.Value[1] = 0x00000000; 984 985 DW26_27.Value[0] = DW26_27.Value[1] = 0x00000000; 986 } 987 988 static const size_t dwSize = 29; 989 static const size_t byteSize = 116; 990 }; 991 992 //! 993 //! \brief HCP_QM_STATE 994 //! \details 995 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 996 //! Commands. Each HCP command has assigned a media instruction command as 997 //! defined in DWord 0, BitField 22:16. 998 //! 999 //! The HCP_QM_STATE command loads the custom HEVC quantization tables into 1000 //! local RAM and may be issued up to 20 times: 3x Colour Component plus 2x 1001 //! intra/inter plus 4x SizeID minus 4 for the 32x32 chroma components. When 1002 //! the scaling_list_enable_flag is set to disable, the scaling matrix is 1003 //! still sent to the decoder, and with all entries programmed to the same 1004 //! value = 16. This is a picture level state command and is issued in both 1005 //! encoding and decoding processes. 1006 //! 1007 //! Dwords 2-17 form a table for the DCT coefficients, 4 8-bit 1008 //! coefficients/DWord. Size 4x4 for SizeID0, DWords 2-5. 1009 //! Size 8x8 for SizeID1/2/3, DWords 2-17. 1010 //! 1011 //! 1012 //! SizeID 0 (Table 4-10) 1013 //! 1014 struct HCP_QM_STATE_CMD 1015 { 1016 union 1017 { 1018 struct 1019 { 1020 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1021 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1022 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 1023 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 1024 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 1025 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1026 }; 1027 uint32_t Value; 1028 } DW0; 1029 union 1030 { 1031 struct 1032 { 1033 uint32_t PredictionType : __CODEGEN_BITFIELD( 0, 0) ; //!< PREDICTION_TYPE 1034 uint32_t Sizeid : __CODEGEN_BITFIELD( 1, 2) ; //!< SIZEID 1035 uint32_t ColorComponent : __CODEGEN_BITFIELD( 3, 4) ; //!< COLOR_COMPONENT 1036 uint32_t DcCoefficient : __CODEGEN_BITFIELD( 5, 12) ; //!< DC Coefficient 1037 uint32_t Reserved45 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1038 }; 1039 uint32_t Value; 1040 } DW1; 1041 uint32_t Quantizermatrix[16]; //!< QuantizerMatrix 1042 1043 //! \name Local enumerations 1044 1045 enum MEDIA_INSTRUCTION_COMMAND 1046 { 1047 MEDIA_INSTRUCTION_COMMAND_HCPQMSTATE = 4, //!< No additional details 1048 }; 1049 1050 //! \brief MEDIA_INSTRUCTION_OPCODE 1051 //! \details 1052 //! Codec/Engine Name = HCP = 7h 1053 enum MEDIA_INSTRUCTION_OPCODE 1054 { 1055 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1056 }; 1057 1058 enum PIPELINE_TYPE 1059 { 1060 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1061 }; 1062 1063 enum COMMAND_TYPE 1064 { 1065 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1066 }; 1067 1068 enum PREDICTION_TYPE 1069 { 1070 PREDICTION_TYPE_INTRA = 0, //!< No additional details 1071 PREDICTION_TYPE_INTER = 1, //!< No additional details 1072 }; 1073 1074 enum SIZEID 1075 { 1076 SIZEID_4X4 = 0, //!< No additional details 1077 SIZEID_8X8 = 1, //!< No additional details 1078 SIZEID_16X16 = 2, //!< No additional details 1079 SIZEID_32X32 = 3, //!< (Illegal Value for Colour Component Chroma Cr and Cb.) 1080 }; 1081 1082 //! \brief COLOR_COMPONENT 1083 //! \details 1084 //! Encoder: When RDOQ is enabled, scaling list for all 3 color components 1085 //! must be same. So this field is set to always 0. 1086 enum COLOR_COMPONENT 1087 { 1088 COLOR_COMPONENT_LUMA = 0, //!< No additional details 1089 COLOR_COMPONENT_CHROMACB = 1, //!< No additional details 1090 COLOR_COMPONENT_CHROMACR = 2, //!< No additional details 1091 }; 1092 1093 //! \name Initializations 1094 1095 //! \brief Explicit member initialization function HCP_QM_STATE_CMDHCP_QM_STATE_CMD1096 HCP_QM_STATE_CMD() 1097 { 1098 DW0.Value = 0x73840010; 1099 //DW0.DwordLength = GetOpLength(dwSize); 1100 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPQMSTATE; 1101 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 1102 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 1103 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 1104 1105 DW1.Value = 0x00000000; 1106 //DW1.PredictionType = PREDICTION_TYPE_INTRA; 1107 //DW1.Sizeid = SIZEID_4X4; 1108 //DW1.ColorComponent = COLOR_COMPONENT_LUMA; 1109 1110 memset(&Quantizermatrix, 0, sizeof(Quantizermatrix)); 1111 } 1112 1113 static const size_t dwSize = 18; 1114 static const size_t byteSize = 72; 1115 }; 1116 1117 //! 1118 //! \brief HCP_PIC_STATE 1119 //! \details 1120 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 1121 //! Commands. Each HCP command has assigned a media instruction command as 1122 //! defined in DWord 0, BitField 22:16. 1123 //! 1124 //! This is a picture level command and is issued only once per workload for 1125 //! both encoding and decoding processes. 1126 //! 1127 struct HCP_PIC_STATE_CMD 1128 { 1129 union 1130 { 1131 struct 1132 { 1133 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1134 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1135 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 1136 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 1137 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 1138 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1139 }; 1140 uint32_t Value; 1141 } DW0; 1142 union 1143 { 1144 struct 1145 { 1146 uint32_t Framewidthinmincbminus1 : __CODEGEN_BITFIELD( 0, 10) ; //!< FrameWidthInMinCbMinus1 1147 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 14) ; //!< Reserved 1148 uint32_t PakTransformSkipEnable : __CODEGEN_BITFIELD(15, 15) ; //!< PAK Transform Skip Enable 1149 uint32_t Frameheightinmincbminus1 : __CODEGEN_BITFIELD(16, 26) ; //!< FrameHeightInMinCbMinus1 1150 uint32_t Reserved59 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1151 }; 1152 uint32_t Value; 1153 } DW1; 1154 union 1155 { 1156 struct 1157 { 1158 uint32_t Mincusize : __CODEGEN_BITFIELD( 0, 1) ; //!< MINCUSIZE 1159 uint32_t CtbsizeLcusize : __CODEGEN_BITFIELD( 2, 3) ; //!< CTBSIZE_LCUSIZE 1160 uint32_t Mintusize : __CODEGEN_BITFIELD( 4, 5) ; //!< MINTUSIZE 1161 uint32_t Maxtusize : __CODEGEN_BITFIELD( 6, 7) ; //!< MAXTUSIZE 1162 uint32_t Minpcmsize : __CODEGEN_BITFIELD( 8, 9) ; //!< MINPCMSIZE 1163 uint32_t Maxpcmsize : __CODEGEN_BITFIELD(10, 11) ; //!< MAXPCMSIZE 1164 uint32_t Log2SaoOffsetScaleLuma : __CODEGEN_BITFIELD(12, 14) ; //!< LOG2_SAO_OFFSET_SCALE_LUMA 1165 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1166 uint32_t Log2SaoOffsetScaleChroma : __CODEGEN_BITFIELD(16, 18) ; //!< LOG2_SAO_OFFSET_SCALE_CHROMA 1167 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved 1168 uint32_t ChromaQpOffsetListLenMinus1 : __CODEGEN_BITFIELD(20, 22) ; //!< chroma_qp_offset_list_len_minus1 1169 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 1170 uint32_t DiffCuChromaQpOffsetDepth : __CODEGEN_BITFIELD(24, 27) ; //!< diff_cu_chroma_qp_offset_depth 1171 uint32_t ChromaQpOffsetListEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< chroma_qp_offset_list_enabled_flag 1172 uint32_t ChromaSubsampling : __CODEGEN_BITFIELD(29, 31) ; //!< CHROMA_SUBSAMPLING 1173 }; 1174 uint32_t Value; 1175 } DW2; 1176 union 1177 { 1178 struct 1179 { 1180 uint32_t Colpicisi : __CODEGEN_BITFIELD( 0, 0) ; //!< COLPICISI 1181 uint32_t Curpicisi : __CODEGEN_BITFIELD( 1, 1) ; //!< CURPICISI 1182 uint32_t Inserttestflag : __CODEGEN_BITFIELD( 2, 2) ; //!< INSERTTESTFLAG 1183 uint32_t Reserved99 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1184 uint32_t TileNumber : __CODEGEN_BITFIELD( 8, 13) ; //!< Tile number 1185 uint32_t FrameNumber : __CODEGEN_BITFIELD(14, 17) ; //!< Frame number 1186 uint32_t Reserved114 : __CODEGEN_BITFIELD(18, 18) ; //!< Reserved 1187 uint32_t HighPrecisionOffsetsEnableFlag : __CODEGEN_BITFIELD(19, 19) ; //!< High Precision Offsets Enable Flag 1188 uint32_t Log2Maxtransformskipsize : __CODEGEN_BITFIELD(20, 22) ; //!< Log2MaxTransformSkipSize 1189 uint32_t CrossComponentPredictionEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< cross_component_prediction_enabled_flag 1190 uint32_t CabacBypassAlignmentEnabledFlag : __CODEGEN_BITFIELD(24, 24) ; //!< cabac_bypass_alignment_enabled_flag 1191 uint32_t PersistentRiceAdaptationEnabledFlag : __CODEGEN_BITFIELD(25, 25) ; //!< persistent_rice_adaptation_enabled_flag 1192 uint32_t IntraSmoothingDisabledFlag : __CODEGEN_BITFIELD(26, 26) ; //!< intra_smoothing_disabled_flag 1193 uint32_t ExplicitRdpcmEnabledFlag : __CODEGEN_BITFIELD(27, 27) ; //!< explicit_rdpcm_enabled_flag 1194 uint32_t ImplicitRdpcmEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< implicit_rdpcm_enabled_flag 1195 uint32_t TransformSkipContextEnabledFlag : __CODEGEN_BITFIELD(29, 29) ; //!< transform_skip_context_enabled_flag 1196 uint32_t TransformSkipRotationEnabledFlag : __CODEGEN_BITFIELD(30, 30) ; //!< transform_skip_rotation_enabled_flag 1197 uint32_t SpsRangeExtensionEnableFlag : __CODEGEN_BITFIELD(31, 31) ; //!< sps_range_extension_enable_flag 1198 }; 1199 uint32_t Value; 1200 } DW3; 1201 union 1202 { 1203 struct 1204 { 1205 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 1206 uint32_t SampleAdaptiveOffsetEnabledFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< sample_adaptive_offset_enabled_flag 1207 uint32_t PcmEnabledFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< pcm_enabled_flag 1208 uint32_t CuQpDeltaEnabledFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< CU_QP_DELTA_ENABLED_FLAG 1209 uint32_t DiffCuQpDeltaDepthOrNamedAsMaxDqpDepth : __CODEGEN_BITFIELD( 6, 7) ; //!< diff_cu_qp_delta_depth (or named as max_dqp_depth) 1210 uint32_t PcmLoopFilterDisableFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< pcm_loop_filter_disable_flag 1211 uint32_t ConstrainedIntraPredFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< constrained_intra_pred_flag 1212 uint32_t Log2ParallelMergeLevelMinus2 : __CODEGEN_BITFIELD(10, 12) ; //!< log2_parallel_merge_level_minus2 1213 uint32_t SignDataHidingFlag : __CODEGEN_BITFIELD(13, 13) ; //!< SIGN_DATA_HIDING_FLAG 1214 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 1215 uint32_t LoopFilterAcrossTilesEnabledFlag : __CODEGEN_BITFIELD(15, 15) ; //!< loop_filter_across_tiles_enabled_flag 1216 uint32_t EntropyCodingSyncEnabledFlag : __CODEGEN_BITFIELD(16, 16) ; //!< entropy_coding_sync_enabled_flag 1217 uint32_t TilesEnabledFlag : __CODEGEN_BITFIELD(17, 17) ; //!< tiles_enabled_flag 1218 uint32_t WeightedBipredFlag : __CODEGEN_BITFIELD(18, 18) ; //!< weighted_bipred_flag 1219 uint32_t WeightedPredFlag : __CODEGEN_BITFIELD(19, 19) ; //!< weighted_pred_flag 1220 uint32_t Fieldpic : __CODEGEN_BITFIELD(20, 20) ; //!< FIELDPIC 1221 uint32_t Bottomfield : __CODEGEN_BITFIELD(21, 21) ; //!< BOTTOMFIELD 1222 uint32_t TransformSkipEnabledFlag : __CODEGEN_BITFIELD(22, 22) ; //!< TRANSFORM_SKIP_ENABLED_FLAG 1223 uint32_t AmpEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< AMP_ENABLED_FLAG 1224 uint32_t Reserved152 : __CODEGEN_BITFIELD(24, 24) ; //!< Reserved 1225 uint32_t TransquantBypassEnableFlag : __CODEGEN_BITFIELD(25, 25) ; //!< TRANSQUANT_BYPASS_ENABLE_FLAG 1226 uint32_t StrongIntraSmoothingEnableFlag : __CODEGEN_BITFIELD(26, 26) ; //!< strong_intra_smoothing_enable_flag 1227 uint32_t CuPacketStructure : __CODEGEN_BITFIELD(27, 27) ; //!< CU packet structure 1228 uint32_t Reserved156 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1229 }; 1230 uint32_t Value; 1231 } DW4; 1232 union 1233 { 1234 struct 1235 { 1236 uint32_t PicCbQpOffset : __CODEGEN_BITFIELD( 0, 4) ; //!< pic_cb_qp_offset 1237 uint32_t PicCrQpOffset : __CODEGEN_BITFIELD( 5, 9) ; //!< pic_cr_qp_offset 1238 uint32_t MaxTransformHierarchyDepthIntraOrNamedAsTuMaxDepthIntra : __CODEGEN_BITFIELD(10, 12) ; //!< max_transform_hierarchy_depth_intra (or named as tu_max_depth_intra) 1239 uint32_t MaxTransformHierarchyDepthInterOrNamedAsTuMaxDepthInter : __CODEGEN_BITFIELD(13, 15) ; //!< max_transform_hierarchy_depth_inter(or named as tu_max_depth_inter) 1240 uint32_t PcmSampleBitDepthChromaMinus1 : __CODEGEN_BITFIELD(16, 19) ; //!< pcm_sample_bit_depth_chroma_minus1 1241 uint32_t PcmSampleBitDepthLumaMinus1 : __CODEGEN_BITFIELD(20, 23) ; //!< pcm_sample_bit_depth_luma_minus1 1242 uint32_t BitDepthChromaMinus8 : __CODEGEN_BITFIELD(24, 26) ; //!< BIT_DEPTH_CHROMA_MINUS8 1243 uint32_t BitDepthLumaMinus8 : __CODEGEN_BITFIELD(27, 29) ; //!< BIT_DEPTH_LUMA_MINUS8 1244 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1245 }; 1246 uint32_t Value; 1247 } DW5; 1248 union 1249 { 1250 struct 1251 { 1252 uint32_t LcuMaxBitsizeAllowed : __CODEGEN_BITFIELD( 0, 15) ; //!< LCU Max BitSize Allowed 1253 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NonFirstPassFlag 1254 uint32_t LcuMaxBitSizeAllowedMsb2its : __CODEGEN_BITFIELD(17, 18) ; //!< LCU Max BitSize Allowed MSB 2bits 1255 uint32_t Reserved : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1256 uint32_t LcumaxbitstatusenLcumaxsizereportmask : __CODEGEN_BITFIELD(24, 24) ; //!< LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1257 uint32_t FrameszoverstatusenFramebitratemaxreportmask : __CODEGEN_BITFIELD(25, 25) ; //!< FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1258 uint32_t FrameszunderstatusenFramebitrateminreportmask : __CODEGEN_BITFIELD(26, 26) ; //!< FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1259 uint32_t Reserved219 : __CODEGEN_BITFIELD(27, 28) ; //!< Reserved 1260 uint32_t LoadSlicePointerFlag : __CODEGEN_BITFIELD(29, 29) ; //!< LOAD_SLICE_POINTER_FLAG 1261 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1262 }; 1263 uint32_t Value; 1264 } DW6; 1265 union 1266 { 1267 struct 1268 { 1269 uint32_t Framebitratemax : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMax 1270 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 1271 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT 1272 }; 1273 uint32_t Value; 1274 } DW7; 1275 union 1276 { 1277 struct 1278 { 1279 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 1280 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 1281 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMINUNIT 1282 }; 1283 uint32_t Value; 1284 } DW8; 1285 union 1286 { 1287 struct 1288 { 1289 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FRAMEBITRATEMINDELTA 1290 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1291 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 1292 uint32_t Reserved319 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1293 }; 1294 uint32_t Value; 1295 } DW9; 1296 union 1297 { 1298 struct 1299 { 1300 uint64_t Framedeltaqpmax ; //!< FrameDeltaQpMax 1301 }; 1302 uint32_t Value[2]; 1303 } DW10_11; 1304 union 1305 { 1306 struct 1307 { 1308 uint64_t Framedeltaqpmin ; //!< FrameDeltaQpMin 1309 }; 1310 uint32_t Value[2]; 1311 } DW12_13; 1312 union 1313 { 1314 struct 1315 { 1316 uint64_t Framedeltaqpmaxrange ; //!< FrameDeltaQpMaxRange 1317 }; 1318 uint32_t Value[2]; 1319 } DW14_15; 1320 union 1321 { 1322 struct 1323 { 1324 uint64_t Framedeltaqpminrange ; //!< FrameDeltaQpMinRange 1325 }; 1326 uint32_t Value[2]; 1327 } DW16_17; 1328 union 1329 { 1330 struct 1331 { 1332 uint32_t Minframesize : __CODEGEN_BITFIELD( 0, 15) ; //!< MINFRAMESIZE 1333 uint32_t Reserved592 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 1334 uint32_t Minframesizeunits : __CODEGEN_BITFIELD(30, 31) ; //!< MINFRAMESIZEUNITS 1335 }; 1336 uint32_t Value; 1337 } DW18; 1338 union 1339 { 1340 struct 1341 { 1342 uint32_t FractionalQpInput : __CODEGEN_BITFIELD( 0, 2) ; //!< Fractional QP Input 1343 uint32_t FractionalQpOffset : __CODEGEN_BITFIELD( 3, 5) ; //!< Fractional QP Offset 1344 uint32_t RhodomainRateControlEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< RhoDomain Rate Control Enable 1345 uint32_t FractionalQpAdjustmentEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Fractional QP adjustment enable 1346 uint32_t Rhodomainframelevelqp : __CODEGEN_BITFIELD( 8, 13) ; //!< RhoDomainFrameLevelQP 1347 uint32_t PakDynamicSliceModeEnable : __CODEGEN_BITFIELD(14, 14) ; //!< PAK Dynamic Slice Mode Enable 1348 uint32_t NoOutputOfPriorPicsFlag : __CODEGEN_BITFIELD(15, 15) ; //!< no_output_of_prior_pics_flag 1349 uint32_t FirstSliceSegmentInPicFlag : __CODEGEN_BITFIELD(16, 16) ; //!< first_slice_segment_in_pic_flag 1350 uint32_t Nalunittypeflag : __CODEGEN_BITFIELD(17, 17) ; //!< NalUnitTypeFlag 1351 uint32_t SlicePicParameterSetId : __CODEGEN_BITFIELD(18, 23) ; //!< slice_pic_parameter_set_id 1352 uint32_t SseEnable : __CODEGEN_BITFIELD(24, 24) ; //!< SSE Enable 1353 uint32_t RdoqEnable : __CODEGEN_BITFIELD(25, 25) ; //!< RDOQ Enable 1354 uint32_t NumberoflcusinnormalSliceSizeConformanceMode : __CODEGEN_BITFIELD(26, 27) ; //!< NumberOfLCUsInNormal Slice size conformance Mode 1355 uint32_t Reserved636 : __CODEGEN_BITFIELD(28, 29) ; //!< Reserved 1356 uint32_t PartialFrameUpdateMode : __CODEGEN_BITFIELD(30, 30) ; //!< Partial Frame Update Mode 1357 uint32_t TemporalMvPredDisable : __CODEGEN_BITFIELD(31, 31) ; //!< Temporal MV pred disable 1358 }; 1359 uint32_t Value; 1360 } DW19; 1361 union 1362 { 1363 struct 1364 { 1365 uint32_t Reserved640 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1366 uint32_t Intratucountbasedrdoqdisable : __CODEGEN_BITFIELD( 6, 6) ; //!< IntraTuCountBasedRDOQdisable 1367 uint32_t Reserved647 : __CODEGEN_BITFIELD( 7, 31) ; //!< Reserved 1368 }; 1369 uint32_t Value; 1370 } DW20; 1371 union 1372 { 1373 struct 1374 { 1375 uint32_t SliceSizeThresholdInBytes ; //!< Slice Size Threshold in Bytes 1376 }; 1377 uint32_t Value; 1378 } DW21; 1379 union 1380 { 1381 struct 1382 { 1383 uint32_t TargetSliceSizeInBytes ; //!< Target Slice Size in Bytes 1384 }; 1385 uint32_t Value; 1386 } DW22; 1387 union 1388 { 1389 struct 1390 { 1391 uint32_t Class0SseThreshold0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Class0_SSE_Threshold0 1392 uint32_t Class0SseThreshold1 : __CODEGEN_BITFIELD(16, 31) ; //!< Class0_SSE_Threshold1 1393 }; 1394 uint32_t Value; 1395 } DW23; 1396 uint32_t SseThresholdsForClass18[8]; //!< SSE thresholds for Class1-8 1397 union 1398 { 1399 struct 1400 { 1401 uint32_t CbQpOffsetList0 : __CODEGEN_BITFIELD( 0, 4) ; //!< cb_qp_offset_list[0] 1402 uint32_t CbQpOffsetList1 : __CODEGEN_BITFIELD( 5, 9) ; //!< cb_qp_offset_list[1] 1403 uint32_t CbQpOffsetList2 : __CODEGEN_BITFIELD(10, 14) ; //!< cb_qp_offset_list[2] 1404 uint32_t CbQpOffsetList3 : __CODEGEN_BITFIELD(15, 19) ; //!< cb_qp_offset_list[3] 1405 uint32_t CbQpOffsetList4 : __CODEGEN_BITFIELD(20, 24) ; //!< cb_qp_offset_list[4] 1406 uint32_t CbQpOffsetList5 : __CODEGEN_BITFIELD(25, 29) ; //!< cb_qp_offset_list[5] 1407 uint32_t Reserved1054 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1408 }; 1409 uint32_t Value; 1410 } DW32; 1411 union 1412 { 1413 struct 1414 { 1415 uint32_t CrQpOffsetList0 : __CODEGEN_BITFIELD( 0, 4) ; //!< cr_qp_offset_list[0] 1416 uint32_t CrQpOffsetList1 : __CODEGEN_BITFIELD( 5, 9) ; //!< cr_qp_offset_list[1] 1417 uint32_t CrQpOffsetList2 : __CODEGEN_BITFIELD(10, 14) ; //!< cr_qp_offset_list[2] 1418 uint32_t CrQpOffsetList3 : __CODEGEN_BITFIELD(15, 19) ; //!< cr_qp_offset_list[3] 1419 uint32_t CrQpOffsetList4 : __CODEGEN_BITFIELD(20, 24) ; //!< cr_qp_offset_list[4] 1420 uint32_t CrQpOffsetList5 : __CODEGEN_BITFIELD(25, 29) ; //!< cr_qp_offset_list[5] 1421 uint32_t Reserved1086 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1422 }; 1423 uint32_t Value; 1424 } DW33; 1425 union 1426 { 1427 struct 1428 { 1429 uint32_t IbcMotionCompensationBufferReferenceIdc : __CODEGEN_BITFIELD( 0, 2) ; //!< IBC Motion Compensation Buffer Reference IDC 1430 uint32_t Reserved1091 : __CODEGEN_BITFIELD( 3, 5) ; //!< Reserved 1431 uint32_t DeblockingFilterOverrideEnabledFlag : __CODEGEN_BITFIELD( 6, 6) ; //!< deblocking_filter_override_enabled_flag 1432 uint32_t PpsDeblockingFilterDisabledFlag : __CODEGEN_BITFIELD( 7, 7) ; //!< pps_deblocking_filter_disabled_flag 1433 uint32_t PpsActCrQpOffsetPlus3 : __CODEGEN_BITFIELD( 8, 13) ; //!< pps_act_cr_qp_offset_plus3 1434 uint32_t PpsActCbQpOffsetPlus5 : __CODEGEN_BITFIELD(14, 19) ; //!< pps_act_cb_qp_offset_plus5 1435 uint32_t PpsActYOffsetPlus5 : __CODEGEN_BITFIELD(20, 25) ; //!< pps_act_y_offset_plus5 1436 uint32_t PpsSliceActQpOffsetsPresentFlag : __CODEGEN_BITFIELD(26, 26) ; //!< pps_slice_act_qp_offsets_present_flag 1437 uint32_t ResidualAdaptiveColourTransformEnabledFlag : __CODEGEN_BITFIELD(27, 27) ; //!< residual_adaptive_colour_transform_enabled_flag 1438 uint32_t PpsCurrPicRefEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< pps_curr_pic_ref_enabled_flag 1439 uint32_t MotionVectorResolutionControlIdc : __CODEGEN_BITFIELD(29, 30) ; //!< MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1440 uint32_t IntraBoundaryFilteringDisabledFlag : __CODEGEN_BITFIELD(31, 31) ; //!< intra_boundary_filtering_disabled_flag 1441 }; 1442 uint32_t Value; 1443 } DW34; 1444 union 1445 { 1446 struct 1447 { 1448 uint32_t PaletteMaxSize : __CODEGEN_BITFIELD( 0, 6) ; //!< palette_max_size 1449 uint32_t Reserved1127 : __CODEGEN_BITFIELD( 7, 9) ; //!< Reserved 1450 uint32_t DeltaPaletteMaxPredictorSize : __CODEGEN_BITFIELD(10, 16) ; //!< delta_palette_max_predictor_size 1451 uint32_t Reserved1137 : __CODEGEN_BITFIELD(17, 18) ; //!< Reserved 1452 uint32_t IbcMotionVectorErrorHandlingDisable : __CODEGEN_BITFIELD(19, 19) ; //!< IBC Motion Vector Error Handling Disable 1453 uint32_t ChromaBitDepthEntryMinus8 : __CODEGEN_BITFIELD(20, 23) ; //!< chroma_bit_depth_entry_minus8 1454 uint32_t LumaBitDepthEntryMinus8 : __CODEGEN_BITFIELD(24, 27) ; //!< luma_bit_depth_entry_minus8 1455 uint32_t IbcConfiguration : __CODEGEN_BITFIELD(28, 29) ; //!< IBC_CONFIGURATION 1456 uint32_t MonochromePaletteFlag : __CODEGEN_BITFIELD(30, 30) ; //!< monochrome_palette_flag 1457 uint32_t PaletteModeEnabledFlag : __CODEGEN_BITFIELD(31, 31) ; //!< palette_mode_enabled_flag 1458 }; 1459 uint32_t Value; 1460 } DW35; 1461 union 1462 { 1463 struct 1464 { 1465 uint32_t EnableFpakMessaging : __CODEGEN_BITFIELD( 0, 0) ; //!< Enable FPAK Messaging 1466 uint32_t Reserved1153 : __CODEGEN_BITFIELD( 1, 29) ; //!< Reserved 1467 uint32_t FrameCrcType : __CODEGEN_BITFIELD(30, 30) ; //!< FRAME_CRC_TYPE 1468 uint32_t FrameCrcEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Frame CRC Enable 1469 }; 1470 uint32_t Value; 1471 } DW36; 1472 union 1473 { 1474 struct 1475 { 1476 uint32_t Rdoqintratuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< RDOQIntraTUThreshold 1477 uint32_t Reserved1200 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1478 }; 1479 uint32_t Value; 1480 } DW37; 1481 union 1482 { 1483 struct 1484 { 1485 uint32_t Rdoqintra16X16Tuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< RDOQIntra16x16TUThreshold 1486 uint32_t Rdoqintra32X32Tuthreshold : __CODEGEN_BITFIELD(16, 31) ; //!< RDOQIntra32x32TUThreshold 1487 }; 1488 uint32_t Value; 1489 } DW38; 1490 union 1491 { 1492 struct 1493 { 1494 uint64_t SsethresholdsForClass910 ; //!< SSEThresholds for Class9 ..10 1495 }; 1496 uint32_t Value[2]; 1497 } DW39_40; 1498 1499 //! \name Local enumerations 1500 1501 enum MEDIA_INSTRUCTION_COMMAND 1502 { 1503 MEDIA_INSTRUCTION_COMMAND_HCPPICSTATE = 16, //!< No additional details 1504 }; 1505 1506 //! \brief MEDIA_INSTRUCTION_OPCODE 1507 //! \details 1508 //! Codec/Engine Name = HCP = 7h 1509 enum MEDIA_INSTRUCTION_OPCODE 1510 { 1511 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1512 }; 1513 1514 enum PIPELINE_TYPE 1515 { 1516 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1517 }; 1518 1519 enum COMMAND_TYPE 1520 { 1521 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1522 }; 1523 1524 //! \brief MINCUSIZE 1525 //! \details 1526 //! Specifies the smallest coding block size. 1527 enum MINCUSIZE 1528 { 1529 MINCUSIZE_8X8 = 0, //!< No additional details 1530 MINCUSIZE_16X16 = 1, //!< No additional details 1531 MINCUSIZE_32X32 = 2, //!< No additional details 1532 MINCUSIZE_64X64 = 3, //!< No additional details 1533 }; 1534 1535 //! \brief CTBSIZE_LCUSIZE 1536 //! \details 1537 //! Specifies the coding tree block size. 1538 enum CTBSIZE_LCUSIZE 1539 { 1540 CTBSIZE_LCUSIZE_ILLEGALRESERVED = 0, //!< No additional details 1541 CTBSIZE_LCUSIZE_16X16 = 1, //!< No additional details 1542 CTBSIZE_LCUSIZE_32X32 = 2, //!< No additional details 1543 CTBSIZE_LCUSIZE_64X64 = 3, //!< No additional details 1544 }; 1545 1546 //! \brief MINTUSIZE 1547 //! \details 1548 //! Specifies the smallest allowed transform block size. 1549 enum MINTUSIZE 1550 { 1551 MINTUSIZE_4X4 = 0, //!< No additional details 1552 MINTUSIZE_8X8 = 1, //!< No additional details 1553 MINTUSIZE_16X16 = 2, //!< No additional details 1554 MINTUSIZE_32X32 = 3, //!< No additional details 1555 }; 1556 1557 //! \brief MAXTUSIZE 1558 //! \details 1559 //! Specifies the largest allowed transform block size. 1560 enum MAXTUSIZE 1561 { 1562 MAXTUSIZE_4X4 = 0, //!< No additional details 1563 MAXTUSIZE_8X8 = 1, //!< No additional details 1564 MAXTUSIZE_16X16 = 2, //!< No additional details 1565 MAXTUSIZE_32X32 = 3, //!< No additional details 1566 }; 1567 1568 //! \brief MINPCMSIZE 1569 //! \details 1570 //! Specifies the smallest allowed PCM coding block size. 1571 enum MINPCMSIZE 1572 { 1573 MINPCMSIZE_8X8 = 0, //!< No additional details 1574 MINPCMSIZE_16X16 = 1, //!< No additional details 1575 MINPCMSIZE_32X32 = 2, //!< No additional details 1576 }; 1577 1578 //! \brief MAXPCMSIZE 1579 //! \details 1580 //! Specifies the largest allowed PCM coding block size. 1581 enum MAXPCMSIZE 1582 { 1583 MAXPCMSIZE_8X8 = 0, //!< No additional details 1584 MAXPCMSIZE_16X16 = 1, //!< No additional details 1585 MAXPCMSIZE_32X32 = 2, //!< No additional details 1586 }; 1587 1588 //! \brief LOG2_SAO_OFFSET_SCALE_LUMA 1589 //! \details 1590 //! <p>To scale SAO offset values for luma samples</p> 1591 //! <p>0 to Max(0,BitDepth<sub><font size="2">C</font></sub>−10)</p> 1592 //! <p>Default = 0</p> 1593 enum LOG2_SAO_OFFSET_SCALE_LUMA 1594 { 1595 LOG2_SAO_OFFSET_SCALE_LUMA_0 = 0, //!< No additional details 1596 LOG2_SAO_OFFSET_SCALE_LUMA_1 = 1, //!< No additional details 1597 LOG2_SAO_OFFSET_SCALE_LUMA_2 = 2, //!< No additional details 1598 }; 1599 1600 //! \brief LOG2_SAO_OFFSET_SCALE_CHROMA 1601 //! \details 1602 //! <p>To scale SAO offset values for chroma samples.</p> 1603 //! <p>0 to Max(0,BitDepth<sub>C</sub>−10)</p> 1604 //! <p>default = 0</p> 1605 //! <p>Decoder Only</p> 1606 enum LOG2_SAO_OFFSET_SCALE_CHROMA 1607 { 1608 LOG2_SAO_OFFSET_SCALE_CHROMA_0 = 0, //!< No additional details 1609 LOG2_SAO_OFFSET_SCALE_CHROMA_1 = 1, //!< No additional details 1610 LOG2_SAO_OFFSET_SCALE_CHROMA_2 = 2, //!< No additional details 1611 }; 1612 1613 //! \brief CHROMA_SUBSAMPLING 1614 //! \details 1615 //! <p>Specify the chroma subsampling of the current bitstream to be decoded 1616 //! or encoded.</p> 1617 //! <p>000 (0h) - Reserved (This setting is reserved for Monochrome 1618 //! setting--currently not suppported)</p> 1619 //! <p>001 (1h) - 4:2:0</p> 1620 //! <p>010 (2h) - 4:2:2</p> 1621 //! <p>011 (3h) - 4:4:4</p> 1622 //! <p>All other values are invalid for both encoder and decoder.</p> 1623 enum CHROMA_SUBSAMPLING 1624 { 1625 CHROMA_SUBSAMPLING_420 = 1, //!< No additional details 1626 CHROMA_SUBSAMPLING_422 = 2, //!< No additional details 1627 CHROMA_SUBSAMPLING_444 = 3, //!< No additional details 1628 }; 1629 1630 //! \brief COLPICISI 1631 //! \details 1632 //! Specifies that the collocated picture is comprised solely of I slices 1633 //! and that there are no P or B slices in the picture. 1634 enum COLPICISI 1635 { 1636 COLPICISI_COLLOCATEDPICTUREHASATLEASTONEPORBSLICE = 0, //!< No additional details 1637 }; 1638 1639 //! \brief CURPICISI 1640 //! \details 1641 //! Specifies that the current picture is comprised solely of I slices and 1642 //! that there are no P or B slices in the picture. 1643 enum CURPICISI 1644 { 1645 CURPICISI_CURRENTPICTUREHASATLEASTONEPORBSLICE = 0, //!< No additional details 1646 }; 1647 1648 //! \brief INSERTTESTFLAG 1649 //! \details 1650 //! <p>CABAC 0 Word Insertion Test Enable (Encoder Only)This bit will modify 1651 //! CABAC K equation so that a positive K value can be generated easily. 1652 //! This is done for validation purpose only. In normal usage this bit 1653 //! should be set to 0.</p> 1654 //! <p>Regular equation for generating 'K' value when CABAC 0 Word Insertion 1655 //! Test Enable is set to 0.</p> 1656 //! <pre>K = {[((96 * pic_bin_count()) - (RawMinCUBits * PicSizeInMinCUs *3) 1657 //! + 1023) / 1024] - bytes_in_picture} / 3</pre> 1658 //! 1659 //! <p>Modified equation when CABAC 0 Word Insertion Test Enable bit set to 1660 //! 1.</p> 1661 //! 1662 //! <pre>K = {[((1536 * pic_bin_count()) - (RawMinCUBits * PicSizeInMinCUs 1663 //! *3) + 1023) / 1024] - bytes_in_picture} / 3</pre> 1664 //! 1665 //! <p>Encoder only feature.</p> 1666 enum INSERTTESTFLAG 1667 { 1668 INSERTTESTFLAG_UNNAMED0 = 0, //!< No additional details 1669 INSERTTESTFLAG_UNNAMED1 = 1, //!< No additional details 1670 }; 1671 1672 //! \brief CU_QP_DELTA_ENABLED_FLAG 1673 //! \details 1674 //! <p>cu_qp_delta_enabled_flag = 1 and Max_DQP_Level = 0 or 3 is supported 1675 //! for PAK standalone andVDEnc modes.</p> 1676 enum CU_QP_DELTA_ENABLED_FLAG 1677 { 1678 CU_QP_DELTA_ENABLED_FLAG_DISABLE = 0, //!< Does not allow QP change at CU or LCU level, the same QP is used for the entire slice. Max_DQP_Level = 0 (i.e. diff_cu_qp_delta_depath = 0). 1679 CU_QP_DELTA_ENABLED_FLAG_ENABLE = 1, //!< Allow QP change at CU level. MAX_DQP_level can be >0. 1680 }; 1681 1682 //! \brief SIGN_DATA_HIDING_FLAG 1683 //! \details 1684 //! Currently not supported in encoder, so must be set to 0 for encoding 1685 //! session. 1686 enum SIGN_DATA_HIDING_FLAG 1687 { 1688 SIGN_DATA_HIDING_FLAG_DISABLE = 0, //!< Specifies that sign bit hiding is disabled. 1689 SIGN_DATA_HIDING_FLAG_ENABLE = 1, //!< Specifies that sign bit hiding is enabled. 1690 }; 1691 1692 //! \brief FIELDPIC 1693 //! \details 1694 //! <p>Must be zero for encoder only.</p> 1695 enum FIELDPIC 1696 { 1697 FIELDPIC_VIDEOFRAME = 0, //!< No additional details 1698 FIELDPIC_VIDEOFIELD = 1, //!< No additional details 1699 }; 1700 1701 //! \brief BOTTOMFIELD 1702 //! \details 1703 //! <p>Must be zero for encoder only</p> 1704 enum BOTTOMFIELD 1705 { 1706 BOTTOMFIELD_BOTTOMFIELD = 0, //!< No additional details 1707 BOTTOMFIELD_TOPFIELD = 1, //!< No additional details 1708 }; 1709 1710 enum TRANSFORM_SKIP_ENABLED_FLAG 1711 { 1712 TRANSFORM_SKIP_ENABLED_FLAG_DISABLE = 0, //!< transform_skip_flag is not supported in the residual coding 1713 TRANSFORM_SKIP_ENABLED_FLAG_ENABLE = 1, //!< transform_skip_flag is supported 1714 }; 1715 1716 //! \brief AMP_ENABLED_FLAG 1717 //! \details 1718 //! In VDENC mode, this bit should be set to 1. 1719 enum AMP_ENABLED_FLAG 1720 { 1721 AMP_ENABLED_FLAG_DISABLE = 0, //!< Asymmetric motion partitions cannot be used in coding tree blocks. 1722 AMP_ENABLED_FLAG_ENABLE = 1, //!< Support asymmetric motion partitions, i.e. PartMode equal to PART_2NxnU, PART_2NxnD, PART_nLx2N, or PART_nRx2N. 1723 }; 1724 1725 enum TRANSQUANT_BYPASS_ENABLE_FLAG 1726 { 1727 TRANSQUANT_BYPASS_ENABLE_FLAG_DISABLE = 0, //!< cu_transquant_bypass is not supported 1728 TRANSQUANT_BYPASS_ENABLE_FLAG_ENABLE = 1, //!< cu_transquant_bypass is supported 1729 }; 1730 1731 //! \brief BIT_DEPTH_CHROMA_MINUS8 1732 //! \details 1733 //! This specifies the number of bit allow for Chroma pixels. In 8 bit mode, 1734 //! this must be set to 0. Encoder: Supports bit depths 8, 10 and 12 only. 1735 //! And also it must be same as Luma. Encoder: Does not support 10 or 12 bit 1736 //! Source Pixels and 8bit PAK. i.e. The source pixel depth should be less 1737 //! than or equal to the PAK bit depth. 1738 enum BIT_DEPTH_CHROMA_MINUS8 1739 { 1740 BIT_DEPTH_CHROMA_MINUS8_CHROMA8BIT = 0, //!< No additional details 1741 BIT_DEPTH_CHROMA_MINUS8_CHROMA9BIT = 1, //!< Only HEVC decoder supports 9 bits chroma.HEVC encoder does not supports 9 bits chroma. 1742 BIT_DEPTH_CHROMA_MINUS8_CHROMA10BIT = 2, //!< No additional details 1743 BIT_DEPTH_CHROMA_MINUS8_CHROMA11BIT = 3, //!< HEVC SCC does not support 11 bits chromaAlso only HEVC decoder (non-SCC) support 11 bits chromaHEVC encoder (non-SCC) does not support 11 bits chroma 1744 BIT_DEPTH_CHROMA_MINUS8_CHROMA12BIT = 4, //!< HEVC SCC does not support 12bits Luma 1745 }; 1746 1747 //! \brief BIT_DEPTH_LUMA_MINUS8 1748 //! \details 1749 //! This specifies the number of bit allow for Luma pixels. In 8 bit mode, 1750 //! this must be set to 0. Encoder: Suports bit depths 8, 10 and 12 only. 1751 //! Encoder: Does not support 10 or 12 bit Source Pixels and 8bit PAK i.e. 1752 //! the source pixel depth should be less than or equal to PAK bit depth. 1753 enum BIT_DEPTH_LUMA_MINUS8 1754 { 1755 BIT_DEPTH_LUMA_MINUS8_LUMA8BIT = 0, //!< No additional details 1756 BIT_DEPTH_LUMA_MINUS8_LUMA9BIT = 1, //!< Only HEVC decoder supports 9 bits luma.HEVC encoder does not supports 9 bits luma. 1757 BIT_DEPTH_LUMA_MINUS8_LUMA10BIT = 2, //!< No additional details 1758 BIT_DEPTH_LUMA_MINUS8_LUMA11BIT = 3, //!< HEVC SCC does not support 11 bits LumaAlso only HEVC decoder (non-SCC) support 11 bits LumaHEVC encoder (non-SCC) does not support 11 bits Luma 1759 BIT_DEPTH_LUMA_MINUS8_LUMA12BIT = 4, //!< HEVC SCC does not support 12bits Luma 1760 }; 1761 1762 //! \brief NONFIRSTPASSFLAG 1763 //! \details 1764 //! This signals the current pass is not the first pass. It will imply 1765 //! designate HW behavior. 1766 enum NONFIRSTPASSFLAG 1767 { 1768 NONFIRSTPASSFLAG_DISABLE = 0, //!< If it is initial-Pass, this bit is set to 0. 1769 NONFIRSTPASSFLAG_ENABLE = 1, //!< For subsequent passes, this bit is set to 1. 1770 }; 1771 1772 //! \brief LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1773 //! \details 1774 //! This is a mask bit controlling if the condition of any LCU in the frame 1775 //! exceeds LCUMaxSize. 1776 enum LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1777 { 1778 LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit 0 of HCP_IMAGE_STATUS control register. 1779 LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_ENABLE = 1, //!< HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. 1780 }; 1781 1782 //! \brief FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1783 //! \details 1784 //! This is a mask bit controlling if the condition of frame level bit count 1785 //! exceeds FrameBitRateMax. 1786 enum FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1787 { 1788 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit 1 of HCP_IMAGE_STATUS control register. 1789 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. It's used pass the bit inHCP_IMAGE_STATUS_MASK register 1790 }; 1791 1792 //! \brief FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1793 //! \details 1794 //! This is a mask bit controlling if the condition of frame level bit count 1795 //! is less than FrameBitRateMin. 1796 enum FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1797 { 1798 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit 2 (Frame Bit Count Violate -- under run) of HCP_IMAGE_STATUS control register. 1799 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< Set bit 2 (Frame Bit Count Violate -- under run) of HCP_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit Rate Minimum limit. HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. It's used pass the bit in HCP_IMAGE_STATUS_MASK register 1800 }; 1801 1802 //! \brief LOAD_SLICE_POINTER_FLAG 1803 //! \details 1804 //! <p>LoadBitStreamPointerPerSlice (Encoder-only)</p> 1805 //! <p>To support multiple slice picture and additional header/data 1806 //! insertion before and after an encoded slice. When this field is set to 1807 //! 0, bitstream pointer is only loaded once for the first slice of a frame. 1808 //! For subsequent slices in the frame, bitstream data are stitched together 1809 //! to form a single output data stream. When this field is set to 1, 1810 //! bitstream pointer is loaded for each slice of a frame. Basically 1811 //! bitstream data for different slices of a frame will be written to 1812 //! different memory locations.</p> 1813 enum LOAD_SLICE_POINTER_FLAG 1814 { 1815 LOAD_SLICE_POINTER_FLAG_DISABLE = 0, //!< Load BitStream Pointer only once for the first slice of a frame. 1816 LOAD_SLICE_POINTER_FLAG_ENABLE = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of thebitstream buffer from the Indirect PAK-BSE Object Data Start Address field. 1817 }; 1818 1819 //! \brief FRAMEBITRATEMAXUNIT 1820 //! \details 1821 //! This field is the Frame Bitrate Maximum Limit Units. 1822 enum FRAMEBITRATEMAXUNIT 1823 { 1824 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< 32byte unit 1825 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< 4kbyte unit 1826 }; 1827 1828 //! \brief FRAMEBITRATEMINUNIT 1829 //! \details 1830 //! This field is the Frame Bitrate Minimum Limit Units. 1831 enum FRAMEBITRATEMINUNIT 1832 { 1833 FRAMEBITRATEMINUNIT_BYTE = 0, //!< 32byte unit 1834 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< 4kbyte unit 1835 }; 1836 1837 //! \brief FRAMEBITRATEMINDELTA 1838 //! \details 1839 //! This field is used to select the slice delta QP when FrameBitRateMin Is 1840 //! exceeded. It shares the same 1841 //! FrameBitrateMinUnit. 1842 enum FRAMEBITRATEMINDELTA 1843 { 1844 FRAMEBITRATEMINDELTA_UNNAMED0 = 0, //!< No additional details 1845 }; 1846 1847 //! \brief FRAMEBITRATEMAXDELTA 1848 //! \details 1849 //! This field is used to select the slice delta QP when FrameBitRateMax Is 1850 //! exceeded. It shares the same 1851 //! FrameBitrateMaxUnit. 1852 enum FRAMEBITRATEMAXDELTA 1853 { 1854 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 1855 }; 1856 1857 //! \brief MINFRAMESIZE 1858 //! \details 1859 //! <p>Minimum Frame Size [15:0] (in Word, 16-bit)(Encoder Only)</p> 1860 //! <p>Mininum Frame Size is specified to compensate for intel Rate Control 1861 //! Currently zero fill (no need to perform emulation byte insertion) is 1862 //! done only to the end of the CABAC_ZERO_WORD insertion (if any) at the 1863 //! last slice of a picture. It is needed for CBR. Intel encoder parameter. 1864 //! The caller should always make sure that the value, represented by 1865 //! Mininum Frame Size, is always less than maximum frame size 1866 //! FrameBitRateMax. This field is reserved in Decode mode.</p> 1867 enum MINFRAMESIZE 1868 { 1869 MINFRAMESIZE_UNNAMED0 = 0, //!< No additional details 1870 }; 1871 1872 //! \brief MINFRAMESIZEUNITS 1873 //! \details 1874 //! This field is the Minimum Frame Size Units 1875 enum MINFRAMESIZEUNITS 1876 { 1877 MINFRAMESIZEUNITS_4KB = 0, //!< Minimum Frame Size is in 4Kbytes. 1878 MINFRAMESIZEUNITS_16KB = 1, //!< Minimum Frame Size is in 16Kbytes. 1879 MINFRAMESIZEUNITS_COMPATIBILITYMODE = 2, //!< Minimum Frame Size is in 4bytes 1880 MINFRAMESIZEUNITS_16BYTES = 3, //!< Minimum Frame Size is 16 bytes. 1881 }; 1882 1883 //! \brief MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1884 //! \details 1885 //! <p>This controls the presense and inference of the use_integer_mv_flag 1886 //! that specifies the resolution of motion vectors for inter 1887 //! prediction.</p> 1888 //! <p>Decoder only (Encoder default to "00")</p> 1889 enum MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1890 { 1891 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_NOINTEGERMVFORTHEFRAME = 0, //!< No additional details 1892 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_ONLYINTEGERMVFORTHEFRAME = 1, //!< No additional details 1893 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_ADAPTIVEINTEGERMVFORTHEFRAME = 2, //!< Slice signal use_inter_mv_flag will indicate if the slice will use interger MV or not 1894 }; 1895 1896 //! \brief IBC_CONFIGURATION 1897 //! \details 1898 //! <p>IBC configuration is used configure Intra block copy.</p> 1899 //! <p>- Disable Intra block copy.</p> 1900 //! <p>- Limit Intra block copy from Left blocks only.</p> 1901 //! <p>- Allow full range of Intra block copy as specified in spec.</p> 1902 //! <p></p> 1903 enum IBC_CONFIGURATION 1904 { 1905 IBC_CONFIGURATION_UNNAMED0 = 0, //!< When IBC configuration is 0, intra block copy is disabled and it applies for both Fixed function encoder and decoder. 1906 IBC_CONFIGURATION_UNNAMED1 = 1, //!< When IBC configuration in fixed function encoder (VDENC) mode is set to 1, Intra block search includes only left region. 1907 IBC_CONFIGURATION_UNNAMED2 = 2, //!< No additional details 1908 IBC_CONFIGURATION_UNNAMED3 = 3, //!< When IBC configuration in VDENC mode is set to 3, Intra block search includes top and left regions.In decoder mode, When SCC is enabled this field should be set to 3. 1909 }; 1910 1911 //! \brief FRAME_CRC_TYPE 1912 //! \details 1913 //! <p>This indicates how CRC is generated. This bit is ignored and must be 1914 //! programmed to 0 if Frame CRC Enable is "0"</p> 1915 enum FRAME_CRC_TYPE 1916 { 1917 FRAME_CRC_TYPE_CRCWITHYUVVALUE = 0, //!< No additional details 1918 FRAME_CRC_TYPE_CRCWITHYVALUEONLY = 1, //!< No additional details 1919 }; 1920 1921 //! \name Initializations 1922 1923 //! \brief Explicit member initialization function HCP_PIC_STATE_CMDHCP_PIC_STATE_CMD1924 HCP_PIC_STATE_CMD() 1925 { 1926 DW0.Value = 0x73900027; 1927 //DW0.DwordLength = GetOpLength(dwSize); 1928 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPICSTATE; 1929 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 1930 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 1931 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 1932 1933 DW1.Value = 0x00000000; 1934 1935 DW2.Value = 0x00000000; 1936 //DW2.Mincusize = MINCUSIZE_8X8; 1937 //DW2.CtbsizeLcusize = CTBSIZE_LCUSIZE_ILLEGALRESERVED; 1938 //DW2.Mintusize = MINTUSIZE_4X4; 1939 //DW2.Maxtusize = MAXTUSIZE_4X4; 1940 //DW2.Minpcmsize = MINPCMSIZE_8X8; 1941 //DW2.Maxpcmsize = MAXPCMSIZE_8X8; 1942 //DW2.Log2SaoOffsetScaleLuma = LOG2_SAO_OFFSET_SCALE_LUMA_0; 1943 //DW2.Log2SaoOffsetScaleChroma = LOG2_SAO_OFFSET_SCALE_CHROMA_0; 1944 //DW2.ChromaSubsampling = 0; 1945 1946 DW3.Value = 0x00000000; 1947 //DW3.Colpicisi = COLPICISI_COLLOCATEDPICTUREHASATLEASTONEPORBSLICE; 1948 //DW3.Curpicisi = CURPICISI_CURRENTPICTUREHASATLEASTONEPORBSLICE; 1949 //DW3.Inserttestflag = INSERTTESTFLAG_UNNAMED0; 1950 1951 DW4.Value = 0x00000000; 1952 //DW4.CuQpDeltaEnabledFlag = CU_QP_DELTA_ENABLED_FLAG_DISABLE; 1953 //DW4.SignDataHidingFlag = SIGN_DATA_HIDING_FLAG_DISABLE; 1954 //DW4.Fieldpic = FIELDPIC_VIDEOFRAME; 1955 //DW4.Bottomfield = BOTTOMFIELD_BOTTOMFIELD; 1956 //DW4.TransformSkipEnabledFlag = TRANSFORM_SKIP_ENABLED_FLAG_DISABLE; 1957 //DW4.AmpEnabledFlag = AMP_ENABLED_FLAG_DISABLE; 1958 //DW4.TransquantBypassEnableFlag = TRANSQUANT_BYPASS_ENABLE_FLAG_DISABLE; 1959 1960 DW5.Value = 0x00000000; 1961 //DW5.BitDepthChromaMinus8 = BIT_DEPTH_CHROMA_MINUS8_CHROMA8BIT; 1962 //DW5.BitDepthLumaMinus8 = BIT_DEPTH_LUMA_MINUS8_LUMA8BIT; 1963 1964 DW6.Value = 0x00000000; 1965 //DW6.Nonfirstpassflag = NONFIRSTPASSFLAG_DISABLE; 1966 //DW6.LcumaxbitstatusenLcumaxsizereportmask = LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_DISABLE; 1967 //DW6.FrameszoverstatusenFramebitratemaxreportmask = FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE; 1968 //DW6.FrameszunderstatusenFramebitrateminreportmask = FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE; 1969 //DW6.LoadSlicePointerFlag = LOAD_SLICE_POINTER_FLAG_DISABLE; 1970 1971 DW7.Value = 0x00000000; 1972 //DW7.Framebitratemaxunit = FRAMEBITRATEMAXUNIT_BYTE; 1973 1974 DW8.Value = 0x00000000; 1975 //DW8.Framebitrateminunit = FRAMEBITRATEMINUNIT_BYTE; 1976 1977 DW9.Value = 0x00000000; 1978 //DW9.Framebitratemindelta = FRAMEBITRATEMINDELTA_UNNAMED0; 1979 //DW9.Framebitratemaxdelta = FRAMEBITRATEMAXDELTA_UNNAMED0; 1980 1981 DW10_11.Value[0] = DW10_11.Value[1] = 0x00000000; 1982 1983 DW12_13.Value[0] = DW12_13.Value[1] = 0x00000000; 1984 1985 DW14_15.Value[0] = DW14_15.Value[1] = 0x00000000; 1986 1987 DW16_17.Value[0] = DW16_17.Value[1] = 0x00000000; 1988 1989 DW18.Value = 0x00000000; 1990 //DW18.Minframesize = MINFRAMESIZE_UNNAMED0; 1991 //DW18.Minframesizeunits = MINFRAMESIZEUNITS_4KB; 1992 1993 DW19.Value = 0x00000000; 1994 1995 DW20.Value = 0x00000000; 1996 1997 DW21.Value = 0x00000000; 1998 1999 DW22.Value = 0x00000000; 2000 2001 DW23.Value = 0x00000000; 2002 2003 memset(&SseThresholdsForClass18, 0, sizeof(SseThresholdsForClass18)); 2004 2005 DW32.Value = 0x00000000; 2006 2007 DW33.Value = 0x00000000; 2008 2009 DW34.Value = 0x00000000; 2010 //DW34.MotionVectorResolutionControlIdc = MOTION_VECTOR_RESOLUTION_CONTROL_IDC_NOINTEGERMVFORTHEFRAME; 2011 2012 DW35.Value = 0x00000000; 2013 //DW35.IbcConfiguration = IBC_CONFIGURATION_UNNAMED0; 2014 2015 DW36.Value = 0x00000000; 2016 //DW36.FrameCrcType = FRAME_CRC_TYPE_CRCWITHYUVVALUE; 2017 2018 DW37.Value = 0x00000000; 2019 2020 DW38.Value = 0x00000000; 2021 2022 DW39_40.Value[0] = DW39_40.Value[1] = 0x00000000; 2023 } 2024 2025 static const size_t dwSize = 41; 2026 static const size_t byteSize = 164; 2027 }; 2028 2029 //! 2030 //! \brief HCP_TILE_POSITION_IN_CTB 2031 //! \details 2032 //! 2033 //! 2034 struct HCP_TILE_POSITION_IN_CTB_CMD 2035 { 2036 union 2037 { 2038 struct 2039 { 2040 uint32_t Ctbpos0I : __CODEGEN_BITFIELD( 0, 7) ; //!< CtbPos0+i 2041 uint32_t Ctbpos1I : __CODEGEN_BITFIELD( 8, 15) ; //!< CtbPos1+i 2042 uint32_t Ctbpos2I : __CODEGEN_BITFIELD(16, 23) ; //!< CtbPos2+i 2043 uint32_t Ctbpos3I : __CODEGEN_BITFIELD(24, 31) ; //!< CtbPos3+i 2044 }; 2045 uint32_t Value; 2046 } DW0; 2047 2048 //! \name Local enumerations 2049 2050 //! \name Initializations 2051 2052 //! \brief Explicit member initialization function HCP_TILE_POSITION_IN_CTB_CMDHCP_TILE_POSITION_IN_CTB_CMD2053 HCP_TILE_POSITION_IN_CTB_CMD() 2054 { 2055 DW0.Value = 0x00000000; 2056 } 2057 2058 static const size_t dwSize = 1; 2059 static const size_t byteSize = 4; 2060 }; 2061 2062 //! 2063 //! \brief HCP_TILE_POSITION_IN_CTB_MSB 2064 //! \details 2065 //! Added to support 16k picture size. 2066 //! 2067 struct HCP_TILE_POSITION_IN_CTB_MSB_CMD 2068 { 2069 union 2070 { 2071 struct 2072 { 2073 uint32_t CtbRowPositionOfTileColumn098 : __CODEGEN_BITFIELD( 0, 1) ; //!< Ctb row position of tile column 0 [9:8] 2074 uint32_t CtbRowPositionOfTileColumn198 : __CODEGEN_BITFIELD( 2, 3) ; //!< Ctb row position of tile column 1 [9:8] 2075 uint32_t CtbRowPositionOfTileColumn298 : __CODEGEN_BITFIELD( 4, 5) ; //!< Ctb row position of tile column 2 [9:8] 2076 uint32_t CtbRowPositionOfTileColumn398 : __CODEGEN_BITFIELD( 6, 7) ; //!< Ctb row position of tile column 3 [9:8] 2077 uint32_t CtbRowPositionOfTileColumn498 : __CODEGEN_BITFIELD( 8, 9) ; //!< Ctb row position of tile column 4 [9:8] 2078 uint32_t CtbRowPositionOfTileColumn598 : __CODEGEN_BITFIELD(10, 11) ; //!< Ctb row position of tile column 5 [9:8] 2079 uint32_t CtbRowPositionOfTileColumn698 : __CODEGEN_BITFIELD(12, 13) ; //!< Ctb row position of tile column 6 [9:8] 2080 uint32_t CtbRowPositionOfTileColumn798 : __CODEGEN_BITFIELD(14, 15) ; //!< Ctb row position of tile column 7 [9:8] 2081 uint32_t CtbRowPositionOfTileColumn898 : __CODEGEN_BITFIELD(16, 17) ; //!< Ctb row position of tile column 8 [9:8] 2082 uint32_t CtbRowPositionOfTileColumn998 : __CODEGEN_BITFIELD(18, 19) ; //!< Ctb row position of tile column 9 [9:8] 2083 uint32_t CtbRowPositionOfTileColumn1098 : __CODEGEN_BITFIELD(20, 21) ; //!< Ctb row position of tile column 10 [9:8] 2084 uint32_t CtbRowPositionOfTileColumn1198 : __CODEGEN_BITFIELD(22, 23) ; //!< Ctb row position of tile column 11 [9:8] 2085 uint32_t CtbRowPositionOfTileColumn1298 : __CODEGEN_BITFIELD(24, 25) ; //!< Ctb row position of tile column 12 [9:8] 2086 uint32_t CtbRowPositionOfTileColumn1398 : __CODEGEN_BITFIELD(26, 27) ; //!< Ctb row position of tile column 13 [9:8] 2087 uint32_t CtbRowPositionOfTileColumn1498 : __CODEGEN_BITFIELD(28, 29) ; //!< Ctb row position of tile column 14 [9:8] 2088 uint32_t CtbRowPositionOfTileColumn1598 : __CODEGEN_BITFIELD(30, 31) ; //!< Ctb row position of tile column 15 [9:8] 2089 }; 2090 uint32_t Value; 2091 } DW0; 2092 union 2093 { 2094 struct 2095 { 2096 uint32_t CtbRowPositionOfTileColumn1698 : __CODEGEN_BITFIELD( 0, 1) ; //!< Ctb row position of tile column 16 [9:8] 2097 uint32_t CtbRowPositionOfTileColumn1798 : __CODEGEN_BITFIELD( 2, 3) ; //!< Ctb row position of tile column 17 [9:8] 2098 uint32_t CtbRowPositionOfTileColumn1898 : __CODEGEN_BITFIELD( 4, 5) ; //!< Ctb row position of tile column 18 [9:8] 2099 uint32_t CtbRowPositionOfTileColumn1998 : __CODEGEN_BITFIELD( 6, 7) ; //!< Ctb row position of tile column 19 [9:8] 2100 uint32_t CtbRowPositionOfTileColumn2098 : __CODEGEN_BITFIELD( 8, 9) ; //!< Ctb row position of tile column 20 [9:8] 2101 uint32_t CtbPositionOfTile2198 : __CODEGEN_BITFIELD(10, 11) ; //!< Ctb position of tile 21 [9:8] 2102 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 2103 }; 2104 uint32_t Value; 2105 } DW1; 2106 2107 //! \name Local enumerations 2108 2109 //! \name Initializations 2110 2111 //! \brief Explicit member initialization function HCP_TILE_POSITION_IN_CTB_MSB_CMDHCP_TILE_POSITION_IN_CTB_MSB_CMD2112 HCP_TILE_POSITION_IN_CTB_MSB_CMD() 2113 { 2114 DW0.Value = 0x00000000; 2115 2116 DW1.Value = 0x00000000; 2117 } 2118 2119 static const size_t dwSize = 2; 2120 static const size_t byteSize = 8; 2121 }; 2122 2123 //! 2124 //! \brief HCP_TILE_STATE 2125 //! \details 2126 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2127 //! Commands. Each HCP command has assigned a media instruction command as 2128 //! defined in DWord 0, BitField 22:16. 2129 //! 2130 //! This command is valid for decoder only. 2131 //! 2132 struct HCP_TILE_STATE_CMD 2133 { 2134 union 2135 { 2136 struct 2137 { 2138 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2139 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2140 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2141 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2142 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2143 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2144 }; 2145 uint32_t Value; 2146 } DW0; 2147 union 2148 { 2149 struct 2150 { 2151 uint32_t Numtilerowsminus1 : __CODEGEN_BITFIELD( 0, 4) ; //!< NumTileRowsMinus1 2152 uint32_t Numtilecolumnsminus1 : __CODEGEN_BITFIELD( 5, 9) ; //!< NumTileColumnsMinus1 2153 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 2154 }; 2155 uint32_t Value; 2156 } DW1; 2157 HCP_TILE_POSITION_IN_CTB_CMD CtbColumnPositionOfTileColumn[5]; //!< DW2..6, Ctb column position of tile column 2158 HCP_TILE_POSITION_IN_CTB_CMD CtbRowPositionOfTileRow[6]; //!< DW7..12, Ctb row position of tile row 2159 HCP_TILE_POSITION_IN_CTB_MSB_CMD CtbColumnPositionMsb; //!< DW13..14, Ctb column position MSB 2160 HCP_TILE_POSITION_IN_CTB_MSB_CMD CtbRowPositionMsb; //!< DW15..16, Ctb row position MSB 2161 2162 //! \name Local enumerations 2163 2164 enum MEDIA_INSTRUCTION_COMMAND 2165 { 2166 MEDIA_INSTRUCTION_COMMAND_HCPTILESTATE = 17, //!< No additional details 2167 }; 2168 2169 //! \brief MEDIA_INSTRUCTION_OPCODE 2170 //! \details 2171 //! Codec/Engine Name = HCP = 7h 2172 enum MEDIA_INSTRUCTION_OPCODE 2173 { 2174 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2175 }; 2176 2177 enum PIPELINE_TYPE 2178 { 2179 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2180 }; 2181 2182 enum COMMAND_TYPE 2183 { 2184 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2185 }; 2186 2187 //! \name Initializations 2188 2189 //! \brief Explicit member initialization function HCP_TILE_STATE_CMDHCP_TILE_STATE_CMD2190 HCP_TILE_STATE_CMD() 2191 { 2192 DW0.Value = 0x7391000f; 2193 //DW0.DwordLength = GetOpLength(dwSize); 2194 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPTILESTATE; 2195 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 2196 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 2197 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 2198 2199 DW1.Value = 0x00000000; 2200 } 2201 2202 static const size_t dwSize = 17; 2203 static const size_t byteSize = 68; 2204 }; 2205 2206 //! 2207 //! \brief HCP_REF_LIST_ENTRY 2208 //! \details 2209 //! 2210 //! 2211 struct HCP_REF_LIST_ENTRY_CMD 2212 { 2213 union 2214 { 2215 struct 2216 { 2217 uint32_t ReferencePictureTbValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Reference Picture tb Value 2218 uint32_t ListEntryLxReferencePictureFrameIdRefaddr07 : __CODEGEN_BITFIELD( 8, 10) ; //!< list_entry_lX: Reference Picture Frame ID (RefAddr[0-7]) 2219 uint32_t ChromaWeightLxFlag : __CODEGEN_BITFIELD(11, 11) ; //!< CHROMA_WEIGHT_LX_FLAG 2220 uint32_t LumaWeightLxFlag : __CODEGEN_BITFIELD(12, 12) ; //!< LUMA_WEIGHT_LX_FLAG 2221 uint32_t Longtermreference : __CODEGEN_BITFIELD(13, 13) ; //!< LONGTERMREFERENCE 2222 uint32_t FieldPicFlag : __CODEGEN_BITFIELD(14, 14) ; //!< FIELD_PIC_FLAG 2223 uint32_t BottomFieldFlag : __CODEGEN_BITFIELD(15, 15) ; //!< BOTTOM_FIELD_FLAG 2224 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2225 }; 2226 uint32_t Value; 2227 } DW0; 2228 2229 //! \name Local enumerations 2230 2231 //! \brief CHROMA_WEIGHT_LX_FLAG 2232 //! \details 2233 //! Where X is the RefPicListNum and i is the list entry number 0 through 2234 //! 15. DW2 corresponds to i=0, 2235 //! DW17 corresponds to i=15. 2236 enum CHROMA_WEIGHT_LX_FLAG 2237 { 2238 CHROMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORCHROMA = 0, //!< No additional details 2239 CHROMA_WEIGHT_LX_FLAG_EXPLICITWEIGHTEDPREDICTIONFORCHROMA = 1, //!< No additional details 2240 }; 2241 2242 //! \brief LUMA_WEIGHT_LX_FLAG 2243 //! \details 2244 //! Where X is the RefPicListNum and i is the list entry number 0 through 2245 //! 15. DW2 corresponds to i=0, 2246 //! DW17 corresponds to i=15. 2247 enum LUMA_WEIGHT_LX_FLAG 2248 { 2249 LUMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORLUMA = 0, //!< No additional details 2250 LUMA_WEIGHT_LX_FLAG_EXPLICITWEIGHTEDPREDICTIONFORLUMA = 1, //!< No additional details 2251 }; 2252 2253 //! \brief LONGTERMREFERENCE 2254 //! \details 2255 //! Where X is the RefPicListNum and i is the list entry number 0 through 2256 //! 15. DW2 corresponds to i=0, 2257 //! DW17 corresponds to i=15. 2258 enum LONGTERMREFERENCE 2259 { 2260 LONGTERMREFERENCE_SHORTTERMREFERENCE = 0, //!< No additional details 2261 LONGTERMREFERENCE_LONGTERMREFERENCE = 1, //!< No additional details 2262 }; 2263 2264 //! \brief FIELD_PIC_FLAG 2265 //! \details 2266 //! Where X is the RefPicListNum and i is the list entry number 0 through 2267 //! 15. DW2 corresponds to i=0, 2268 //! DW17 corresponds to i=15. 2269 enum FIELD_PIC_FLAG 2270 { 2271 FIELD_PIC_FLAG_VIDEOFRAME = 0, //!< No additional details 2272 FIELD_PIC_FLAG_VIDEOFIELD = 1, //!< No additional details 2273 }; 2274 2275 //! \brief BOTTOM_FIELD_FLAG 2276 //! \details 2277 //! Where X is the RefPicListNum and i is the list entry number 0 through 2278 //! 15. DW2 corresponds to i=0, 2279 //! DW17 corresponds to i=15. 2280 enum BOTTOM_FIELD_FLAG 2281 { 2282 BOTTOM_FIELD_FLAG_BOTTOMFIELD = 0, //!< No additional details 2283 BOTTOM_FIELD_FLAG_TOPFIELD = 1, //!< No additional details 2284 }; 2285 2286 //! \name Initializations 2287 2288 //! \brief Explicit member initialization function HCP_REF_LIST_ENTRY_CMDHCP_REF_LIST_ENTRY_CMD2289 HCP_REF_LIST_ENTRY_CMD() 2290 { 2291 DW0.Value = 0x00000000; 2292 //DW0.ChromaWeightLxFlag = CHROMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORCHROMA; 2293 //DW0.LumaWeightLxFlag = LUMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORLUMA; 2294 //DW0.Longtermreference = LONGTERMREFERENCE_SHORTTERMREFERENCE; 2295 //DW0.FieldPicFlag = FIELD_PIC_FLAG_VIDEOFRAME; 2296 //DW0.BottomFieldFlag = BOTTOM_FIELD_FLAG_BOTTOMFIELD; 2297 } 2298 2299 static const size_t dwSize = 1; 2300 static const size_t byteSize = 4; 2301 }; 2302 2303 //! 2304 //! \brief HCP_REF_IDX_STATE 2305 //! \details 2306 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2307 //! Commands. Each HCP command has assigned a media instruction command as 2308 //! defined in DWord 0, BitField 22:16. 2309 //! 2310 //! This is a slice level command used in both encoding and decoding 2311 //! processes. For decoder, it is issued with the HCP_BSD_OBJECT command. 2312 //! 2313 //! Unlike AVC, HEVC allows 16 reference idx entries in each of the L0 and 2314 //! L1 list for a progressive picture. Hence, a max total 32 reference idx 2315 //! in both lists together. The same when the picture is a field picture. 2316 //! Regardless the number of reference idx entries, there are only max 8 2317 //! reference pictures exist at any one time. Multiple reference idx can 2318 //! point to the same reference picture and can optionally pic a top or 2319 //! bottom field, or frame. 2320 //! 2321 //! For P-Slice, this command is issued only once, representing L0 list. For 2322 //! B-Slice, this command can be issued up to two times, one for L0 list and 2323 //! one for L1 list. 2324 //! 2325 struct HCP_REF_IDX_STATE_CMD 2326 { 2327 union 2328 { 2329 struct 2330 { 2331 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2332 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2333 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2334 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2335 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2336 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2337 }; 2338 uint32_t Value; 2339 } DW0; 2340 union 2341 { 2342 struct 2343 { 2344 uint32_t Refpiclistnum : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLISTNUM 2345 uint32_t NumRefIdxLRefpiclistnumActiveMinus1 : __CODEGEN_BITFIELD( 1, 4) ; //!< num_ref_idx_l[RefPicListNum]_active_minus1 2346 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 31) ; //!< Reserved 2347 }; 2348 uint32_t Value; 2349 } DW1; 2350 HCP_REF_LIST_ENTRY_CMD Entries[16]; //!< DW2..17, Entries 2351 2352 //! \name Local enumerations 2353 2354 enum MEDIA_INSTRUCTION_COMMAND 2355 { 2356 MEDIA_INSTRUCTION_COMMAND_HCPREFIDXSTATE = 18, //!< No additional details 2357 }; 2358 2359 //! \brief MEDIA_INSTRUCTION_OPCODE 2360 //! \details 2361 //! Codec/Engine Name = HCP = 7h 2362 enum MEDIA_INSTRUCTION_OPCODE 2363 { 2364 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2365 }; 2366 2367 enum PIPELINE_TYPE 2368 { 2369 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2370 }; 2371 2372 enum COMMAND_TYPE 2373 { 2374 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2375 }; 2376 2377 enum REFPICLISTNUM 2378 { 2379 REFPICLISTNUM_REFERENCEPICTURELIST0 = 0, //!< No additional details 2380 REFPICLISTNUM_REFERENCEPICTURELIST1 = 1, //!< No additional details 2381 }; 2382 2383 //! \name Initializations 2384 2385 //! \brief Explicit member initialization function HCP_REF_IDX_STATE_CMDHCP_REF_IDX_STATE_CMD2386 HCP_REF_IDX_STATE_CMD() 2387 { 2388 DW0.Value = 0x73920010; 2389 //DW0.DwordLength = GetOpLength(dwSize); 2390 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPREFIDXSTATE; 2391 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 2392 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 2393 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 2394 2395 DW1.Value = 0x00000000; 2396 //DW1.Refpiclistnum = REFPICLISTNUM_REFERENCEPICTURELIST0; 2397 } 2398 2399 static const size_t dwSize = 18; 2400 static const size_t byteSize = 72; 2401 }; 2402 2403 //! 2404 //! \brief HCP_WEIGHTOFFSET_LUMA_ENTRY 2405 //! \details 2406 //! 2407 //! 2408 struct HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD 2409 { 2410 union 2411 { 2412 struct 2413 { 2414 uint32_t DeltaLumaWeightLxI : __CODEGEN_BITFIELD( 0, 7) ; //!< delta_luma_weight_lX[i] 2415 uint32_t LumaOffsetLxI : __CODEGEN_BITFIELD( 8, 15) ; //!< luma_offset_lX[i] 2416 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 2417 uint32_t LumaOffsetLxIMsbyte : __CODEGEN_BITFIELD(24, 31) ; //!< luma_offset_lX[i] MSByte 2418 }; 2419 uint32_t Value; 2420 } DW0; 2421 2422 //! \name Local enumerations 2423 2424 //! \name Initializations 2425 2426 //! \brief Explicit member initialization function HCP_WEIGHTOFFSET_LUMA_ENTRY_CMDHCP_WEIGHTOFFSET_LUMA_ENTRY_CMD2427 HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD() 2428 { 2429 DW0.Value = 0x00000000; 2430 } 2431 2432 static const size_t dwSize = 1; 2433 static const size_t byteSize = 4; 2434 }; 2435 2436 //! 2437 //! \brief HCP_WEIGHTOFFSET_CHROMA_ENTRY 2438 //! \details 2439 //! 2440 //! 2441 struct HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD 2442 { 2443 union 2444 { 2445 struct 2446 { 2447 uint32_t DeltaChromaWeightLxI0 : __CODEGEN_BITFIELD( 0, 7) ; //!< delta_chroma_weight_lX[i][0] 2448 uint32_t ChromaoffsetlxI0 : __CODEGEN_BITFIELD( 8, 15) ; //!< ChromaOffsetLX[i][0] 2449 uint32_t DeltaChromaWeightLxI1 : __CODEGEN_BITFIELD(16, 23) ; //!< delta_chroma_weight_lX[i][1] 2450 uint32_t ChromaoffsetlxI1 : __CODEGEN_BITFIELD(24, 31) ; //!< ChromaOffsetLX [i][1] 2451 }; 2452 uint32_t Value; 2453 } DW0; 2454 2455 //! \name Local enumerations 2456 2457 //! \name Initializations 2458 2459 //! \brief Explicit member initialization function HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMDHCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD2460 HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD() 2461 { 2462 DW0.Value = 0x00000000; 2463 } 2464 2465 static const size_t dwSize = 1; 2466 static const size_t byteSize = 4; 2467 }; 2468 2469 //! 2470 //! \brief HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY 2471 //! \details 2472 //! 2473 //! 2474 struct HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD 2475 { 2476 union 2477 { 2478 struct 2479 { 2480 uint32_t ChromaoffsetlxI0Msbyte : __CODEGEN_BITFIELD( 0, 7) ; //!< ChromaOffsetLX[i][0] MSByte 2481 uint32_t ChromaoffsetlxI10Msbyte : __CODEGEN_BITFIELD( 8, 15) ; //!< ChromaOffsetLX[i+1][0] MSByte 2482 uint32_t ChromaoffsetlxI1Msbyte : __CODEGEN_BITFIELD(16, 23) ; //!< ChromaOffsetLX[i][1] MSByte 2483 uint32_t ChromaoffsetlxI11Msbyte : __CODEGEN_BITFIELD(24, 31) ; //!< ChromaOffsetLX[i+1][1] MSByte 2484 }; 2485 uint32_t Value; 2486 } DW0; 2487 2488 //! \name Local enumerations 2489 2490 //! \name Initializations 2491 2492 //! \brief Explicit member initialization function HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMDHCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD2493 HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD() 2494 { 2495 DW0.Value = 0x00000000; 2496 } 2497 2498 static const size_t dwSize = 1; 2499 static const size_t byteSize = 4; 2500 }; 2501 2502 //! 2503 //! \brief HCP_WEIGHTOFFSET_STATE 2504 //! \details 2505 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2506 //! Commands. Each HCP command has assigned a media instruction command as 2507 //! defined in DWord 0, BitField 22:16. 2508 //! 2509 //! This slice level command is issued in both the encoding and decoding 2510 //! processes, if the weighted_pred_flag or weighted_bipred_flag equals one. 2511 //! If zero, then this command is not issued. Weight Prediction Values are 2512 //! provided in this command. Only Explicit Weight Prediction is supported 2513 //! in encoder. For P-Slice, this command is issued only once together with 2514 //! HCP_REF_IDX_STATE Command for L0 list. For B-Slice, this command can be 2515 //! issued up to two times together with HCP_REF_IDX_STATE Command, one for 2516 //! L0 list and one for L1 list. 2517 //! 2518 struct HCP_WEIGHTOFFSET_STATE_CMD 2519 { 2520 union 2521 { 2522 struct 2523 { 2524 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2525 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2526 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2527 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2528 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2529 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2530 }; 2531 uint32_t Value; 2532 } DW0; 2533 union 2534 { 2535 struct 2536 { 2537 uint32_t Refpiclistnum : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLISTNUM 2538 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2539 }; 2540 uint32_t Value; 2541 } DW1; 2542 HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD Lumaoffsets[16]; //!< DW2..17, LumaOffsets 2543 HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD Chromaoffsets[16]; //!< DW18..33, ChromaOffsets 2544 HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD Chromaoffsetsext[8]; //!< DW34..41, ChromaOffsetsExt 2545 2546 //! \name Local enumerations 2547 2548 enum MEDIA_INSTRUCTION_COMMAND 2549 { 2550 MEDIA_INSTRUCTION_COMMAND_HCPWEIGHTOFFSETSTATE = 19, //!< No additional details 2551 }; 2552 2553 //! \brief MEDIA_INSTRUCTION_OPCODE 2554 //! \details 2555 //! Codec/Engine Name = HCP = 7h 2556 enum MEDIA_INSTRUCTION_OPCODE 2557 { 2558 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2559 }; 2560 2561 enum PIPELINE_TYPE 2562 { 2563 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2564 }; 2565 2566 enum COMMAND_TYPE 2567 { 2568 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2569 }; 2570 2571 enum REFPICLISTNUM 2572 { 2573 REFPICLISTNUM_REFERENCEPICTURELIST0 = 0, //!< No additional details 2574 REFPICLISTNUM_REFERENCEPICTURELIST1 = 1, //!< No additional details 2575 }; 2576 2577 //! \name Initializations 2578 2579 //! \brief Explicit member initialization function HCP_WEIGHTOFFSET_STATE_CMDHCP_WEIGHTOFFSET_STATE_CMD2580 HCP_WEIGHTOFFSET_STATE_CMD() 2581 { 2582 DW0.Value = 0x73930028; 2583 //DW0.DwordLength = GetOpLength(dwSize); 2584 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPWEIGHTOFFSETSTATE; 2585 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 2586 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 2587 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 2588 2589 DW1.Value = 0x00000000; 2590 //DW1.Refpiclistnum = REFPICLISTNUM_REFERENCEPICTURELIST0; 2591 } 2592 2593 static const size_t dwSize = 42; 2594 static const size_t byteSize = 168; 2595 }; 2596 2597 //! 2598 //! \brief HCP_SLICE_STATE 2599 //! \details 2600 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2601 //! Commands. Each HCP command has assigned a media instruction command as 2602 //! defined in DWord 0, BitField 22:16. 2603 //! 2604 //! This is a slice level command used in both encoding and decoding 2605 //! processes. For decoder, it is issued with the HCP_BSD_OBJECT command. 2606 //! 2607 struct HCP_SLICE_STATE_CMD 2608 { 2609 union 2610 { 2611 struct 2612 { 2613 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2614 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2615 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2616 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2617 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2618 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2619 }; 2620 uint32_t Value; 2621 } DW0; 2622 union 2623 { 2624 struct 2625 { 2626 uint32_t SlicestartctbxOrSliceStartLcuXEncoder : __CODEGEN_BITFIELD( 0, 9) ; //!< SliceStartCtbX or (slice_start_lcu_x encoder) 2627 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2628 uint32_t SlicestartctbyOrSliceStartLcuYEncoder : __CODEGEN_BITFIELD(16, 25) ; //!< SliceStartCtbY or (slice_start_lcu_y encoder) 2629 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2630 }; 2631 uint32_t Value; 2632 } DW1; 2633 union 2634 { 2635 struct 2636 { 2637 uint32_t NextslicestartctbxOrNextSliceStartLcuXEncoder : __CODEGEN_BITFIELD( 0, 9) ; //!< NextSliceStartCtbX or (next_slice_start_lcu_x encoder) 2638 uint32_t Reserved74 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2639 uint32_t NextslicestartctbyOrNextSliceStartLcuYEncoder : __CODEGEN_BITFIELD(16, 26) ; //!< NextSliceStartCtbY or (next_slice_start_lcu_y encoder) 2640 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 2641 }; 2642 uint32_t Value; 2643 } DW2; 2644 union 2645 { 2646 struct 2647 { 2648 uint32_t SliceType : __CODEGEN_BITFIELD( 0, 1) ; //!< SLICE_TYPE 2649 uint32_t Lastsliceofpic : __CODEGEN_BITFIELD( 2, 2) ; //!< LASTSLICEOFPIC 2650 uint32_t SliceqpSignFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< SliceQp Sign Flag 2651 uint32_t DependentSliceFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< dependent_slice_flag 2652 uint32_t SliceTemporalMvpEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< slice_temporal_mvp_enable_flag 2653 uint32_t Sliceqp : __CODEGEN_BITFIELD( 6, 11) ; //!< SliceQp 2654 uint32_t SliceCbQpOffset : __CODEGEN_BITFIELD(12, 16) ; //!< SLICE_CB_QP_OFFSET 2655 uint32_t SliceCrQpOffset : __CODEGEN_BITFIELD(17, 21) ; //!< SLICE_CR_QP_OFFSET 2656 uint32_t Intrareffetchdisable : __CODEGEN_BITFIELD(22, 22) ; //!< IntraRefFetchDisable 2657 uint32_t CuChromaQpOffsetEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< cu_chroma_qp_offset_enabled_flag 2658 uint32_t Lastsliceoftile : __CODEGEN_BITFIELD(24, 24) ; //!< LastSliceOfTile 2659 uint32_t Lastsliceoftilecolumn : __CODEGEN_BITFIELD(25, 25) ; //!< LastSliceOfTileColumn 2660 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2661 }; 2662 uint32_t Value; 2663 } DW3; 2664 union 2665 { 2666 struct 2667 { 2668 uint32_t SliceHeaderDisableDeblockingFilterFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< slice_header_disable_deblocking_filter_flag 2669 uint32_t SliceTcOffsetDiv2OrFinalTcOffsetDiv2Encoder : __CODEGEN_BITFIELD( 1, 4) ; //!< slice_tc_offset_div2 or (final tc_offset_div2 Encoder) 2670 uint32_t SliceBetaOffsetDiv2OrFinalBetaOffsetDiv2Encoder : __CODEGEN_BITFIELD( 5, 8) ; //!< slice_beta_offset_div2 or (final Beta_Offset_div2 Encoder) 2671 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 2672 uint32_t SliceLoopFilterAcrossSlicesEnabledFlag : __CODEGEN_BITFIELD(10, 10) ; //!< slice_loop_filter_across_slices_enabled_flag 2673 uint32_t SliceSaoChromaFlag : __CODEGEN_BITFIELD(11, 11) ; //!< slice_sao_chroma_flag 2674 uint32_t SliceSaoLumaFlag : __CODEGEN_BITFIELD(12, 12) ; //!< slice_sao_luma_flag 2675 uint32_t MvdL1ZeroFlag : __CODEGEN_BITFIELD(13, 13) ; //!< mvd_l1_zero_flag 2676 uint32_t Islowdelay : __CODEGEN_BITFIELD(14, 14) ; //!< isLowDelay 2677 uint32_t CollocatedFromL0Flag : __CODEGEN_BITFIELD(15, 15) ; //!< collocated_from_l0_flag 2678 uint32_t Chromalog2Weightdenom : __CODEGEN_BITFIELD(16, 18) ; //!< ChromaLog2WeightDenom 2679 uint32_t LumaLog2WeightDenom : __CODEGEN_BITFIELD(19, 21) ; //!< luma_log2_weight_denom 2680 uint32_t CabacInitFlag : __CODEGEN_BITFIELD(22, 22) ; //!< cabac_init_flag 2681 uint32_t Maxmergeidx : __CODEGEN_BITFIELD(23, 25) ; //!< MAXMERGEIDX 2682 uint32_t Collocatedrefidx : __CODEGEN_BITFIELD(26, 28) ; //!< CollocatedRefIDX 2683 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2684 }; 2685 uint32_t Value; 2686 } DW4; 2687 union 2688 { 2689 struct 2690 { 2691 uint32_t Sliceheaderlength : __CODEGEN_BITFIELD( 0, 15) ; //!< SliceHeaderLength 2692 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2693 }; 2694 uint32_t Value; 2695 } DW5; 2696 union 2697 { 2698 struct 2699 { 2700 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 19) ; //!< Reserved 2701 uint32_t Roundintra : __CODEGEN_BITFIELD(20, 23) ; //!< ROUNDINTRA 2702 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 25) ; //!< Reserved 2703 uint32_t Roundinter : __CODEGEN_BITFIELD(26, 29) ; //!< ROUNDINTER 2704 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2705 }; 2706 uint32_t Value; 2707 } DW6; 2708 union 2709 { 2710 struct 2711 { 2712 uint32_t DependentSliceDueToTileSplit : __CODEGEN_BITFIELD( 0, 0) ; //!< Dependent Slice due to Tile Split 2713 uint32_t Cabaczerowordinsertionenable : __CODEGEN_BITFIELD( 1, 1) ; //!< CABACZEROWORDINSERTIONENABLE 2714 uint32_t Emulationbytesliceinsertenable : __CODEGEN_BITFIELD( 2, 2) ; //!< EMULATIONBYTESLICEINSERTENABLE 2715 uint32_t Reserved227 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 2716 uint32_t TailInsertionEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< TAIL_INSERTION_ENABLE 2717 uint32_t SlicedataEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SLICEDATA_ENABLE 2718 uint32_t HeaderInsertionEnable : __CODEGEN_BITFIELD(10, 10) ; //!< HEADER_INSERTION_ENABLE 2719 uint32_t Reserved235 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 2720 }; 2721 uint32_t Value; 2722 } DW7; 2723 union 2724 { 2725 struct 2726 { 2727 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 2728 uint32_t IndirectPakBseDataStartOffsetWrite : __CODEGEN_BITFIELD( 6, 28) ; //!< Indirect PAK-BSE Data Start Offset (Write) 2729 uint32_t Reserved285 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2730 }; 2731 uint32_t Value; 2732 } DW8; 2733 union 2734 { 2735 struct 2736 { 2737 uint32_t TransformskipLambda : __CODEGEN_BITFIELD( 0, 15) ; //!< Transformskip_lambda 2738 uint32_t Reserved304 : __CODEGEN_BITFIELD(16, 30) ; //!< Reserved 2739 uint32_t ForceSaoParametersToZero : __CODEGEN_BITFIELD(31, 31) ; //!< Force SAO parameters to zero 2740 }; 2741 uint32_t Value; 2742 } DW9; 2743 union 2744 { 2745 struct 2746 { 2747 uint32_t TransformskipNumzerocoeffsFactor0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Transformskip_numzerocoeffs_factor0 2748 uint32_t TransformskipNumnonzerocoeffsFactor0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Transformskip_numnonzerocoeffs_factor0 2749 uint32_t TransformskipNumzerocoeffsFactor1 : __CODEGEN_BITFIELD(16, 23) ; //!< Transformskip_numzerocoeffs_factor1 2750 uint32_t TransformskipNumnonzerocoeffsFactor1 : __CODEGEN_BITFIELD(24, 31) ; //!< Transformskip_numnonzerocoeffs_factor1 2751 }; 2752 uint32_t Value; 2753 } DW10; 2754 union 2755 { 2756 struct 2757 { 2758 uint32_t Originalslicestartctbx : __CODEGEN_BITFIELD( 0, 9) ; //!< OriginalSliceStartCtbX 2759 uint32_t Reserved362 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2760 uint32_t Originalslicestartctby : __CODEGEN_BITFIELD(16, 25) ; //!< OriginalSliceStartCtbY 2761 uint32_t Reserved378 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2762 }; 2763 uint32_t Value; 2764 } DW11; 2765 union 2766 { 2767 struct 2768 { 2769 uint32_t SliceActCrQpOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< slice_act_cr_qp_offset 2770 uint32_t SliceActCbQpOffset : __CODEGEN_BITFIELD( 6, 11) ; //!< slice_act_cb_qp_offset 2771 uint32_t SliceActYQpOffset : __CODEGEN_BITFIELD(12, 17) ; //!< slice_act_y_qp_offset 2772 uint32_t Reserved402 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 2773 uint32_t UseIntegerMvFlag : __CODEGEN_BITFIELD(31, 31) ; //!< use_integer_mv_flag 2774 }; 2775 uint32_t Value; 2776 } DW12; 2777 2778 //! \name Local enumerations 2779 2780 enum MEDIA_INSTRUCTION_COMMAND 2781 { 2782 MEDIA_INSTRUCTION_COMMAND_HCPSLICESTATE = 20, //!< No additional details 2783 }; 2784 2785 //! \brief MEDIA_INSTRUCTION_OPCODE 2786 //! \details 2787 //! Codec/Engine Name = HCP = 7h 2788 enum MEDIA_INSTRUCTION_OPCODE 2789 { 2790 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2791 }; 2792 2793 enum PIPELINE_TYPE 2794 { 2795 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2796 }; 2797 2798 enum COMMAND_TYPE 2799 { 2800 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2801 }; 2802 2803 //! \brief SLICE_TYPE 2804 //! \details 2805 //! In VDENC mode, for HEVC standard this field can be 0 or 2 only. 2806 enum SLICE_TYPE 2807 { 2808 SLICE_TYPE_B_SLICE = 0, //!< No additional details 2809 SLICE_TYPE_P_SLICE = 1, //!< No additional details 2810 SLICE_TYPE_I_SLICE = 2, //!< No additional details 2811 SLICE_TYPE_ILLEGALRESERVED = 3, //!< No additional details 2812 }; 2813 2814 //! \brief LASTSLICEOFPIC 2815 //! \details 2816 //! This indicates the current slice is the very last slice of the current 2817 //! picture 2818 enum LASTSLICEOFPIC 2819 { 2820 LASTSLICEOFPIC_NOTTHELASTSLICEOFTHEPICTURE = 0, //!< No additional details 2821 LASTSLICEOFPIC_LASTSLICEOFTHEPICTURE = 1, //!< No additional details 2822 }; 2823 2824 //! \brief SLICE_CB_QP_OFFSET 2825 //! \details 2826 //! For deblocking purpose, the pic and slice level cb qp offset must be 2827 //! provided separately. 2828 enum SLICE_CB_QP_OFFSET 2829 { 2830 SLICE_CB_QP_OFFSET_0 = 0, //!< No additional details 2831 SLICE_CB_QP_OFFSET_1 = 1, //!< No additional details 2832 SLICE_CB_QP_OFFSET_2 = 2, //!< No additional details 2833 SLICE_CB_QP_OFFSET_3 = 3, //!< No additional details 2834 SLICE_CB_QP_OFFSET_4 = 4, //!< No additional details 2835 SLICE_CB_QP_OFFSET_5 = 5, //!< No additional details 2836 SLICE_CB_QP_OFFSET_6 = 6, //!< No additional details 2837 SLICE_CB_QP_OFFSET_7 = 7, //!< No additional details 2838 SLICE_CB_QP_OFFSET_8 = 8, //!< No additional details 2839 SLICE_CB_QP_OFFSET_9 = 9, //!< No additional details 2840 SLICE_CB_QP_OFFSET_10 = 10, //!< No additional details 2841 SLICE_CB_QP_OFFSET_11 = 11, //!< No additional details 2842 SLICE_CB_QP_OFFSET_12 = 12, //!< No additional details 2843 SLICE_CB_QP_OFFSET_NEG_12 = 20, //!< No additional details 2844 SLICE_CB_QP_OFFSET_NEG_11 = 21, //!< No additional details 2845 SLICE_CB_QP_OFFSET_NEG_10 = 22, //!< No additional details 2846 SLICE_CB_QP_OFFSET_NEG_9 = 23, //!< No additional details 2847 SLICE_CB_QP_OFFSET_NEG_8 = 24, //!< No additional details 2848 SLICE_CB_QP_OFFSET_NEG_7 = 25, //!< No additional details 2849 SLICE_CB_QP_OFFSET_NEG_6 = 26, //!< No additional details 2850 SLICE_CB_QP_OFFSET_NEG_5 = 27, //!< No additional details 2851 SLICE_CB_QP_OFFSET_NEG_4 = 28, //!< No additional details 2852 SLICE_CB_QP_OFFSET_NEG_3 = 29, //!< No additional details 2853 SLICE_CB_QP_OFFSET_NEG_2 = 30, //!< No additional details 2854 SLICE_CB_QP_OFFSET_NEG_1 = 31, //!< No additional details 2855 }; 2856 2857 //! \brief SLICE_CR_QP_OFFSET 2858 //! \details 2859 //! For deblocking purpose, the pic and slice level cr qp offset must be 2860 //! provided separately. 2861 enum SLICE_CR_QP_OFFSET 2862 { 2863 SLICE_CR_QP_OFFSET_0 = 0, //!< No additional details 2864 SLICE_CR_QP_OFFSET_1 = 1, //!< No additional details 2865 SLICE_CR_QP_OFFSET_2 = 2, //!< No additional details 2866 SLICE_CR_QP_OFFSET_3 = 3, //!< No additional details 2867 SLICE_CR_QP_OFFSET_4 = 4, //!< No additional details 2868 SLICE_CR_QP_OFFSET_5 = 5, //!< No additional details 2869 SLICE_CR_QP_OFFSET_6 = 6, //!< No additional details 2870 SLICE_CR_QP_OFFSET_7 = 7, //!< No additional details 2871 SLICE_CR_QP_OFFSET_8 = 8, //!< No additional details 2872 SLICE_CR_QP_OFFSET_9 = 9, //!< No additional details 2873 SLICE_CR_QP_OFFSET_10 = 10, //!< No additional details 2874 SLICE_CR_QP_OFFSET_11 = 11, //!< No additional details 2875 SLICE_CR_QP_OFFSET_12 = 12, //!< No additional details 2876 SLICE_CR_QP_OFFSET_NEG_12 = 20, //!< No additional details 2877 SLICE_CR_QP_OFFSET_NEG_11 = 21, //!< No additional details 2878 SLICE_CR_QP_OFFSET_NEG_10 = 22, //!< No additional details 2879 SLICE_CR_QP_OFFSET_NEG_9 = 23, //!< No additional details 2880 SLICE_CR_QP_OFFSET_NEG_8 = 24, //!< No additional details 2881 SLICE_CR_QP_OFFSET_NEG_7 = 25, //!< No additional details 2882 SLICE_CR_QP_OFFSET_NEG_6 = 26, //!< No additional details 2883 SLICE_CR_QP_OFFSET_NEG_5 = 27, //!< No additional details 2884 SLICE_CR_QP_OFFSET_NEG_4 = 28, //!< No additional details 2885 SLICE_CR_QP_OFFSET_NEG_3 = 29, //!< No additional details 2886 SLICE_CR_QP_OFFSET_NEG_2 = 30, //!< No additional details 2887 SLICE_CR_QP_OFFSET_NEG_1 = 31, //!< No additional details 2888 }; 2889 2890 //! \brief MAXMERGEIDX 2891 //! \details 2892 //! MaxNumMergeCand = 5 - five_minus_max_num_merge_cand -1. 2893 enum MAXMERGEIDX 2894 { 2895 MAXMERGEIDX_0 = 0, //!< No additional details 2896 MAXMERGEIDX_1 = 1, //!< No additional details 2897 MAXMERGEIDX_2 = 2, //!< No additional details 2898 MAXMERGEIDX_3 = 3, //!< No additional details 2899 MAXMERGEIDX_4 = 4, //!< No additional details 2900 }; 2901 2902 //! \brief ROUNDINTRA 2903 //! \details 2904 //! In VDENC mode, this field is ignored. 2905 enum ROUNDINTRA 2906 { 2907 ROUNDINTRA_132 = 0, //!< No additional details 2908 ROUNDINTRA_232 = 1, //!< No additional details 2909 ROUNDINTRA_332 = 2, //!< No additional details 2910 ROUNDINTRA_432 = 3, //!< No additional details 2911 ROUNDINTRA_532 = 4, //!< No additional details 2912 ROUNDINTRA_632 = 5, //!< No additional details 2913 ROUNDINTRA_732 = 6, //!< No additional details 2914 ROUNDINTRA_832 = 7, //!< No additional details 2915 ROUNDINTRA_932 = 8, //!< No additional details 2916 ROUNDINTRA_1032 = 9, //!< No additional details 2917 ROUNDINTRA_1132 = 10, //!< No additional details 2918 ROUNDINTRA_1232 = 11, //!< No additional details 2919 ROUNDINTRA_1332 = 12, //!< No additional details 2920 ROUNDINTRA_1432 = 13, //!< No additional details 2921 ROUNDINTRA_1532 = 14, //!< No additional details 2922 ROUNDINTRA_1632 = 15, //!< No additional details 2923 }; 2924 2925 //! \brief ROUNDINTER 2926 //! \details 2927 //! In VDENC mode, this field is ignored. 2928 enum ROUNDINTER 2929 { 2930 ROUNDINTER_132 = 0, //!< No additional details 2931 ROUNDINTER_232 = 1, //!< No additional details 2932 ROUNDINTER_332 = 2, //!< No additional details 2933 ROUNDINTER_432 = 3, //!< No additional details 2934 ROUNDINTER_532 = 4, //!< No additional details 2935 ROUNDINTER_632 = 5, //!< No additional details 2936 ROUNDINTER_732 = 6, //!< No additional details 2937 ROUNDINTER_832 = 7, //!< No additional details 2938 ROUNDINTER_932 = 8, //!< No additional details 2939 ROUNDINTER_1032 = 9, //!< No additional details 2940 ROUNDINTER_1132 = 10, //!< No additional details 2941 ROUNDINTER_1232 = 11, //!< No additional details 2942 ROUNDINTER_1332 = 12, //!< No additional details 2943 ROUNDINTER_1432 = 13, //!< No additional details 2944 ROUNDINTER_1532 = 14, //!< No additional details 2945 ROUNDINTER_1632 = 15, //!< No additional details 2946 }; 2947 2948 //! \brief CABACZEROWORDINSERTIONENABLE 2949 //! \details 2950 //! To pad the end of a SliceLayer RBSP to meet the encoded size 2951 //! requirement. 2952 enum CABACZEROWORDINSERTIONENABLE 2953 { 2954 CABACZEROWORDINSERTIONENABLE_UNNAMED0 = 0, //!< No Cabac_Zero_Word Insertion. 2955 CABACZEROWORDINSERTIONENABLE_UNNAMED1 = 1, //!< Allow internal Cabac_Zero_Word generation and append to the end of RBSP (effectively can be usedas an indicator for last slice of a picture, if the assumption is only the last slice of a pictureneeds to insert CABAC_ZERO_WORDs). 2956 }; 2957 2958 //! \brief EMULATIONBYTESLICEINSERTENABLE 2959 //! \details 2960 //! To have PAK outputting SODB or EBSP to the output bitstream buffer. 2961 enum EMULATIONBYTESLICEINSERTENABLE 2962 { 2963 EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGRBSP = 0, //!< No additional details 2964 EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGEBSP = 1, //!< No additional details 2965 }; 2966 2967 //! \brief TAIL_INSERTION_ENABLE 2968 //! \details 2969 //! Must be followed by the PAK Insertion Object Command to perform the 2970 //! actual insertion. 2971 enum TAIL_INSERTION_ENABLE 2972 { 2973 TAIL_INSERTION_ENABLE_UNNAMED0 = 0, //!< No tail insertion into the output bitstream buffer, after the current slice encoded bits. 2974 TAIL_INSERTION_ENABLE_UNNAMED1 = 1, //!< Tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits.SKL restriction: Tail insertion is only possible at the end of frame but not in the middle (say slice end) 2975 }; 2976 2977 //! \brief SLICEDATA_ENABLE 2978 //! \details 2979 //! <p>Must always be enabled.</p> 2980 //! <p>Encoder only feature.</p> 2981 enum SLICEDATA_ENABLE 2982 { 2983 SLICEDATA_ENABLE_UNNAMED0 = 0, //!< No operation; no insertion. 2984 SLICEDATA_ENABLE_UNNAMED1 = 1, //!< Slice Data insertion by PAK Object Commands into the output bitstream buffer. 2985 }; 2986 2987 //! \brief HEADER_INSERTION_ENABLE 2988 //! \details 2989 //! Must be followed by the PAK Insertion Object Command to perform the 2990 //! actual insertion. 2991 enum HEADER_INSERTION_ENABLE 2992 { 2993 HEADER_INSERTION_ENABLE_UNNAMED0 = 0, //!< No header insertion into the output bitstream buffer, before the current slice encoded bits. 2994 HEADER_INSERTION_ENABLE_UNNAMED1 = 1, //!< Header insertion into the output bitstream buffer is present, and is before the current slice encoded bits. 2995 }; 2996 2997 //! \name Initializations 2998 2999 //! \brief Explicit member initialization function HCP_SLICE_STATE_CMDHCP_SLICE_STATE_CMD3000 HCP_SLICE_STATE_CMD() 3001 { 3002 DW0.Value = 0x7394000b; 3003 //DW0.DwordLength = GetOpLength(dwSize); 3004 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPSLICESTATE; 3005 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3006 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3007 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3008 3009 DW1.Value = 0x00000000; 3010 3011 DW2.Value = 0x00000000; 3012 3013 DW3.Value = 0x00000000; 3014 //DW3.SliceType = SLICE_TYPE_B_SLICE; 3015 //DW3.Lastsliceofpic = LASTSLICEOFPIC_NOTTHELASTSLICEOFTHEPICTURE; 3016 //DW3.SliceCbQpOffset = SLICE_CB_QP_OFFSET_0; 3017 //DW3.SliceCrQpOffset = SLICE_CR_QP_OFFSET_0; 3018 3019 DW4.Value = 0x00000000; 3020 //DW4.Maxmergeidx = MAXMERGEIDX_0; 3021 3022 DW5.Value = 0x00000000; 3023 3024 DW6.Value = 0x10400000; 3025 //DW6.Roundintra = ROUNDINTRA_532; 3026 //DW6.Roundinter = ROUNDINTER_532; 3027 3028 DW7.Value = 0x00000000; 3029 //DW7.Cabaczerowordinsertionenable = CABACZEROWORDINSERTIONENABLE_UNNAMED0; 3030 //DW7.Emulationbytesliceinsertenable = EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGRBSP; 3031 //DW7.TailInsertionEnable = TAIL_INSERTION_ENABLE_UNNAMED0; 3032 //DW7.SlicedataEnable = SLICEDATA_ENABLE_UNNAMED0; 3033 //DW7.HeaderInsertionEnable = HEADER_INSERTION_ENABLE_UNNAMED0; 3034 3035 DW8.Value = 0x00000000; 3036 3037 DW9.Value = 0x00000000; 3038 3039 DW10.Value = 0x00000000; 3040 3041 DW11.Value = 0x00000000; 3042 3043 DW12.Value = 0x00000000; 3044 } 3045 3046 static const size_t dwSize = 13; 3047 static const size_t byteSize = 52; 3048 }; 3049 3050 //! 3051 //! \brief HCP_BSD_OBJECT 3052 //! \details 3053 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 3054 //! Commands. Each HCP command has assigned a media instruction command as 3055 //! defined in DWord 0, BitField 22:16. 3056 //! 3057 //! The HCP_BSD_OBJECT command fetches the HEVC bit stream for a slice 3058 //! starting with the first byte in the slice. The bit stream ends with the 3059 //! last non-zero bit of the frame and does not include any zero-padding at 3060 //! the end of the bit stream. There can be multiple slices in a HEVC frame 3061 //! and thus this command can be issued multiple times per frame. 3062 //! 3063 //! The HCP_BSD_OBJECT command must be the last command issued in the 3064 //! sequence of batch commands before the HCP starts decoding. Prior to 3065 //! issuing this command, it is assumed that all configuration parameters in 3066 //! the HCP have been loaded including workload configuration registers and 3067 //! configuration tables. When this command is issued, the HCP is waiting 3068 //! for bit stream data to be presented to the shift register. 3069 //! 3070 struct HCP_BSD_OBJECT_CMD 3071 { 3072 union 3073 { 3074 struct 3075 { 3076 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3077 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3078 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3079 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3080 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3081 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3082 }; 3083 uint32_t Value; 3084 } DW0; 3085 union 3086 { 3087 struct 3088 { 3089 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 3090 }; 3091 uint32_t Value; 3092 } DW1; 3093 union 3094 { 3095 struct 3096 { 3097 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 3098 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3099 }; 3100 uint32_t Value; 3101 } DW2; 3102 3103 //! \name Local enumerations 3104 3105 enum MEDIA_INSTRUCTION_COMMAND 3106 { 3107 MEDIA_INSTRUCTION_COMMAND_HCPBSDOBJECTSTATE = 32, //!< No additional details 3108 }; 3109 3110 //! \brief MEDIA_INSTRUCTION_OPCODE 3111 //! \details 3112 //! Codec/Engine Name = HCP = 7h 3113 enum MEDIA_INSTRUCTION_OPCODE 3114 { 3115 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3116 }; 3117 3118 enum PIPELINE_TYPE 3119 { 3120 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3121 }; 3122 3123 enum COMMAND_TYPE 3124 { 3125 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3126 }; 3127 3128 //! \name Initializations 3129 3130 //! \brief Explicit member initialization function HCP_BSD_OBJECT_CMDHCP_BSD_OBJECT_CMD3131 HCP_BSD_OBJECT_CMD() 3132 { 3133 DW0.Value = 0x73a00001; 3134 //DW0.DwordLength = GetOpLength(dwSize); 3135 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPBSDOBJECTSTATE; 3136 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3137 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3138 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3139 3140 DW1.Value = 0x00000000; 3141 3142 DW2.Value = 0x00000000; 3143 } 3144 3145 static const size_t dwSize = 3; 3146 static const size_t byteSize = 12; 3147 }; 3148 3149 //! 3150 //! \brief HCP_VP9_SEGMENT_STATE 3151 //! \details 3152 //! 3153 //! 3154 struct HCP_VP9_SEGMENT_STATE_CMD 3155 { 3156 union 3157 { 3158 struct 3159 { 3160 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3161 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3162 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3163 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3164 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3165 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3166 }; 3167 uint32_t Value; 3168 } DW0; 3169 union 3170 { 3171 struct 3172 { 3173 uint32_t SegmentId : __CODEGEN_BITFIELD( 0, 2) ; //!< Segment ID 3174 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 31) ; //!< Reserved 3175 }; 3176 uint32_t Value; 3177 } DW1; 3178 union 3179 { 3180 struct 3181 { 3182 uint32_t SegmentSkipped : __CODEGEN_BITFIELD( 0, 0) ; //!< Segment Skipped 3183 uint32_t SegmentReference : __CODEGEN_BITFIELD( 1, 2) ; //!< Segment Reference 3184 uint32_t SegmentReferenceEnabled : __CODEGEN_BITFIELD( 3, 3) ; //!< Segment Reference Enabled 3185 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 3186 }; 3187 uint32_t Value; 3188 } DW2; 3189 union 3190 { 3191 struct 3192 { 3193 uint32_t Filterlevelref0Mode0 : __CODEGEN_BITFIELD( 0, 5) ; //!< FilterLevelRef0Mode0 3194 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 3195 uint32_t Filterlevelref0Mode1 : __CODEGEN_BITFIELD( 8, 13) ; //!< FilterLevelRef0Mode1 3196 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3197 uint32_t Filterlevelref1Mode0 : __CODEGEN_BITFIELD(16, 21) ; //!< FilterLevelRef1Mode0 3198 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 3199 uint32_t Filterlevelref1Mode1 : __CODEGEN_BITFIELD(24, 29) ; //!< FilterLevelRef1Mode1 3200 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3201 }; 3202 uint32_t Value; 3203 } DW3; 3204 union 3205 { 3206 struct 3207 { 3208 uint32_t Filterlevelref2Mode0 : __CODEGEN_BITFIELD( 0, 5) ; //!< FilterLevelRef2Mode0 3209 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 3210 uint32_t Filterlevelref2Mode1 : __CODEGEN_BITFIELD( 8, 13) ; //!< FilterLevelRef2Mode1 3211 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3212 uint32_t Filterlevelref3Mode0 : __CODEGEN_BITFIELD(16, 21) ; //!< FilterLevelRef3Mode0 3213 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 3214 uint32_t Filterlevelref3Mode1 : __CODEGEN_BITFIELD(24, 29) ; //!< FilterLevelRef3Mode1 3215 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3216 }; 3217 uint32_t Value; 3218 } DW4; 3219 union 3220 { 3221 struct 3222 { 3223 uint32_t LumaDcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD( 0, 15) ; //!< Luma DC Quant Scale (Decode mode Only) 3224 uint32_t LumaAcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD(16, 31) ; //!< Luma AC Quant Scale (Decode mode Only) 3225 }; 3226 uint32_t Value; 3227 } DW5; 3228 union 3229 { 3230 struct 3231 { 3232 uint32_t ChromaDcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD( 0, 15) ; //!< Chroma DC Quant Scale (Decode mode Only) 3233 uint32_t ChromaAcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD(16, 31) ; //!< Chroma AC Quant Scale (Decode mode Only) 3234 }; 3235 uint32_t Value; 3236 } DW6; 3237 union 3238 { 3239 struct 3240 { 3241 uint32_t SegmentQindexDeltaEncodeModeOnly : __CODEGEN_BITFIELD( 0, 8) ; //!< Segment QIndex Delta (encode mode only) 3242 uint32_t Reserved233 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 3243 uint32_t SegmentLfLevelDeltaEncodeModeOnly : __CODEGEN_BITFIELD(16, 22) ; //!< Segment LF Level Delta (Encode mode Only) 3244 uint32_t Reserved247 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 3245 }; 3246 uint32_t Value; 3247 } DW7; 3248 3249 //! \name Local enumerations 3250 3251 enum MEDIA_INSTRUCTION_COMMAND 3252 { 3253 MEDIA_INSTRUCTION_COMMAND_HCPVP9SEGMENTSTATE = 50, //!< No additional details 3254 }; 3255 3256 //! \brief MEDIA_INSTRUCTION_OPCODE 3257 //! \details 3258 //! Codec/Engine Name = HUC = Bh 3259 enum MEDIA_INSTRUCTION_OPCODE 3260 { 3261 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3262 }; 3263 3264 enum PIPELINE_TYPE 3265 { 3266 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3267 }; 3268 3269 enum COMMAND_TYPE 3270 { 3271 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3272 }; 3273 3274 //! \name Initializations 3275 3276 //! \brief Explicit member initialization function HCP_VP9_SEGMENT_STATE_CMDHCP_VP9_SEGMENT_STATE_CMD3277 HCP_VP9_SEGMENT_STATE_CMD() 3278 { 3279 DW0.Value = 0x73b20006; 3280 //DW0.DwordLength = GetOpLength(dwSize); 3281 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPVP9SEGMENTSTATE; 3282 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3283 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3284 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3285 3286 DW1.Value = 0x00000000; 3287 3288 DW2.Value = 0x00000000; 3289 3290 DW3.Value = 0x00000000; 3291 3292 DW4.Value = 0x00000000; 3293 3294 DW5.Value = 0x00000000; 3295 3296 DW6.Value = 0x00000000; 3297 3298 DW7.Value = 0x00000000; 3299 } 3300 3301 static const size_t dwSize = 8; 3302 static const size_t byteSize = 32; 3303 }; 3304 3305 //! 3306 //! \brief HCP_FQM_STATE 3307 //! \details 3308 //! The HCP_FQM_STATE command loads the custom HEVC quantization tables into 3309 //! local RAM and may be issued up to 8 times: 4 scaling list per intra and 3310 //! inter. 3311 //! 3312 //! Driver is responsible for performing the Scaling List division. So, save 3313 //! the division HW cost in HW. The 1/x value is provided in 16-bit 3314 //! fixed-point precision as ((1<<17)/QM +1) >> 1. . 3315 //! 3316 //! Note: FQM is computed as (2^16)/QM. If QM=1, FQM=all 1's. 3317 //! 3318 //! To simplify the design, only a limited number of scaling lists are 3319 //! provided at the PAK interface: default two SizeID0 and two SizeID123 3320 //! (one set for inter and the other set for intra), and the encoder only 3321 //! allows custom entries for these four matrices. The DC value of SizeID2 3322 //! and SizeID3 will be provided. 3323 //! 3324 //! When the scaling_list_enable_flag is set to disable, the scaling matrix 3325 //! is still sent to the PAK, and with all entries programmed to the same 3326 //! value of 16. 3327 //! 3328 //! This is a picture level state command and is issued in encoding 3329 //! processes only. 3330 //! 3331 //! Dwords 2-33 form a table for the DCT coefficients, 2 16-bit 3332 //! coefficients/DWord. Size 4x4 for SizeID0, DWords 2-9. 3333 //! Size 8x8 for SizeID1/2/3, DWords 2-33. 3334 //! 3335 //! 3336 //! SizeID 0 (Table 4-13) 3337 //! 3338 struct HCP_FQM_STATE_CMD 3339 { 3340 union 3341 { 3342 struct 3343 { 3344 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3345 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3346 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3347 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3348 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3349 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3350 }; 3351 uint32_t Value; 3352 } DW0; 3353 union 3354 { 3355 struct 3356 { 3357 uint32_t IntraInter : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAINTER 3358 uint32_t Sizeid : __CODEGEN_BITFIELD( 1, 2) ; //!< SIZEID 3359 uint32_t ColorComponent : __CODEGEN_BITFIELD( 3, 4) ; //!< COLOR_COMPONENT 3360 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 3361 uint32_t FqmDcValue1Dc : __CODEGEN_BITFIELD(16, 31) ; //!< FQM DC Value: (1/DC): 3362 }; 3363 uint32_t Value; 3364 } DW1; 3365 uint32_t Quantizermatrix[32]; //!< QuantizerMatrix 3366 3367 //! \name Local enumerations 3368 3369 enum MEDIA_INSTRUCTION_COMMAND 3370 { 3371 MEDIA_INSTRUCTION_COMMAND_HCPFQMSTATE = 5, //!< No additional details 3372 }; 3373 3374 //! \brief MEDIA_INSTRUCTION_OPCODE 3375 //! \details 3376 //! Codec/Engine Name = HCP = 7h 3377 enum MEDIA_INSTRUCTION_OPCODE 3378 { 3379 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3380 }; 3381 3382 enum PIPELINE_TYPE 3383 { 3384 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3385 }; 3386 3387 enum COMMAND_TYPE 3388 { 3389 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3390 }; 3391 3392 //! \brief INTRAINTER 3393 //! \details 3394 //! This field specifies the quant matrix intra or inter type. 3395 enum INTRAINTER 3396 { 3397 INTRAINTER_INTRA = 0, //!< No additional details 3398 INTRAINTER_INTER = 1, //!< No additional details 3399 }; 3400 3401 enum SIZEID 3402 { 3403 SIZEID_SIZEID04X4 = 0, //!< No additional details 3404 SIZEID_SIZEID1_2_3_8X8_16X16_32X32 = 1, //!< No additional details 3405 SIZEID_SIZEID2_FORDCVALUEIN16X16 = 2, //!< No additional details 3406 SIZEID_SIZEID3_FORDCVALUEIN32X32 = 3, //!< No additional details 3407 }; 3408 3409 //! \brief COLOR_COMPONENT 3410 //! \details 3411 //! <p>Luma and Chroma's share the same scaling list and DC value for the 3412 //! same SizeID.</p> 3413 enum COLOR_COMPONENT 3414 { 3415 COLOR_COMPONENT_LUMA = 0, //!< No additional details 3416 COLOR_COMPONENT_CHROMACB = 1, //!< No additional details 3417 COLOR_COMPONENT_CHROMACR = 2, //!< No additional details 3418 }; 3419 3420 //! \name Initializations 3421 3422 //! \brief Explicit member initialization function HCP_FQM_STATE_CMDHCP_FQM_STATE_CMD3423 HCP_FQM_STATE_CMD() 3424 { 3425 DW0.Value = 0x73850020; 3426 //DW0.DwordLength = GetOpLength(dwSize); 3427 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPFQMSTATE; 3428 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3429 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3430 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3431 3432 DW1.Value = 0x00000000; 3433 //DW1.IntraInter = INTRAINTER_INTRA; 3434 //DW1.Sizeid = SIZEID_SIZEID04X4; 3435 //DW1.ColorComponent = COLOR_COMPONENT_LUMA; 3436 3437 memset(&Quantizermatrix, 0, sizeof(Quantizermatrix)); 3438 } 3439 3440 static const size_t dwSize = 34; 3441 static const size_t byteSize = 136; 3442 }; 3443 3444 //! 3445 //! \brief HCP_PAK_INSERT_OBJECT 3446 //! \details 3447 //! It is an encoder only command, operating at bitstream level, before and 3448 //! after SliceData compressed bitstream. It is setup by the header and tail 3449 //! present flags in the Slice State command. If these flags are set and no 3450 //! subsequent PAK_INSERT_OBJECT commands are issued, the pipeline will 3451 //! hang. 3452 //! 3453 //! The HCP_ PAK_ INSERT _OBJECT command supports both inline and indirect 3454 //! data payload, but only one can be active at any time. It is issued to 3455 //! insert a chunk of bits (payload) into the current compressed bitstream 3456 //! output buffer (specified in the HCP_PAK-BSE Object Base Address field of 3457 //! the HCP_IND_OBJ_BASE_ADDR_STATE command) starting at its current write 3458 //! pointer bit position. Hardware will keep track of this write pointer's 3459 //! byte position and the associated next bit insertion position index. 3460 //! 3461 //! It is a variable length command when the payload (data to be inserted) 3462 //! is presented as inline data within the command itself. The inline 3463 //! payload is a multiple of 32-bit (1 DW), as the data bus to the 3464 //! compressed bitstream output buffer is 32-bit wide. 3465 //! 3466 //! The payload data is required to be byte aligned on the left (first 3467 //! transmitted bit order) and may or may not be byte aligned on the right 3468 //! (last transmitted bits). The command will specify the bit offset of the 3469 //! last valid DW. Note that : Stitch Command is used if the beginning 3470 //! position of data is in bit position. When PAK Insert Command is used the 3471 //! beginning position must be in byte position. 3472 //! 3473 //! Multiple insertion commands can be issued back to back in a series. It 3474 //! is host software's responsibility to make sure their corresponding data 3475 //! will properly stitch together to form a valid bitstream. 3476 //! 3477 //! Internally, HCP hardware will keep track of the very last two bytes' 3478 //! (the very last byte can be a partial byte) values of the previous 3479 //! insertion. It is required that the next Insertion Object Command or the 3480 //! next PAK Object Command to perform the start code emulation sequence 3481 //! check and prevention 0x03 byte insertion with this end condition of the 3482 //! previous insertion. 3483 //! 3484 //! The payload data may have already been processed for start code 3485 //! emulation byte insertion, except the possibility of the last 2 bytes 3486 //! plus the very last partial byte (if any). Hence, when hardware 3487 //! performing the concatenation of multiple consecutive insertion commands, 3488 //! or concatenation of an insertion command and a PAK object command, it 3489 //! must check and perform the necessary start code emulation byte insert at 3490 //! the junction. 3491 //! 3492 //! Data to be inserted can be a valid NAL units or a partial NAL unit. It 3493 //! can be any encoded syntax elements bit data before the encoded Slice 3494 //! Data (PAK Object Command) of the current Slice - SPS NAL, PPS NAL, SEI 3495 //! NAL and Other Non-Slice NAL, Leading_Zero_8_bits (as many bytes as there 3496 //! is), Start Code , Slice Header. Any encoded syntax elements bit data 3497 //! after the encoded Slice Data (PAK Object Command) of the current Slice 3498 //! and prior to the next encoded Slice Data of the next Slice or prior to 3499 //! the end of the bitstream, whichever comes first Cabac_Zero_Word or 3500 //! Trailing_Zero_8bits (as many bytes as there is). 3501 //! 3502 //! Certain NAL unit has a minimum byte size requirement. As such the 3503 //! hardware will optionally (enabled by SLICE STATE Command) determines the 3504 //! number of CABAC_ZERO_WORD to be inserted to the end of the current NAL, 3505 //! based on the minimum byte size of a NAL and the actual bin count of the 3506 //! encoded Slice. Since prior to the CABAC_ZERO_WORD insertion, the RBSP or 3507 //! EBSP is already byte-aligned, so each CABAC_ZERO_WORD insertion is 3508 //! actually a 3-byte sequence 0x00 00 03. 3509 //! 3510 //! Context switch interrupt is not supported by this command. 3511 //! 3512 struct HCP_PAK_INSERT_OBJECT_CMD 3513 { 3514 union 3515 { 3516 struct 3517 { 3518 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< Dword Length 3519 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3520 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3521 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3522 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3523 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3524 }; 3525 uint32_t Value; 3526 } DW0; 3527 union 3528 { 3529 struct 3530 { 3531 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 3532 uint32_t EndofsliceflagLastdstdatainsertcommandflag : __CODEGEN_BITFIELD( 1, 1) ; //!< EndOfSliceFlag - LastDstDataInsertCommandFlag 3533 uint32_t LastheaderflagLastsrcheaderdatainsertcommandflag : __CODEGEN_BITFIELD( 2, 2) ; //!< LastHeaderFlag - LastSrcHeaderDataInsertCommandFlag 3534 uint32_t EmulationflagEmulationbytebitsinsertenable : __CODEGEN_BITFIELD( 3, 3) ; //!< EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3535 uint32_t SkipemulbytecntSkipEmulationByteCount : __CODEGEN_BITFIELD( 4, 7) ; //!< SkipEmulByteCnt - Skip Emulation Byte Count 3536 uint32_t DatabitsinlastdwSrcdataendingbitinclusion50 : __CODEGEN_BITFIELD( 8, 13) ; //!< DataBitsInLastDW - SrCDataEndingBitInclusion[5:0] 3537 uint32_t SliceHeaderIndicator : __CODEGEN_BITFIELD(14, 14) ; //!< Slice Header Indicator 3538 uint32_t Headerlengthexcludefrmsize : __CODEGEN_BITFIELD(15, 15) ; //!< HEADERLENGTHEXCLUDEFRMSIZE_ 3539 uint32_t DatabyteoffsetSrcdatastartingbyteoffset10 : __CODEGEN_BITFIELD(16, 17) ; //!< DataByteOffset - SrcDataStartingByteOffset[1:0] 3540 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 3541 uint32_t IndirectPayloadEnable : __CODEGEN_BITFIELD(31, 31) ; //!< INDIRECT_PAYLOAD_ENABLE 3542 }; 3543 uint32_t Value; 3544 } DW1; 3545 3546 //! \name Local enumerations 3547 3548 enum MEDIA_INSTRUCTION_COMMAND 3549 { 3550 MEDIA_INSTRUCTION_COMMAND_HCPPAKINSERTOBJECT = 34, //!< No additional details 3551 }; 3552 3553 //! \brief MEDIA_INSTRUCTION_OPCODE 3554 //! \details 3555 //! Codec/Engine Name = HCP = 7h 3556 enum MEDIA_INSTRUCTION_OPCODE 3557 { 3558 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3559 }; 3560 3561 enum PIPELINE_TYPE 3562 { 3563 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3564 }; 3565 3566 enum COMMAND_TYPE 3567 { 3568 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3569 }; 3570 3571 //! \brief EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3572 //! \details 3573 //! Only valid for HEVC and reserved for VP9. 3574 enum EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3575 { 3576 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_STARTCODEPREFIX = 1, //!< Instruct the hardware to perform Start Code Prefix (0x 00 00 01/02/03/00) Search and Prevention Byte (0x 03) insertion on the insertion data of this command. It is required that hardware will handle a start code prefix crossing the boundary between. 3577 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_INSERTIONCOMMAND = 2, //!< Insertion commands, or an insertion command followed by a PAK Object command. 3578 }; 3579 3580 //! \brief HEADERLENGTHEXCLUDEFRMSIZE_ 3581 //! \details 3582 //! <p>In case this flag is on, bits are NOT accumulated during current 3583 //! access unit coding neither for Cabac Zero Word insertion bits counting 3584 //! or for output in MMIO register 3585 //! HCP_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER.</p> 3586 //! <p>When using HeaderLenghtExcludeFrmSize for header insertion, the 3587 //! software needs to make sure that data comes already with inserted start 3588 //! code emulation bytes. SW shouldn't set EmulationFlag bit ( Bit 3 of 3589 //! DWORD1 of HCP_PAK_INSERT_OBJECT).</p> 3590 //! <table border="1" cellpadding="0" cellspacing="0" style="width: 100%;" 3591 //! width="100%"> 3592 //! <tbody> 3593 //! <tr> 3594 //! <td> 3595 //! <p align="center"><b>Value</b></p></td> 3596 //! <td> 3597 //! <p align="center"><b style="text-align: 3598 //! -webkit-center;">Description</b></p></td> 3599 //! </tr> 3600 //! <tr> 3601 //! <td> 3602 //! <p>0</p></td> 3603 //! <td> 3604 //! <p>All bits accumulated</p></td> 3605 //! </tr> 3606 //! <tr> 3607 //! <td> 3608 //! <p>1</p></td> 3609 //! <td> 3610 //! <p>Bits during current call are not accumulated</p></td> 3611 //! </tr> 3612 //! </tbody> 3613 //! </table> 3614 //! 3615 //! <p></p> 3616 enum HEADERLENGTHEXCLUDEFRMSIZE_ 3617 { 3618 HEADERLENGTHEXCLUDEFRMSIZE_ALLBITSACCUMULATED = 0, //!< No additional details 3619 HEADERLENGTHEXCLUDEFRMSIZE_BITSDURINGCURRENTCALLARENOTACCUMULATED = 1, //!< No additional details 3620 }; 3621 3622 //! \brief INDIRECT_PAYLOAD_ENABLE 3623 //! \details 3624 //! <p>Only one of these two payload modes can be active at any time.</p> 3625 //! <p>When Slice Size Conformance is enable the Payload(header) must be 3626 //! inline only so this bit set to MBZ.</p> 3627 enum INDIRECT_PAYLOAD_ENABLE 3628 { 3629 INDIRECT_PAYLOAD_ENABLE_INLINEPAYLOADISUSED = 0, //!< No additional details 3630 INDIRECT_PAYLOAD_ENABLE_INDIRECTPAYLOADISUSED = 1, //!< No additional details 3631 }; 3632 3633 //! \name Initializations 3634 3635 //! \brief Explicit member initialization function HCP_PAK_INSERT_OBJECT_CMDHCP_PAK_INSERT_OBJECT_CMD3636 HCP_PAK_INSERT_OBJECT_CMD() 3637 { 3638 DW0.Value = 0x73a20000; 3639 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPAKINSERTOBJECT; 3640 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3641 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3642 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3643 3644 DW1.Value = 0x00000000; 3645 //DW1.EmulationflagEmulationbytebitsinsertenable = 0; 3646 //DW1.Headerlengthexcludefrmsize = HEADERLENGTHEXCLUDEFRMSIZE_ALLBITSACCUMULATED; 3647 //DW1.IndirectPayloadEnable = INDIRECT_PAYLOAD_ENABLE_INLINEPAYLOADISUSED; 3648 } 3649 3650 static const size_t dwSize = 2; 3651 static const size_t byteSize = 8; 3652 }; 3653 3654 //! 3655 //! \brief HCP_VP9_PIC_STATE 3656 //! \details 3657 //! 3658 //! 3659 struct HCP_VP9_PIC_STATE_CMD 3660 { 3661 union 3662 { 3663 struct 3664 { 3665 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3666 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3667 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3668 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3669 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3670 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3671 }; 3672 uint32_t Value; 3673 } DW0; 3674 union 3675 { 3676 struct 3677 { 3678 uint32_t FrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Frame Width In Pixels Minus 1 3679 uint32_t Reserved46 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3680 uint32_t FrameHeightInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Frame Height In Pixels Minus 1 3681 uint32_t Reserved62 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3682 }; 3683 uint32_t Value; 3684 } DW1; 3685 union 3686 { 3687 struct 3688 { 3689 uint32_t FrameType : __CODEGEN_BITFIELD( 0, 0) ; //!< FRAME_TYPE 3690 uint32_t AdaptProbabilitiesFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< ADAPT_PROBABILITIES_FLAG 3691 uint32_t IntraonlyFlag : __CODEGEN_BITFIELD( 2, 2) ; //!< IntraOnly Flag 3692 uint32_t AllowHiPrecisionMv : __CODEGEN_BITFIELD( 3, 3) ; //!< ALLOW_HI_PRECISION_MV 3693 uint32_t McompFilterType : __CODEGEN_BITFIELD( 4, 6) ; //!< MCOMP_FILTER_TYPE 3694 uint32_t RefFrameSignBias02 : __CODEGEN_BITFIELD( 7, 9) ; //!< Ref Frame Sign Bias[0..2] 3695 uint32_t UsePrevInFindMvReferences : __CODEGEN_BITFIELD(10, 10) ; //!< Use Prev in Find MV References 3696 uint32_t HybridPredictionMode : __CODEGEN_BITFIELD(11, 11) ; //!< HYBRID_PREDICTION_MODE 3697 uint32_t SelectableTxMode : __CODEGEN_BITFIELD(12, 12) ; //!< SELECTABLE_TX_MODE 3698 uint32_t LastFrameType : __CODEGEN_BITFIELD(13, 13) ; //!< LAST_FRAME_TYPE 3699 uint32_t RefreshFrameContext : __CODEGEN_BITFIELD(14, 14) ; //!< REFRESH_FRAME_CONTEXT 3700 uint32_t ErrorResilientMode : __CODEGEN_BITFIELD(15, 15) ; //!< ERROR_RESILIENT_MODE 3701 uint32_t FrameParallelDecodingMode : __CODEGEN_BITFIELD(16, 16) ; //!< FRAME_PARALLEL_DECODING_MODE 3702 uint32_t FilterLevel : __CODEGEN_BITFIELD(17, 22) ; //!< Filter Level 3703 uint32_t SharpnessLevel : __CODEGEN_BITFIELD(23, 25) ; //!< Sharpness Level 3704 uint32_t SegmentationEnabled : __CODEGEN_BITFIELD(26, 26) ; //!< SEGMENTATION_ENABLED 3705 uint32_t SegmentationUpdateMap : __CODEGEN_BITFIELD(27, 27) ; //!< SEGMENTATION_UPDATE_MAP 3706 uint32_t SegmentationTemporalUpdate : __CODEGEN_BITFIELD(28, 28) ; //!< SEGMENTATION_TEMPORAL_UPDATE 3707 uint32_t LosslessMode : __CODEGEN_BITFIELD(29, 29) ; //!< LOSSLESS_MODE 3708 uint32_t SegmentIdStreamoutEnable : __CODEGEN_BITFIELD(30, 30) ; //!< SEGMENT_ID_STREAMOUT_ENABLE 3709 uint32_t SegmentIdStreaminEnable : __CODEGEN_BITFIELD(31, 31) ; //!< SEGMENT_ID_STREAMIN_ENABLE 3710 }; 3711 uint32_t Value; 3712 } DW2; 3713 union 3714 { 3715 struct 3716 { 3717 uint32_t Log2TileColumn : __CODEGEN_BITFIELD( 0, 3) ; //!< LOG2_TILE_COLUMN 3718 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 3719 uint32_t Log2TileRow : __CODEGEN_BITFIELD( 8, 9) ; //!< LOG2_TILE_ROW 3720 uint32_t Reserved106 : __CODEGEN_BITFIELD(10, 20) ; //!< Reserved 3721 uint32_t SseEnable : __CODEGEN_BITFIELD(21, 21) ; //!< SSE Enable 3722 uint32_t ChromaSamplingFormat : __CODEGEN_BITFIELD(22, 23) ; //!< CHROMA_SAMPLING_FORMAT 3723 uint32_t Bitdepthminus8 : __CODEGEN_BITFIELD(24, 27) ; //!< BITDEPTHMINUS8 3724 uint32_t ProfileLevel : __CODEGEN_BITFIELD(28, 31) ; //!< PROFILE_LEVEL 3725 }; 3726 uint32_t Value; 3727 } DW3; 3728 union 3729 { 3730 struct 3731 { 3732 uint32_t VerticalScaleFactorForLast : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for LAST 3733 uint32_t HorizontalScaleFactorForLast : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for LAST 3734 }; 3735 uint32_t Value; 3736 } DW4; 3737 union 3738 { 3739 struct 3740 { 3741 uint32_t VerticalScaleFactorForGolden : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for GOLDEN 3742 uint32_t HorizontalScaleFactorForGolden : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for GOLDEN 3743 }; 3744 uint32_t Value; 3745 } DW5; 3746 union 3747 { 3748 struct 3749 { 3750 uint32_t VerticalScaleFactorForAltref : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for ALTREF 3751 uint32_t HorizontalScaleFactorForAltref : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for ALTREF 3752 }; 3753 uint32_t Value; 3754 } DW6; 3755 union 3756 { 3757 struct 3758 { 3759 uint32_t LastFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Last Frame Width In Pixels Minus 1 3760 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3761 uint32_t LastFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Last Frame Hieght In Pixels Minus 1 3762 uint32_t Reserved254 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3763 }; 3764 uint32_t Value; 3765 } DW7; 3766 union 3767 { 3768 struct 3769 { 3770 uint32_t GoldenFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Golden Frame Width In Pixels Minus 1 3771 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3772 uint32_t GoldenFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Golden Frame Hieght In Pixels Minus 1 3773 uint32_t Reserved286 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3774 }; 3775 uint32_t Value; 3776 } DW8; 3777 union 3778 { 3779 struct 3780 { 3781 uint32_t AltrefFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Altref Frame Width In Pixels Minus 1 3782 uint32_t Reserved302 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3783 uint32_t AltrefFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Altref Frame Hieght In Pixels Minus 1 3784 uint32_t Reserved318 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3785 }; 3786 uint32_t Value; 3787 } DW9; 3788 union 3789 { 3790 struct 3791 { 3792 uint32_t UncompressedHeaderLengthInBytes70 : __CODEGEN_BITFIELD( 0, 7) ; //!< Uncompressed Header Length in Bytes [7:0] 3793 uint32_t Reserved328 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 3794 uint32_t FirstPartitionSizeInBytes150 : __CODEGEN_BITFIELD(16, 31) ; //!< First Partition Size in Bytes [15:0] 3795 }; 3796 uint32_t Value; 3797 } DW10; 3798 union 3799 { 3800 struct 3801 { 3802 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 3803 uint32_t MotionCompScalingEnableBit : __CODEGEN_BITFIELD( 1, 1) ; //!< MOTION_COMP_SCALING_ENABLE_BIT 3804 uint32_t Reserved354 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 3805 }; 3806 uint32_t Value; 3807 } DW11; 3808 union 3809 { 3810 struct 3811 { 3812 uint32_t Reserved384 ; //!< Reserved 3813 }; 3814 uint32_t Value; 3815 } DW12; 3816 union 3817 { 3818 struct 3819 { 3820 uint32_t CompressedHeaderBinCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Compressed header BIN count 3821 uint32_t BaseQIndexSameAsLumaAc : __CODEGEN_BITFIELD(16, 23) ; //!< Base Q Index (Same as Luma AC) 3822 uint32_t TailInsertionEnable : __CODEGEN_BITFIELD(24, 24) ; //!< Tail Insertion Enable 3823 uint32_t HeaderInsertionEnable : __CODEGEN_BITFIELD(25, 25) ; //!< Header Insertion Enable 3824 uint32_t Reserved442 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 3825 }; 3826 uint32_t Value; 3827 } DW13; 3828 union 3829 { 3830 struct 3831 { 3832 uint32_t ChromaacQindexdelta : __CODEGEN_BITFIELD( 0, 4) ; //!< ChromaAC_QindexDelta 3833 uint32_t Reserved453 : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserved 3834 uint32_t ChromadcQindexdelta : __CODEGEN_BITFIELD( 8, 12) ; //!< ChromaDC_QindexDelta 3835 uint32_t Reserved461 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 3836 uint32_t LumaDcQIndexDelta : __CODEGEN_BITFIELD(16, 20) ; //!< Luma DC Q Index Delta 3837 uint32_t Reserved469 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 3838 }; 3839 uint32_t Value; 3840 } DW14; 3841 union 3842 { 3843 struct 3844 { 3845 uint32_t LfRefDelta0 : __CODEGEN_BITFIELD( 0, 6) ; //!< LF_ref_delta0 3846 uint32_t Reserved487 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3847 uint32_t LfRefDelta1 : __CODEGEN_BITFIELD( 8, 14) ; //!< LF_ref_delta1 3848 uint32_t Reserved495 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 3849 uint32_t LfRefDelta2 : __CODEGEN_BITFIELD(16, 22) ; //!< LF_ref_delta2 3850 uint32_t Reserved503 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 3851 uint32_t LfRefDelta3 : __CODEGEN_BITFIELD(24, 30) ; //!< LF_ref_delta3 3852 uint32_t Reserved511 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 3853 }; 3854 uint32_t Value; 3855 } DW15; 3856 union 3857 { 3858 struct 3859 { 3860 uint32_t LfModeDelta0 : __CODEGEN_BITFIELD( 0, 6) ; //!< LF Mode Delta 0 3861 uint32_t Reserved519 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3862 uint32_t LfModeDelta1 : __CODEGEN_BITFIELD( 8, 14) ; //!< LF Mode Delta 1 3863 uint32_t Reserved527 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 3864 }; 3865 uint32_t Value; 3866 } DW16; 3867 union 3868 { 3869 struct 3870 { 3871 uint32_t Bitoffsetforlfrefdelta : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForLFRefDelta 3872 uint32_t Bitoffsetforlfmodedelta : __CODEGEN_BITFIELD(16, 31) ; //!< BitOffsetForLFModeDelta 3873 }; 3874 uint32_t Value; 3875 } DW17; 3876 union 3877 { 3878 struct 3879 { 3880 uint32_t Bitoffsetforqindex : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForQindex 3881 uint32_t Bitoffsetforlflevel : __CODEGEN_BITFIELD(16, 31) ; //!< BitOffsetForLFLevel 3882 }; 3883 uint32_t Value; 3884 } DW18; 3885 union 3886 { 3887 struct 3888 { 3889 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 3890 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NONFIRSTPASSFLAG 3891 uint32_t VdencPakOnlyPass : __CODEGEN_BITFIELD(17, 17) ; //!< VDENC PAK_ONLY PASS 3892 uint32_t Reserved626 : __CODEGEN_BITFIELD(18, 24) ; //!< Reserved 3893 uint32_t FrameszoverstatusenFramebitratemaxreportmask : __CODEGEN_BITFIELD(25, 25) ; //!< FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 3894 uint32_t FrameszunderstatusenFramebitrateminreportmask : __CODEGEN_BITFIELD(26, 26) ; //!< FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 3895 uint32_t Reserved635 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 3896 }; 3897 uint32_t Value; 3898 } DW19; 3899 union 3900 { 3901 struct 3902 { 3903 uint32_t Framebitratemax : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMax 3904 uint32_t Reserved654 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 3905 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT 3906 }; 3907 uint32_t Value; 3908 } DW20; 3909 union 3910 { 3911 struct 3912 { 3913 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 3914 uint32_t Reserved686 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 3915 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMINUNIT 3916 }; 3917 uint32_t Value; 3918 } DW21; 3919 union 3920 { 3921 struct 3922 { 3923 uint64_t Framedeltaqindexmax ; //!< FrameDeltaQindexMax 3924 }; 3925 uint32_t Value[2]; 3926 } DW22_23; 3927 union 3928 { 3929 struct 3930 { 3931 uint32_t Framedeltaqindexmin ; //!< FrameDeltaQindexMin 3932 }; 3933 uint32_t Value; 3934 } DW24; 3935 union 3936 { 3937 struct 3938 { 3939 uint64_t Framedeltalfmax ; //!< FrameDeltaLFMax 3940 }; 3941 uint32_t Value[2]; 3942 } DW25_26; 3943 union 3944 { 3945 struct 3946 { 3947 uint32_t Framedeltalfmin ; //!< FrameDeltaLFMin 3948 }; 3949 uint32_t Value; 3950 } DW27; 3951 union 3952 { 3953 struct 3954 { 3955 uint64_t Framedeltaqindexlfmaxrange ; //!< FrameDeltaQindexLFMaxRange 3956 }; 3957 uint32_t Value[2]; 3958 } DW28_29; 3959 union 3960 { 3961 struct 3962 { 3963 uint32_t Framedeltaqindexlfminrange ; //!< FrameDeltaQindexLFMinRange 3964 }; 3965 uint32_t Value; 3966 } DW30; 3967 union 3968 { 3969 struct 3970 { 3971 uint32_t Minframsize : __CODEGEN_BITFIELD( 0, 15) ; //!< MinFramSize 3972 uint32_t Reserved1008 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 3973 uint32_t Minframesizeunits : __CODEGEN_BITFIELD(30, 31) ; //!< MINFRAMESIZEUNITS 3974 }; 3975 uint32_t Value; 3976 } DW31; 3977 union 3978 { 3979 struct 3980 { 3981 uint32_t Bitoffsetforfirstpartitionsize : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForFirstPartitionSize 3982 uint32_t Reserved1040 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 3983 }; 3984 uint32_t Value; 3985 } DW32; 3986 union 3987 { 3988 struct 3989 { 3990 uint32_t Class0SseThreshold0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Class0_SSE_Threshold0 3991 uint32_t Class0SseThreshold1 : __CODEGEN_BITFIELD(16, 31) ; //!< Class0_SSE_Threshold1 3992 }; 3993 uint32_t Value; 3994 } DW33; 3995 uint32_t SseThresholdsForClass18[8]; //!< SSE thresholds for Class1-8 3996 3997 //! \name Local enumerations 3998 3999 enum MEDIA_INSTRUCTION_COMMAND 4000 { 4001 MEDIA_INSTRUCTION_COMMAND_HCPVP9PICSTATE = 48, //!< No additional details 4002 }; 4003 4004 //! \brief MEDIA_INSTRUCTION_OPCODE 4005 //! \details 4006 //! Codec/Engine Name = HUC = Bh 4007 enum MEDIA_INSTRUCTION_OPCODE 4008 { 4009 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 4010 }; 4011 4012 enum PIPELINE_TYPE 4013 { 4014 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4015 }; 4016 4017 enum COMMAND_TYPE 4018 { 4019 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4020 }; 4021 4022 //! \brief FRAME_TYPE 4023 //! \details 4024 //! Specifies the VP9 frame type 4025 enum FRAME_TYPE 4026 { 4027 FRAME_TYPE_KEYFRAME = 0, //!< No additional details 4028 FRAME_TYPE_INTERFRAME = 1, //!< No additional details 4029 }; 4030 4031 //! \brief ADAPT_PROBABILITIES_FLAG 4032 //! \details 4033 //! Indicates that the probabilities used to decode this frame should be 4034 //! adapted 4035 enum ADAPT_PROBABILITIES_FLAG 4036 { 4037 ADAPT_PROBABILITIES_FLAG_0DONOTADAPT_ERRORRESILIENTORFRAMEPARALLELMODEARESET = 0, //!< No additional details 4038 ADAPT_PROBABILITIES_FLAG_1ADAPT_NOTERRORRESILIENTANDNOTFRAMEPARALLELMODE = 1, //!< No additional details 4039 }; 4040 4041 //! \brief ALLOW_HI_PRECISION_MV 4042 //! \details 4043 //! Indicate high precision mode for Motion Vector prediction 4044 enum ALLOW_HI_PRECISION_MV 4045 { 4046 ALLOW_HI_PRECISION_MV_NORMALMODE = 0, //!< No additional details 4047 ALLOW_HI_PRECISION_MV_HIGHPRECISIONMODE = 1, //!< No additional details 4048 }; 4049 4050 //! \brief MCOMP_FILTER_TYPE 4051 //! \details 4052 //! Indicate Motion Compensation Filter type. 4053 enum MCOMP_FILTER_TYPE 4054 { 4055 MCOMP_FILTER_TYPE_EIGHT_TAP = 0, //!< No additional details 4056 MCOMP_FILTER_TYPE_EIGHT_TAP_SMOOTH = 1, //!< No additional details 4057 MCOMP_FILTER_TYPE_EIGHT_TAP_SHARP = 2, //!< No additional details 4058 MCOMP_FILTER_TYPE_BILINEAR = 3, //!< No additional details 4059 MCOMP_FILTER_TYPE_SWITCHABLE = 4, //!< No additional details 4060 }; 4061 4062 //! \brief HYBRID_PREDICTION_MODE 4063 //! \details 4064 //! Indicates if comp_pred_mode is hybrid 4065 enum HYBRID_PREDICTION_MODE 4066 { 4067 HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERDOESNOTPACKCOMPPREDMODEINTERPREDCOMPINPAKOBJINTOBITSTREAM = 0, //!< No additional details 4068 HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERPACKSCOMPPREDMODEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER = 1, //!< No additional details 4069 }; 4070 4071 //! \brief SELECTABLE_TX_MODE 4072 //! \details 4073 //! Indicates if tx_mode is selectable 4074 enum SELECTABLE_TX_MODE 4075 { 4076 SELECTABLE_TX_MODE_ENCODERDOESNOTPACKTUSIZEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER = 0, //!< No additional details 4077 SELECTABLE_TX_MODE_ENCODERPACKSTUSIZEINTOBITSTREAM = 1, //!< No additional details 4078 }; 4079 4080 //! \brief LAST_FRAME_TYPE 4081 //! \details 4082 //! <p>It indicates the frame type of previous frame (Key or Non-Key 4083 //! Frame)</p> 4084 enum LAST_FRAME_TYPE 4085 { 4086 LAST_FRAME_TYPE_KEYFRAME = 0, //!< No additional details 4087 LAST_FRAME_TYPE_NONKEYFRAME = 1, //!< No additional details 4088 }; 4089 4090 //! \brief REFRESH_FRAME_CONTEXT 4091 //! \details 4092 //! <p>Indicates if Frame Context should be refresh. This bit should come 4093 //! from Uncompressed header</p> 4094 enum REFRESH_FRAME_CONTEXT 4095 { 4096 REFRESH_FRAME_CONTEXT_DISABLE = 0, //!< No additional details 4097 REFRESH_FRAME_CONTEXT_ENABLE = 1, //!< No additional details 4098 }; 4099 4100 //! \brief ERROR_RESILIENT_MODE 4101 //! \details 4102 //! <p>Indicates if error resilient mode is enabled. This bit should come 4103 //! from Uncompressed header.When error resilient is 1, Frame Parallel 4104 //! Decoding Mode will be 1, and Refresh Frame Context will be 0.When error 4105 //! resilient is 0, Frame Parallel Decoding Mode and Refresh Frame Context 4106 //! read from bit stream.Together with Frame Parallel Decoding mode, they 4107 //! decide the value of AdaptProbabilityFlag.</p> 4108 enum ERROR_RESILIENT_MODE 4109 { 4110 ERROR_RESILIENT_MODE_DISABLE = 0, //!< No additional details 4111 ERROR_RESILIENT_MODE_ENABLE = 1, //!< No additional details 4112 }; 4113 4114 //! \brief FRAME_PARALLEL_DECODING_MODE 4115 //! \details 4116 //! <p>Indicates if parallel decoding mode is enabled. This bit should come 4117 //! from Uncompressed header. Together with Error Resilient mode, they 4118 //! decide the value of AdaptProbabilityFlag.</p> 4119 enum FRAME_PARALLEL_DECODING_MODE 4120 { 4121 FRAME_PARALLEL_DECODING_MODE_DISABLE = 0, //!< No additional details 4122 FRAME_PARALLEL_DECODING_MODE_ENABLE = 1, //!< No additional details 4123 }; 4124 4125 //! \brief SEGMENTATION_ENABLED 4126 //! \details 4127 //! Indicate if segementation is enabled or not 4128 enum SEGMENTATION_ENABLED 4129 { 4130 SEGMENTATION_ENABLED_ALLBLOCKSAREIMPLIEDTOBELONGTOSEGMENT0 = 0, //!< No additional details 4131 SEGMENTATION_ENABLED_SEGIDDETERMINATIONDEPENDSONSEGMENTATIONUPDATEMAPSETTING = 1, //!< No additional details 4132 }; 4133 4134 //! \brief SEGMENTATION_UPDATE_MAP 4135 //! \details 4136 //! Indicates how hardware determines segmentation ID 4137 enum SEGMENTATION_UPDATE_MAP 4138 { 4139 SEGMENTATION_UPDATE_MAP_UNNAMED0 = 0, //!< Intra block: segment ID is zero Inter block: get segment ID from previous frame (streamIN) 4140 SEGMENTATION_UPDATE_MAP_UNNAMED1 = 1, //!< Intra block: decode segment ID from bitstream. Inter block: determins from segmentation_temporal_update setting 4141 }; 4142 4143 //! \brief SEGMENTATION_TEMPORAL_UPDATE 4144 //! \details 4145 //! Indicates whether segID is decoding from bitstream or predicted from 4146 //! previous frame. 4147 enum SEGMENTATION_TEMPORAL_UPDATE 4148 { 4149 SEGMENTATION_TEMPORAL_UPDATE_DECODESEGIDFROMBITSTREAM = 0, //!< No additional details 4150 SEGMENTATION_TEMPORAL_UPDATE_GETSEGIDEITHERFROMBITSTREAMORFROMPREVIOUSFRAME = 1, //!< No additional details 4151 }; 4152 4153 //! \brief LOSSLESS_MODE 4154 //! \details 4155 //! This bitSet to indicate lossless coding mode. 4156 enum LOSSLESS_MODE 4157 { 4158 LOSSLESS_MODE_NORMALMODE = 0, //!< No additional details 4159 LOSSLESS_MODE_LOLESSMODE = 1, //!< No additional details 4160 }; 4161 4162 //! \brief SEGMENT_ID_STREAMOUT_ENABLE 4163 //! \details 4164 //! Indicates SegmentID of current frame needs to be streamOut for next 4165 //! frame 4166 enum SEGMENT_ID_STREAMOUT_ENABLE 4167 { 4168 SEGMENT_ID_STREAMOUT_ENABLE_DISABLE = 0, //!< No additional details 4169 SEGMENT_ID_STREAMOUT_ENABLE_ENABLE = 1, //!< No additional details 4170 }; 4171 4172 //! \brief SEGMENT_ID_STREAMIN_ENABLE 4173 //! \details 4174 //! Indicates SegmentID from previous frame needs to be streamIn for Segment 4175 //! ID prediction 4176 enum SEGMENT_ID_STREAMIN_ENABLE 4177 { 4178 SEGMENT_ID_STREAMIN_ENABLE_DISABLE = 0, //!< No additional details 4179 SEGMENT_ID_STREAMIN_ENABLE_ENABLE = 1, //!< No additional details 4180 }; 4181 4182 //! \brief LOG2_TILE_COLUMN 4183 //! \details 4184 //! This indicates the number of tile rows (log2). 4185 enum LOG2_TILE_COLUMN 4186 { 4187 LOG2_TILE_COLUMN_1TILECOLUMN = 0, //!< No additional details 4188 LOG2_TILE_COLUMN_2TILECOLUMN = 1, //!< No additional details 4189 LOG2_TILE_COLUMN_4TILECOLUMN = 2, //!< No additional details 4190 LOG2_TILE_COLUMN_8TILECOLUMN = 3, //!< No additional details 4191 LOG2_TILE_COLUMN_16TILECOLUMN = 4, //!< No additional details 4192 LOG2_TILE_COLUMN_32TILECOLUMN = 5, //!< No additional details 4193 LOG2_TILE_COLUMN_64TILECOLUMN = 6, //!< No additional details 4194 }; 4195 4196 //! \brief LOG2_TILE_ROW 4197 //! \details 4198 //! This indicates the number of tile rows (log2). 4199 enum LOG2_TILE_ROW 4200 { 4201 LOG2_TILE_ROW_1TILEROW = 0, //!< No additional details 4202 LOG2_TILE_ROW_2TILEROW = 1, //!< No additional details 4203 LOG2_TILE_ROW_4TILEROW = 2, //!< No additional details 4204 }; 4205 4206 //! \brief CHROMA_SAMPLING_FORMAT 4207 //! \details 4208 //! This indicates the chroma sampling format of the bitstream 4209 enum CHROMA_SAMPLING_FORMAT 4210 { 4211 CHROMA_SAMPLING_FORMAT_FORMAT420 = 0, //!< No additional details 4212 CHROMA_SAMPLING_FORMAT_FORMAT444 = 2, //!< No additional details 4213 }; 4214 4215 //! \brief BITDEPTHMINUS8 4216 //! \details 4217 //! This indicates the bitdepth (minus 8) of the pixels 4218 enum BITDEPTHMINUS8 4219 { 4220 BITDEPTHMINUS8_BITDEPTH8 = 0, //!< No additional details 4221 BITDEPTHMINUS8_BITDEPTH10 = 2, //!< No additional details 4222 BITDEPTHMINUS8_BITDEPTH12 = 4, //!< No additional details 4223 }; 4224 4225 //! \brief PROFILE_LEVEL 4226 //! \details 4227 //! This indicates VP9 Profile level from bitstream 4228 enum PROFILE_LEVEL 4229 { 4230 PROFILE_LEVEL_PROFILE0 = 0, //!< Profile 0 only supports 8 bit 420 only 4231 PROFILE_LEVEL_PROFILE1 = 1, //!< Profile 1 only supports 8 bit 444 only 4232 PROFILE_LEVEL_PROFILE2 = 2, //!< Profile 2 only supports 10 bits 420 only 4233 PROFILE_LEVEL_PROFILE3 = 3, //!< Profile 3 only supports 10-bit 444 only 4234 }; 4235 4236 //! \brief MOTION_COMP_SCALING_ENABLE_BIT 4237 //! \details 4238 //! This bit must be set to "1" 4239 enum MOTION_COMP_SCALING_ENABLE_BIT 4240 { 4241 MOTION_COMP_SCALING_ENABLE_BIT_ENABLE = 1, //!< This enables Motion Comp Scaling 4242 }; 4243 4244 //! \brief NONFIRSTPASSFLAG 4245 //! \details 4246 //! This signals the current pass is not the first pass. It will imply 4247 //! designate HW behavior. 4248 enum NONFIRSTPASSFLAG 4249 { 4250 NONFIRSTPASSFLAG_DISABLE = 0, //!< If it is initial-Pass, this bit is set to 0. 4251 NONFIRSTPASSFLAG_ENABLE = 1, //!< For subsequent passes, this bit is set to 1. 4252 }; 4253 4254 //! \brief FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 4255 //! \details 4256 //! This is a mask bit controlling if the condition of frame level bit count 4257 //! exceeds FrameBitRateMax. 4258 enum FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 4259 { 4260 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit 1 of HCP_VP9_IMAGE_STATUS control register. 4261 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< Set bit 1 of HCP_VP9_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit Rate Maximum limit. 4262 }; 4263 4264 //! \brief FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 4265 //! \details 4266 //! This is a mask bit controlling if the condition of frame level bit count 4267 //! is less than FrameBitRateMin. 4268 enum FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 4269 { 4270 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit 2 (Frame Bit Count Violate -- under run) of HCP_VP9_IMAGE_STATUS control register. 4271 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< Set bit 2 (Frame Bit Count Violate -- under run) of HCP_VP9_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit Rate Minimum limit. 4272 }; 4273 4274 //! \brief FRAMEBITRATEMAXUNIT 4275 //! \details 4276 //! This field is the Frame Bitrate Maximum Limit Units. 4277 enum FRAMEBITRATEMAXUNIT 4278 { 4279 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< 32byte unit 4280 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< 4Kbyte unit 4281 }; 4282 4283 //! \brief FRAMEBITRATEMINUNIT 4284 //! \details 4285 //! This field is the Frame Bitrate Maximum Limit Units. 4286 enum FRAMEBITRATEMINUNIT 4287 { 4288 FRAMEBITRATEMINUNIT_BYTE = 0, //!< 32byte unit 4289 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< 4Kbyte unit 4290 }; 4291 4292 //! \brief MINFRAMESIZEUNITS 4293 //! \details 4294 //! This field is the Minimum Frame Size Units 4295 enum MINFRAMESIZEUNITS 4296 { 4297 MINFRAMESIZEUNITS_4KB = 0, //!< Minimum Frame Size is in 4Kbytes. 4298 MINFRAMESIZEUNITS_16KB = 1, //!< Minimum Frame Size is in 4Kbytes. 4299 MINFRAMESIZEUNITS_COMAPTIBILITYMODE = 2, //!< No additional details 4300 MINFRAMESIZEUNITS_6BYTES = 3, //!< No additional details 4301 }; 4302 4303 //! \name Initializations 4304 4305 //! \brief Explicit member initialization function HCP_VP9_PIC_STATE_CMDHCP_VP9_PIC_STATE_CMD4306 HCP_VP9_PIC_STATE_CMD() 4307 { 4308 DW0.Value = 0x73b00028; 4309 //DW0.DwordLength = GetOpLength(dwSize); 4310 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPVP9PICSTATE; 4311 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 4312 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 4313 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4314 4315 DW1.Value = 0x00000000; 4316 4317 DW2.Value = 0x00000000; 4318 //DW2.FrameType = FRAME_TYPE_KEYFRAME; 4319 //DW2.AdaptProbabilitiesFlag = ADAPT_PROBABILITIES_FLAG_0DONOTADAPT_ERRORRESILIENTORFRAMEPARALLELMODEARESET; 4320 //DW2.AllowHiPrecisionMv = ALLOW_HI_PRECISION_MV_NORMALMODE; 4321 //DW2.McompFilterType = MCOMP_FILTER_TYPE_EIGHT_TAP; 4322 //DW2.HybridPredictionMode = HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERDOESNOTPACKCOMPPREDMODEINTERPREDCOMPINPAKOBJINTOBITSTREAM; 4323 //DW2.SelectableTxMode = SELECTABLE_TX_MODE_ENCODERDOESNOTPACKTUSIZEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER; 4324 //DW2.LastFrameType = LAST_FRAME_TYPE_KEYFRAME; 4325 //DW2.RefreshFrameContext = REFRESH_FRAME_CONTEXT_DISABLE; 4326 //DW2.ErrorResilientMode = ERROR_RESILIENT_MODE_DISABLE; 4327 //DW2.FrameParallelDecodingMode = FRAME_PARALLEL_DECODING_MODE_DISABLE; 4328 //DW2.SegmentationEnabled = SEGMENTATION_ENABLED_ALLBLOCKSAREIMPLIEDTOBELONGTOSEGMENT0; 4329 //DW2.SegmentationUpdateMap = SEGMENTATION_UPDATE_MAP_UNNAMED0; 4330 //DW2.SegmentationTemporalUpdate = SEGMENTATION_TEMPORAL_UPDATE_DECODESEGIDFROMBITSTREAM; 4331 //DW2.LosslessMode = LOSSLESS_MODE_NORMALMODE; 4332 //DW2.SegmentIdStreamoutEnable = SEGMENT_ID_STREAMOUT_ENABLE_DISABLE; 4333 //DW2.SegmentIdStreaminEnable = SEGMENT_ID_STREAMIN_ENABLE_DISABLE; 4334 4335 DW3.Value = 0x00000000; 4336 //DW3.Log2TileColumn = LOG2_TILE_COLUMN_1TILECOLUMN; 4337 //DW3.Log2TileRow = LOG2_TILE_ROW_1TILEROW; 4338 //DW3.ChromaSamplingFormat = CHROMA_SAMPLING_FORMAT_FORMAT420; 4339 //DW3.Bitdepthminus8 = BITDEPTHMINUS8_BITDEPTH8; 4340 //DW3.ProfileLevel = PROFILE_LEVEL_PROFILE0; 4341 4342 DW4.Value = 0x00000000; 4343 4344 DW5.Value = 0x00000000; 4345 4346 DW6.Value = 0x00000000; 4347 4348 DW7.Value = 0x00000000; 4349 4350 DW8.Value = 0x00000000; 4351 4352 DW9.Value = 0x00000000; 4353 4354 DW10.Value = 0x00000000; 4355 4356 DW11.Value = 0x00000002; 4357 //DW11.MotionCompScalingEnableBit = MOTION_COMP_SCALING_ENABLE_BIT_ENABLE; 4358 4359 DW12.Value = 0x00000000; 4360 4361 DW13.Value = 0x00000000; 4362 4363 DW14.Value = 0x00000000; 4364 4365 DW15.Value = 0x00000000; 4366 4367 DW16.Value = 0x00000000; 4368 4369 DW17.Value = 0x00000000; 4370 4371 DW18.Value = 0x00000000; 4372 4373 DW19.Value = 0x00000000; 4374 //DW19.Nonfirstpassflag = NONFIRSTPASSFLAG_DISABLE; 4375 //DW19.FrameszoverstatusenFramebitratemaxreportmask = FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE; 4376 //DW19.FrameszunderstatusenFramebitrateminreportmask = FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE; 4377 4378 DW20.Value = 0x00000000; 4379 //DW20.Framebitratemaxunit = FRAMEBITRATEMAXUNIT_BYTE; 4380 4381 DW21.Value = 0x00000000; 4382 //DW21.Framebitrateminunit = FRAMEBITRATEMINUNIT_BYTE; 4383 4384 DW22_23.Value[0] = DW22_23.Value[1] = 0x00000000; 4385 4386 DW24.Value = 0x00000000; 4387 4388 DW25_26.Value[0] = DW25_26.Value[1] = 0x00000000; 4389 4390 DW27.Value = 0x00000000; 4391 4392 DW28_29.Value[0] = DW28_29.Value[1] = 0x00000000; 4393 4394 DW30.Value = 0x00000000; 4395 4396 DW31.Value = 0x00000000; 4397 //DW31.Minframesizeunits = MINFRAMESIZEUNITS_4KB; 4398 4399 DW32.Value = 0x00000000; 4400 4401 DW33.Value = 0x00000000; 4402 4403 memset(&SseThresholdsForClass18, 0, sizeof(SseThresholdsForClass18)); 4404 } 4405 4406 static const size_t dwSize = 42; 4407 static const size_t byteSize = 168; 4408 }; 4409 4410 //! 4411 //! \brief HEVC_VP9_RDOQ_LAMBDA_FIELDS 4412 //! \details 4413 //! 4414 //! 4415 struct HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD 4416 { 4417 union 4418 { 4419 struct 4420 { 4421 uint32_t Lambdavalue0 : __CODEGEN_BITFIELD( 0, 15) ; //!< LambdaValue0 4422 uint32_t Lambdavalue1 : __CODEGEN_BITFIELD(16, 31) ; //!< LambdaValue1 4423 }; 4424 uint32_t Value; 4425 } DW0; 4426 4427 //! \name Local enumerations 4428 4429 //! \name Initializations 4430 4431 //! \brief Explicit member initialization function HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMDHEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD4432 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD() 4433 { 4434 DW0.Value = 0x00000000; 4435 } 4436 4437 static const size_t dwSize = 1; 4438 static const size_t byteSize = 4; 4439 }; 4440 4441 //! 4442 //! \brief HEVC_VP9_RDOQ_STATE 4443 //! \details 4444 //! 4445 //! 4446 struct HEVC_VP9_RDOQ_STATE_CMD 4447 { 4448 union 4449 { 4450 struct 4451 { 4452 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4453 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4454 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 4455 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 4456 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 4457 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 4458 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4459 }; 4460 uint32_t Value; 4461 } DW0; 4462 union 4463 { 4464 struct 4465 { 4466 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 29) ; //!< Reserved 4467 uint32_t DisableHtqPerformanceFix1 : __CODEGEN_BITFIELD(30, 30) ; //!< Disable HTQ performance fix1 4468 uint32_t DisableHtqPerformanceFix0 : __CODEGEN_BITFIELD(31, 31) ; //!< Disable HTQ performance fix0 4469 }; 4470 uint32_t Value; 4471 } DW1; 4472 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intralumalambda[32]; //!< DW2..33, IntraLumaLambda 4473 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intrachromalambda[32]; //!< DW34..65, IntraChromaLambda 4474 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interlumalambda[32]; //!< DW66..97, InterLumaLambda 4475 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interchromalambda[32]; //!< DW98..129, InterChromaLambda 4476 4477 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intralumalambda12bit[6]; //!< DW130..135, IntraLumaLambda 4478 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intrachromalambda12bit[6]; //!< DW136..141, IntraChromaLambda 4479 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interlumalambda12bit[6]; //!< DW142..147, InterLumaLambda 4480 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interchromalambda12bit[6]; //!< DW148..153, InterChromaLambda 4481 4482 //! \name Local enumerations 4483 4484 enum SUBOPB 4485 { 4486 SUBOPB_UNNAMED8 = 8, //!< No additional details 4487 }; 4488 4489 enum SUBOPA 4490 { 4491 SUBOPA_UNNAMED0 = 0, //!< No additional details 4492 }; 4493 4494 //! \brief OPCODE 4495 //! \details 4496 //! Codec/Engine Name = HCP = 7h 4497 enum OPCODE 4498 { 4499 OPCODE_UNNAMED7 = 7, //!< No additional details 4500 }; 4501 4502 //! \brief PIPELINE 4503 //! \details 4504 //! MFX_COMMON 4505 enum PIPELINE 4506 { 4507 PIPELINE_UNNAMED2 = 2, //!< No additional details 4508 }; 4509 4510 //! \brief COMMAND_TYPE 4511 //! \details 4512 //! PARALLEL_VIDEO_PIPE 4513 enum COMMAND_TYPE 4514 { 4515 COMMAND_TYPE_UNNAMED3 = 3, //!< No additional details 4516 }; 4517 4518 //! \name Initializations 4519 4520 //! \brief Explicit member initialization function HEVC_VP9_RDOQ_STATE_CMDHEVC_VP9_RDOQ_STATE_CMD4521 HEVC_VP9_RDOQ_STATE_CMD() 4522 { 4523 DW0.Value = 0x73880098; 4524 //DW0.DwordLength = GetOpLength(dwSize); 4525 //DW0.Subopb = SUBOPB_UNNAMED8; 4526 //DW0.Subopa = SUBOPA_UNNAMED0; 4527 //DW0.Opcode = OPCODE_UNNAMED7; 4528 //DW0.Pipeline = PIPELINE_UNNAMED2; 4529 //DW0.CommandType = COMMAND_TYPE_UNNAMED3; 4530 4531 DW1.Value = 0x00000000; 4532 } 4533 4534 static const size_t dwSize = 154; 4535 static const size_t byteSize = 616; 4536 }; 4537 4538 //! 4539 //! \brief HCP_TILE_CODING 4540 //! \details 4541 //! This command is used for both HEVC and VP9 codecs 4542 //! 4543 struct HCP_TILE_CODING_CMD 4544 { 4545 union 4546 { 4547 struct 4548 { 4549 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4550 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4551 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 4552 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 4553 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 4554 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4555 }; 4556 uint32_t Value; 4557 } DW0; 4558 union 4559 { 4560 struct 4561 { 4562 uint32_t NumberOfActiveBePipes : __CODEGEN_BITFIELD( 0, 7) ; //!< Number of Active BE Pipes 4563 uint32_t TileRowStoreSelect : __CODEGEN_BITFIELD( 8, 8) ; //!< Tile Row store Select 4564 uint32_t TileColumnStoreSelect : __CODEGEN_BITFIELD( 9, 9) ; //!< Tile Column store Select 4565 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved MBZ 4566 uint32_t NumOfTileColumnsInAFrame : __CODEGEN_BITFIELD(16, 31) ; //!< Num of Tile columns in a Frame 4567 }; 4568 uint32_t Value; 4569 } DW1; 4570 union 4571 { 4572 struct 4573 { 4574 uint32_t TileColumnPosition : __CODEGEN_BITFIELD( 0, 9) ; //!< Tile Column Position 4575 uint32_t NonFirstPassTile : __CODEGEN_BITFIELD(10, 10) ; //!< Non First Pass Tile 4576 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 4577 uint32_t TileRowPosition : __CODEGEN_BITFIELD(16, 25) ; //!< Tile Row Position 4578 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 29) ; //!< Reserved 4579 uint32_t Islasttileofrow : __CODEGEN_BITFIELD(30, 30) ; //!< IsLastTileOfRow 4580 uint32_t Islasttileofcolumn : __CODEGEN_BITFIELD(31, 31) ; //!< IsLastTileOfColumn 4581 }; 4582 uint32_t Value; 4583 } DW2; 4584 union 4585 { 4586 struct 4587 { 4588 uint32_t Tileheightinmincbminus1 : __CODEGEN_BITFIELD( 0, 10) ; //!< TileHeightInMinCbMinus1 4589 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 4590 uint32_t Tilewidthinmincbminus1 : __CODEGEN_BITFIELD(16, 26) ; //!< TileWidthInMinCbMinus1 4591 uint32_t Reserved123 : __CODEGEN_BITFIELD(27, 30) ; //!< Reserved 4592 uint32_t LastpassoftileValidationonly : __CODEGEN_BITFIELD(31, 31) ; //!< LastPassOfTile (ValidationOnly) 4593 }; 4594 uint32_t Value; 4595 } DW3; 4596 union 4597 { 4598 struct 4599 { 4600 uint32_t BitstreamByteOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Bitstream Byte Offset Enable 4601 uint32_t Reserved129 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 4602 uint32_t BitstreamByteOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Bitstream Byte Offset 4603 }; 4604 uint32_t Value; 4605 } DW4; 4606 union 4607 { 4608 struct 4609 { 4610 uint32_t Reserved160 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4611 uint32_t PakFrameStatisticsOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< PAK Frame Statistics Offset 4612 }; 4613 uint32_t Value; 4614 } DW5; 4615 union 4616 { 4617 struct 4618 { 4619 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4620 uint32_t CuLevelStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< CU Level Streamout Offset 4621 }; 4622 uint32_t Value; 4623 } DW6; 4624 union 4625 { 4626 struct 4627 { 4628 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4629 uint32_t SliceSizeStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Slice Size Streamout Offset 4630 }; 4631 uint32_t Value; 4632 } DW7; 4633 union 4634 { 4635 struct 4636 { 4637 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4638 uint32_t CuRecordOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< CU record offset 4639 }; 4640 uint32_t Value; 4641 } DW8; 4642 union 4643 { 4644 struct 4645 { 4646 uint32_t Reserved288 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4647 uint32_t SseRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< SSE RowStore offset 4648 }; 4649 uint32_t Value; 4650 } DW9; 4651 union 4652 { 4653 struct 4654 { 4655 uint32_t Reserved320 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4656 uint32_t SaoRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< SAO RowStore offset 4657 }; 4658 uint32_t Value; 4659 } DW10; 4660 union 4661 { 4662 struct 4663 { 4664 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4665 uint32_t TileSizeStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile Size StreamOut Offset 4666 }; 4667 uint32_t Value; 4668 } DW11; 4669 union 4670 { 4671 struct 4672 { 4673 uint32_t Reserved384 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4674 uint32_t Vp9ProbabilityCounterStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< VP9 Probability Counter Streamout Offset 4675 }; 4676 uint32_t Value; 4677 } DW12; 4678 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilitySynchronizeBufferBaseAddress; //!< DW13..14, HCP Scalability Synchronize Buffer - Base Address 4679 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilitySynchronizeBufferAttributes; //!< DW15, HCP Scalability Synchronize Buffer - Attributes 4680 union 4681 { 4682 struct 4683 { 4684 uint32_t Reserved512 ; //!< Reserved 4685 }; 4686 uint32_t Value; 4687 } DW16; 4688 union 4689 { 4690 struct 4691 { 4692 uint32_t Reserved544 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 4693 uint32_t TileNumber : __CODEGEN_BITFIELD( 8, 13) ; //!< Tile number 4694 uint32_t FrameNumber : __CODEGEN_BITFIELD(14, 17) ; //!< Frame Number 4695 uint32_t Reserved562 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 4696 }; 4697 uint32_t Value; 4698 } DW17; 4699 union 4700 { 4701 struct 4702 { 4703 uint32_t TilemetadataDw1 ; //!< TileMetaData_DW1 4704 }; 4705 uint32_t Value; 4706 } DW18; 4707 union 4708 { 4709 struct 4710 { 4711 uint32_t TilemetadataDw2 ; //!< TileMetaData_DW2 4712 }; 4713 uint32_t Value; 4714 } DW19; 4715 4716 //! \name Local enumerations 4717 4718 enum MEDIA_INSTRUCTION_COMMAND 4719 { 4720 MEDIA_INSTRUCTION_COMMAND_HCPTILECODING = 21, //!< No additional details 4721 }; 4722 4723 enum MEDIA_INSTRUCTION_OPCODE 4724 { 4725 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 4726 }; 4727 4728 enum PIPELINE_TYPE 4729 { 4730 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4731 }; 4732 4733 enum COMMAND_TYPE 4734 { 4735 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4736 }; 4737 4738 //! \name Initializations 4739 4740 //! \brief Explicit member initialization function HCP_TILE_CODING_CMDHCP_TILE_CODING_CMD4741 HCP_TILE_CODING_CMD() 4742 { 4743 DW0.Value = 0x73950012; 4744 //DW0.DwordLength = GetOpLength(dwSize); 4745 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPTILECODING; 4746 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 4747 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 4748 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4749 4750 DW1.Value = 0x00000000; 4751 4752 DW2.Value = 0x00000000; 4753 4754 DW3.Value = 0x00000000; 4755 4756 DW4.Value = 0x00000000; 4757 4758 DW5.Value = 0x00000000; 4759 4760 DW6.Value = 0x00000000; 4761 4762 DW7.Value = 0x00000000; 4763 4764 DW8.Value = 0x00000000; 4765 4766 DW9.Value = 0x00000000; 4767 4768 DW10.Value = 0x00000000; 4769 4770 DW11.Value = 0x00000000; 4771 4772 DW12.Value = 0x00000000; 4773 4774 DW16.Value = 0x00000000; 4775 4776 DW17.Value = 0x00000000; 4777 4778 DW18.Value = 0x00000000; 4779 4780 DW19.Value = 0x00000000; 4781 } 4782 4783 static const size_t dwSize = 20; 4784 static const size_t byteSize = 80; 4785 }; 4786 4787 //! 4788 //! \brief HCP_PALETTE_INITIALIZER_STATE 4789 //! \details 4790 //! The HCP is selected with theMedia Instruction Opcode "7h"for all HCP 4791 //! Commands. Each HCP command has assigned a media instruction command as 4792 //! defined in DWord 0, BitField 22:16. 4793 //! 4794 //! The HCP_PALETTE_INITIALIZER_STATE command loads in the SCC Palette 4795 //! Initilizer Table to the HW. 4796 //! Decoder only command. 4797 //! 4798 //! Dword#2 - 193form a fixed size table for the Palette Initializer Table. 4799 //! Max PaletteInitializer Table is 128entries. Each entry has 3 components 4800 //! (Y, Cb and Cr) for a color. 4801 //! Each component is 16-bits, even though currently only support up to 4802 //! 10-bit SCC extension. The upper (higher bits) 6 bits are set to zero - 4803 //! that is Least Significant Bit alignment. 4804 //! Each entry of thePalette Initializer Table will consume 1.5 Dwords. 4805 //! Every two entries will consume 2 Dwords. Hence, total requires 96 4806 //! Dwords. 4807 //! Dword#2 Bit 31 Cb#0 15:0 Luma#0 15:0 Bit 0 4808 //! Dword#3 Bit 31 Luma#115:0 Cr#015:0 Bit 0 4809 //! Dword#4 Bit 31 Cr#115:0 Cb#115:0 Bit 0 4810 //! Dword#2 correspondsto the entry# 0 of thePalette Initializer Table. 4811 //! Dword#193correspondsto the entry# 127of thePalette Initializer Table. 4812 //! 4813 //! Palette Initialization needs to happen at the beginning of each 4814 //! frame/tiles or start of each independent slice. Palette initialization 4815 //! is not needed at the start of dependent slices (except the start of a 4816 //! new tiles since each tile needs to re-initialize the palette list) and 4817 //! the palette list is inherited from previous slice. 4818 //! The following is the programming restriction: 4819 //! (1) Palette Initialization commandmust be programmedin palette mode at 4820 //! the beginning of each frame and tiles (regardless if the slice 4821 //! isindependent/dependent)and also the start of each independent slices. 4822 //! (2) Palette Initialization command must not be programmed for dependent 4823 //! slices except the dependent slices are start of tiles (first slice in 4824 //! frame must be independent slice). 4825 //! 4826 //! 4827 struct HCP_PALETTE_INITIALIZER_STATE_CMD 4828 { 4829 union 4830 { 4831 struct 4832 { 4833 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4834 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4835 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 4836 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 4837 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 4838 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4839 }; 4840 uint32_t Value; 4841 } DW0; 4842 union 4843 { 4844 struct 4845 { 4846 uint32_t ActivePaletteInitializerTableEntries : __CODEGEN_BITFIELD( 0, 7) ; //!< Active Palette Initializer Table Entries 4847 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 4848 }; 4849 uint32_t Value; 4850 } DW1; 4851 uint32_t First64ColorEntries[96]; //!< First 64 Color Entries 4852 uint32_t Second64ColorEntries[96]; //!< Second 64 Color Entries 4853 4854 //! \name Local enumerations 4855 4856 enum MEDIA_INSTRUCTION_COMMAND 4857 { 4858 MEDIA_INSTRUCTION_COMMAND_HCPPALETTEINITIALIZERSTATE = 9, //!< No additional details 4859 }; 4860 4861 //! \brief MEDIA_INSTRUCTION_OPCODE 4862 //! \details 4863 //! Codec/Engine Name = HCP = 7h 4864 enum MEDIA_INSTRUCTION_OPCODE 4865 { 4866 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 4867 }; 4868 4869 enum PIPELINE_TYPE 4870 { 4871 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4872 }; 4873 4874 enum COMMAND_TYPE 4875 { 4876 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4877 }; 4878 4879 //! \name Initializations 4880 4881 //! \brief Explicit member initialization function HCP_PALETTE_INITIALIZER_STATE_CMDHCP_PALETTE_INITIALIZER_STATE_CMD4882 HCP_PALETTE_INITIALIZER_STATE_CMD() 4883 { 4884 DW0.Value = 0x738900c0; 4885 //DW0.DwordLength = GetOpLength(dwSize); 4886 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPALETTEINITIALIZERSTATE; 4887 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 4888 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 4889 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4890 4891 DW1.Value = 0x00000000; 4892 4893 memset(&First64ColorEntries, 0, sizeof(First64ColorEntries)); 4894 4895 memset(&Second64ColorEntries, 0, sizeof(Second64ColorEntries)); 4896 } 4897 4898 static const size_t dwSize = 194; 4899 static const size_t byteSize = 776; 4900 }; 4901 }; 4902 } // namespace xe_xpm_plus 4903 } // namespace xe_xpm_plus_base 4904 } // namespace hcp 4905 } // namespace vdbox 4906 } // namespace mhw 4907 4908 #pragma pack() 4909 4910 #endif // __MHW_VDBOX_HCP_HWCMD_XE_XPM_PLUS_H__ 4911