1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_vdenc_hwcmd_g9_skl.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g9_skl as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_VDBOX_VDENC_HWCMD_G9_SKL_H__ 29 #define __MHW_VDBOX_VDENC_HWCMD_G9_SKL_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_vdbox_vdenc_g9_skl 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief VDENC_64B_Aligned_Lower_Address 50 //! \details 51 //! 52 //! 53 struct VDENC_64B_Aligned_Lower_Address_CMD 54 { 55 union 56 { 57 //!< DWORD 0 58 struct 59 { 60 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 61 uint32_t Address : __CODEGEN_BITFIELD( 6, 31) ; //!< Address 62 }; 63 uint32_t Value; 64 } DW0; 65 66 //! \name Local enumerations 67 68 //! \name Initializations 69 70 //! \brief Explicit member initialization function 71 VDENC_64B_Aligned_Lower_Address_CMD(); 72 73 static const size_t dwSize = 1; 74 static const size_t byteSize = 4; 75 }; 76 77 //! 78 //! \brief VDENC_64B_Aligned_Upper_Address 79 //! \details 80 //! 81 //! 82 struct VDENC_64B_Aligned_Upper_Address_CMD 83 { 84 union 85 { 86 //!< DWORD 0 87 struct 88 { 89 uint32_t AddressUpperDword : __CODEGEN_BITFIELD( 0, 15) ; //!< Address Upper DWord 90 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 91 }; 92 uint32_t Value; 93 } DW0; 94 95 //! \name Local enumerations 96 97 //! \name Initializations 98 99 //! \brief Explicit member initialization function 100 VDENC_64B_Aligned_Upper_Address_CMD(); 101 102 static const size_t dwSize = 1; 103 static const size_t byteSize = 4; 104 }; 105 106 //! 107 //! \brief VDENC_Surface_Control_Bits 108 //! \details 109 //! 110 //! 111 struct VDENC_Surface_Control_Bits_CMD 112 { 113 union 114 { 115 //!< DWORD 0 116 struct 117 { 118 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Index to Memory Object Control State (MOCS) Tables: 119 uint32_t ArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< ARBITRATION_PRIORITY_CONTROL 120 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< MEMORY_COMPRESSION_ENABLE 121 uint32_t MemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< MEMORY_COMPRESSION_MODE 122 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 123 uint32_t CacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< CACHE_SELECT 124 uint32_t TiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< TILED_RESOURCE_MODE 125 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 126 }; 127 uint32_t Value; 128 } DW0; 129 130 //! \name Local enumerations 131 132 //! \brief ARBITRATION_PRIORITY_CONTROL 133 //! \details 134 //! This field controls the priority of arbitration used in the GAC/GAM 135 //! pipeline for this surface. 136 enum ARBITRATION_PRIORITY_CONTROL 137 { 138 ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 139 ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 140 ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 141 ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 142 }; 143 144 //! \brief MEMORY_COMPRESSION_ENABLE 145 //! \details 146 //! Memory compression will be attempted for this surface. 147 enum MEMORY_COMPRESSION_ENABLE 148 { 149 MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 150 MEMORY_COMPRESSION_ENABLE_ENABLE = 1, //!< No additional details 151 }; 152 153 //! \brief MEMORY_COMPRESSION_MODE 154 //! \details 155 //! Distinguishes Vertical from Horizontal compression. Please refer to 156 //! vol1a <b>Memory Data</b>. 157 enum MEMORY_COMPRESSION_MODE 158 { 159 MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 160 MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 161 }; 162 163 //! \brief CACHE_SELECT 164 //! \details 165 //! This field controls if the Row Store is going to store inside Media 166 //! Cache (rowstore cache) or to LLC. 167 enum CACHE_SELECT 168 { 169 CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 170 CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 171 }; 172 173 //! \brief TILED_RESOURCE_MODE 174 //! \details 175 //! <b>For Media Surfaces</b>: This field specifies the tiled resource mode. 176 enum TILED_RESOURCE_MODE 177 { 178 TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource. 179 TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 180 TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 181 }; 182 183 //! \name Initializations 184 185 //! \brief Explicit member initialization function 186 VDENC_Surface_Control_Bits_CMD(); 187 188 static const size_t dwSize = 1; 189 static const size_t byteSize = 4; 190 }; 191 192 //! 193 //! \brief VDENC_Sub_Mb_Pred_Mode 194 //! \details 195 //! 196 //! 197 struct VDENC_Sub_Mb_Pred_Mode_CMD 198 { 199 union 200 { 201 //!< WORD 0 202 struct 203 { 204 uint8_t Submbpredmode0 : __CODEGEN_BITFIELD( 0, 1) ; //!< SubMbPredMode[0] 205 uint8_t Submbpredmode1 : __CODEGEN_BITFIELD( 2, 3) ; //!< SubMbPredMode[1] 206 uint8_t Submbpredmode2 : __CODEGEN_BITFIELD( 4, 5) ; //!< SubMbPredMode[2] 207 uint8_t Submbpredmode3 : __CODEGEN_BITFIELD( 6, 7) ; //!< SubMbPredMode[3] 208 }; 209 uint8_t Value; 210 } DW0; 211 212 //! \name Local enumerations 213 214 //! \name Initializations 215 216 //! \brief Explicit member initialization function 217 VDENC_Sub_Mb_Pred_Mode_CMD(); 218 219 static const size_t dwSize = 0; 220 static const size_t byteSize = 1; 221 }; 222 223 //! 224 //! \brief VDENC_Block_8x8_4 225 //! \details 226 //! 227 //! 228 struct VDENC_Block_8x8_4_CMD 229 { 230 union 231 { 232 //!< WORD 0 233 struct 234 { 235 uint16_t Block8X80 : __CODEGEN_BITFIELD( 0, 3) ; //!< Block8x8[0] 236 uint16_t Block8X81 : __CODEGEN_BITFIELD( 4, 7) ; //!< Block8x8[1] 237 uint16_t Block8X82 : __CODEGEN_BITFIELD( 8, 11) ; //!< Block8x8[2] 238 uint16_t Block8X83 : __CODEGEN_BITFIELD(12, 15) ; //!< Block8x8[3] 239 }; 240 uint16_t Value; 241 } DW0; 242 243 //! \name Local enumerations 244 245 //! \name Initializations 246 247 //! \brief Explicit member initialization function 248 VDENC_Block_8x8_4_CMD(); 249 250 static const size_t dwSize = 0; 251 static const size_t byteSize = 2; 252 }; 253 254 //! 255 //! \brief VDENC_Delta_MV_XY 256 //! \details 257 //! 258 //! 259 //! Calculates the difference between the actual MV for the Sub Macroblock 260 //! and the predicted MV based on the availability of the neighbors. 261 //! 262 //! This is calculated and populated for Inter frames only. In case of an 263 //! Intra MB in Inter frames, this value should be 0. 264 //! 265 struct VDENC_Delta_MV_XY_CMD 266 { 267 union 268 { 269 //!< DWORD 0 270 struct 271 { 272 uint32_t X0 : __CODEGEN_BITFIELD( 0, 15) ; //!< X0 273 uint32_t Y0 : __CODEGEN_BITFIELD(16, 31) ; //!< Y0 274 }; 275 uint32_t Value; 276 } DW0; 277 union 278 { 279 //!< DWORD 1 280 struct 281 { 282 uint32_t X1 : __CODEGEN_BITFIELD( 0, 15) ; //!< X1 283 uint32_t Y1 : __CODEGEN_BITFIELD(16, 31) ; //!< Y1 284 }; 285 uint32_t Value; 286 } DW1; 287 union 288 { 289 //!< DWORD 2 290 struct 291 { 292 uint32_t X2 : __CODEGEN_BITFIELD( 0, 15) ; //!< X2 293 uint32_t Y2 : __CODEGEN_BITFIELD(16, 31) ; //!< Y2 294 }; 295 uint32_t Value; 296 } DW2; 297 union 298 { 299 //!< DWORD 3 300 struct 301 { 302 uint32_t X3 : __CODEGEN_BITFIELD( 0, 15) ; //!< X3 303 uint32_t Y3 : __CODEGEN_BITFIELD(16, 31) ; //!< Y3 304 }; 305 uint32_t Value; 306 } DW3; 307 308 //! \name Local enumerations 309 310 //! \brief X0 311 //! \details 312 enum X0 313 { 314 X0_UNNAMED0 = 0, //!< No additional details 315 }; 316 317 //! \brief Y0 318 //! \details 319 enum Y0 320 { 321 Y0_UNNAMED0 = 0, //!< No additional details 322 }; 323 324 //! \brief X1 325 //! \details 326 enum X1 327 { 328 X1_UNNAMED0 = 0, //!< No additional details 329 }; 330 331 //! \brief Y1 332 //! \details 333 enum Y1 334 { 335 Y1_UNNAMED0 = 0, //!< No additional details 336 }; 337 338 //! \brief X2 339 //! \details 340 //! <table> 341 //! <p>Calculates the x-axis MV for Picture List N for the 342 //! following:</p> 343 //! <tr> 344 //! <th>Mb_type</th> 345 //! <th>PartID</th> 346 //! </tr> 347 //! <tr> 348 //! <td align="center">8x8</td> 349 //! <td align="center">7</td> 350 //! </tr> 351 //! </table> 352 enum X2 353 { 354 X2_UNNAMED0 = 0, //!< No additional details 355 }; 356 357 //! \brief Y2 358 //! \details 359 enum Y2 360 { 361 Y2_UNNAMED0 = 0, //!< No additional details 362 }; 363 364 //! \brief X3 365 //! \details 366 enum X3 367 { 368 X3_UNNAMED0 = 0, //!< No additional details 369 }; 370 371 //! \brief Y3 372 //! \details 373 enum Y3 374 { 375 Y3_UNNAMED0 = 0, //!< No additional details 376 }; 377 378 //! \name Initializations 379 380 //! \brief Explicit member initialization function 381 VDENC_Delta_MV_XY_CMD(); 382 383 static const size_t dwSize = 4; 384 static const size_t byteSize = 16; 385 }; 386 387 //! 388 //! \brief VDENC_Colocated_MV_Picture 389 //! \details 390 //! 391 //! 392 struct VDENC_Colocated_MV_Picture_CMD 393 { 394 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 395 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 396 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 397 398 //! \name Local enumerations 399 400 //! \name Initializations 401 402 //! \brief Explicit member initialization function 403 VDENC_Colocated_MV_Picture_CMD(); 404 405 static const size_t dwSize = 3; 406 static const size_t byteSize = 12; 407 }; 408 409 //! 410 //! \brief VDENC_Down_Scaled_Reference_Picture 411 //! \details 412 //! 413 //! 414 struct VDENC_Down_Scaled_Reference_Picture_CMD 415 { 416 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 417 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 418 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 419 420 //! \name Local enumerations 421 422 //! \name Initializations 423 424 //! \brief Explicit member initialization function 425 VDENC_Down_Scaled_Reference_Picture_CMD(); 426 427 static const size_t dwSize = 3; 428 static const size_t byteSize = 12; 429 }; 430 431 //! 432 //! \brief VDENC_FRAME_BASED_STATISTICS_STREAMOUT 433 //! \details 434 //! 435 //! 436 struct VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD 437 { 438 union 439 { 440 //!< DWORD 0 441 struct 442 { 443 uint32_t SumSadHaarForBestMbChoice ; //!< Sum sad\haar for best MB choice 444 }; 445 uint32_t Value; 446 } DW0; 447 union 448 { 449 //!< DWORD 1 450 struct 451 { 452 uint32_t IntraIso16X16MbCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra iso 16x16 MB count 453 uint32_t IntraMbCount : __CODEGEN_BITFIELD(16, 31) ; //!< Intra MB count 454 }; 455 uint32_t Value; 456 } DW1; 457 union 458 { 459 //!< DWORD 2 460 struct 461 { 462 uint32_t IntraIso4X4MbCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra iso 4x4 MB count 463 uint32_t IntraIso8X8MbCount : __CODEGEN_BITFIELD(16, 31) ; //!< Intra iso 8x8 MB count 464 }; 465 uint32_t Value; 466 } DW2; 467 union 468 { 469 //!< DWORD 3 470 struct 471 { 472 uint32_t SegmentMapCount0 : __CODEGEN_BITFIELD( 0, 15) ; //!< segment map count 0 473 uint32_t SegmentMapCount1 : __CODEGEN_BITFIELD(16, 31) ; //!< segment map count 1 474 }; 475 uint32_t Value; 476 } DW3; 477 union 478 { 479 //!< DWORD 4 480 struct 481 { 482 uint32_t SegmentMapCount2 : __CODEGEN_BITFIELD( 0, 15) ; //!< segment map count 2 483 uint32_t SegmentMapCount3 : __CODEGEN_BITFIELD(16, 31) ; //!< segment map count 3 484 }; 485 uint32_t Value; 486 } DW4; 487 488 uint32_t Reserved160[12]; //!< Reserved 489 490 union 491 { 492 //!< DWORD 17 493 struct 494 { 495 uint32_t SumSadHaarForBestMbChoiceBottomHalfPopulation ; //!< Sum sad\haar for best MB choice bottom half population 496 }; 497 uint32_t Value; 498 } DW17; 499 union 500 { 501 //!< DWORD 18 502 struct 503 { 504 uint32_t SumSadHaarForBestMbChoiceTopHalfPopulation ; //!< Sum sad\haar for best MB choice top half population 505 }; 506 uint32_t Value; 507 } DW18; 508 union 509 { 510 //!< DWORD 19 511 struct 512 { 513 uint32_t SumTopHalfPopulationOccurrences : __CODEGEN_BITFIELD( 0, 15) ; //!< Sum top half population occurrences 514 uint32_t SumBottomHalfPopulationOccurrences : __CODEGEN_BITFIELD(16, 31) ; //!< Sum bottom half population occurrences 515 }; 516 uint32_t Value; 517 } DW19; 518 519 //! \name Local enumerations 520 521 //! \name Initializations 522 523 //! \brief Explicit member initialization function 524 VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD(); 525 526 static const size_t dwSize = 20; 527 static const size_t byteSize = 80; 528 }; 529 530 //! 531 //! \brief VDENC_Mode_StreamOut_Data 532 //! \details 533 //! 534 //! 535 struct VDENC_Mode_StreamOut_Data_CMD 536 { 537 union 538 { 539 //!< DWORD 0 540 struct 541 { 542 uint32_t MbX : __CODEGEN_BITFIELD( 0, 7) ; //!< MB.X 543 uint32_t MbY : __CODEGEN_BITFIELD( 8, 15) ; //!< MB.Y 544 uint32_t MinimalDistortion : __CODEGEN_BITFIELD(16, 31) ; //!< Minimal Distortion 545 }; 546 uint32_t Value; 547 } DW0; 548 union 549 { 550 //!< DWORD 1 551 struct 552 { 553 uint32_t Skiprawdistortion : __CODEGEN_BITFIELD( 0, 15) ; //!< SkipRawDistortion 554 uint32_t Interrawdistortion : __CODEGEN_BITFIELD(16, 31) ; //!< InterRawDistortion 555 }; 556 uint32_t Value; 557 } DW1; 558 union 559 { 560 //!< DWORD 2 561 struct 562 { 563 uint32_t Bestintrarawdistortion : __CODEGEN_BITFIELD( 0, 15) ; //!< BestIntraRawDistortion 564 uint32_t IntermbmodeChromaPredictionMode : __CODEGEN_BITFIELD(16, 17) ; //!< INTERMBMODECHROMA_PREDICTION_MODE 565 uint32_t Intrambmode : __CODEGEN_BITFIELD(18, 19) ; //!< INTRAMBMODE 566 uint32_t Intrambflag : __CODEGEN_BITFIELD(20, 20) ; //!< INTRAMBFLAG 567 uint32_t Lastmbflag : __CODEGEN_BITFIELD(21, 21) ; //!< LASTMBFLAG 568 uint32_t CoefficientClampOccurred : __CODEGEN_BITFIELD(22, 22) ; //!< Coefficient Clamp Occurred 569 uint32_t ConformanceViolation : __CODEGEN_BITFIELD(23, 23) ; //!< Conformance Violation 570 uint32_t Submbpredmode : __CODEGEN_BITFIELD(24, 31) ; //!< SubMbPredMode 571 }; 572 uint32_t Value; 573 } DW2; 574 union 575 { 576 //!< DWORD 3 577 struct 578 { 579 uint32_t Lumaintramode0 : __CODEGEN_BITFIELD( 0, 15) ; //!< LumaIntraMode[0] 580 uint32_t Lumaintramode1 : __CODEGEN_BITFIELD(16, 31) ; //!< LumaIntraMode[1] 581 }; 582 uint32_t Value; 583 } DW3; 584 union 585 { 586 //!< DWORD 4 587 struct 588 { 589 uint32_t Lumaintramode2 : __CODEGEN_BITFIELD( 0, 15) ; //!< LumaIntraMode[2] 590 uint32_t Lumaintramode3 : __CODEGEN_BITFIELD(16, 31) ; //!< LumaIntraMode[3] 591 }; 592 uint32_t Value; 593 } DW4; 594 VDENC_Delta_MV_XY_CMD DeltaMv0 ; //!< Delta MV0 595 VDENC_Delta_MV_XY_CMD DeltaMv1 ; //!< Delta MV1 596 union 597 { 598 //!< DWORD 13 599 struct 600 { 601 uint32_t FwdRefids : __CODEGEN_BITFIELD( 0, 15) ; //!< FWD REFIDs 602 uint32_t BwdRefids : __CODEGEN_BITFIELD(16, 31) ; //!< BWD REFIDs 603 }; 604 uint32_t Value; 605 } DW13; 606 union 607 { 608 //!< DWORD 14 609 struct 610 { 611 uint32_t QpY : __CODEGEN_BITFIELD( 0, 5) ; //!< QP_y 612 uint32_t MbBitCount : __CODEGEN_BITFIELD( 6, 18) ; //!< MB_Bit_Count 613 uint32_t MbHeaderCount : __CODEGEN_BITFIELD(19, 31) ; //!< MB_Header_Count 614 }; 615 uint32_t Value; 616 } DW14; 617 union 618 { 619 //!< DWORD 15 620 struct 621 { 622 uint32_t MbType : __CODEGEN_BITFIELD( 0, 4) ; //!< MB Type 623 uint32_t BlockCbp : __CODEGEN_BITFIELD( 5, 30) ; //!< Block CBP 624 uint32_t Skipmbflag : __CODEGEN_BITFIELD(31, 31) ; //!< SkipMbFlag 625 }; 626 uint32_t Value; 627 } DW15; 628 629 //! \name Local enumerations 630 631 //! \brief INTERMBMODECHROMA_PREDICTION_MODE 632 //! \details 633 //! This field indicates the InterMB Parition type for Inter MB. 634 //! <br>OR</br> 635 //! This field indicates Chroma Prediction Mode for Intra MB. 636 enum INTERMBMODECHROMA_PREDICTION_MODE 637 { 638 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED0 = 0, //!< 16x16 639 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED1 = 1, //!< 16x8 640 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED2 = 2, //!< 8x16 641 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED3 = 3, //!< 8x8 642 }; 643 644 //! \brief INTRAMBMODE 645 //! \details 646 //! This field indicates the Best Intra Partition. 647 enum INTRAMBMODE 648 { 649 INTRAMBMODE_UNNAMED0 = 0, //!< 16x16 650 INTRAMBMODE_UNNAMED1 = 1, //!< 8x8 651 INTRAMBMODE_UNNAMED2 = 2, //!< 4x4 652 }; 653 654 //! \brief INTRAMBFLAG 655 //! \details 656 //! This field specifies whether the current macroblock is an Intra (I) 657 //! macroblock. 658 enum INTRAMBFLAG 659 { 660 INTRAMBFLAG_INTER = 0, //!< inter macroblock 661 INTRAMBFLAG_INTRA = 1, //!< intra macroblock 662 }; 663 664 enum LASTMBFLAG 665 { 666 LASTMBFLAG_NOTLAST = 0, //!< The current MB is not the last MB in the current Slice. 667 LASTMBFLAG_LAST = 1, //!< The current MB is the last MB in the current Slice. 668 }; 669 670 //! \name Initializations 671 672 //! \brief Explicit member initialization function 673 VDENC_Mode_StreamOut_Data_CMD(); 674 675 static const size_t dwSize = 16; 676 static const size_t byteSize = 64; 677 }; 678 679 //! 680 //! \brief VDENC_Original_Uncompressed_Picture 681 //! \details 682 //! 683 //! 684 struct VDENC_Original_Uncompressed_Picture_CMD 685 { 686 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 687 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 688 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 689 690 //! \name Local enumerations 691 692 //! \name Initializations 693 694 //! \brief Explicit member initialization function 695 VDENC_Original_Uncompressed_Picture_CMD(); 696 697 static const size_t dwSize = 3; 698 static const size_t byteSize = 12; 699 }; 700 701 //! 702 //! \brief VDENC_Reference_Picture 703 //! \details 704 //! 705 //! 706 struct VDENC_Reference_Picture_CMD 707 { 708 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 709 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 710 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 711 712 //! \name Local enumerations 713 714 //! \name Initializations 715 716 //! \brief Explicit member initialization function 717 VDENC_Reference_Picture_CMD(); 718 719 static const size_t dwSize = 3; 720 static const size_t byteSize = 12; 721 }; 722 723 //! 724 //! \brief VDENC_Row_Store_Scratch_Buffer_Picture 725 //! \details 726 //! 727 //! 728 struct VDENC_Row_Store_Scratch_Buffer_Picture_CMD 729 { 730 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 731 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 732 VDENC_Surface_Control_Bits_CMD BufferPictureFields ; //!< Buffer Picture Fields 733 734 //! \name Local enumerations 735 736 //! \name Initializations 737 738 //! \brief Explicit member initialization function 739 VDENC_Row_Store_Scratch_Buffer_Picture_CMD(); 740 741 static const size_t dwSize = 3; 742 static const size_t byteSize = 12; 743 }; 744 745 //! 746 //! \brief VDENC_Statistics_Streamout 747 //! \details 748 //! 749 //! 750 struct VDENC_Statistics_Streamout_CMD 751 { 752 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 753 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 754 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 755 756 //! \name Local enumerations 757 758 //! \name Initializations 759 760 //! \brief Explicit member initialization function 761 VDENC_Statistics_Streamout_CMD(); 762 763 static const size_t dwSize = 3; 764 static const size_t byteSize = 12; 765 }; 766 767 //! 768 //! \brief VDENC_Streamin_Data_Picture 769 //! \details 770 //! 771 //! 772 struct VDENC_Streamin_Data_Picture_CMD 773 { 774 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 775 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 776 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 777 778 //! \name Local enumerations 779 780 //! \name Initializations 781 782 //! \brief Explicit member initialization function 783 VDENC_Streamin_Data_Picture_CMD(); 784 785 static const size_t dwSize = 3; 786 static const size_t byteSize = 12; 787 }; 788 789 //! 790 //! \brief VDENC_STREAMIN_STATE 791 //! \details 792 //! 793 //! 794 struct VDENC_STREAMIN_STATE_CMD 795 { 796 union 797 { 798 //!< DWORD 0 799 struct 800 { 801 uint32_t RegionOfInterestRoiSelection : __CODEGEN_BITFIELD( 0, 7) ; //!< Region of Interest (ROI) Selection 802 uint32_t Forceintra : __CODEGEN_BITFIELD( 8, 8) ; //!< FORCEINTRA 803 uint32_t Forceskip : __CODEGEN_BITFIELD( 9, 9) ; //!< FORCESKIP 804 uint32_t Reserved10 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 805 }; 806 uint32_t Value; 807 } DW0; 808 union 809 { 810 //!< DWORD 1 811 struct 812 { 813 uint32_t Qpprimey : __CODEGEN_BITFIELD( 0, 7) ; //!< QPPRIMEY 814 uint32_t Targetsizeinword : __CODEGEN_BITFIELD( 8, 15) ; //!< TargetSizeInWord 815 uint32_t Maxsizeinword : __CODEGEN_BITFIELD(16, 23) ; //!< MaxSizeInWord 816 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 817 }; 818 uint32_t Value; 819 } DW1; 820 union 821 { 822 //!< DWORD 2 823 struct 824 { 825 uint32_t FwdPredictorX : __CODEGEN_BITFIELD( 0, 15) ; //!< Fwd Predictor.X 826 uint32_t FwdPredictorY : __CODEGEN_BITFIELD(16, 31) ; //!< Fwd Predictor.Y 827 }; 828 uint32_t Value; 829 } DW2; 830 union 831 { 832 //!< DWORD 3 833 struct 834 { 835 uint32_t BwdPredictorX : __CODEGEN_BITFIELD( 0, 15) ; //!< Bwd Predictor.X 836 uint32_t BwdPredictorY : __CODEGEN_BITFIELD(16, 31) ; //!< Bwd Predictor.Y 837 }; 838 uint32_t Value; 839 } DW3; 840 union 841 { 842 //!< DWORD 4 843 struct 844 { 845 uint32_t FwdRefid0 : __CODEGEN_BITFIELD( 0, 3) ; //!< Fwd RefID0 846 uint32_t BwdRefid0 : __CODEGEN_BITFIELD( 4, 7) ; //!< Bwd RefID0 847 uint32_t Reserved136 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 848 }; 849 uint32_t Value; 850 } DW4; 851 852 uint32_t Reserved160[11]; //!< Reserved 853 854 //! \name Local enumerations 855 856 //! \brief FORCEINTRA 857 //! \details 858 //! This field specifies whether current macroblock should be coded as an 859 //! intra macroblock. 860 //! It is illegal to enable both ForceSkip and ForceIntra for 861 //! the same macroblock. 862 //! This should be disabled if Rolling-I is enabled in the 863 //! VDEnc Image State. 864 enum FORCEINTRA 865 { 866 FORCEINTRA_DISABLE = 0, //!< VDEnc determined macroblock type 867 FORCEINTRA_ENABLE = 1, //!< Force to be coded as an intra macroblock 868 }; 869 870 //! \brief FORCESKIP 871 //! \details 872 //! This field specifies whether current macroblock should be coded as a 873 //! skipped macroblock. 874 //! It is illegal to enable both ForceSkip and ForceIntra for 875 //! the same macroblock. 876 //! This should be disabled if Rolling-I is enabled in the 877 //! VDEnc Image State. 878 //! It is illegal to enable ForceSkip for I-Frames. 879 enum FORCESKIP 880 { 881 FORCESKIP_DISABLE = 0, //!< VDEnc determined macroblock type 882 FORCESKIP_ENABLE = 1, //!< Force to be coded as a skipped macroblock 883 }; 884 885 //! \brief QPPRIMEY 886 //! \details 887 //! Quantization parameter for Y. 888 enum QPPRIMEY 889 { 890 QPPRIMEY_UNNAMED0 = 0, //!< No additional details 891 QPPRIMEY_UNNAMED51 = 51, //!< No additional details 892 }; 893 894 //! \name Initializations 895 896 //! \brief Explicit member initialization function 897 VDENC_STREAMIN_STATE_CMD(); 898 899 static const size_t dwSize = 16; 900 static const size_t byteSize = 64; 901 }; 902 903 //! 904 //! \brief VDENC_Surface_State_Fields 905 //! \details 906 //! 907 //! 908 struct VDENC_Surface_State_Fields_CMD 909 { 910 union 911 { 912 //!< DWORD 0 913 struct 914 { 915 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< Cr(V)/Cb(U) Pixel Offset V Direction 916 uint32_t SurfaceFormatByteSwizzle : __CODEGEN_BITFIELD( 2, 2) ; //!< Surface Format Byte Swizzle 917 uint32_t ColorSpaceSelection : __CODEGEN_BITFIELD( 3, 3) ; //!< Color space selection 918 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 919 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 920 }; 921 uint32_t Value; 922 } DW0; 923 union 924 { 925 //!< DWORD 1 926 struct 927 { 928 uint32_t TileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< TILE_WALK 929 uint32_t TiledSurface : __CODEGEN_BITFIELD( 1, 1) ; //!< TILED_SURFACE 930 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< HALF_PITCH_FOR_CHROMA 931 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Surface Pitch 932 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 26) ; //!< Reserved 933 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(27, 27) ; //!< INTERLEAVE_CHROMA_ 934 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(28, 31) ; //!< SURFACE_FORMAT 935 }; 936 uint32_t Value; 937 } DW1; 938 union 939 { 940 //!< DWORD 2 941 struct 942 { 943 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) 944 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 945 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 30) ; //!< X Offset for U(Cb) 946 uint32_t Reserved95 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 947 }; 948 uint32_t Value; 949 } DW2; 950 union 951 { 952 //!< DWORD 3 953 struct 954 { 955 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 15) ; //!< Y Offset for V(Cr) 956 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 28) ; //!< X Offset for V(Cr) 957 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 958 }; 959 uint32_t Value; 960 } DW3; 961 962 //! \name Local enumerations 963 964 //! \brief TILE_WALK 965 //! \details 966 //! (This field must be set to 1: TILEWALK_YMAJOR.) This field specifies the 967 //! type of memory tiling 968 //! (XMajor or YMajor) employed to tile this surface. See Memory 969 //! Interface Functions for details 970 //! on memory tiling and restrictions.This field is ignored when the 971 //! surface is linear. Internally 972 //! H/W always treats this as set to 1 for all VDEnc usage. 973 enum TILE_WALK 974 { 975 TILE_WALK_XMAJOR = 0, //!< TILEWALK_XMAJOR 976 TILE_WALK_YMAJOR = 1, //!< TILEWALK_YMAJOR 977 }; 978 979 //! \brief TILED_SURFACE 980 //! \details 981 //! (This field must be set to TRUE: Tiled.) This field specifies whether 982 //! the surface is tiled. 983 //! This field is ignored by VDEnc usage. 984 enum TILED_SURFACE 985 { 986 TILED_SURFACE_FALSE = 0, //!< Linear 987 TILED_SURFACE_TRUE = 1, //!< Tiled 988 }; 989 990 //! \brief HALF_PITCH_FOR_CHROMA 991 //! \details 992 //! (This field must be set to Disable.) This field indicates that the 993 //! chroma plane(s) will use a pitch equal 994 //! to half the value specified in the Surface Pitch field. This field 995 //! is only used for PLANAR surface formats. 996 //! This field is igored by VDEnc (unless we support YV12). 997 enum HALF_PITCH_FOR_CHROMA 998 { 999 HALF_PITCH_FOR_CHROMA_DISABLE = 0, //!< No additional details 1000 HALF_PITCH_FOR_CHROMA_ENABLE = 1, //!< No additional details 1001 }; 1002 1003 //! \brief INTERLEAVE_CHROMA_ 1004 //! \details 1005 //! This field indicates that the chroma fields are interleaved in a single 1006 //! plane rather than stored as 1007 //! two separate planes. This field is only used for PLANAR surface 1008 //! formats. 1009 enum INTERLEAVE_CHROMA_ 1010 { 1011 INTERLEAVE_CHROMA_DISABLE = 0, //!< No additional details 1012 INTERLEAVE_CHROMA_ENABLE = 1, //!< No additional details 1013 }; 1014 1015 //! \brief SURFACE_FORMAT 1016 //! \details 1017 //! Specifies the format of the surface. 1018 enum SURFACE_FORMAT 1019 { 1020 SURFACE_FORMAT_YUV422 = 0, //!< YUYV/YUY2 (8:8:8:8 MSB V0 Y1 U0 Y0) 1021 SURFACE_FORMAT_RGBA4444 = 1, //!< RGBA 32-bit 4:4:4:4 packed (8:8:8:8 MSB-X:B:G:R) 1022 SURFACE_FORMAT_YUV444 = 2, //!< YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-A:Y:U:V) 1023 SURFACE_FORMAT_Y8UNORM = 3, //!< No additional details 1024 SURFACE_FORMAT_PLANAR4208 = 4, //!< (NV12, IMC1,2,3,4, YV12) 1025 }; 1026 1027 //! \name Initializations 1028 1029 //! \brief Explicit member initialization function 1030 VDENC_Surface_State_Fields_CMD(); 1031 1032 static const size_t dwSize = 4; 1033 static const size_t byteSize = 16; 1034 }; 1035 1036 //! 1037 //! \brief VD_PIPELINE_FLUSH 1038 //! \details 1039 //! 1040 //! 1041 struct VD_PIPELINE_FLUSH_CMD 1042 { 1043 union 1044 { 1045 //!< DWORD 0 1046 struct 1047 { 1048 uint32_t DwordCountN : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_COUNT_N 1049 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1050 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1051 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1052 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1053 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1054 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1055 }; 1056 uint32_t Value; 1057 } DW0; 1058 union 1059 { 1060 //!< DWORD 1 1061 struct 1062 { 1063 uint32_t HevcPipelineDone : __CODEGEN_BITFIELD( 0, 0) ; //!< HEVC pipeline Done 1064 uint32_t VdencPipelineDone : __CODEGEN_BITFIELD( 1, 1) ; //!< VD-ENC pipeline Done 1065 uint32_t MflPipelineDone : __CODEGEN_BITFIELD( 2, 2) ; //!< MFL pipeline Done 1066 uint32_t MfxPipelineDone : __CODEGEN_BITFIELD( 3, 3) ; //!< MFX pipeline Done 1067 uint32_t VdCommandMessageParserDone : __CODEGEN_BITFIELD( 4, 4) ; //!< VD command/message parser Done 1068 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 1069 uint32_t HevcPipelineCommandFlush : __CODEGEN_BITFIELD(16, 16) ; //!< HEVC pipeline command flush 1070 uint32_t VdencPipelineCommandFlush : __CODEGEN_BITFIELD(17, 17) ; //!< VD-ENC pipeline command flush 1071 uint32_t MflPipelineCommandFlush : __CODEGEN_BITFIELD(18, 18) ; //!< MFL pipeline command flush 1072 uint32_t MfxPipelineCommandFlush : __CODEGEN_BITFIELD(19, 19) ; //!< MFX pipeline command flush 1073 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 1074 }; 1075 uint32_t Value; 1076 } DW1; 1077 1078 //! \name Local enumerations 1079 1080 //! \brief DWORD_COUNT_N 1081 //! \details 1082 //! Total Length - 2 1083 enum DWORD_COUNT_N 1084 { 1085 DWORD_COUNT_N_EXCLUDESDWORD_0 = 0, //!< No additional details 1086 }; 1087 1088 enum SUBOPCODEB 1089 { 1090 SUBOPCODEB_UNNAMED0 = 0, //!< No additional details 1091 }; 1092 1093 enum SUBOPCODEA 1094 { 1095 SUBOPCODEA_UNNAMED0 = 0, //!< No additional details 1096 }; 1097 1098 enum MEDIA_COMMAND_OPCODE 1099 { 1100 MEDIA_COMMAND_OPCODE_EXTENDEDCOMMAND = 15, //!< No additional details 1101 }; 1102 1103 enum PIPELINE 1104 { 1105 PIPELINE_MEDIA = 2, //!< No additional details 1106 }; 1107 1108 enum COMMAND_TYPE 1109 { 1110 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1111 }; 1112 1113 //! \name Initializations 1114 1115 //! \brief Explicit member initialization function 1116 VD_PIPELINE_FLUSH_CMD(); 1117 1118 static const size_t dwSize = 2; 1119 static const size_t byteSize = 8; 1120 }; 1121 1122 //! 1123 //! \brief VDENC_CONST_QPT_STATE 1124 //! \details 1125 //! This commands provides the tables for frame constants to the VDEnc HW. 1126 //! The specific parameter value is picked by the VDEnc HW based on the 1127 //! frame level QP. The QP Lambda array for costing (motion-vectors and mode 1128 //! costs) has 42 entires. Skip Threshold tables has 27 entries. 7 FTQ 1129 //! thresholds [0-6] are programmed using 4 sets of tables with 27 entires 1130 //! each. 1131 //! 1132 struct VDENC_CONST_QPT_STATE_CMD 1133 { 1134 union 1135 { 1136 //!< DWORD 0 1137 struct 1138 { 1139 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1140 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1141 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1142 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1143 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1144 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1145 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1146 }; 1147 uint32_t Value; 1148 } DW0; 1149 union { 1150 //!< DWORD 1..10 1151 struct { 1152 uint8_t QpLambdaArrayIndex[40]; //!< QP Lambda Array Index[n] 1153 }; 1154 uint32_t Value[10]; 1155 } DW1_10; 1156 union { 1157 //!< DWORD 11 1158 struct { 1159 uint32_t QpLambdaArrayIndex40 : __CODEGEN_BITFIELD(0, 7); 1160 uint32_t QpLambdaArrayIndex41 : __CODEGEN_BITFIELD(8, 15); 1161 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1162 }; 1163 uint32_t Value; 1164 } DW11; 1165 union { 1166 //!< DWORD 12..24 1167 struct { 1168 uint16_t SkipThresholdArrayIndex[26]; //!< Skip Threshold Array Index[n] 1169 }; 1170 uint32_t Value[13]; 1171 } DW12_24; 1172 union { 1173 //!< DWORD 25 1174 struct { 1175 uint32_t SkipThresholdArrayIndex26 : __CODEGEN_BITFIELD(0, 15); 1176 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1177 }; 1178 uint32_t Value; 1179 } DW25; 1180 union { 1181 //!< DWORD 26..38 1182 struct { 1183 uint16_t SicForwardTransformCoeffThresholdMatrix0ArrayIndex[26]; //!< SIC Forward Transform Coeff Threshold Matrix0 Array Index[n] 1184 }; 1185 uint32_t Value[13]; 1186 } DW26_38; 1187 union { 1188 //!< DWORD 39 1189 struct { 1190 uint32_t SicForwardTransformCoeffThresholdMatrix0ArrayIndex26 : __CODEGEN_BITFIELD(0, 15); 1191 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1192 }; 1193 uint32_t Value; 1194 } DW39; 1195 union { 1196 //!< DWORD 40..45 1197 struct { 1198 uint8_t SicForwardTransformCoeffThresholdMatrix135ArrayIndexN[24]; //!< SIC Forward Transform Coeff Threshold Matrix1/3/5 Array Index[n] 1199 }; 1200 uint32_t Value[6]; 1201 } DW40_45; 1202 union { 1203 //!< DWORD 46 1204 struct { 1205 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1206 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1207 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1208 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1209 }; 1210 uint32_t Value; 1211 } DW46; 1212 union { 1213 //!< DWORD 47..52 1214 struct { 1215 uint8_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex[24]; //!< SIC Forward Transform Coeff Threshold Matrix2 Array Index[n] 1216 }; 1217 uint32_t Value[6]; 1218 } DW47_52; 1219 union { 1220 //!< DWORD 53 1221 struct { 1222 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1223 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1224 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1225 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1226 }; 1227 uint32_t Value; 1228 } DW53; 1229 union { 1230 //!< DWORD 54..59 1231 struct { 1232 uint8_t SicForwardTransformCoeffThresholdMatrix46ArrayIndexN[24]; //!< SIC Forward Transform Coeff Threshold Matrix4/6 Array Index[n] 1233 }; 1234 uint32_t Value[6]; 1235 } DW54_59; 1236 union { 1237 //!< DWORD 60 1238 struct { 1239 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1240 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1241 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1242 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1243 }; 1244 uint32_t Value; 1245 } DW60; 1246 1247 //! \name Local enumerations 1248 1249 enum SUBOPB 1250 { 1251 SUBOPB_VDENCCONSTQPTSTATE = 6, //!< No additional details 1252 }; 1253 1254 enum SUBOPA 1255 { 1256 SUBOPA_UNNAMED0 = 0, //!< No additional details 1257 }; 1258 1259 enum OPCODE 1260 { 1261 OPCODE_VDENCPIPE = 1, //!< No additional details 1262 }; 1263 1264 enum PIPELINE 1265 { 1266 PIPELINE_MFXCOMMON = 2, //!< No additional details 1267 }; 1268 1269 enum COMMAND_TYPE 1270 { 1271 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1272 }; 1273 1274 //! \name Initializations 1275 1276 //! \brief Explicit member initialization function 1277 VDENC_CONST_QPT_STATE_CMD(); 1278 1279 static const size_t dwSize = 61; 1280 static const size_t byteSize = 244; 1281 }; 1282 1283 //! 1284 //! \brief VDENC_DS_REF_SURFACE_STATE 1285 //! \details 1286 //! This command specifies the surface state parameters for the downscaled 1287 //! reference surfaces. 1288 //! 1289 struct VDENC_DS_REF_SURFACE_STATE_CMD 1290 { 1291 union 1292 { 1293 //!< DWORD 0 1294 struct 1295 { 1296 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1297 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1298 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1299 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1300 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1301 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1302 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1303 }; 1304 uint32_t Value; 1305 } DW0; 1306 union 1307 { 1308 //!< DWORD 1 1309 struct 1310 { 1311 uint32_t Reserved32 ; //!< Reserved 1312 }; 1313 uint32_t Value; 1314 } DW1; 1315 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 1316 1317 //! \name Local enumerations 1318 1319 enum SUBOPB 1320 { 1321 SUBOPB_VDENCDSREFSURFACESTATE = 3, //!< No additional details 1322 }; 1323 1324 enum SUBOPA 1325 { 1326 SUBOPA_UNNAMED0 = 0, //!< No additional details 1327 }; 1328 1329 enum OPCODE 1330 { 1331 OPCODE_VDENCPIPE = 1, //!< No additional details 1332 }; 1333 1334 enum PIPELINE 1335 { 1336 PIPELINE_MFXCOMMON = 2, //!< No additional details 1337 }; 1338 1339 enum COMMAND_TYPE 1340 { 1341 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1342 }; 1343 1344 //! \name Initializations 1345 1346 //! \brief Explicit member initialization function 1347 VDENC_DS_REF_SURFACE_STATE_CMD(); 1348 1349 static const size_t dwSize = 6; 1350 static const size_t byteSize = 24; 1351 }; 1352 1353 //! 1354 //! \brief VDENC_IMG_STATE 1355 //! \details 1356 //! This command programs the frame level parameters required by the VDEnc 1357 //! pipeline. 1358 //! 1359 struct VDENC_IMG_STATE_CMD 1360 { 1361 union 1362 { 1363 //!< DWORD 0 1364 struct 1365 { 1366 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1367 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1368 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1369 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1370 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1371 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1372 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1373 }; 1374 uint32_t Value; 1375 } DW0; 1376 union 1377 { 1378 //!< DWORD 1 1379 struct 1380 { 1381 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1382 uint32_t BidirectionalMixDisable : __CODEGEN_BITFIELD( 2, 2) ; //!< BIDIRECTIONAL_MIX_DISABLE 1383 uint32_t VdencPerfmode : __CODEGEN_BITFIELD( 3, 3) ; //!< VDENC_PERFMODE 1384 uint32_t TimeBudgetOverflowCheck : __CODEGEN_BITFIELD( 4, 4) ; //!< TIME_BUDGET_OVERFLOW_CHECK 1385 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 5) ; //!< Reserved 1386 uint32_t VdencExtendedPakObjCmdEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 1387 uint32_t Transform8X8Flag : __CODEGEN_BITFIELD( 7, 7) ; //!< TRANSFORM_8X8_FLAG 1388 uint32_t VdencL1CachePriority : __CODEGEN_BITFIELD( 8, 9) ; //!< VDENC_L1_CACHE_PRIORITY 1389 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1390 uint32_t LambdaValueForTrellis : __CODEGEN_BITFIELD(16, 31) ; //!< Lambda value for Trellis 1391 }; 1392 uint32_t Value; 1393 } DW1; 1394 union 1395 { 1396 //!< DWORD 2 1397 struct 1398 { 1399 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1400 uint32_t BidirectionalWeight : __CODEGEN_BITFIELD(16, 21) ; //!< BIDIRECTIONAL_WEIGHT 1401 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 27) ; //!< Reserved 1402 uint32_t UnidirectionalMixDisable : __CODEGEN_BITFIELD(28, 28) ; //!< Unidirectional Mix Disable 1403 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1404 }; 1405 uint32_t Value; 1406 } DW2; 1407 union 1408 { 1409 //!< DWORD 3 1410 struct 1411 { 1412 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1413 uint32_t PictureWidth : __CODEGEN_BITFIELD(16, 31) ; //!< Picture Width 1414 }; 1415 uint32_t Value; 1416 } DW3; 1417 union 1418 { 1419 //!< DWORD 4 1420 struct 1421 { 1422 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1423 uint32_t SubPelMode : __CODEGEN_BITFIELD(12, 13) ; //!< SUB_PEL_MODE 1424 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 16) ; //!< Reserved 1425 uint32_t ForwardTransformSkipCheckEnable : __CODEGEN_BITFIELD(17, 17) ; //!< FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 1426 uint32_t BmeDisableForFbrMessage : __CODEGEN_BITFIELD(18, 18) ; //!< BME_DISABLE_FOR_FBR_MESSAGE 1427 uint32_t BlockBasedSkipEnabled : __CODEGEN_BITFIELD(19, 19) ; //!< BLOCK_BASED_SKIP_ENABLED 1428 uint32_t InterSadMeasureAdjustment : __CODEGEN_BITFIELD(20, 21) ; //!< INTER_SAD_MEASURE_ADJUSTMENT 1429 uint32_t IntraSadMeasureAdjustment : __CODEGEN_BITFIELD(22, 23) ; //!< INTRA_SAD_MEASURE_ADJUSTMENT 1430 uint32_t SubMacroblockSubPartitionMask : __CODEGEN_BITFIELD(24, 30) ; //!< SUB_MACROBLOCK_SUB_PARTITION_MASK 1431 uint32_t BlockBasedSkipType : __CODEGEN_BITFIELD(31, 31) ; //!< BLOCK_BASED_SKIP_TYPE 1432 }; 1433 uint32_t Value; 1434 } DW4; 1435 union 1436 { 1437 //!< DWORD 5 1438 struct 1439 { 1440 uint32_t PictureHeightMinusOne : __CODEGEN_BITFIELD( 0, 15) ; //!< Picture Height Minus One 1441 uint32_t CrePrefetchEnable : __CODEGEN_BITFIELD(16, 16) ; //!< CRE_PREFETCH_ENABLE 1442 uint32_t HmeRef1Disable : __CODEGEN_BITFIELD(17, 17) ; //!< HME_REF1_DISABLE 1443 uint32_t MbSliceThresholdValue : __CODEGEN_BITFIELD(18, 21) ; //!< MB Slice Threshold Value 1444 uint32_t Reserved182 : __CODEGEN_BITFIELD(22, 25) ; //!< Reserved 1445 uint32_t ConstrainedIntraPredictionFlag : __CODEGEN_BITFIELD(26, 26) ; //!< CONSTRAINED_INTRA_PREDICTION_FLAG 1446 uint32_t Reserved187 : __CODEGEN_BITFIELD(27, 28) ; //!< Reserved 1447 uint32_t PictureType : __CODEGEN_BITFIELD(29, 30) ; //!< PICTURE_TYPE 1448 uint32_t Reserved191 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1449 }; 1450 uint32_t Value; 1451 } DW5; 1452 union 1453 { 1454 //!< DWORD 6 1455 struct 1456 { 1457 uint32_t SliceMacroblockHeightMinusOne : __CODEGEN_BITFIELD( 0, 15) ; //!< Slice Macroblock Height Minus One 1458 uint32_t Reserved208 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1459 }; 1460 uint32_t Value; 1461 } DW6; 1462 union 1463 { 1464 //!< DWORD 7 1465 struct 1466 { 1467 uint32_t Hme0XOffset : __CODEGEN_BITFIELD( 0, 7) ; //!< HME0 X Offset 1468 uint32_t Hme0YOffset : __CODEGEN_BITFIELD( 8, 15) ; //!< HME0 Y Offset 1469 uint32_t Hme1XOffset : __CODEGEN_BITFIELD(16, 23) ; //!< HME1 X Offset 1470 uint32_t Hme1YOffset : __CODEGEN_BITFIELD(24, 31) ; //!< HME1 Y Offset 1471 }; 1472 uint32_t Value; 1473 } DW7; 1474 union 1475 { 1476 //!< DWORD 8 1477 struct 1478 { 1479 uint32_t LumaIntraPartitionMask : __CODEGEN_BITFIELD( 0, 4) ; //!< LUMA_INTRA_PARTITION_MASK 1480 uint32_t NonSkipZeroMvCostAdded : __CODEGEN_BITFIELD( 5, 5) ; //!< Non Skip Zero MV Cost Added 1481 uint32_t NonSkipMbModeCostAdded : __CODEGEN_BITFIELD( 6, 6) ; //!< Non Skip MB Mode Cost Added 1482 uint32_t Reserved263 : __CODEGEN_BITFIELD( 7, 15) ; //!< Reserved 1483 uint32_t MvCostScalingFactor : __CODEGEN_BITFIELD(16, 17) ; //!< MV_COST_SCALING_FACTOR 1484 uint32_t BilinearFilterEnable : __CODEGEN_BITFIELD(18, 18) ; //!< BiLinear Filter Enable 1485 uint32_t Reserved275 : __CODEGEN_BITFIELD(19, 21) ; //!< Reserved 1486 uint32_t RefidCostModeSelect : __CODEGEN_BITFIELD(22, 22) ; //!< REFID_COST_MODE_SELECT 1487 uint32_t Reserved279 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 1488 }; 1489 uint32_t Value; 1490 } DW8; 1491 union 1492 { 1493 //!< DWORD 9 1494 struct 1495 { 1496 uint32_t Mode0Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 0 Cost 1497 uint32_t Mode1Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 1 Cost 1498 uint32_t Mode2Cost : __CODEGEN_BITFIELD(16, 23) ; //!< Mode 2 Cost 1499 uint32_t Mode3Cost : __CODEGEN_BITFIELD(24, 31) ; //!< Mode 3 Cost 1500 }; 1501 uint32_t Value; 1502 } DW9; 1503 union 1504 { 1505 //!< DWORD 10 1506 struct 1507 { 1508 uint32_t Mode4Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 4 Cost 1509 uint32_t Mode5Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 5 Cost 1510 uint32_t Mode6Cost : __CODEGEN_BITFIELD(16, 23) ; //!< Mode 6 Cost 1511 uint32_t Mode7Cost : __CODEGEN_BITFIELD(24, 31) ; //!< Mode 7 Cost 1512 }; 1513 uint32_t Value; 1514 } DW10; 1515 union 1516 { 1517 //!< DWORD 11 1518 struct 1519 { 1520 uint32_t Mode8Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 8 Cost 1521 uint32_t Mode9Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 9 Cost 1522 uint32_t RefIdCost : __CODEGEN_BITFIELD(16, 23) ; //!< RefID Cost 1523 uint32_t ChromaIntraModeCost : __CODEGEN_BITFIELD(24, 31) ; //!< Chroma Intra Mode Cost 1524 }; 1525 uint32_t Value; 1526 } DW11; 1527 union 1528 { 1529 //!< DWORD 12 1530 struct 1531 { 1532 uint32_t MvCost0 : __CODEGEN_BITFIELD( 0, 7) ; //!< MvCost 0 1533 uint32_t MvCost1 : __CODEGEN_BITFIELD( 8, 15) ; //!< MvCost 1 1534 uint32_t MvCost2 : __CODEGEN_BITFIELD(16, 23) ; //!< MvCost 2 1535 uint32_t MvCost3 : __CODEGEN_BITFIELD(24, 31) ; //!< MvCost 3 1536 }; 1537 uint32_t Value; 1538 } DW12; 1539 union 1540 { 1541 //!< DWORD 13 1542 struct 1543 { 1544 uint32_t MvCost4 : __CODEGEN_BITFIELD( 0, 7) ; //!< MvCost 4 1545 uint32_t MvCost5 : __CODEGEN_BITFIELD( 8, 15) ; //!< MvCost 5 1546 uint32_t MvCost6 : __CODEGEN_BITFIELD(16, 23) ; //!< MvCost 6 1547 uint32_t MvCost7 : __CODEGEN_BITFIELD(24, 31) ; //!< MvCost 7 1548 }; 1549 uint32_t Value; 1550 } DW13; 1551 union 1552 { 1553 //!< DWORD 14 1554 struct 1555 { 1556 uint32_t QpPrimeY : __CODEGEN_BITFIELD( 0, 7) ; //!< QpPrimeY 1557 uint32_t Reserved456 : __CODEGEN_BITFIELD( 8, 23) ; //!< Reserved 1558 uint32_t TargetSizeInWord : __CODEGEN_BITFIELD(24, 31) ; //!< TargetSizeInWord 1559 }; 1560 uint32_t Value; 1561 } DW14; 1562 union 1563 { 1564 //!< DWORD 15 1565 struct 1566 { 1567 uint32_t Reserved480 ; //!< Reserved 1568 }; 1569 uint32_t Value; 1570 } DW15; 1571 union 1572 { 1573 //!< DWORD 16 1574 struct 1575 { 1576 uint32_t Reserved512 ; //!< Reserved 1577 }; 1578 uint32_t Value; 1579 } DW16; 1580 union 1581 { 1582 //!< DWORD 17 1583 struct 1584 { 1585 uint32_t AvcIntra4X4ModeMask : __CODEGEN_BITFIELD( 0, 8) ; //!< AVC Intra 4x4 Mode Mask 1586 uint32_t Reserved553 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 1587 uint32_t AvcIntra8X8ModeMask : __CODEGEN_BITFIELD(16, 24) ; //!< AVC Intra 8x8 Mode Mask 1588 uint32_t Reserved569 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 1589 }; 1590 uint32_t Value; 1591 } DW17; 1592 union 1593 { 1594 //!< DWORD 18 1595 struct 1596 { 1597 uint32_t AvcIntra16X16ModeMask : __CODEGEN_BITFIELD( 0, 3) ; //!< AVC_INTRA_16X16_MODE_MASK 1598 uint32_t AvcIntraChromaModeMask : __CODEGEN_BITFIELD( 4, 7) ; //!< AVC_INTRA_CHROMA_MODE_MASK 1599 uint32_t IntraComputeTypeIntracomputetype : __CODEGEN_BITFIELD( 8, 9) ; //!< INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 1600 uint32_t Reserved586 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 1601 }; 1602 uint32_t Value; 1603 } DW18; 1604 union 1605 { 1606 //!< DWORD 19 1607 struct 1608 { 1609 uint32_t Reserved608 ; //!< Reserved 1610 }; 1611 uint32_t Value; 1612 } DW19; 1613 union 1614 { 1615 //!< DWORD 20 1616 struct 1617 { 1618 uint32_t PenaltyForIntra16X16NondcPrediction : __CODEGEN_BITFIELD( 0, 7) ; //!< Penalty for Intra16x16 NonDC Prediction. 1619 uint32_t PenaltyForIntra8X8NondcPrediction : __CODEGEN_BITFIELD( 8, 15) ; //!< Penalty for Intra8x8 NonDC Prediction. 1620 uint32_t PenaltyForIntra4X4NondcPrediction : __CODEGEN_BITFIELD(16, 23) ; //!< Penalty for Intra4x4 NonDC Prediction. 1621 uint32_t Reserved664 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1622 }; 1623 uint32_t Value; 1624 } DW20; 1625 union 1626 { 1627 //!< DWORD 21 1628 struct 1629 { 1630 uint32_t IntraRefreshMBPos : __CODEGEN_BITFIELD( 0, 7) ; //!< IntraRefreshMBPos 1631 uint32_t IntraRefreshMBSizeMinusOne : __CODEGEN_BITFIELD( 8, 15) ; //!< IntraRefreshMBSizeMinusOne 1632 uint32_t IntraRefreshEnableRollingIEnable : __CODEGEN_BITFIELD(16, 16) ; //!< INTRAREFRESHENABLE_ROLLING_I_ENABLE 1633 uint32_t IntraRefreshMode : __CODEGEN_BITFIELD(17, 17) ; //!< INTRAREFRESHMODE 1634 uint32_t Reserved690 : __CODEGEN_BITFIELD(18, 23) ; //!< Reserved 1635 uint32_t QpAdjustmentForRollingI : __CODEGEN_BITFIELD(24, 31) ; //!< QP adjustment for Rolling-I 1636 }; 1637 uint32_t Value; 1638 } DW21; 1639 union 1640 { 1641 //!< DWORD 22 1642 struct 1643 { 1644 uint32_t Panicmodembthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< PanicModeMBThreshold 1645 uint32_t Smallmbsizeinword : __CODEGEN_BITFIELD(16, 23) ; //!< SmallMbSizeInWord 1646 uint32_t Largembsizeinword : __CODEGEN_BITFIELD(24, 31) ; //!< LargeMbSizeInWord 1647 }; 1648 uint32_t Value; 1649 } DW22; 1650 union 1651 { 1652 //!< DWORD 23 1653 struct 1654 { 1655 uint32_t L0NumberOfReferencesMinusOne : __CODEGEN_BITFIELD( 0, 7) ; //!< L0 number of references Minus one 1656 uint32_t Reserved744 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1657 uint32_t L1NumberOfReferencesMinusOne : __CODEGEN_BITFIELD(16, 23) ; //!< L1 number of references Minus One 1658 uint32_t Reserved760 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1659 }; 1660 uint32_t Value; 1661 } DW23; 1662 union 1663 { 1664 //!< DWORD 24 1665 struct 1666 { 1667 uint32_t Reserved768 ; //!< Reserved 1668 }; 1669 uint32_t Value; 1670 } DW24; 1671 union 1672 { 1673 //!< DWORD 25 1674 struct 1675 { 1676 uint32_t Reserved800 ; //!< Reserved 1677 }; 1678 uint32_t Value; 1679 } DW25; 1680 union 1681 { 1682 //!< DWORD 26 1683 struct 1684 { 1685 uint32_t Reserved832 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 1686 uint32_t HmeRefWindowsCombiningThreshold : __CODEGEN_BITFIELD( 8, 15) ; //!< HME_REF_WINDOWS_COMBINING_THRESHOLD 1687 uint32_t Reserved848 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1688 }; 1689 uint32_t Value; 1690 } DW26; 1691 union 1692 { 1693 //!< DWORD 27 1694 struct 1695 { 1696 uint32_t MaxHmvR : __CODEGEN_BITFIELD( 0, 15) ; //!< MAXHMVR 1697 uint32_t MaxVmvR : __CODEGEN_BITFIELD(16, 31) ; //!< MAXVMVR 1698 }; 1699 uint32_t Value; 1700 } DW27; 1701 union 1702 { 1703 //!< DWORD 28 1704 struct 1705 { 1706 uint32_t HmeMvCost0 : __CODEGEN_BITFIELD( 0, 7) ; //!< HmeMvCost 0 1707 uint32_t HmeMvCost1 : __CODEGEN_BITFIELD( 8, 15) ; //!< HmeMvCost 1 1708 uint32_t HmeMvCost2 : __CODEGEN_BITFIELD(16, 23) ; //!< HmeMvCost 2 1709 uint32_t HmeMvCost3 : __CODEGEN_BITFIELD(24, 31) ; //!< HmeMvCost 3 1710 }; 1711 uint32_t Value; 1712 } DW28; 1713 union 1714 { 1715 //!< DWORD 29 1716 struct 1717 { 1718 uint32_t HmeMvCost4 : __CODEGEN_BITFIELD( 0, 7) ; //!< HmeMvCost 4 1719 uint32_t HmeMvCost5 : __CODEGEN_BITFIELD( 8, 15) ; //!< HmeMvCost 5 1720 uint32_t HmeMvCost6 : __CODEGEN_BITFIELD(16, 23) ; //!< HmeMvCost 6 1721 uint32_t HmeMvCost7 : __CODEGEN_BITFIELD(24, 31) ; //!< HmeMvCost 7 1722 }; 1723 uint32_t Value; 1724 } DW29; 1725 union 1726 { 1727 //!< DWORD 30 1728 struct 1729 { 1730 uint32_t RoiQpAdjustmentForZone0 : __CODEGEN_BITFIELD( 0, 3) ; //!< ROI QP adjustment for Zone0 1731 uint32_t RoiQpAdjustmentForZone1 : __CODEGEN_BITFIELD( 4, 7) ; //!< ROI QP adjustment for Zone1 1732 uint32_t RoiQpAdjustmentForZone2 : __CODEGEN_BITFIELD( 8, 11) ; //!< ROI QP adjustment for Zone2 1733 uint32_t RoiQpAdjustmentForZone3 : __CODEGEN_BITFIELD(12, 15) ; //!< ROI QP adjustment for Zone3 1734 uint32_t QpAdjustmentForShapeBestIntra4X4Winner : __CODEGEN_BITFIELD(16, 19) ; //!< QP adjustment for shape best intra 4x4 winner 1735 uint32_t QpAdjustmentForShapeBestIntra8X8Winner : __CODEGEN_BITFIELD(20, 23) ; //!< QP adjustment for shape best intra 8x8 winner 1736 uint32_t QpAdjustmentForShapeBestIntra16X16Winner : __CODEGEN_BITFIELD(24, 27) ; //!< QP adjustment for shape best intra 16x16 winner 1737 uint32_t Reserved988 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1738 }; 1739 uint32_t Value; 1740 } DW30; 1741 union 1742 { 1743 //!< DWORD 31 1744 struct 1745 { 1746 uint32_t BestdistortionQpAdjustmentForZone0 : __CODEGEN_BITFIELD( 0, 3) ; //!< BestDistortion QP adjustment for Zone0 1747 uint32_t BestdistortionQpAdjustmentForZone1 : __CODEGEN_BITFIELD( 4, 7) ; //!< BestDistortion QP adjustment for Zone1 1748 uint32_t BestdistortionQpAdjustmentForZone2 : __CODEGEN_BITFIELD( 8, 11) ; //!< BestDistortion QP adjustment for Zone2 1749 uint32_t BestdistortionQpAdjustmentForZone3 : __CODEGEN_BITFIELD(12, 15) ; //!< BestDistortion QP adjustment for Zone3 1750 uint32_t SadHaarThreshold0 : __CODEGEN_BITFIELD(16, 31) ; //!< Sad/Haar_Threshold_0 1751 }; 1752 uint32_t Value; 1753 } DW31; 1754 union 1755 { 1756 //!< DWORD 32 1757 struct 1758 { 1759 uint32_t SadHaarThreshold1 : __CODEGEN_BITFIELD( 0, 15) ; //!< Sad/Haar_Threshold_1 1760 uint32_t SadHaarThreshold2 : __CODEGEN_BITFIELD(16, 31) ; //!< Sad/Haar_Threshold_2 1761 }; 1762 uint32_t Value; 1763 } DW32; 1764 union 1765 { 1766 //!< DWORD 33 1767 struct 1768 { 1769 uint32_t MaxQp : __CODEGEN_BITFIELD( 0, 7) ; //!< MaxQP 1770 uint32_t MinQp : __CODEGEN_BITFIELD( 8, 15) ; //!< MinQP 1771 uint32_t Reserved1072 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 1772 uint32_t Maxdeltaqp : __CODEGEN_BITFIELD(24, 27) ; //!< MaxDeltaQP 1773 uint32_t Reserved1084 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1774 }; 1775 uint32_t Value; 1776 } DW33; 1777 union 1778 { 1779 //!< DWORD 34 1780 struct 1781 { 1782 uint32_t RoiEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< ROI_Enable 1783 uint32_t FwdPredictor0MvEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Fwd/Predictor0 MV Enable 1784 uint32_t BwdPredictor1MvEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< Bwd/Predictor1 MV Enable 1785 uint32_t MbLevelQpEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< MB Level QP Enable 1786 uint32_t TargetsizeinwordsmbMaxsizeinwordsmbEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< TargetSizeinWordsMB/MaxSizeinWordsMB Enable 1787 uint32_t Reserverd : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserverd 1788 uint32_t PpmvDisable : __CODEGEN_BITFIELD( 8, 8) ; //!< PPMV_DISABLE 1789 uint32_t CoefficientClampEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Coefficient Clamp Enable 1790 uint32_t LongtermReferenceFrameBwdRef0Indicator : __CODEGEN_BITFIELD(10, 10) ; //!< LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 1791 uint32_t LongtermReferenceFrameFwdRef2Indicator : __CODEGEN_BITFIELD(11, 11) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 1792 uint32_t LongtermReferenceFrameFwdRef1Indicator : __CODEGEN_BITFIELD(12, 12) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 1793 uint32_t LongtermReferenceFrameFwdRef0Indicator : __CODEGEN_BITFIELD(13, 13) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 1794 uint32_t ImageStateQpOverride : __CODEGEN_BITFIELD(14, 14) ; //!< IMAGE_STATE_QP_OVERRIDE 1795 uint32_t Reserved1102 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1796 uint32_t MidpointSadHaar : __CODEGEN_BITFIELD(16, 31) ; //!< Midpoint sad/haar 1797 }; 1798 uint32_t Value; 1799 } DW34; 1800 1801 //! \name Local enumerations 1802 1803 enum SUBOPB 1804 { 1805 SUBOPB_VDENCIMGSTATE = 5, //!< No additional details 1806 }; 1807 1808 enum SUBOPA 1809 { 1810 SUBOPA_UNNAMED0 = 0, //!< No additional details 1811 }; 1812 1813 enum OPCODE 1814 { 1815 OPCODE_VDENCPIPE = 1, //!< No additional details 1816 }; 1817 1818 enum PIPELINE 1819 { 1820 PIPELINE_MFXCOMMON = 2, //!< No additional details 1821 }; 1822 1823 enum COMMAND_TYPE 1824 { 1825 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1826 }; 1827 1828 enum BIDIRECTIONAL_MIX_DISABLE 1829 { 1830 BIDIRECTIONAL_MIX_DISABLE_SUBBLOCKENABLED = 0, //!< Bidirectional decision on subblock level that bidirectional mode is enabled. 1831 BIDIRECTIONAL_MIX_DISABLE_WHOLEMACROBLOCKENABLED = 1, //!< Bidirectional decision on whole macroblock. 1832 }; 1833 1834 //! \brief VDENC_PERFMODE 1835 //! \details 1836 //! This bit indicates if VDEnc is configured for normal or speed mode of 1837 //! operation. 1838 enum VDENC_PERFMODE 1839 { 1840 VDENC_PERFMODE_NORMAL = 0, //!< VDEnc is running in normal mode. IME Search: 3x3 SU per each reference. HME Search: 88x92 search window per HME instance (0 & 1). 1841 VDENC_PERFMODE_SPEED = 1, //!< VDEnc is configured for speed mode. IME Search: 2x2 SU per each reference. HME Search: 48x92 search window per HME instance (0 & 1). 1842 }; 1843 1844 //! \brief TIME_BUDGET_OVERFLOW_CHECK 1845 //! \details 1846 //! <p>This bit enables the frame time budget detection in VDEnc.</p> 1847 //! <p>To detect if a Time Budget Overflow happened in a frame, SW 1848 //! can read "PAK_Stream-Out Report (Errors)" register in MFX. When Time 1849 //! budget overflow condition happens in the frame, this register bits 15:8 1850 //! indicate MB y position and bits 7:0 indicate MB x position where Time 1851 //! budget overflow occured. When there is no time budget overflow in a 1852 //! frame, "<span style="line-height: 20.7999992370605px;">PAK_Stream-Out 1853 //! Report (Errors)" register reads zero.</span></p> 1854 enum TIME_BUDGET_OVERFLOW_CHECK 1855 { 1856 TIME_BUDGET_OVERFLOW_CHECK_DISABLED = 0, //!< No additional details 1857 TIME_BUDGET_OVERFLOW_CHECK_ENABLED = 1, //!< No additional details 1858 }; 1859 1860 //! \brief VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 1861 //! \details 1862 //! This bit enables the distortion data to be populated in the VDenc PAK 1863 //! Obj inline data. 1864 enum VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 1865 { 1866 VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE_DISABLE = 0, //!< The extra two DWS from VDEnc (MDC) to PAK will be Zero. 1867 VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE_ENABLE = 1, //!< The last two DWs from VDEnc (MDC) to PAK will be populated with distortion data. (Defined in the PAK Object command DW 22,23.) 1868 }; 1869 1870 //! \brief TRANSFORM_8X8_FLAG 1871 //! \details 1872 //! 8x8 IDCT Transform Mode Flag, trans8x8_mode_flag specifies 8x8 IDCT 1873 //! transform may be used in this 1874 //! picture. It is set to the value of the syntax element in the 1875 //! current active PPS. 1876 enum TRANSFORM_8X8_FLAG 1877 { 1878 TRANSFORM_8X8_FLAG_DISABLED = 0, //!< No 8x8 IDCT Transform, only 4x4 IDCT transform blocks are present. 1879 TRANSFORM_8X8_FLAG_ENABLED = 1, //!< 8x8 Transform is allowed. 1880 }; 1881 1882 //! \brief VDENC_L1_CACHE_PRIORITY 1883 //! \details 1884 //! L1 Cache inside VDEnc has 3 clients - IME, CRE and VMC. These bits 1885 //! indicate the priority order for 1886 //! L1 cache to service the client requests. 1887 enum VDENC_L1_CACHE_PRIORITY 1888 { 1889 VDENC_L1_CACHE_PRIORITY_UNNAMED0 = 0, //!< CRE High Priority, VMC and IME round robin. 1890 VDENC_L1_CACHE_PRIORITY_UNNAMED1 = 1, //!< CRE and VMC round robin, IME low priority. 1891 VDENC_L1_CACHE_PRIORITY_UNNAMED2 = 2, //!< CRE High Priority, IME Medium, VMC Low. 1892 VDENC_L1_CACHE_PRIORITY_UNNAMED3 = 3, //!< VMC High Priority, CRE Medium, IME low. 1893 }; 1894 1895 //! \brief BIDIRECTIONAL_WEIGHT 1896 //! \details 1897 //! Default value: Depends on the distance between the B and reference 1898 //! pictures. 1899 enum BIDIRECTIONAL_WEIGHT 1900 { 1901 BIDIRECTIONAL_WEIGHT_UNNAMED16 = 16, //!< No additional details 1902 BIDIRECTIONAL_WEIGHT_UNNAMED21 = 21, //!< No additional details 1903 BIDIRECTIONAL_WEIGHT_UNNAMED32 = 32, //!< No additional details 1904 BIDIRECTIONAL_WEIGHT_UNNAMED43 = 43, //!< No additional details 1905 BIDIRECTIONAL_WEIGHT_UNNAMED48 = 48, //!< No additional details 1906 }; 1907 1908 //! \brief SUB_PEL_MODE 1909 //! \details 1910 //! This field defines the half/quarter pel modes. The mode is inclusive, 1911 //! i.e., higher precision mode samples lower precision locations. 1912 enum SUB_PEL_MODE 1913 { 1914 SUB_PEL_MODE_UNNAMED0 = 0, //!< Integer mode searching. 1915 SUB_PEL_MODE_UNNAMED1 = 1, //!< Half-pel mode searching. 1916 SUB_PEL_MODE_UNNAMED3 = 3, //!< Quarter-pel mode searching. 1917 }; 1918 1919 //! \brief FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 1920 //! \details 1921 //! This field enables the forward transform calculation for skip check. It 1922 //! does not override the other 1923 //! skip calculations but it does decrease the performance marginally 1924 //! so don't enable it unless the transform is necessary. 1925 enum FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 1926 { 1927 FORWARD_TRANSFORM_SKIP_CHECK_ENABLE_FTDISABLED = 0, //!< No additional details 1928 FORWARD_TRANSFORM_SKIP_CHECK_ENABLE_FTENABLED = 1, //!< No additional details 1929 }; 1930 1931 //! \brief BME_DISABLE_FOR_FBR_MESSAGE 1932 //! \details 1933 //! FBR messages that do not want bidirectional motion estimation performed 1934 //! will set this bit and VME will 1935 //! only perform fractional refinement on the shapes identified by 1936 //! subpredmode. Note: only the LSB of the 1937 //! subpredmode for each shape will be considered in FBR (a shape is 1938 //! either FWD or BWD as input of FBR, 1939 //! output however could change to BI if BME is enabled). 1940 enum BME_DISABLE_FOR_FBR_MESSAGE 1941 { 1942 BME_DISABLE_FOR_FBR_MESSAGE_BMEENABLED = 0, //!< No additional details 1943 BME_DISABLE_FOR_FBR_MESSAGE_BMEDISABLED = 1, //!< No additional details 1944 }; 1945 1946 //! \brief BLOCK_BASED_SKIP_ENABLED 1947 //! \details 1948 //! When this field is set on the skip thresholding passing criterion will 1949 //! be based on the maximal distortion 1950 //! of individual blocks (8x8's or 4x4's) instead of their sum (i.e. 1951 //! the distortion of 16x16). 1952 enum BLOCK_BASED_SKIP_ENABLED 1953 { 1954 BLOCK_BASED_SKIP_ENABLED_UNNAMED0 = 0, //!< 16x16 Block Based Skip threshold check. 1955 BLOCK_BASED_SKIP_ENABLED_BLOCK_BASEDSKIPTYPE = 1, //!< Parameter indicates 8x8 vs. 4x4 based check. 1956 }; 1957 1958 //! \brief INTER_SAD_MEASURE_ADJUSTMENT 1959 //! \details 1960 //! This field specifies distortion measure adjustments used for the motion 1961 //! search SAD comparison. 1962 //! This field applies to both luma and chroma inter measurement. 1963 enum INTER_SAD_MEASURE_ADJUSTMENT 1964 { 1965 INTER_SAD_MEASURE_ADJUSTMENT_NONE = 0, //!< No additional details 1966 INTER_SAD_MEASURE_ADJUSTMENT_HAARTRANSFORMADJUSTED = 2, //!< No additional details 1967 }; 1968 1969 //! \brief INTRA_SAD_MEASURE_ADJUSTMENT 1970 //! \details 1971 //! This field specifies distortion measure adjustments used for the motion 1972 //! search SAD comparison. 1973 //! This field applies to both luma and chroma intra measurement. 1974 enum INTRA_SAD_MEASURE_ADJUSTMENT 1975 { 1976 INTRA_SAD_MEASURE_ADJUSTMENT_NONE = 0, //!< No additional details 1977 INTRA_SAD_MEASURE_ADJUSTMENT_HAARTRANSFORMADJUSTED = 2, //!< No additional details 1978 }; 1979 1980 //! \brief SUB_MACROBLOCK_SUB_PARTITION_MASK 1981 //! \details 1982 //! This field defines the bit-mask for disabling 1983 //! <ul> 1984 //! <li>sub-partition (minor partition [30:28]) modes</li> 1985 //! <li>sub-macroblock (major partition [27:24]) modes</li> 1986 //! </ul> 1987 enum SUB_MACROBLOCK_SUB_PARTITION_MASK 1988 { 1989 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED113 = 113, //!< 16x16 sub-macroblock disabled 1990 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED114 = 114, //!< 2x(16x8) sub-macroblock within 16x16 disabled 1991 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED116 = 116, //!< 2x(8x16) sub-macroblock within 16x16 disabled 1992 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED120 = 120, //!< 1x(8x8) sub-partition for 4x(8x8) within 16x16 disabled 1993 }; 1994 1995 //! \brief BLOCK_BASED_SKIP_TYPE 1996 //! \details 1997 //! The skip thresholding passing criterion will be based on the maximal 1998 //! distortion of individual blocks 1999 //! (8x8's or 4x4's) instead of their sum (i.e. the distortion of 2000 //! 16x16). This field is only valid when 2001 //! <b>Block-Based Skip Enabled</b> = 1. 2002 enum BLOCK_BASED_SKIP_TYPE 2003 { 2004 BLOCK_BASED_SKIP_TYPE_UNNAMED0 = 0, //!< 4x4 block-based skip threshold check. 2005 BLOCK_BASED_SKIP_TYPE_UNNAMED1 = 1, //!< 8x8 block-based skip threshold check. 2006 }; 2007 2008 //! \brief CRE_PREFETCH_ENABLE 2009 //! \details 2010 //! This field determines if IME will prefetch the fractional CLs that are 2011 //! required by CRE ahead of time 2012 //! while fetching the reference windows around the IME predictors. The 2013 //! recommendation for driver is to 2014 //! always program this bit to 1 unless some usages restrict SubPelMode 2015 //! to be "<i>Integer mode searching</i>". 2016 enum CRE_PREFETCH_ENABLE 2017 { 2018 CRE_PREFETCH_ENABLE_UNNAMED0 = 0, //!< Disable 2019 CRE_PREFETCH_ENABLE_UNNAMED1 = 1, //!< Enable 2020 }; 2021 2022 //! \brief HME_REF1_DISABLE 2023 //! \details 2024 //! This field indicates if HME is disabled for reference 1 (second forward 2025 //! reference). 2026 enum HME_REF1_DISABLE 2027 { 2028 HME_REF1_DISABLE_UNNAMED0 = 0, //!< HME search is performed on forward reference 1. 2029 HME_REF1_DISABLE_UNNAMED1 = 1, //!< HME search is disabled on forward reference 1. 2030 }; 2031 2032 enum CONSTRAINED_INTRA_PREDICTION_FLAG 2033 { 2034 CONSTRAINED_INTRA_PREDICTION_FLAG_UNNAMED0 = 0, //!< Allows both intra and inter neighboring MB to be used in the intra-prediction decoding of the current MB. 2035 CONSTRAINED_INTRA_PREDICTION_FLAG_UNNAMED1 = 1, //!< Allows only to use neighboring Intra MBs in the intra-prediction decoding of the current MB.If the neighbor is an inter MB, it is considered as not available. 2036 }; 2037 2038 //! \brief PICTURE_TYPE 2039 //! \details 2040 //! This field specifies how the current picture is predicted. (It might be 2041 //! redundant from the kernel type.) 2042 enum PICTURE_TYPE 2043 { 2044 PICTURE_TYPE_I = 0, //!< No additional details 2045 PICTURE_TYPE_P = 1, //!< No additional details 2046 }; 2047 2048 //! \brief LUMA_INTRA_PARTITION_MASK 2049 //! \details 2050 //! This field specifies which Luma Intra partition is enabled/disabled for 2051 //! intra mode decision. 2052 enum LUMA_INTRA_PARTITION_MASK 2053 { 2054 LUMA_INTRA_PARTITION_MASK_UNNAMED1 = 1, //!< luma_intra_16x16 disabled 2055 LUMA_INTRA_PARTITION_MASK_UNNAMED2 = 2, //!< luma_intra_8x8 disabled 2056 LUMA_INTRA_PARTITION_MASK_UNNAMED4 = 4, //!< luma_intra_4x4 disabled 2057 }; 2058 2059 enum MV_COST_SCALING_FACTOR 2060 { 2061 MV_COST_SCALING_FACTOR_QPEL = 0, //!< Qpel difference between MV and cost center: eff cost range 0-15pel 2062 MV_COST_SCALING_FACTOR_HPEL = 1, //!< Hpel difference between MV and cost center: eff cost range 0-31pel 2063 MV_COST_SCALING_FACTOR_PEL = 2, //!< Pel difference between MV and cost center: eff cost range 0-63pel 2064 MV_COST_SCALING_FACTOR_2PEL = 3, //!< 2Pel difference between MV and cost center: eff cost range 0-127pel 2065 }; 2066 2067 enum REFID_COST_MODE_SELECT 2068 { 2069 REFID_COST_MODE_SELECT_MODE0 = 0, //!< AVC 2070 REFID_COST_MODE_SELECT_MODE1 = 1, //!< Linear 2071 }; 2072 2073 enum AVC_INTRA_16X16_MODE_MASK 2074 { 2075 AVC_INTRA_16X16_MODE_MASK_VERT = 1, //!< No additional details 2076 AVC_INTRA_16X16_MODE_MASK_HORZ = 2, //!< No additional details 2077 AVC_INTRA_16X16_MODE_MASK_DC = 4, //!< No additional details 2078 AVC_INTRA_16X16_MODE_MASK_PLANAR = 8, //!< No additional details 2079 }; 2080 2081 enum AVC_INTRA_CHROMA_MODE_MASK 2082 { 2083 AVC_INTRA_CHROMA_MODE_MASK_VERT = 1, //!< No additional details 2084 AVC_INTRA_CHROMA_MODE_MASK_HORZ = 2, //!< No additional details 2085 AVC_INTRA_CHROMA_MODE_MASK_DC = 4, //!< No additional details 2086 AVC_INTRA_CHROMA_MODE_MASK_PLANAR = 8, //!< No additional details 2087 }; 2088 2089 //! \brief INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2090 //! \details 2091 //! This field specifies the pixel components measured for Intra prediction. 2092 enum INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2093 { 2094 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED0 = 0, //!< Luma+Chroma enabled. 2095 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED1 = 1, //!< Luma Only. 2096 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED2 = 2, //!< Intra Disabled. 2097 }; 2098 2099 //! \brief INTRAREFRESHENABLE_ROLLING_I_ENABLE 2100 //! \details 2101 //! <p>This parameter indicates if the IntraRefresh is enabled or 2102 //! disabled.</p> 2103 //! 2104 //! <p>This must be disabled on I-Frames.</p> 2105 enum INTRAREFRESHENABLE_ROLLING_I_ENABLE 2106 { 2107 INTRAREFRESHENABLE_ROLLING_I_ENABLE_DISABLE = 0, //!< No additional details 2108 INTRAREFRESHENABLE_ROLLING_I_ENABLE_ENABLE = 1, //!< No additional details 2109 }; 2110 2111 //! \brief INTRAREFRESHMODE 2112 //! \details 2113 //! This parameter indicates if the IntraRefresh is row based or column 2114 //! based. 2115 enum INTRAREFRESHMODE 2116 { 2117 INTRAREFRESHMODE_ROWBASED = 0, //!< No additional details 2118 INTRAREFRESHMODE_COLUMNBASED = 1, //!< No additional details 2119 }; 2120 2121 //! \brief HME_REF_WINDOWS_COMBINING_THRESHOLD 2122 //! \details 2123 //! When the reference windows of the HME refinement VME call and the 2124 //! regular VME call are overlapped 2125 //! and the difference of the locations is within this threshold in 2126 //! quarter pixel unit, the two calls 2127 //! are merged to a single call. 2128 enum HME_REF_WINDOWS_COMBINING_THRESHOLD 2129 { 2130 HME_REF_WINDOWS_COMBINING_THRESHOLD_UNNAMED0 = 0, //!< No additional details 2131 HME_REF_WINDOWS_COMBINING_THRESHOLD_UNNAMED255 = 255, //!< No additional details 2132 }; 2133 2134 //! \brief MAXHMVR 2135 //! \details 2136 //! Horizontal MV component range. The MV range is restricted to 2137 //! [-MaxHmvR+1, MaxHmvR-1] in luma quarter pel unit, 2138 //! which corresponds to [-MaxHmvR/4 + 0.25, MaxHmvR/4-0.25] in luma 2139 //! integer pel unit. 2140 enum MAXHMVR 2141 { 2142 MAXHMVR_UNNAMED256 = 256, //!< No additional details 2143 MAXHMVR_UNNAMED512 = 512, //!< No additional details 2144 MAXHMVR_UNNAMED1024 = 1024, //!< No additional details 2145 MAXHMVR_UNNAMED2048 = 2048, //!< No additional details 2146 MAXHMVR_UNNAMED4096 = 4096, //!< No additional details 2147 MAXHMVR_UNNAMED8192 = 8192, //!< No additional details 2148 }; 2149 2150 //! \brief MAXVMVR 2151 //! \details 2152 //! Vertical MV component range defined in the AVC Spec Annex A. The MV 2153 //! range is restricted to [-MaxVmvR+1, MaxVmvR-1] 2154 //! in luma quarter pel unit, which corresponds to [-MaxVmvR/4 + 0.25, 2155 //! MaxVmvR/4-0.25] in luma integer pel unit. 2156 enum MAXVMVR 2157 { 2158 MAXVMVR_UNNAMED256 = 256, //!< No additional details 2159 MAXVMVR_UNNAMED512 = 512, //!< No additional details 2160 MAXVMVR_UNNAMED1024 = 1024, //!< No additional details 2161 MAXVMVR_UNNAMED2048 = 2048, //!< No additional details 2162 }; 2163 2164 //! \brief PPMV_DISABLE 2165 //! \details 2166 //! This bit forces the IME to use the actual PMV predictor for the IME 2167 //! search. 2168 enum PPMV_DISABLE 2169 { 2170 PPMV_DISABLE_UNNAMED0 = 0, //!< Use PPMV based IME search. 2171 PPMV_DISABLE_UNNAMED1 = 1, //!< Use PMV based IME search. 2172 }; 2173 2174 //! \brief LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2175 //! \details 2176 //! Indicates whether the reference frame is a long or short term reference. 2177 enum LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2178 { 2179 LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2180 LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2181 }; 2182 2183 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2184 //! \details 2185 //! Indicates whether the reference frame is a long or short term reference. 2186 enum LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2187 { 2188 LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2189 LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2190 }; 2191 2192 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2193 //! \details 2194 //! Indicates whether the reference frame is a long or short term reference. 2195 enum LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2196 { 2197 LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2198 LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2199 }; 2200 2201 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2202 //! \details 2203 //! Indicates whether the reference frame is a long or short term reference. 2204 enum LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2205 { 2206 LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2207 LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2208 }; 2209 2210 //! \name Initializations 2211 2212 //! \brief Explicit member initialization function 2213 VDENC_IMG_STATE_CMD(); 2214 2215 static const size_t dwSize = 35; 2216 static const size_t byteSize = 140; 2217 }; 2218 2219 //! 2220 //! \brief VDENC_PIPE_BUF_ADDR_STATE 2221 //! \details 2222 //! This state command provides the memory base addresses for all row 2223 //! stores, Streamin/StreamOut, DMV buffer along with the uncompressed 2224 //! source, reference pictures and downscaled reference pictures required by 2225 //! the VDENC pipeline. All reference pixel surfaces in the Encoder are 2226 //! programmed with the same surface state (NV12 and TileY format), except 2227 //! each has its own frame buffer base address. Same holds true for the 2228 //! down-scaled reference pictures too. In the tile format, there is no need 2229 //! to provide buffer offset for each slice; since from each MB address, the 2230 //! hardware can calculated the corresponding memory location within the 2231 //! frame buffer directly. VDEnc supports 3 Downscaled reference frames ( 2 2232 //! fwd, 1 bwd) and 4 normal reference frames ( 3 fwd, 1 bwd). The driver 2233 //! will sort out the base address from the DPB table and populate the base 2234 //! addresses that map to the corresponding reference index for both DS 2235 //! references and normal reference frames. Each of the individual DS ref/ 2236 //! Normal ref frames have their own MOCS DW that corresponds to the 2237 //! respective base address. The only thing that is different in the MOCS DW 2238 //! amongst the DS reference frames is the MMCD controls (specified in bits 2239 //! [10:9] of the MOCS DW). Driver needs to ensure that the other bits need 2240 //! to be the same across the different DS ref frames. The same is 2241 //! applicable for the normal reference frames. 2242 //! 2243 struct VDENC_PIPE_BUF_ADDR_STATE_CMD 2244 { 2245 union 2246 { 2247 //!< DWORD 0 2248 struct 2249 { 2250 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2251 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2252 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 2253 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 2254 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 2255 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2256 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2257 }; 2258 uint32_t Value; 2259 } DW0; 2260 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef0 ; //!< DS FWD REF0 2261 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef1 ; //!< DS FWD REF1 2262 VDENC_Down_Scaled_Reference_Picture_CMD DsBwdRef0 ; //!< DS BWD REF0 2263 VDENC_Original_Uncompressed_Picture_CMD OriginalUncompressedPicture ; //!< Original Uncompressed Picture 2264 VDENC_Streamin_Data_Picture_CMD StreaminDataPicture ; //!< Streamin Data Picture 2265 VDENC_Row_Store_Scratch_Buffer_Picture_CMD RowStoreScratchBuffer ; //!< Row Store Scratch Buffer 2266 VDENC_Colocated_MV_Picture_CMD ColocatedMv ; //!< Colocated MV 2267 VDENC_Reference_Picture_CMD FwdRef0 ; //!< FWD REF0 2268 VDENC_Reference_Picture_CMD FwdRef1 ; //!< FWD REF1 2269 VDENC_Reference_Picture_CMD FwdRef2 ; //!< FWD REF2 2270 VDENC_Reference_Picture_CMD BwdRef0 ; //!< BWD REF0 2271 VDENC_Statistics_Streamout_CMD VdencStatisticsStreamout ; //!< VDEnc Statistics Streamout 2272 2273 //! \name Local enumerations 2274 2275 enum SUBOPB 2276 { 2277 SUBOPB_VDENCPIPEBUFADDRSTATE = 4, //!< No additional details 2278 }; 2279 2280 enum SUBOPA 2281 { 2282 SUBOPA_UNNAMED0 = 0, //!< No additional details 2283 }; 2284 2285 enum OPCODE 2286 { 2287 OPCODE_VDENCPIPE = 1, //!< No additional details 2288 }; 2289 2290 enum PIPELINE 2291 { 2292 PIPELINE_MFXCOMMON = 2, //!< No additional details 2293 }; 2294 2295 enum COMMAND_TYPE 2296 { 2297 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2298 }; 2299 2300 //! \name Initializations 2301 2302 //! \brief Explicit member initialization function 2303 VDENC_PIPE_BUF_ADDR_STATE_CMD(); 2304 2305 static const size_t dwSize = 37; 2306 static const size_t byteSize = 148; 2307 }; 2308 2309 //! 2310 //! \brief VDENC_PIPE_MODE_SELECT 2311 //! \details 2312 //! Specifies which codec and hardware module is being used to encode/decode 2313 //! the video data, on a per-frame basis. The VDENC_PIPE_MODE_SELECT command 2314 //! specifies which codec and hardware module is being used to encode/decode 2315 //! the video data, on a per-frame basis. It also configures the hardware 2316 //! pipeline according to the active encoder/decoder operating mode for 2317 //! encoding/decoding the current picture. 2318 //! 2319 struct VDENC_PIPE_MODE_SELECT_CMD 2320 { 2321 union 2322 { 2323 //!< DWORD 0 2324 struct 2325 { 2326 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2327 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2328 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 2329 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 2330 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 2331 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2332 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2333 }; 2334 uint32_t Value; 2335 } DW0; 2336 union 2337 { 2338 //!< DWORD 1 2339 struct 2340 { 2341 uint32_t StandardSelect : __CODEGEN_BITFIELD( 0, 3) ; //!< STANDARD_SELECT 2342 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 2343 uint32_t FrameStatisticsStreamOutEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< FRAME_STATISTICS_STREAM_OUT_ENABLE 2344 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 6) ; //!< Reserved 2345 uint32_t TlbPrefetchEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< TLB_PREFETCH_ENABLE 2346 uint32_t PakThresholdCheckEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< PAK_THRESHOLD_CHECK_ENABLE 2347 uint32_t VdencStreamInEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< VDENC_STREAM_IN_ENABLE 2348 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 14) ; //!< Reserved 2349 uint32_t PakChromaSubSamplingType : __CODEGEN_BITFIELD(15, 16) ; //!< PAK_CHROMA_SUB_SAMPLING_TYPE 2350 uint32_t OutputRangeControlAfterColorSpaceConversion : __CODEGEN_BITFIELD(17, 17) ; //!< output range control after color space conversion 2351 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 2352 uint32_t DisableSpeedModeFetchOptimization : __CODEGEN_BITFIELD(31, 31) ; //!< Disable Speed Mode fetch optimization 2353 }; 2354 uint32_t Value; 2355 } DW1; 2356 2357 //! \name Local enumerations 2358 2359 enum SUBOPB 2360 { 2361 SUBOPB_VDENCPIPEMODESELECT = 0, //!< No additional details 2362 }; 2363 2364 enum SUBOPA 2365 { 2366 SUBOPA_UNNAMED0 = 0, //!< No additional details 2367 }; 2368 2369 enum OPCODE 2370 { 2371 OPCODE_VDENCPIPE = 1, //!< No additional details 2372 }; 2373 2374 enum PIPELINE 2375 { 2376 PIPELINE_MFXCOMMON = 2, //!< No additional details 2377 }; 2378 2379 enum COMMAND_TYPE 2380 { 2381 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2382 }; 2383 2384 enum STANDARD_SELECT 2385 { 2386 STANDARD_SELECT_AVC = 2, //!< No additional details 2387 }; 2388 2389 //! \brief FRAME_STATISTICS_STREAM_OUT_ENABLE 2390 //! \details 2391 //! This field controls whether the frame statistics stream-out is enabled. 2392 enum FRAME_STATISTICS_STREAM_OUT_ENABLE 2393 { 2394 FRAME_STATISTICS_STREAM_OUT_ENABLE_DISABLE = 0, //!< No additional details 2395 FRAME_STATISTICS_STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 2396 }; 2397 2398 //! \brief TLB_PREFETCH_ENABLE 2399 //! \details 2400 //! This field controls whether TLB prefetching is enabled. 2401 enum TLB_PREFETCH_ENABLE 2402 { 2403 TLB_PREFETCH_ENABLE_DISABLE = 0, //!< No additional details 2404 TLB_PREFETCH_ENABLE_ENABLE = 1, //!< No additional details 2405 }; 2406 2407 //! \brief PAK_THRESHOLD_CHECK_ENABLE 2408 //! \details 2409 //! <p>For AVC standard: This field controls whether VDEnc will check the 2410 //! PAK indicator for bits overflow and terminates the slice. This mode is 2411 //! called Dynamic Slice Mode. When this field is disabled, VDEnc is in 2412 //! Static Slice Mode. It uses the driver programmed Slice Macroblock Height 2413 //! Minus One to terminate the slice. This feature is also referred to as 2414 //! slice size conformance.</p> 2415 //! <p>For HEVC standard: This bit is used to enable dynamic slice size 2416 //! control.</p> 2417 enum PAK_THRESHOLD_CHECK_ENABLE 2418 { 2419 PAK_THRESHOLD_CHECK_ENABLE_DISABLESTATICSLICEMODE = 0, //!< No additional details 2420 PAK_THRESHOLD_CHECK_ENABLE_ENABLEDYNAMICSLICEMODE = 1, //!< No additional details 2421 }; 2422 2423 //! \brief VDENC_STREAM_IN_ENABLE 2424 //! \details 2425 //! <p>This field controls whether VDEnc will read the stream-in surface 2426 //! that is programmed. Currently the stream-in surface has MB level QP, 2427 //! ROI, predictors and MaxSize/TargetSizeinWordsMB parameters. The 2428 //! individual enables for each of the fields is programmed in the 2429 //! VDENC_IMG_STATE.</p> 2430 //! <p>(ROI_Enable, Fwd/Predictor0 MV Enable, Bwd/Predictor1 MV Enable, MB 2431 //! Level QP Enable, TargetSizeinWordsMB/MaxSizeinWordsMB Enable).</p> 2432 //! <p>This bit is valid only in AVC mode. In HEVC / VP9 mode this bit is 2433 //! reserved and should be set to zero.</p> 2434 enum VDENC_STREAM_IN_ENABLE 2435 { 2436 VDENC_STREAM_IN_ENABLE_DISABLE = 0, //!< No additional details 2437 VDENC_STREAM_IN_ENABLE_ENABLE = 1, //!< No additional details 2438 }; 2439 2440 //! \brief PAK_CHROMA_SUB_SAMPLING_TYPE 2441 //! \details 2442 //! <p>This field is applicable only in HEVC and VP9. In AVC, this field is 2443 //! ignored.</p> 2444 //! <p></p> 2445 enum PAK_CHROMA_SUB_SAMPLING_TYPE 2446 { 2447 PAK_CHROMA_SUB_SAMPLING_TYPE_420 = 1, //!< Used for Main8 and Main10 HEVC, VP9 profile0, AVC. 2448 PAK_CHROMA_SUB_SAMPLING_TYPE_444 = 3, //!< HEVC RExt 444, VP9 444 profiles. 2449 }; 2450 2451 //! \name Initializations 2452 2453 //! \brief Explicit member initialization function 2454 VDENC_PIPE_MODE_SELECT_CMD(); 2455 2456 static const size_t dwSize = 2; 2457 static const size_t byteSize = 8; 2458 }; 2459 2460 //! 2461 //! \brief VDENC_REF_SURFACE_STATE 2462 //! \details 2463 //! This command specifies the surface state parameters for the normal 2464 //! reference surfaces. 2465 //! 2466 struct VDENC_REF_SURFACE_STATE_CMD 2467 { 2468 union 2469 { 2470 //!< DWORD 0 2471 struct 2472 { 2473 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2474 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2475 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 2476 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 2477 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 2478 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2479 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2480 }; 2481 uint32_t Value; 2482 } DW0; 2483 union 2484 { 2485 //!< DWORD 1 2486 struct 2487 { 2488 uint32_t Reserved32 ; //!< Reserved 2489 }; 2490 uint32_t Value; 2491 } DW1; 2492 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 2493 2494 //! \name Local enumerations 2495 2496 enum SUBOPB 2497 { 2498 SUBOPB_VDENCREFSURFACESTATE = 2, //!< No additional details 2499 }; 2500 2501 enum SUBOPA 2502 { 2503 SUBOPA_UNNAMED0 = 0, //!< No additional details 2504 }; 2505 2506 enum OPCODE 2507 { 2508 OPCODE_VDENCPIPE = 1, //!< No additional details 2509 }; 2510 2511 enum PIPELINE 2512 { 2513 PIPELINE_MFXCOMMON = 2, //!< No additional details 2514 }; 2515 2516 enum COMMAND_TYPE 2517 { 2518 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2519 }; 2520 2521 //! \name Initializations 2522 2523 //! \brief Explicit member initialization function 2524 VDENC_REF_SURFACE_STATE_CMD(); 2525 2526 static const size_t dwSize = 6; 2527 static const size_t byteSize = 24; 2528 }; 2529 2530 //! 2531 //! \brief VDENC_SRC_SURFACE_STATE 2532 //! \details 2533 //! This command specifies the uncompressed original input picture to be 2534 //! encoded. The actual base address is defined in the 2535 //! VDENC_PIPE_BUF_ADDR_STATE. Pitch can be wider than the Picture Width in 2536 //! pixels and garbage will be there at the end of each line. The following 2537 //! describes all the different formats that are supported in WLV+ VDEnc: 2538 //! NV12 - 4:2:0 only; UV interleaved; Full Pitch, U and V offset is set to 2539 //! 0 (the only format supported for video codec); vertical UV offset is MB 2540 //! aligned; UV xoffsets = 0. 2541 //! This surface state here is identical to the Surface State for 2542 //! deinterlace and sample_8x8 messages described in the Shared Function 2543 //! Volume and Sampler Chapter. For non pixel data, such as row stores, DMV 2544 //! and streamin/out, a linear buffer is employed. For row stores, the H/W 2545 //! is designed to guarantee legal memory accesses (read and write). For the 2546 //! remaining cases, indirect object base address, indirect object address 2547 //! upper bound, object data start address (offset) and object data length 2548 //! are used to fully specified their corresponding buffer. This mechanism 2549 //! is chosen over the pixel surface type because of their variable record 2550 //! sizes. All row store surfaces are linear surface. Their addresses are 2551 //! programmed in VDEnc_Pipe_Buf_Base_State. 2552 //! 2553 struct VDENC_SRC_SURFACE_STATE_CMD 2554 { 2555 union 2556 { 2557 //!< DWORD 0 2558 struct 2559 { 2560 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2561 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2562 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 2563 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 2564 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 2565 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2566 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2567 }; 2568 uint32_t Value; 2569 } DW0; 2570 union 2571 { 2572 //!< DWORD 1 2573 struct 2574 { 2575 uint32_t Reserved32 ; //!< Reserved 2576 }; 2577 uint32_t Value; 2578 } DW1; 2579 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 2580 2581 //! \name Local enumerations 2582 2583 enum SUBOPB 2584 { 2585 SUBOPB_VDENCSRCSURFACESTATE = 1, //!< No additional details 2586 }; 2587 2588 enum SUBOPA 2589 { 2590 SUBOPA_UNNAMED0 = 0, //!< No additional details 2591 }; 2592 2593 enum OPCODE 2594 { 2595 OPCODE_VDENCPIPE = 1, //!< No additional details 2596 }; 2597 2598 enum PIPELINE 2599 { 2600 PIPELINE_MFXCOMMON = 2, //!< No additional details 2601 }; 2602 2603 enum COMMAND_TYPE 2604 { 2605 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2606 }; 2607 2608 //! \name Initializations 2609 2610 //! \brief Explicit member initialization function 2611 VDENC_SRC_SURFACE_STATE_CMD(); 2612 2613 static const size_t dwSize = 6; 2614 static const size_t byteSize = 24; 2615 }; 2616 2617 //! 2618 //! \brief VDENC_WALKER_STATE 2619 //! \details 2620 //! This command provides the macroblock start location for the VDEnc 2621 //! walker. Current programming to always have this command at the frame 2622 //! level, hence the macroblock X,Y location need to be programmed to 0,0 to 2623 //! always start at frame origin. Once the hardware receives this command 2624 //! packet, it internally starts the VDEnc pipeline. This should be the last 2625 //! command that is programmed for the VDEnc pipeline. 2626 //! 2627 struct VDENC_WALKER_STATE_CMD 2628 { 2629 union 2630 { 2631 //!< DWORD 0 2632 struct 2633 { 2634 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2635 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2636 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 2637 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 2638 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 2639 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2640 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2641 }; 2642 uint32_t Value; 2643 } DW0; 2644 union 2645 { 2646 //!< DWORD 1 2647 struct 2648 { 2649 uint32_t MbLcuStartYPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< MB/LCU Start Y Position 2650 uint32_t Reserved41 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2651 uint32_t MbLcuStartXPosition : __CODEGEN_BITFIELD(16, 24) ; //!< MB/LCU Start X Position 2652 uint32_t Reserved57 : __CODEGEN_BITFIELD(25, 27) ; //!< Reserved 2653 uint32_t FirstSuperSlice : __CODEGEN_BITFIELD(28, 28) ; //!< First Super Slice 2654 uint32_t Reserved61 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2655 }; 2656 uint32_t Value; 2657 } DW1; 2658 2659 //! \name Local enumerations 2660 2661 enum SUBOPB 2662 { 2663 SUBOPB_VDENCWALKERSTATE = 7, //!< No additional details 2664 }; 2665 2666 enum SUBOPA 2667 { 2668 SUBOPA_UNNAMED0 = 0, //!< No additional details 2669 }; 2670 2671 enum OPCODE 2672 { 2673 OPCODE_VDENCPIPE = 1, //!< No additional details 2674 }; 2675 2676 enum PIPELINE 2677 { 2678 PIPELINE_MFXCOMMON = 2, //!< No additional details 2679 }; 2680 2681 enum COMMAND_TYPE 2682 { 2683 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2684 }; 2685 2686 //! \name Initializations 2687 2688 //! \brief Explicit member initialization function 2689 VDENC_WALKER_STATE_CMD(); 2690 2691 static const size_t dwSize = 2; 2692 static const size_t byteSize = 8; 2693 }; 2694 2695 }; 2696 2697 #pragma pack() 2698 2699 #endif // __MHW_VDBOX_VDENC_HWCMD_G9_SKL_H__ 2700