1 /**
2 VIDIX driver for SiS 300 and 310/325 series chips.
3
4 Copyright 2003 Jake Page, Sugar Media.
5
6 Based on SiS Xv driver:
7 Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22
23 2003/10/08 integrated into mplayer/vidix architecture -- Alex Beregszaszi
24 **/
25
26 #include <errno.h>
27 #include <stdio.h>
28 #include <stdlib.h>
29 #include <string.h>
30 #include <inttypes.h>
31 #include <unistd.h>
32
33 #include "vidix.h"
34 #include "fourcc.h"
35 #include "libdha.h"
36 #include "pci_ids.h"
37 #include "pci_names.h"
38
39 #include "sis_regs.h"
40 #include "sis_defs.h"
41
42
43 /** Random defines **/
44
45 #define WATCHDOG_DELAY 500000 /* Watchdog counter for retrace waiting */
46 #define IMAGE_MIN_WIDTH 32 /* Min and max source image sizes */
47 #define IMAGE_MIN_HEIGHT 24
48 #define IMAGE_MAX_WIDTH 720
49 #define IMAGE_MAX_HEIGHT 576
50 #define IMAGE_MAX_WIDTH_M650 1920
51 #define IMAGE_MAX_HEIGHT_M650 1080
52
53 #define OVERLAY_MIN_WIDTH 32 /* Minimum overlay sizes */
54 #define OVERLAY_MIN_HEIGHT 24
55
56 #define DISPMODE_SINGLE1 0x1 /* TW: CRT1 only */
57 #define DISPMODE_SINGLE2 0x2 /* TW: CRT2 only */
58 #define DISPMODE_MIRROR 0x4 /* TW: CRT1 + CRT2 MIRROR */
59
60 #define VMODE_INTERLACED 0x1
61 #define VMODE_DOUBLESCAN 0x2
62
63 typedef struct {
64 short x1, y1, x2, y2;
65 } BoxRec;
66
67 typedef struct {
68 int pixelFormat;
69
70 uint16_t pitch;
71 uint16_t origPitch;
72
73 uint8_t keyOP;
74 uint16_t HUSF;
75 uint16_t VUSF;
76 uint8_t IntBit;
77 uint8_t wHPre;
78
79 uint16_t srcW;
80 uint16_t srcH;
81
82 BoxRec dstBox;
83
84 uint32_t PSY;
85 uint32_t PSV;
86 uint32_t PSU;
87 uint8_t bobEnable;
88
89 uint8_t contrastCtrl;
90 uint8_t contrastFactor;
91
92 uint8_t lineBufSize;
93
94 uint8_t(*VBlankActiveFunc) ();
95
96 uint16_t SCREENheight;
97
98 } SISOverlayRec, *SISOverlayPtr;
99
100
101 /** static variable definitions **/
102 static int sis_probed = 0;
103 static pciinfo_t pci_info;
104 unsigned int sis_verbose = 0;
105
106 static uint8_t *sis_mem_base;
107 /* static void *sis_reg_base; */
108 unsigned short sis_iobase;
109
110 unsigned int sis_vga_engine = UNKNOWN_VGA;
111 static unsigned int sis_displaymode = DISPMODE_SINGLE1;
112 static unsigned int sis_has_two_overlays = 0;
113 static unsigned int sis_bridge_is_slave = 0;
114 static unsigned int sis_shift_value = 1;
115 static unsigned int sis_vmode = 0;
116 unsigned int sis_vbflags = DISPTYPE_DISP1;
117 unsigned int sis_overlay_on_crt1 = 1;
118 unsigned int sis_crt1_off = -1;
119 unsigned int sis_detected_crt2_devices;
120 unsigned int sis_force_crt2_type = CRT2_DEFAULT;
121 unsigned int sis_device_id = -1;
122
123 static int sis_format;
124 static int sis_Yoff = 0;
125 static int sis_Voff = 0;
126 static int sis_Uoff = 0;
127 static int sis_screen_width = 640;
128 static int sis_screen_height = 480;
129
130 static int sis_frames[VID_PLAY_MAXFRAMES];
131
132 static vidix_grkey_t sis_grkey;
133
134 static vidix_capability_t sis_cap = {
135 "SiS 300/310/325 Video Driver",
136 "Jake Page",
137 TYPE_OUTPUT,
138 {0, 0, 0, 0},
139 2048,
140 2048,
141 4,
142 4,
143 -1,
144 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER,
145 VENDOR_SIS,
146 -1,
147 {0, 0, 0, 0}
148 };
149
150 vidix_video_eq_t sis_equal = {
151 VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST,
152 200, 0, 0, 0, 0, 0, 0, 0
153 };
154
155 static unsigned short sis_card_ids[] = {
156 DEVICE_SIS_300,
157 DEVICE_SIS_315H,
158 DEVICE_SIS_315,
159 DEVICE_SIS_315PRO,
160 DEVICE_SIS_330,
161 DEVICE_SIS_540_VGA,
162 DEVICE_SIS_550_VGA,
163 DEVICE_SIS_630_VGA,
164 DEVICE_SIS_650_VGA
165 };
166
167 /** function declarations **/
168
169 extern void sis_init_video_bridge();
170
171
172 static void set_overlay(SISOverlayPtr pOverlay, int index);
173 static void close_overlay(void);
174 static void calc_scale_factor(SISOverlayPtr pOverlay,
175 int index, int iscrt2);
176 static void set_line_buf_size(SISOverlayPtr pOverlay);
177 static void merge_line_buf(int enable);
178 static void set_format(SISOverlayPtr pOverlay);
179 static void set_colorkey(void);
180
181 static void set_brightness(uint8_t brightness);
182 static void set_contrast(uint8_t contrast);
183 static void set_saturation(char saturation);
184 static void set_hue(uint8_t hue);
185 #if 0
186 static void set_alpha(uint8_t alpha);
187 #endif
188
189 /* IO Port access functions */
getvideoreg(uint8_t reg)190 static uint8_t getvideoreg(uint8_t reg)
191 {
192 uint8_t ret;
193 inSISIDXREG(SISVID, reg, ret);
194 return (ret);
195 }
196
setvideoreg(uint8_t reg,uint8_t data)197 static void setvideoreg(uint8_t reg, uint8_t data)
198 {
199 outSISIDXREG(SISVID, reg, data);
200 }
201
setvideoregmask(uint8_t reg,uint8_t data,uint8_t mask)202 static void setvideoregmask(uint8_t reg, uint8_t data, uint8_t mask)
203 {
204 uint8_t old;
205
206 inSISIDXREG(SISVID, reg, old);
207 data = (data & mask) | (old & (~mask));
208 outSISIDXREG(SISVID, reg, data);
209 }
210
setsrregmask(uint8_t reg,uint8_t data,uint8_t mask)211 static void setsrregmask(uint8_t reg, uint8_t data, uint8_t mask)
212 {
213 uint8_t old;
214
215 inSISIDXREG(SISSR, reg, old);
216 data = (data & mask) | (old & (~mask));
217 outSISIDXREG(SISSR, reg, data);
218 }
219
220 /* vblank checking*/
vblank_active_CRT1()221 static uint8_t vblank_active_CRT1()
222 {
223 /* this may be too simplistic? */
224 return (inSISREG(SISINPSTAT) & 0x08);
225 }
226
vblank_active_CRT2()227 static uint8_t vblank_active_CRT2()
228 {
229 uint8_t ret;
230 if (sis_vga_engine == SIS_315_VGA) {
231 inSISIDXREG(SISPART1, Index_310_CRT2_FC_VR, ret);
232 } else {
233 inSISIDXREG(SISPART1, Index_CRT2_FC_VR, ret);
234 }
235 return ((ret & 0x02) ^ 0x02);
236 }
237
238
vixGetVersion(void)239 unsigned int vixGetVersion(void)
240 {
241 return (VIDIX_VERSION);
242 }
243
find_chip(unsigned chip_id)244 static int find_chip(unsigned chip_id)
245 {
246 unsigned i;
247 for (i = 0; i < sizeof(sis_card_ids) / sizeof(unsigned short); i++) {
248 if (chip_id == sis_card_ids[i])
249 return i;
250 }
251 return -1;
252 }
253
vixProbe(int verbose,int force)254 int vixProbe(int verbose, int force)
255 {
256 pciinfo_t lst[MAX_PCI_DEVICES];
257 unsigned i, num_pci;
258 int err;
259
260 sis_verbose = verbose;
261 force = force;
262 err = pci_scan(lst, &num_pci);
263 if (err) {
264 printf("[SiS] Error occurred during pci scan: %s\n", strerror(err));
265 return err;
266 } else if(!enable_app_io()){
267 err = ENXIO;
268 for (i = 0; i < num_pci; i++) {
269 if (lst[i].vendor == VENDOR_SIS) {
270 int idx;
271 const char *dname;
272 idx = find_chip(lst[i].device);
273 if (idx == -1)
274 continue;
275 dname = pci_device_name(VENDOR_SIS, lst[i].device);
276 dname = dname ? dname : "Unknown chip";
277 if (sis_verbose > 0)
278 printf("[SiS] Found chip: %s (0x%X)\n",
279 dname, lst[i].device);
280 sis_device_id = sis_cap.device_id = lst[i].device;
281 err = 0;
282 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
283
284 sis_has_two_overlays = 0;
285 switch (sis_cap.device_id) {
286 case DEVICE_SIS_300:
287 case DEVICE_SIS_630_VGA:
288 sis_has_two_overlays = 1;
289 case DEVICE_SIS_540_VGA:
290 sis_vga_engine = SIS_300_VGA;
291 break;
292 case DEVICE_SIS_330:
293 case DEVICE_SIS_550_VGA:
294 sis_has_two_overlays = 1;
295 case DEVICE_SIS_315H:
296 case DEVICE_SIS_315:
297 case DEVICE_SIS_315PRO:
298 case DEVICE_SIS_650_VGA:
299 /* M650 & 651 have 2 overlays */
300 /* JCP: I think this works, but not really tested yet */
301 {
302 unsigned char CR5F;
303 unsigned char tempreg1, tempreg2;
304
305 inSISIDXREG(SISCR, 0x5F, CR5F);
306 CR5F &= 0xf0;
307 andSISIDXREG(SISCR, 0x5c, 0x07);
308 inSISIDXREG(SISCR, 0x5c, tempreg1);
309 tempreg1 &= 0xf8;
310 setSISIDXREG(SISCR, 0x5c, 0x07, 0xf8);
311 inSISIDXREG(SISCR, 0x5c, tempreg2);
312 tempreg2 &= 0xf8;
313 if ((!tempreg1) || (tempreg2)) {
314 if (CR5F & 0x80) {
315 sis_has_two_overlays = 1;
316 }
317 } else {
318 sis_has_two_overlays = 1; /* ? */
319 }
320 if (sis_has_two_overlays) {
321 if (sis_verbose > 0)
322 printf
323 ("[SiS] detected M650/651 with 2 overlays\n");
324 }
325 }
326 sis_vga_engine = SIS_315_VGA;
327 break;
328 default:
329 /* should never get here */
330 sis_vga_engine = UNKNOWN_VGA;
331 break;
332 }
333 }
334 }
335 } else {
336 err = EPERM;
337 }
338
339 if (err && sis_verbose) {
340 printf("[SiS] Can't find chip\n");
341 } else {
342 sis_probed = 1;
343 }
344
345 return err;
346 }
347
vixInit(const char * args)348 int vixInit(const char *args)
349 {
350 uint8_t sr_data, cr_data, cr_data2;
351 char *env_overlay_crt;
352
353 (void)args;
354 if (!sis_probed) {
355 printf("[SiS] driver was not probed but is being initialized\n");
356 return (EINTR);
357 }
358
359 /* JCP: this is WRONG. Need to coordinate w/ sisfb to use correct mem */
360 /* map 16MB scary hack for now. */
361 sis_mem_base = map_phys_mem(pci_info.base0, 0x1000000);
362 /* sis_reg_base = map_phys_mem(pci_info.base1, 0x20000); */
363 sis_iobase = pci_info.base2 & 0xFFFC;
364
365 /* would like to use fb ioctl - or some other method - here to get
366 current resolution. */
367 inSISIDXREG(SISCR, 0x12, cr_data);
368 inSISIDXREG(SISCR, 0x07, cr_data2);
369 sis_screen_height =
370 ((cr_data & 0xff) | ((uint16_t) (cr_data2 & 0x02) << 7) |
371 ((uint16_t) (cr_data2 & 0x40) << 3) | ((uint16_t) (cr_data & 0x02)
372 << 9)) + 1;
373
374 inSISIDXREG(SISSR, 0x0b, sr_data);
375 inSISIDXREG(SISCR, 0x01, cr_data);
376 sis_screen_width = (((cr_data & 0xff) |
377 ((uint16_t) (sr_data & 0x0C) << 6)) + 1) * 8;
378
379 inSISIDXREG(SISSR, Index_SR_Graphic_Mode, sr_data);
380 if (sr_data & 0x20) /* interlaced mode */
381 sis_vmode |= VMODE_INTERLACED;
382
383 #if 0 /* getting back false data here... */
384 /* CR9 bit 7 set = double scan active */
385 inSISIDXREG(SISCR, 0x09, cr_data);
386 if (cr_data & 0x40) {
387 sis_vmode |= VMODE_DOUBLESCAN;
388 }
389 #endif
390
391 /* JCP: eventually I'd like to replace this with a call to sisfb
392 SISFB_GET_INFO ioctl to get video bridge info. Not for now,
393 since it requires a very new and not widely distributed version. */
394 sis_init_video_bridge();
395
396 env_overlay_crt = getenv("VIDIX_CRT");
397 if (env_overlay_crt) {
398 int crt = atoi(env_overlay_crt);
399 if (crt == 1 || crt == 2) {
400 sis_overlay_on_crt1 = (crt == 1);
401 if (sis_verbose > 0) {
402 printf
403 ("[SiS] override: using overlay on CRT%d from VIDIX_CRT\n",
404 crt);
405 }
406 }
407 }
408
409 return 0;
410 }
411
vixDestroy(void)412 void vixDestroy(void)
413 {
414 /* unmap_phys_mem(sis_reg_base, 0x20000); */
415 /* JCP: see above, hence also a hack. */
416 unmap_phys_mem(sis_mem_base, 0x1000000);
417 }
418
vixGetCapability(vidix_capability_t * to)419 int vixGetCapability(vidix_capability_t * to)
420 {
421 memcpy(to, &sis_cap, sizeof(vidix_capability_t));
422 return 0;
423 }
424
is_supported_fourcc(uint32_t fourcc)425 static int is_supported_fourcc(uint32_t fourcc)
426 {
427 switch (fourcc) {
428 case IMGFMT_YV12:
429 case IMGFMT_I420:
430 case IMGFMT_UYVY:
431 case IMGFMT_YUY2:
432 case IMGFMT_RGB15:
433 case IMGFMT_RGB16:
434 return 1;
435 default:
436 return 0;
437 }
438 }
439
vixQueryFourcc(vidix_fourcc_t * to)440 int vixQueryFourcc(vidix_fourcc_t * to)
441 {
442 if (is_supported_fourcc(to->fourcc)) {
443 to->depth = VID_DEPTH_8BPP | VID_DEPTH_16BPP | VID_DEPTH_32BPP;
444 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
445 return 0;
446 } else
447 to->depth = to->flags = 0;
448 return ENOSYS;
449 }
450
bridge_in_slave_mode()451 static int bridge_in_slave_mode()
452 {
453 unsigned char usScratchP1_00;
454
455 if (!(sis_vbflags & VB_VIDEOBRIDGE))
456 return 0;
457
458 inSISIDXREG(SISPART1, 0x00, usScratchP1_00);
459 if (((sis_vga_engine == SIS_300_VGA)
460 && (usScratchP1_00 & 0xa0) == 0x20)
461 || ((sis_vga_engine == SIS_315_VGA)
462 && (usScratchP1_00 & 0x50) == 0x10)) {
463 return 1;
464 } else {
465 return 0;
466 }
467 }
468
469 /* This does not handle X dual head mode, since 1) vidix doesn't support it
470 and 2) it doesn't make sense for other gfx drivers */
set_dispmode()471 static void set_dispmode()
472 {
473 sis_bridge_is_slave = 0;
474
475 if (bridge_in_slave_mode())
476 sis_bridge_is_slave = 1;
477
478 if ((sis_vbflags & VB_DISPMODE_MIRROR) ||
479 (sis_bridge_is_slave && (sis_vbflags & DISPTYPE_DISP2))) {
480 if (sis_has_two_overlays)
481 sis_displaymode = DISPMODE_MIRROR; /* TW: CRT1+CRT2 (2 overlays) */
482 else if (!sis_overlay_on_crt1)
483 sis_displaymode = DISPMODE_SINGLE2;
484 else
485 sis_displaymode = DISPMODE_SINGLE1;
486 } else {
487 if (sis_vbflags & DISPTYPE_DISP1) {
488 sis_displaymode = DISPMODE_SINGLE1; /* TW: CRT1 only */
489 } else {
490 sis_displaymode = DISPMODE_SINGLE2; /* TW: CRT2 only */
491 }
492 }
493 }
494
set_disptype_regs()495 static void set_disptype_regs()
496 {
497 switch (sis_displaymode) {
498 case DISPMODE_SINGLE1: /* TW: CRT1 only */
499 if (sis_verbose > 2) {
500 printf("[SiS] Setting up overlay on CRT1\n");
501 }
502 if (sis_has_two_overlays) {
503 setsrregmask(0x06, 0x00, 0xc0);
504 setsrregmask(0x32, 0x00, 0xc0);
505 } else {
506 setsrregmask(0x06, 0x00, 0xc0);
507 setsrregmask(0x32, 0x00, 0xc0);
508 }
509 break;
510 case DISPMODE_SINGLE2: /* TW: CRT2 only */
511 if (sis_verbose > 2) {
512 printf("[SiS] Setting up overlay on CRT2\n");
513 }
514 if (sis_has_two_overlays) {
515 setsrregmask(0x06, 0x80, 0xc0);
516 setsrregmask(0x32, 0x80, 0xc0);
517 } else {
518 setsrregmask(0x06, 0x40, 0xc0);
519 setsrregmask(0x32, 0x40, 0xc0);
520 }
521 break;
522 case DISPMODE_MIRROR: /* TW: CRT1 + CRT2 */
523 default:
524 if (sis_verbose > 2) {
525 printf("[SiS] Setting up overlay on CRT1 AND CRT2!\n");
526 }
527 setsrregmask(0x06, 0x80, 0xc0);
528 setsrregmask(0x32, 0x80, 0xc0);
529 break;
530 }
531 }
532
init_overlay()533 static void init_overlay()
534 {
535 /* Initialize first overlay (CRT1) */
536
537 /* Write-enable video registers */
538 setvideoregmask(Index_VI_Control_Misc2, 0x80, 0x81);
539
540 /* Disable overlay */
541 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
542
543 /* Disable bobEnable */
544 setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02);
545
546 /* Reset scale control and contrast */
547 setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60);
548 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F);
549
550 setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00);
551 setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00);
552 setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00);
553 setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00);
554 setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00);
555 setvideoreg(Index_VI_Play_Threshold_Low, 0x00);
556 setvideoreg(Index_VI_Play_Threshold_High, 0x00);
557
558 /* may not want to init these here, could already be set to other
559 values by app? */
560 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01);
561 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07);
562 setvideoreg(Index_VI_Brightness, 0x20);
563 if (sis_vga_engine == SIS_315_VGA) {
564 setvideoreg(Index_VI_Hue, 0x00);
565 setvideoreg(Index_VI_Saturation, 0x00);
566 }
567
568 /* Initialize second overlay (CRT2) */
569 if (sis_has_two_overlays) {
570 /* Write-enable video registers */
571 setvideoregmask(Index_VI_Control_Misc2, 0x81, 0x81);
572
573 /* Disable overlay */
574 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
575
576 /* Disable bobEnable */
577 setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02);
578
579 /* Reset scale control and contrast */
580 setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60);
581 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F);
582
583 setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00);
584 setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00);
585 setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00);
586 setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00);
587 setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00);
588 setvideoreg(Index_VI_Play_Threshold_Low, 0x00);
589 setvideoreg(Index_VI_Play_Threshold_High, 0x00);
590
591 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01);
592 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07);
593 setvideoreg(Index_VI_Brightness, 0x20);
594 if (sis_vga_engine == SIS_315_VGA) {
595 setvideoreg(Index_VI_Hue, 0x00);
596 setvideoreg(Index_VI_Saturation, 0x00);
597 }
598 }
599 }
600
vixConfigPlayback(vidix_playback_t * info)601 int vixConfigPlayback(vidix_playback_t * info)
602 {
603 SISOverlayRec overlay;
604 int srcOffsetX = 0, srcOffsetY = 0;
605 int sx, sy;
606 int index = 0, iscrt2 = 0;
607 int total_size;
608
609 short src_w, drw_w;
610 short src_h, drw_h;
611 short src_x, drw_x;
612 short src_y, drw_y;
613 long dga_offset;
614 int pitch;
615 unsigned int i;
616
617 if (!is_supported_fourcc(info->fourcc))
618 return -1;
619
620 /* set chipset/engine.dependent config info */
621 /* which CRT to use, etc.? */
622 switch (sis_vga_engine) {
623 case SIS_315_VGA:
624 sis_shift_value = 1;
625 sis_equal.cap |= VEQ_CAP_SATURATION | VEQ_CAP_HUE;
626 break;
627 case SIS_300_VGA:
628 default:
629 sis_shift_value = 2;
630 break;
631 }
632
633 sis_displaymode = DISPMODE_SINGLE1; /* xV driver code in set_dispmode() */
634 set_dispmode();
635
636 set_disptype_regs();
637
638 init_overlay();
639
640 /* get basic dimension info */
641 src_x = info->src.x;
642 src_y = info->src.y;
643 src_w = info->src.w;
644 src_h = info->src.h;
645
646 drw_x = info->dest.x;
647 drw_y = info->dest.y;
648 drw_w = info->dest.w;
649 drw_h = info->dest.h;
650
651 switch (info->fourcc) {
652 case IMGFMT_YV12:
653 case IMGFMT_I420:
654 pitch = (src_w + 7) & ~7;
655 total_size = (pitch * src_h * 3) >> 1;
656 break;
657 case IMGFMT_YUY2:
658 case IMGFMT_UYVY:
659 case IMGFMT_RGB15:
660 case IMGFMT_RGB16:
661 pitch = ((src_w << 1) + 3) & ~3;
662 total_size = pitch * src_h;
663 break;
664 default:
665 return -1;
666 }
667
668 /* "allocate" memory for overlay! */
669 /* start at 8MB = sisfb's "dri reserved space" -
670 really shouldn't hardcode though */
671 /* XXX: JCP - this can use the sisfb FBIO_ALLOC ioctl to safely
672 allocate "video heap" memory... */
673 dga_offset = 0x800000;
674
675 /* use 7MB for now. need to calc/get real info from sisfb? */
676 /* this can result in a LOT of frames - probably not necessary */
677 info->num_frames = 0x700000 / (total_size * 2);
678 if (info->num_frames > VID_PLAY_MAXFRAMES)
679 info->num_frames = VID_PLAY_MAXFRAMES;
680
681 info->dga_addr = sis_mem_base + dga_offset;
682 info->dest.pitch.y = 16;
683 info->dest.pitch.u = 16;
684 info->dest.pitch.v = 16;
685 info->offset.y = 0;
686 info->offset.u = 0;
687 info->offset.v = 0;
688 info->frame_size = (total_size * 2); /* why times 2 ? */
689 for (i = 0; i < info->num_frames; i++) {
690 info->offsets[i] = info->frame_size * i;
691 /* save ptrs to mem buffers */
692 sis_frames[i] = (dga_offset + info->offsets[i]);
693 }
694
695 memset(&overlay, 0, sizeof(overlay));
696 overlay.pixelFormat = sis_format = info->fourcc;
697 overlay.pitch = overlay.origPitch = pitch;
698
699
700 overlay.keyOP = (sis_grkey.ckey.op == CKEY_TRUE ?
701 VI_ROP_DestKey : VI_ROP_Always);
702
703 overlay.bobEnable = 0x00;
704
705 overlay.SCREENheight = sis_screen_height;
706
707 /* probably will not support X virtual screen > phys very well? */
708 overlay.dstBox.x1 = drw_x; /* - pScrn->frameX0; */
709 overlay.dstBox.x2 = drw_x + drw_w; /* - pScrn->frameX0; ??? */
710 overlay.dstBox.y1 = drw_y; /* - pScrn->frameY0; */
711 overlay.dstBox.y2 = drw_y + drw_h; /* - pScrn->frameY0; ??? */
712
713 if ((overlay.dstBox.x1 > overlay.dstBox.x2) ||
714 (overlay.dstBox.y1 > overlay.dstBox.y2))
715 return -1;
716
717 if ((overlay.dstBox.x2 < 0) || (overlay.dstBox.y2 < 0))
718 return -1;
719
720 if (overlay.dstBox.x1 < 0) {
721 srcOffsetX = src_w * (-overlay.dstBox.x1) / drw_w;
722 overlay.dstBox.x1 = 0;
723 }
724 if (overlay.dstBox.y1 < 0) {
725 srcOffsetY = src_h * (-overlay.dstBox.y1) / drw_h;
726 overlay.dstBox.y1 = 0;
727 }
728
729 switch (info->fourcc) {
730 case IMGFMT_YV12:
731 info->dest.pitch.y = 16;
732 sx = (src_x + srcOffsetX) & ~7;
733 sy = (src_y + srcOffsetY) & ~1;
734 info->offset.y = sis_Yoff = sx + sy * pitch;
735 /* JCP: NOTE reversed u & v here! Not sure why this is needed.
736 maybe mplayer & sis define U & V differently?? */
737 info->offset.u = sis_Voff =
738 src_h * pitch + ((sx + sy * pitch / 2) >> 1);
739 info->offset.v = sis_Uoff =
740 src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1);
741
742 overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value;
743 overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value;
744 overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value;
745 break;
746 case IMGFMT_I420:
747 sx = (src_x + srcOffsetX) & ~7;
748 sy = (src_y + srcOffsetY) & ~1;
749 info->offset.y = sis_Yoff = sx + sy * pitch;
750 /* JCP: see above... */
751 info->offset.u = sis_Voff =
752 src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1);
753 info->offset.v = sis_Uoff =
754 src_h * pitch + ((sx + sy * pitch / 2) >> 1);
755
756 overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value;
757 overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value;
758 overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value;
759 break;
760 case IMGFMT_YUY2:
761 case IMGFMT_UYVY:
762 case IMGFMT_RGB16:
763 case IMGFMT_RGB15:
764 default:
765 sx = (src_x + srcOffsetX) & ~1;
766 sy = (src_y + srcOffsetY);
767 info->offset.y = sis_Yoff = sx * 2 + sy * pitch;
768
769 overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value;
770 break;
771 }
772
773 /* FIXME: is it possible that srcW < 0? */
774 overlay.srcW = src_w - (sx - src_x);
775 overlay.srcH = src_h - (sy - src_y);
776
777 /* JCP: what to do about this? */
778 #if 0
779 if ((pPriv->oldx1 != overlay.dstBox.x1) ||
780 (pPriv->oldx2 != overlay.dstBox.x2) ||
781 (pPriv->oldy1 != overlay.dstBox.y1) ||
782 (pPriv->oldy2 != overlay.dstBox.y2)) {
783 pPriv->mustwait = 1;
784 pPriv->oldx1 = overlay.dstBox.x1;
785 pPriv->oldx2 = overlay.dstBox.x2;
786 pPriv->oldy1 = overlay.dstBox.y1;
787 pPriv->oldy2 = overlay.dstBox.y2;
788 }
789 #endif
790
791 /* set merge line buffer */
792 merge_line_buf(overlay.srcW > 384);
793
794 /* calculate line buffer length */
795 set_line_buf_size(&overlay);
796
797 if (sis_displaymode == DISPMODE_SINGLE2) {
798 if (sis_has_two_overlays) {
799 /* TW: On chips with two overlays we use
800 * overlay 2 for CRT2 */
801 index = 1;
802 iscrt2 = 1;
803 } else {
804 /* TW: On chips with only one overlay we
805 * use that only overlay for CRT2 */
806 index = 0;
807 iscrt2 = 1;
808 }
809 overlay.VBlankActiveFunc = vblank_active_CRT2;
810 /* overlay.GetScanLineFunc = get_scanline_CRT2; */
811 } else {
812 index = 0;
813 iscrt2 = 0;
814 overlay.VBlankActiveFunc = vblank_active_CRT1;
815 /* overlay.GetScanLineFunc = get_scanline_CRT1; */
816 }
817
818 /* calc scale factor (to use below) */
819 calc_scale_factor(&overlay, index, iscrt2);
820
821 /* Select video1 (used for CRT1) or video2 (used for CRT2) */
822 setvideoregmask(Index_VI_Control_Misc2, index, 0x01);
823
824 set_format(&overlay);
825
826 set_colorkey();
827
828 vixPlaybackSetEq(&sis_equal);
829
830 /* set up video overlay registers */
831 set_overlay(&overlay, index);
832
833 /* prevent badness if bits are not at default setting */
834 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x01);
835 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x04);
836
837 /* JCP: Xv driver implementation loops back over above code to
838 setup mirror CRT2 */
839
840 return 0;
841 }
842
vixPlaybackOn(void)843 int vixPlaybackOn(void)
844 {
845 setvideoregmask(Index_VI_Control_Misc0, 0x02, 0x02);
846 return 0;
847 }
848
vixPlaybackOff(void)849 int vixPlaybackOff(void)
850 {
851 unsigned char sridx, cridx;
852 sridx = inSISREG(SISSR);
853 cridx = inSISREG(SISCR);
854 close_overlay();
855 outSISREG(SISSR, sridx);
856 outSISREG(SISCR, cridx);
857
858 return 0;
859 }
860
vixPlaybackFrameSelect(unsigned int frame)861 int vixPlaybackFrameSelect(unsigned int frame)
862 {
863 uint8_t data;
864 int index = 0;
865 uint32_t PSY;
866
867 if (sis_displaymode == DISPMODE_SINGLE2 && sis_has_two_overlays) {
868 index = 1;
869 }
870
871 PSY = (sis_frames[frame] + sis_Yoff) >> sis_shift_value;
872
873 /* Unlock address registers */
874 data = getvideoreg(Index_VI_Control_Misc1);
875 setvideoreg(Index_VI_Control_Misc1, data | 0x20);
876 /* TEST: Is this required? */
877 setvideoreg(Index_VI_Control_Misc1, data | 0x20);
878 /* TEST end */
879 /* TEST: Is this required? */
880 if (sis_vga_engine == SIS_315_VGA)
881 setvideoreg(Index_VI_Control_Misc3, 0x00);
882 /* TEST end */
883
884 /* set Y start address */
885 setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (PSY));
886 setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle, (uint8_t) ((PSY) >> 8));
887 setvideoreg(Index_VI_Disp_Y_Buf_Start_High, (uint8_t) ((PSY) >> 16));
888 /* set 310/325 series overflow bits for Y plane */
889 if (sis_vga_engine == SIS_315_VGA) {
890 setvideoreg(Index_VI_Y_Buf_Start_Over,
891 ((uint8_t) ((PSY) >> 24) & 0x01));
892 }
893
894 /* Set U/V data if using plane formats */
895 if ((sis_format == IMGFMT_YV12) || (sis_format == IMGFMT_I420)) {
896
897 uint32_t PSU, PSV;
898
899 PSU = (sis_frames[frame] + sis_Uoff) >> sis_shift_value;
900 PSV = (sis_frames[frame] + sis_Voff) >> sis_shift_value;
901
902 /* set U/V start address */
903 setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU);
904 setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8));
905 setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16));
906
907 setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV);
908 setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8));
909 setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16));
910
911 /* 310/325 series overflow bits */
912 if (sis_vga_engine == SIS_315_VGA) {
913 setvideoreg(Index_VI_U_Buf_Start_Over,
914 ((uint8_t) (PSU >> 24) & 0x01));
915 setvideoreg(Index_VI_V_Buf_Start_Over,
916 ((uint8_t) (PSV >> 24) & 0x01));
917 }
918 }
919
920 if (sis_vga_engine == SIS_315_VGA) {
921 /* Trigger register copy for 310 series */
922 setvideoreg(Index_VI_Control_Misc3, 1 << index);
923 }
924
925 /* Lock the address registers */
926 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20);
927
928 return 0;
929 }
930
vixGetGrKeys(vidix_grkey_t * grkey)931 int vixGetGrKeys(vidix_grkey_t * grkey)
932 {
933 memcpy(grkey, &sis_grkey, sizeof(vidix_grkey_t));
934 return 0;
935 }
936
vixSetGrKeys(const vidix_grkey_t * grkey)937 int vixSetGrKeys(const vidix_grkey_t * grkey)
938 {
939 memcpy(&sis_grkey, grkey, sizeof(vidix_grkey_t));
940 set_colorkey();
941 return 0;
942 }
943
vixPlaybackGetEq(vidix_video_eq_t * eq)944 int vixPlaybackGetEq(vidix_video_eq_t * eq)
945 {
946 memcpy(eq, &sis_equal, sizeof(vidix_video_eq_t));
947 return 0;
948 }
949
vixPlaybackSetEq(const vidix_video_eq_t * eq)950 int vixPlaybackSetEq(const vidix_video_eq_t * eq)
951 {
952 int br, sat, cr, hue;
953 if (eq->cap & VEQ_CAP_BRIGHTNESS)
954 sis_equal.brightness = eq->brightness;
955 if (eq->cap & VEQ_CAP_CONTRAST)
956 sis_equal.contrast = eq->contrast;
957 if (eq->cap & VEQ_CAP_SATURATION)
958 sis_equal.saturation = eq->saturation;
959 if (eq->cap & VEQ_CAP_HUE)
960 sis_equal.hue = eq->hue;
961 if (eq->cap & VEQ_CAP_RGB_INTENSITY) {
962 sis_equal.red_intensity = eq->red_intensity;
963 sis_equal.green_intensity = eq->green_intensity;
964 sis_equal.blue_intensity = eq->blue_intensity;
965 }
966 sis_equal.flags = eq->flags;
967
968 cr = (sis_equal.contrast + 1000) * 7 / 2000;
969 if (cr < 0)
970 cr = 0;
971 if (cr > 7)
972 cr = 7;
973
974 br = sis_equal.brightness * 127 / 1000;
975 if (br < -128)
976 br = -128;
977 if (br > 127)
978 br = 127;
979
980 sat = (sis_equal.saturation * 7) / 1000;
981 if (sat < -7)
982 sat = -7;
983 if (sat > 7)
984 sat = 7;
985
986 hue = sis_equal.hue * 7 / 1000;
987 if (hue < -8)
988 hue = -8;
989 if (hue > 7)
990 hue = 7;
991
992 set_brightness(br);
993 set_contrast(cr);
994 if (sis_vga_engine == SIS_315_VGA) {
995 set_saturation(sat);
996 set_hue(hue);
997 }
998
999 return 0;
1000 }
1001
set_overlay(SISOverlayPtr pOverlay,int index)1002 static void set_overlay(SISOverlayPtr pOverlay, int index)
1003 {
1004 uint16_t pitch = 0;
1005 uint8_t h_over = 0, v_over = 0;
1006 uint16_t top, bottom, left, right;
1007 uint16_t screenX = sis_screen_width;
1008 uint16_t screenY = sis_screen_height;
1009 uint8_t data;
1010 uint32_t watchdog;
1011
1012 top = pOverlay->dstBox.y1;
1013 bottom = pOverlay->dstBox.y2;
1014 if (bottom > screenY) {
1015 bottom = screenY;
1016 }
1017
1018 left = pOverlay->dstBox.x1;
1019 right = pOverlay->dstBox.x2;
1020 if (right > screenX) {
1021 right = screenX;
1022 }
1023
1024 /* JCP: these aren't really tested... */
1025 /* TW: DoubleScan modes require Y coordinates * 2 */
1026 if (sis_vmode & VMODE_DOUBLESCAN) {
1027 top <<= 1;
1028 bottom <<= 1;
1029 }
1030 /* TW: Interlace modes require Y coordinates / 2 */
1031 if (sis_vmode & VMODE_INTERLACED) {
1032 top >>= 1;
1033 bottom >>= 1;
1034 }
1035
1036 h_over = (((left >> 8) & 0x0f) | ((right >> 4) & 0xf0));
1037 v_over = (((top >> 8) & 0x0f) | ((bottom >> 4) & 0xf0));
1038
1039 pitch = pOverlay->pitch >> sis_shift_value;
1040
1041 /* set line buffer size */
1042 setvideoreg(Index_VI_Line_Buffer_Size, pOverlay->lineBufSize);
1043
1044 /* set color key mode */
1045 setvideoregmask(Index_VI_Key_Overlay_OP, pOverlay->keyOP, 0x0F);
1046
1047 /* TW: We don't have to wait for vertical retrace in all cases */
1048 /* JCP: be safe for now. */
1049 if (1 /*pPriv->mustwait */ ) {
1050 watchdog = WATCHDOG_DELAY;
1051 while (pOverlay->VBlankActiveFunc() && --watchdog);
1052 watchdog = WATCHDOG_DELAY;
1053 while ((!pOverlay->VBlankActiveFunc()) && --watchdog);
1054 if (!watchdog && sis_verbose > 0) {
1055 printf("[SiS]: timed out waiting for vertical retrace\n");
1056 }
1057 }
1058
1059 /* Unlock address registers */
1060 data = getvideoreg(Index_VI_Control_Misc1);
1061 setvideoreg(Index_VI_Control_Misc1, data | 0x20);
1062 /* TEST: Is this required? */
1063 setvideoreg(Index_VI_Control_Misc1, data | 0x20);
1064 /* TEST end */
1065
1066 /* TEST: Is this required? */
1067 if (sis_vga_engine == SIS_315_VGA)
1068 setvideoreg(Index_VI_Control_Misc3, 0x00);
1069 /* TEST end */
1070
1071 /* Set Y buf pitch */
1072 setvideoreg(Index_VI_Disp_Y_Buf_Pitch_Low, (uint8_t) (pitch));
1073 setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle,
1074 (uint8_t) (pitch >> 8), 0x0f);
1075
1076 /* Set Y start address */
1077 setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (pOverlay->PSY));
1078 setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle,
1079 (uint8_t) ((pOverlay->PSY) >> 8));
1080 setvideoreg(Index_VI_Disp_Y_Buf_Start_High,
1081 (uint8_t) ((pOverlay->PSY) >> 16));
1082
1083 /* set 310/325 series overflow bits for Y plane */
1084 if (sis_vga_engine == SIS_315_VGA) {
1085 setvideoreg(Index_VI_Disp_Y_Buf_Pitch_High,
1086 (uint8_t) (pitch >> 12));
1087 setvideoreg(Index_VI_Y_Buf_Start_Over,
1088 ((uint8_t) ((pOverlay->PSY) >> 24) & 0x01));
1089 }
1090
1091 /* Set U/V data if using plane formats */
1092 if ((pOverlay->pixelFormat == IMGFMT_YV12) ||
1093 (pOverlay->pixelFormat == IMGFMT_I420)) {
1094
1095 uint32_t PSU, PSV;
1096
1097 PSU = pOverlay->PSU;
1098 PSV = pOverlay->PSV;
1099
1100 /* Set U/V pitch */
1101 setvideoreg(Index_VI_Disp_UV_Buf_Pitch_Low,
1102 (uint8_t) (pitch >> 1));
1103 setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle,
1104 (uint8_t) (pitch >> 5), 0xf0);
1105
1106 /* set U/V start address */
1107 setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU);
1108 setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8));
1109 setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16));
1110
1111 setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV);
1112 setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8));
1113 setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16));
1114
1115 /* 310/325 series overflow bits */
1116 if (sis_vga_engine == SIS_315_VGA) {
1117 setvideoreg(Index_VI_Disp_UV_Buf_Pitch_High,
1118 (uint8_t) (pitch >> 13));
1119 setvideoreg(Index_VI_U_Buf_Start_Over,
1120 ((uint8_t) (PSU >> 24) & 0x01));
1121 setvideoreg(Index_VI_V_Buf_Start_Over,
1122 ((uint8_t) (PSV >> 24) & 0x01));
1123 }
1124 }
1125
1126 if (sis_vga_engine == SIS_315_VGA) {
1127 /* Trigger register copy for 310 series */
1128 setvideoreg(Index_VI_Control_Misc3, 1 << index);
1129 }
1130
1131 /* set scale factor */
1132 setvideoreg(Index_VI_Hor_Post_Up_Scale_Low,
1133 (uint8_t) (pOverlay->HUSF));
1134 setvideoreg(Index_VI_Hor_Post_Up_Scale_High,
1135 (uint8_t) ((pOverlay->HUSF) >> 8));
1136 setvideoreg(Index_VI_Ver_Up_Scale_Low, (uint8_t) (pOverlay->VUSF));
1137 setvideoreg(Index_VI_Ver_Up_Scale_High,
1138 (uint8_t) ((pOverlay->VUSF) >> 8));
1139
1140 setvideoregmask(Index_VI_Scale_Control, (pOverlay->IntBit << 3)
1141 | (pOverlay->wHPre), 0x7f);
1142
1143 /* set destination window position */
1144 setvideoreg(Index_VI_Win_Hor_Disp_Start_Low, (uint8_t) left);
1145 setvideoreg(Index_VI_Win_Hor_Disp_End_Low, (uint8_t) right);
1146 setvideoreg(Index_VI_Win_Hor_Over, (uint8_t) h_over);
1147
1148 setvideoreg(Index_VI_Win_Ver_Disp_Start_Low, (uint8_t) top);
1149 setvideoreg(Index_VI_Win_Ver_Disp_End_Low, (uint8_t) bottom);
1150 setvideoreg(Index_VI_Win_Ver_Over, (uint8_t) v_over);
1151
1152 setvideoregmask(Index_VI_Control_Misc1, pOverlay->bobEnable, 0x1a);
1153
1154 /* Lock the address registers */
1155 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20);
1156 }
1157
1158
1159 /* TW: Overlay MUST NOT be switched off while beam is over it */
close_overlay()1160 static void close_overlay()
1161 {
1162 uint32_t watchdog;
1163
1164 if ((sis_displaymode == DISPMODE_SINGLE2) ||
1165 (sis_displaymode == DISPMODE_MIRROR)) {
1166 if (sis_has_two_overlays) {
1167 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01);
1168 watchdog = WATCHDOG_DELAY;
1169 while (vblank_active_CRT2() && --watchdog);
1170 watchdog = WATCHDOG_DELAY;
1171 while ((!vblank_active_CRT2()) && --watchdog);
1172 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
1173 watchdog = WATCHDOG_DELAY;
1174 while (vblank_active_CRT2() && --watchdog);
1175 watchdog = WATCHDOG_DELAY;
1176 while ((!vblank_active_CRT2()) && --watchdog);
1177 } else if (sis_displaymode == DISPMODE_SINGLE2) {
1178 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01);
1179 watchdog = WATCHDOG_DELAY;
1180 while (vblank_active_CRT1() && --watchdog);
1181 watchdog = WATCHDOG_DELAY;
1182 while ((!vblank_active_CRT1()) && --watchdog);
1183 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
1184 watchdog = WATCHDOG_DELAY;
1185 while (vblank_active_CRT1() && --watchdog);
1186 watchdog = WATCHDOG_DELAY;
1187 while ((!vblank_active_CRT1()) && --watchdog);
1188 }
1189 }
1190 if ((sis_displaymode == DISPMODE_SINGLE1) ||
1191 (sis_displaymode == DISPMODE_MIRROR)) {
1192 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01);
1193 watchdog = WATCHDOG_DELAY;
1194 while (vblank_active_CRT1() && --watchdog);
1195 watchdog = WATCHDOG_DELAY;
1196 while ((!vblank_active_CRT1()) && --watchdog);
1197 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
1198 watchdog = WATCHDOG_DELAY;
1199 while (vblank_active_CRT1() && --watchdog);
1200 watchdog = WATCHDOG_DELAY;
1201 while ((!vblank_active_CRT1()) && --watchdog);
1202 }
1203 }
1204
1205
1206 static void
calc_scale_factor(SISOverlayPtr pOverlay,int index,int iscrt2)1207 calc_scale_factor(SISOverlayPtr pOverlay, int index, int iscrt2)
1208 {
1209 uint32_t i = 0, mult = 0;
1210 int flag = 0;
1211
1212 int dstW = pOverlay->dstBox.x2 - pOverlay->dstBox.x1;
1213 int dstH = pOverlay->dstBox.y2 - pOverlay->dstBox.y1;
1214 int srcW = pOverlay->srcW;
1215 int srcH = pOverlay->srcH;
1216 /* uint16_t LCDheight = pSiS->LCDheight; */
1217 int srcPitch = pOverlay->origPitch;
1218 int origdstH = dstH;
1219
1220 /* get rid of warnings for now */
1221 index = index;
1222 iscrt2 = iscrt2;
1223
1224 #if 0 /* JCP: don't bother with this for now. */
1225 /* TW: Stretch image due to idiotic LCD "auto"-scaling on LVDS (and 630+301B) */
1226 if (pSiS->VBFlags & CRT2_LCD) {
1227 if (sis_bridge_is_slave) {
1228 if (pSiS->VBFlags & VB_LVDS) {
1229 dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
1230 } else if ((sis_vga_engine == SIS_300_VGA) &&
1231 (pSiS->
1232 VBFlags & (VB_301B | VB_302B | VB_301LV |
1233 VB_302LV))) {
1234 dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
1235 }
1236 } else if (iscrt2) {
1237 if (pSiS->VBFlags & VB_LVDS) {
1238 dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
1239 if (sis_displaymode == DISPMODE_MIRROR)
1240 flag = 1;
1241 } else if ((sis_vga_engine == SIS_300_VGA) &&
1242 (pSiS->
1243 VBFlags & (VB_301B | VB_302B | VB_301LV |
1244 VB_302LV))) {
1245 dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
1246 if (sis_displaymode == DISPMODE_MIRROR)
1247 flag = 1;
1248 }
1249 }
1250 }
1251 #endif
1252
1253 /* TW: For double scan modes, we need to double the height
1254 * (Perhaps we also need to scale LVDS, but I'm not sure.)
1255 * On 310/325 series, we need to double the width as well.
1256 * Interlace mode vice versa.
1257 */
1258 if (sis_vmode & VMODE_DOUBLESCAN) {
1259 dstH = origdstH << 1;
1260 flag = 0;
1261 if (sis_vga_engine == SIS_315_VGA) {
1262 dstW <<= 1;
1263 }
1264 }
1265 if (sis_vmode & VMODE_INTERLACED) {
1266 dstH = origdstH >> 1;
1267 flag = 0;
1268 }
1269
1270 if (dstW < OVERLAY_MIN_WIDTH)
1271 dstW = OVERLAY_MIN_WIDTH;
1272 if (dstW == srcW) {
1273 pOverlay->HUSF = 0x00;
1274 pOverlay->IntBit = 0x05;
1275 pOverlay->wHPre = 0;
1276 } else if (dstW > srcW) {
1277 dstW += 2;
1278 pOverlay->HUSF = (srcW << 16) / dstW;
1279 pOverlay->IntBit = 0x04;
1280 pOverlay->wHPre = 0;
1281 } else {
1282 int tmpW = dstW;
1283
1284 /* TW: It seems, the hardware can't scale below factor .125 (=1/8) if the
1285 pitch isn't a multiple of 256.
1286 TODO: Test this on the 310/325 series!
1287 */
1288 if ((srcPitch % 256) || (srcPitch < 256)) {
1289 if (((dstW * 1000) / srcW) < 125)
1290 dstW = tmpW = ((srcW * 125) / 1000) + 1;
1291 }
1292
1293 i = 0;
1294 pOverlay->IntBit = 0x01;
1295 while (srcW >= tmpW) {
1296 tmpW <<= 1;
1297 i++;
1298 }
1299 pOverlay->wHPre = (uint8_t) (i - 1);
1300 dstW <<= (i - 1);
1301 if ((srcW % dstW))
1302 pOverlay->HUSF = ((srcW - dstW) << 16) / dstW;
1303 else
1304 pOverlay->HUSF = 0x00;
1305 }
1306
1307 if (dstH < OVERLAY_MIN_HEIGHT)
1308 dstH = OVERLAY_MIN_HEIGHT;
1309 if (dstH == srcH) {
1310 pOverlay->VUSF = 0x00;
1311 pOverlay->IntBit |= 0x0A;
1312 } else if (dstH > srcH) {
1313 dstH += 0x02;
1314 pOverlay->VUSF = (srcH << 16) / dstH;
1315 pOverlay->IntBit |= 0x08;
1316 } else {
1317 uint32_t realI;
1318
1319 i = realI = srcH / dstH;
1320 pOverlay->IntBit |= 0x02;
1321
1322 if (i < 2) {
1323 pOverlay->VUSF = ((srcH - dstH) << 16) / dstH;
1324 /* TW: Needed for LCD-scaling modes */
1325 if ((flag) && (mult = (srcH / origdstH)) >= 2)
1326 pOverlay->pitch /= mult;
1327 } else {
1328 #if 0
1329 if (((pOverlay->bobEnable & 0x08) == 0x00) &&
1330 (((srcPitch * i) >> 2) > 0xFFF)) {
1331 pOverlay->bobEnable |= 0x08;
1332 srcPitch >>= 1;
1333 }
1334 #endif
1335 if (((srcPitch * i) >> 2) > 0xFFF) {
1336 i = (0xFFF * 2 / srcPitch);
1337 pOverlay->VUSF = 0xFFFF;
1338 } else {
1339 dstH = i * dstH;
1340 if (srcH % dstH)
1341 pOverlay->VUSF = ((srcH - dstH) << 16) / dstH;
1342 else
1343 pOverlay->VUSF = 0x00;
1344 }
1345 /* set video frame buffer offset */
1346 pOverlay->pitch = (uint16_t) (srcPitch * i);
1347 }
1348 }
1349 }
1350
set_line_buf_size(SISOverlayPtr pOverlay)1351 static void set_line_buf_size(SISOverlayPtr pOverlay)
1352 {
1353 uint8_t preHIDF;
1354 uint32_t i;
1355 uint32_t line = pOverlay->srcW;
1356
1357 if ((pOverlay->pixelFormat == IMGFMT_YV12) ||
1358 (pOverlay->pixelFormat == IMGFMT_I420)) {
1359 preHIDF = pOverlay->wHPre & 0x07;
1360 switch (preHIDF) {
1361 case 3:
1362 if ((line & 0xffffff00) == line)
1363 i = (line >> 8);
1364 else
1365 i = (line >> 8) + 1;
1366 pOverlay->lineBufSize = (uint8_t) (i * 32 - 1);
1367 break;
1368 case 4:
1369 if ((line & 0xfffffe00) == line)
1370 i = (line >> 9);
1371 else
1372 i = (line >> 9) + 1;
1373 pOverlay->lineBufSize = (uint8_t) (i * 64 - 1);
1374 break;
1375 case 5:
1376 if ((line & 0xfffffc00) == line)
1377 i = (line >> 10);
1378 else
1379 i = (line >> 10) + 1;
1380 pOverlay->lineBufSize = (uint8_t) (i * 128 - 1);
1381 break;
1382 case 6:
1383 if ((line & 0xfffff800) == line)
1384 i = (line >> 11);
1385 else
1386 i = (line >> 11) + 1;
1387 pOverlay->lineBufSize = (uint8_t) (i * 256 - 1);
1388 break;
1389 default:
1390 if ((line & 0xffffff80) == line)
1391 i = (line >> 7);
1392 else
1393 i = (line >> 7) + 1;
1394 pOverlay->lineBufSize = (uint8_t) (i * 16 - 1);
1395 break;
1396 }
1397 } else { /* YUV2, UYVY */
1398 if ((line & 0xffffff8) == line)
1399 i = (line >> 3);
1400 else
1401 i = (line >> 3) + 1;
1402 pOverlay->lineBufSize = (uint8_t) (i - 1);
1403 }
1404 }
1405
merge_line_buf(int enable)1406 static void merge_line_buf(int enable)
1407 {
1408 if (enable) {
1409 switch (sis_displaymode) {
1410 case DISPMODE_SINGLE1:
1411 if (sis_has_two_overlays) {
1412 /* dual line merge */
1413 setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11);
1414 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1415 } else {
1416 setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11);
1417 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1418 }
1419 break;
1420 case DISPMODE_SINGLE2:
1421 if (sis_has_two_overlays) {
1422 /* line merge */
1423 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
1424 setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04);
1425 } else {
1426 setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11);
1427 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1428 }
1429 break;
1430 case DISPMODE_MIRROR:
1431 default:
1432 /* line merge */
1433 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
1434 setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04);
1435 if (sis_has_two_overlays) {
1436 /* line merge */
1437 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
1438 setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04);
1439 }
1440 break;
1441 }
1442 } else {
1443 switch (sis_displaymode) {
1444 case DISPMODE_SINGLE1:
1445 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
1446 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1447 break;
1448 case DISPMODE_SINGLE2:
1449 if (sis_has_two_overlays) {
1450 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
1451 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1452 } else {
1453 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
1454 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1455 }
1456 break;
1457 case DISPMODE_MIRROR:
1458 default:
1459 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
1460 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1461 if (sis_has_two_overlays) {
1462 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
1463 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1464 }
1465 break;
1466 }
1467 }
1468 }
1469
1470
set_format(SISOverlayPtr pOverlay)1471 static void set_format(SISOverlayPtr pOverlay)
1472 {
1473 uint8_t fmt;
1474
1475 switch (pOverlay->pixelFormat) {
1476 case IMGFMT_YV12:
1477 case IMGFMT_I420:
1478 fmt = 0x0c;
1479 break;
1480 case IMGFMT_YUY2:
1481 fmt = 0x28;
1482 break;
1483 case IMGFMT_UYVY:
1484 fmt = 0x08;
1485 break;
1486 case IMGFMT_RGB15: /* D[5:4] : 00 RGB555, 01 RGB 565 */
1487 fmt = 0x00;
1488 break;
1489 case IMGFMT_RGB16:
1490 fmt = 0x10;
1491 break;
1492 default:
1493 fmt = 0x00;
1494 break;
1495 }
1496 setvideoregmask(Index_VI_Control_Misc0, fmt, 0x7c);
1497 }
1498
set_colorkey()1499 static void set_colorkey()
1500 {
1501 uint8_t r, g, b;
1502
1503 b = (uint8_t) sis_grkey.ckey.blue;
1504 g = (uint8_t) sis_grkey.ckey.green;
1505 r = (uint8_t) sis_grkey.ckey.red;
1506
1507 /* set color key mode */
1508 setvideoregmask(Index_VI_Key_Overlay_OP,
1509 sis_grkey.ckey.op == CKEY_TRUE ?
1510 VI_ROP_DestKey : VI_ROP_Always, 0x0F);
1511
1512 /* set colorkey values */
1513 setvideoreg(Index_VI_Overlay_ColorKey_Blue_Min, (uint8_t) b);
1514 setvideoreg(Index_VI_Overlay_ColorKey_Green_Min, (uint8_t) g);
1515 setvideoreg(Index_VI_Overlay_ColorKey_Red_Min, (uint8_t) r);
1516
1517 setvideoreg(Index_VI_Overlay_ColorKey_Blue_Max, (uint8_t) b);
1518 setvideoreg(Index_VI_Overlay_ColorKey_Green_Max, (uint8_t) g);
1519 setvideoreg(Index_VI_Overlay_ColorKey_Red_Max, (uint8_t) r);
1520 }
1521
set_brightness(uint8_t brightness)1522 static void set_brightness(uint8_t brightness)
1523 {
1524 setvideoreg(Index_VI_Brightness, brightness);
1525 }
1526
set_contrast(uint8_t contrast)1527 static void set_contrast(uint8_t contrast)
1528 {
1529 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, contrast, 0x07);
1530 }
1531
1532 /* Next 3 functions are 310/325 series only */
1533
set_saturation(char saturation)1534 static void set_saturation(char saturation)
1535 {
1536 uint8_t temp = 0;
1537
1538 if (saturation < 0) {
1539 temp |= 0x88;
1540 saturation = -saturation;
1541 }
1542 temp |= (saturation & 0x07);
1543 temp |= ((saturation & 0x07) << 4);
1544
1545 setvideoreg(Index_VI_Saturation, temp);
1546 }
1547
set_hue(uint8_t hue)1548 static void set_hue(uint8_t hue)
1549 {
1550 setvideoreg(Index_VI_Hue, (hue & 0x08) ? (hue ^ 0x07) : hue);
1551 }
1552
1553 #if 0
1554 /* JCP: not used (I don't think it's correct anyway) */
1555 static void set_alpha(uint8_t alpha)
1556 {
1557 uint8_t data;
1558
1559 data = getvideoreg(Index_VI_Key_Overlay_OP);
1560 data &= 0x0F;
1561 setvideoreg(Index_VI_Key_Overlay_OP, data | (alpha << 4));
1562 }
1563 #endif
1564