1 /*
2 * small utility to extract CPU information
3 * Used by configure to set CPU optimization levels on some operating
4 * systems where /proc/cpuinfo is non-existent or unreliable.
5 *
6 * This file is part of MPlayer.
7 *
8 * MPlayer is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * MPlayer is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with MPlayer; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22
23 #include <stdio.h>
24 #include <sys/time.h>
25 #include <stdlib.h>
26 #include <string.h>
27 #include <unistd.h>
28
29 #ifdef __MINGW32__
30 #define MISSING_USLEEP
31 #include <windows.h>
32 #define sleep(t) Sleep(1000*t);
33 #endif
34
35 #ifdef M_UNIX
36 typedef long long int64_t;
37 #define MISSING_USLEEP
38 #else
39 #include <inttypes.h>
40 #endif
41
42 #define CPUID_FEATURE_DEF(bit, desc, description) \
43 { bit, desc }
44
45 typedef struct cpuid_regs {
46 unsigned int eax;
47 unsigned int ebx;
48 unsigned int ecx;
49 unsigned int edx;
50 } cpuid_regs_t;
51
52 static cpuid_regs_t
cpuid(int func,int sub)53 cpuid(int func, int sub) {
54 cpuid_regs_t regs;
55 #define CPUID ".byte 0x0f, 0xa2; "
56 #ifdef __x86_64__
57 __asm__("mov %%rbx, %%rsi\n\t"
58 #else
59 __asm__("mov %%ebx, %%esi\n\t"
60 #endif
61 CPUID"\n\t"
62 #ifdef __x86_64__
63 "xchg %%rsi, %%rbx\n\t"
64 #else
65 "xchg %%esi, %%ebx\n\t"
66 #endif
67 : "=a" (regs.eax), "=S" (regs.ebx), "=c" (regs.ecx), "=d" (regs.edx)
68 : "0" (func), "2" (sub));
69 return regs;
70 }
71
72
73 static int64_t
rdtsc(void)74 rdtsc(void)
75 {
76 uint32_t hi, lo;
77 #define RDTSC ".byte 0x0f, 0x31; "
78 __asm__ volatile (RDTSC : "=a"(lo), "=d"(hi) : );
79 return (uint64_t) hi << 32 | lo;
80 }
81
82 static const char*
brandname(int i)83 brandname(int i)
84 {
85 static const char* brandmap[] = {
86 NULL,
87 "Intel(R) Celeron(R) processor",
88 "Intel(R) Pentium(R) III processor",
89 "Intel(R) Pentium(R) III Xeon(tm) processor",
90 "Intel(R) Pentium(R) III processor",
91 NULL,
92 "Mobile Intel(R) Pentium(R) III processor-M",
93 "Mobile Intel(R) Celeron(R) processor"
94 };
95
96 if (i >= sizeof(brandmap))
97 return NULL;
98 else
99 return brandmap[i];
100 }
101
102 static void
store32(char * d,unsigned int v)103 store32(char *d, unsigned int v)
104 {
105 d[0] = v & 0xff;
106 d[1] = (v >> 8) & 0xff;
107 d[2] = (v >> 16) & 0xff;
108 d[3] = (v >> 24) & 0xff;
109 }
110
111
112 int
main(void)113 main(void)
114 {
115 cpuid_regs_t regs, regs_ext;
116 char idstr[13];
117 unsigned max_cpuid;
118 unsigned max_ext_cpuid;
119 unsigned int amd_flags;
120 unsigned int amd_flags2;
121 unsigned int ext_flags;
122 const char *model_name = NULL;
123 int i;
124 char processor_name[49];
125
126 regs = cpuid(0, 0);
127 max_cpuid = regs.eax;
128 /* printf("%d CPUID function codes\n", max_cpuid+1); */
129
130 store32(idstr+0, regs.ebx);
131 store32(idstr+4, regs.edx);
132 store32(idstr+8, regs.ecx);
133 idstr[12] = 0;
134 printf("vendor_id\t: %s\n", idstr);
135
136 regs_ext = cpuid((1<<31) + 0, 0);
137 max_ext_cpuid = regs_ext.eax;
138 if (max_ext_cpuid >= (1<<31) + 1) {
139 regs_ext = cpuid((1<<31) + 1, 0);
140 amd_flags = regs_ext.edx;
141 amd_flags2 = regs_ext.ecx;
142
143 if (max_ext_cpuid >= (1<<31) + 4) {
144 for (i = 2; i <= 4; i++) {
145 regs_ext = cpuid((1<<31) + i, 0);
146 store32(processor_name + (i-2)*16, regs_ext.eax);
147 store32(processor_name + (i-2)*16 + 4, regs_ext.ebx);
148 store32(processor_name + (i-2)*16 + 8, regs_ext.ecx);
149 store32(processor_name + (i-2)*16 + 12, regs_ext.edx);
150 }
151 processor_name[48] = 0;
152 model_name = processor_name;
153 while (*model_name == ' ') {
154 model_name++;
155 }
156 }
157 } else {
158 amd_flags = 0;
159 amd_flags2 = 0;
160 }
161
162 if (max_cpuid >= 7) {
163 regs_ext = cpuid(7, 0);
164 ext_flags = regs_ext.ebx;
165 } else {
166 ext_flags = 0;
167 }
168
169 if (max_cpuid >= 1) {
170 static struct {
171 int bit;
172 char *desc;
173 } cap[] = {
174 CPUID_FEATURE_DEF(0, "fpu", "Floating-point unit on-chip"),
175 CPUID_FEATURE_DEF(1, "vme", "Virtual Mode Enhancements"),
176 CPUID_FEATURE_DEF(2, "de", "Debugging Extension"),
177 CPUID_FEATURE_DEF(3, "pse", "Page Size Extension"),
178 CPUID_FEATURE_DEF(4, "tsc", "Time Stamp Counter"),
179 CPUID_FEATURE_DEF(5, "msr", "Pentium Processor MSR"),
180 CPUID_FEATURE_DEF(6, "pae", "Physical Address Extension"),
181 CPUID_FEATURE_DEF(7, "mce", "Machine Check Exception"),
182 CPUID_FEATURE_DEF(8, "cx8", "CMPXCHG8B Instruction Supported"),
183 CPUID_FEATURE_DEF(9, "apic", "On-chip APIC Hardware Enabled"),
184 CPUID_FEATURE_DEF(11, "sep", "SYSENTER and SYSEXIT"),
185 CPUID_FEATURE_DEF(12, "mtrr", "Memory Type Range Registers"),
186 CPUID_FEATURE_DEF(13, "pge", "PTE Global Bit"),
187 CPUID_FEATURE_DEF(14, "mca", "Machine Check Architecture"),
188 CPUID_FEATURE_DEF(15, "cmov", "Conditional Move/Compare Instruction"),
189 CPUID_FEATURE_DEF(16, "pat", "Page Attribute Table"),
190 CPUID_FEATURE_DEF(17, "pse36", "Page Size Extension 36-bit"),
191 CPUID_FEATURE_DEF(18, "pn", "Processor Serial Number"),
192 CPUID_FEATURE_DEF(19, "clflush", "CFLUSH instruction"),
193 CPUID_FEATURE_DEF(21, "dts", "Debug Store"),
194 CPUID_FEATURE_DEF(22, "acpi", "Thermal Monitor and Clock Ctrl"),
195 CPUID_FEATURE_DEF(23, "mmx", "MMX Technology"),
196 CPUID_FEATURE_DEF(24, "fxsr", "FXSAVE/FXRSTOR"),
197 CPUID_FEATURE_DEF(25, "sse", "SSE Extensions"),
198 CPUID_FEATURE_DEF(26, "sse2", "SSE2 Extensions"),
199 CPUID_FEATURE_DEF(27, "ss", "Self Snoop"),
200 CPUID_FEATURE_DEF(28, "ht", "Multi-threading"),
201 CPUID_FEATURE_DEF(29, "tm", "Therm. Monitor"),
202 CPUID_FEATURE_DEF(30, "ia64", "IA-64 Processor"),
203 CPUID_FEATURE_DEF(31, "pbe", "Pend. Brk. EN."),
204 { -1 }
205 };
206 static struct {
207 int bit;
208 char *desc;
209 } cap2[] = {
210 CPUID_FEATURE_DEF(0, "pni", "SSE3 Extensions"),
211 CPUID_FEATURE_DEF(1, "pclmulqdq", "Carryless Multiplication"),
212 CPUID_FEATURE_DEF(2, "dtes64", "64-bit Debug Store"),
213 CPUID_FEATURE_DEF(3, "monitor", "MONITOR/MWAIT"),
214 CPUID_FEATURE_DEF(4, "ds_cpl", "CPL Qualified Debug Store"),
215 CPUID_FEATURE_DEF(5, "vmx", "Virtual Machine Extensions"),
216 CPUID_FEATURE_DEF(6, "smx", "Safer Mode Extensions"),
217 CPUID_FEATURE_DEF(7, "est", "Enhanced Intel SpeedStep Technology"),
218 CPUID_FEATURE_DEF(8, "tm2", "Thermal Monitor 2"),
219 CPUID_FEATURE_DEF(9, "ssse3", "Supplemental SSE3"),
220 CPUID_FEATURE_DEF(10, "cid", "L1 Context ID"),
221 CPUID_FEATURE_DEF(11, "sdbg", "Silicon Debug"),
222 CPUID_FEATURE_DEF(12, "fma", "Fused Multiply Add"),
223 CPUID_FEATURE_DEF(13, "cx16", "CMPXCHG16B Available"),
224 CPUID_FEATURE_DEF(14, "xtpr", "xTPR Disable"),
225 CPUID_FEATURE_DEF(15, "pdcm", "Perf/Debug Capability MSR"),
226 CPUID_FEATURE_DEF(17, "pcid", "Processor-context identifiers"),
227 CPUID_FEATURE_DEF(18, "dca", "Direct Cache Access"),
228 CPUID_FEATURE_DEF(19, "sse4_1", "SSE4.1 Extensions"),
229 CPUID_FEATURE_DEF(20, "sse4_2", "SSE4.2 Extensions"),
230 CPUID_FEATURE_DEF(21, "x2apic", "x2APIC Feature"),
231 CPUID_FEATURE_DEF(22, "movbe", "MOVBE Instruction"),
232 CPUID_FEATURE_DEF(23, "popcnt", "Pop Count Instruction"),
233 CPUID_FEATURE_DEF(24, "tsc_deadline_timer", "TSC Deadline"),
234 CPUID_FEATURE_DEF(25, "aes", "AES Instruction"),
235 CPUID_FEATURE_DEF(26, "xsave", "XSAVE/XRSTOR Extensions"),
236 CPUID_FEATURE_DEF(27, "osxsave", "XSAVE/XRSTOR Enabled in the OS"),
237 CPUID_FEATURE_DEF(28, "avx", "Advanced Vector Extension"),
238 CPUID_FEATURE_DEF(29, "f16c", "Float 16 Instructions"),
239 CPUID_FEATURE_DEF(30, "rdrand", "RDRAND Instruction"),
240 CPUID_FEATURE_DEF(31, "hypervisor", "Reserved for Use by Hypervisor"),
241 { -1 }
242 };
243 static struct {
244 int bit;
245 char *desc;
246 } cap_amd[] = {
247 CPUID_FEATURE_DEF(11, "syscall", "SYSCALL and SYSRET"),
248 CPUID_FEATURE_DEF(19, "mp", "MP Capable"),
249 CPUID_FEATURE_DEF(20, "nx", "No-Execute Page Protection"),
250 CPUID_FEATURE_DEF(22, "mmxext", "MMX Technology (AMD Extensions)"),
251 CPUID_FEATURE_DEF(25, "fxsr_opt", "Fast FXSAVE/FXRSTOR"),
252 CPUID_FEATURE_DEF(26, "pdpe1gb", "PDP Entry for 1GiB Page"),
253 CPUID_FEATURE_DEF(27, "rdtscp", "RDTSCP Instruction"),
254 CPUID_FEATURE_DEF(29, "lm", "Long Mode Capable"),
255 CPUID_FEATURE_DEF(30, "3dnowext", "3DNow! Extensions"),
256 CPUID_FEATURE_DEF(31, "3dnow", "3DNow!"),
257 { -1 }
258 };
259 static struct {
260 int bit;
261 char *desc;
262 } cap_amd2[] = {
263 CPUID_FEATURE_DEF(0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode"),
264 CPUID_FEATURE_DEF(1, "cmp_legacy", "Chip Multi-Core"),
265 CPUID_FEATURE_DEF(2, "svm", "Secure Virtual Machine"),
266 CPUID_FEATURE_DEF(3, "extapic", "Extended APIC Space"),
267 CPUID_FEATURE_DEF(4, "cr8_legacy", "CR8 Available in Legacy Mode"),
268 CPUID_FEATURE_DEF(5, "abm", "Advanced Bit Manipulation"),
269 CPUID_FEATURE_DEF(6, "sse4a", "SSE4A Extensions"),
270 CPUID_FEATURE_DEF(7, "misalignsse", "Misaligned SSE Mode"),
271 CPUID_FEATURE_DEF(8, "3dnowprefetch", "3DNow! Prefetch/PrefetchW"),
272 CPUID_FEATURE_DEF(9, "osvw", "OS Visible Workaround"),
273 CPUID_FEATURE_DEF(10, "ibs", "Instruction Based Sampling"),
274 CPUID_FEATURE_DEF(11, "xop", "XOP Extensions"),
275 CPUID_FEATURE_DEF(12, "skinit", "SKINIT, STGI, and DEV Support"),
276 CPUID_FEATURE_DEF(13, "wdt", "Watchdog Timer Support"),
277 CPUID_FEATURE_DEF(15, "lwp", "Lightweight Profiling"),
278 CPUID_FEATURE_DEF(16, "fma4", "Fused Multiple Add with 4 Operands"),
279 CPUID_FEATURE_DEF(17, "tce", "Translation cache extension"),
280 CPUID_FEATURE_DEF(19, "nodeid_msr", "Support for MSRC001_100C"),
281 CPUID_FEATURE_DEF(21, "tbm", "Trailing Bit Manipulation"),
282 CPUID_FEATURE_DEF(22, "topoext", "CPUID Fn 8000001d - 8000001e"),
283 CPUID_FEATURE_DEF(23, "perfctr_core", "Core performance counter"),
284 CPUID_FEATURE_DEF(24, "perfctr_nb", "NB performance counter"),
285 CPUID_FEATURE_DEF(26, "bpext", "Data breakpoint extensions"),
286 CPUID_FEATURE_DEF(27, "perftsc", "Performance TCS"),
287 CPUID_FEATURE_DEF(28, "perfctr_l2", "L2 performance counter"),
288 CPUID_FEATURE_DEF(29, "mwaitx", "MONITORX/MWAITX"),
289 { -1 }
290 };
291 static struct {
292 int bit;
293 char *desc;
294 } cap_ext[] = {
295 CPUID_FEATURE_DEF(0, "fsgsbase", "{RD/WR}{FS/GS}BASE instructions"),
296 CPUID_FEATURE_DEF(1, "tsc_adjust", "TSC adjustment MSR 0x3b"),
297 CPUID_FEATURE_DEF(2, "sgx", "Software Guard Extensions"),
298 CPUID_FEATURE_DEF(3, "bmi1", "1st group bit manipulation"),
299 CPUID_FEATURE_DEF(4, "hle", "Hardware Lock Elision"),
300 CPUID_FEATURE_DEF(5, "avx2", "AVX2 instructions"),
301 CPUID_FEATURE_DEF(7, "smep", "Supervisor mode execution protection"),
302 CPUID_FEATURE_DEF(8, "bmi2", "2nd group bit manipulation"),
303 CPUID_FEATURE_DEF(9, "erms", "Enhanced REP MOVSB/STOSB"),
304 CPUID_FEATURE_DEF(10, "invpcid", "Invalidate processor context ID"),
305 CPUID_FEATURE_DEF(11, "rtm", "Restricted Transactional Memory"),
306 CPUID_FEATURE_DEF(12, "cqm", "Cache QoS Monitoring"),
307 CPUID_FEATURE_DEF(14, "mpx", "Memory Protection Extension"),
308 CPUID_FEATURE_DEF(16, "avx512f", "AVX-512 Foundation"),
309 CPUID_FEATURE_DEF(17, "avx512dq", "AVX-512 Double/Quad granular"),
310 CPUID_FEATURE_DEF(18, "rdseed", "The RDSEED instruction"),
311 CPUID_FEATURE_DEF(19, "adx", "ADCX and ADOX instructions"),
312 CPUID_FEATURE_DEF(20, "smap", "Supservisor mode access prevention"),
313 CPUID_FEATURE_DEF(22, "pcommit", "PCOMMIT instruction"),
314 CPUID_FEATURE_DEF(23, "clflushopt", "CLFLUSHOPT instruction"),
315 CPUID_FEATURE_DEF(24, "clwb", "CLWB instruction"),
316 CPUID_FEATURE_DEF(26, "avx512pf", "AVX-512 Prefetch"),
317 CPUID_FEATURE_DEF(27, "avx512er", "AVX-512 Exponential and Reciprocal"),
318 CPUID_FEATURE_DEF(28, "avx512cd", "AVX-512 Conflict Detection"),
319 CPUID_FEATURE_DEF(29, "sha_ni", "SHA extensions"),
320 CPUID_FEATURE_DEF(30, "avx512bw", "AVX-512 Byte/Word granular"),
321 CPUID_FEATURE_DEF(31, "avx512vl", "AVX-512 128/256 Vector Length"),
322 { -1 }
323 };
324
325 unsigned int family, model, stepping;
326
327 regs = cpuid(1, 0);
328 family = (regs.eax >> 8) & 0xf;
329 model = (regs.eax >> 4) & 0xf;
330 stepping = regs.eax & 0xf;
331
332 if (family == 0xf)
333 family += (regs.eax >> 20) & 0xff;
334 if (family == 0xf || family == 6)
335 model += ((regs.eax >> 16) & 0xf) << 4;
336
337 printf("cpu family\t: %d\n"
338 "model\t\t: %d\n"
339 "stepping\t: %d\n" ,
340 family,
341 model,
342 stepping);
343
344 if (strstr(idstr, "Intel") && !model_name) {
345 if (family == 6 && model == 0xb && stepping == 1)
346 model_name = "Intel (R) Celeron (R) processor";
347 else
348 model_name = brandname(regs.ebx & 0xf);
349 }
350
351 printf("flags\t\t:");
352 for (i = 0; cap[i].bit >= 0; i++) {
353 if (regs.edx & (1 << cap[i].bit)) {
354 printf(" %s", cap[i].desc);
355 }
356 }
357 for (i = 0; cap2[i].bit >= 0; i++) {
358 if (regs.ecx & (1 << cap2[i].bit)) {
359 printf(" %s", cap2[i].desc);
360 }
361 }
362 /* k6_mtrr is supported by some AMD K6-2/K6-III CPUs but
363 it is not indicated by a CPUID feature bit, so we
364 have to check the family, model and stepping instead. */
365 if (strstr(idstr, "AMD") &&
366 family == 5 &&
367 (model >= 9 || (model == 8 && stepping >= 8)))
368 printf(" %s", "k6_mtrr");
369 /* similar for cyrix_arr. */
370 if (strstr(idstr, "Cyrix") &&
371 (family == 5 && (model < 4 || family == 6)))
372 printf(" %s", "cyrix_arr");
373 /* as well as centaur_mcr. */
374 if (strstr(idstr, "Centaur") &&
375 family == 5)
376 printf(" %s", "centaur_mcr");
377
378 for (i = 0; cap_amd[i].bit >= 0; i++) {
379 if (amd_flags & (1 << cap_amd[i].bit)) {
380 printf(" %s", cap_amd[i].desc);
381 }
382 }
383 for (i = 0; cap_amd2[i].bit >= 0; i++) {
384 if (amd_flags2 & (1 << cap_amd2[i].bit)) {
385 printf(" %s", cap_amd2[i].desc);
386 }
387 }
388 for (i = 0; cap_ext[i].bit >= 0; i++) {
389 if (ext_flags & (1 << cap_ext[i].bit)) {
390 printf(" %s", cap_ext[i].desc);
391 }
392 }
393 printf("\n");
394
395 if (regs.edx & (1 << 4)) {
396 int64_t tsc_start, tsc_end;
397 struct timeval tv_start, tv_end;
398 int usec_delay;
399
400 tsc_start = rdtsc();
401 gettimeofday(&tv_start, NULL);
402 #ifdef MISSING_USLEEP
403 sleep(1);
404 #else
405 usleep(100000);
406 #endif
407 tsc_end = rdtsc();
408 gettimeofday(&tv_end, NULL);
409
410 usec_delay = 1000000 * (tv_end.tv_sec - tv_start.tv_sec)
411 + (tv_end.tv_usec - tv_start.tv_usec);
412
413 printf("cpu MHz\t\t: %.3f\n",
414 (double)(tsc_end-tsc_start) / usec_delay);
415 }
416 }
417
418 printf("model name\t: ");
419 if (model_name)
420 printf("%s\n", model_name);
421 else
422 printf("Unknown %s CPU\n", idstr);
423 }
424