1 /*
2 * VIDIX driver for ATI Mach64 and 3DRage chipsets.
3 *
4 * Copyright (C) 2002 Nick Kurshev
5 * This file is based on sources from
6 * GATOS (gatos.sf.net) and X11 (www.xfree86.org)
7 *
8 * This file is part of MPlayer.
9 *
10 * MPlayer is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * MPlayer is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with MPlayer; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25 #include <errno.h>
26 #include <stdio.h>
27 #include <stdlib.h>
28 #include <string.h>
29 #include <math.h>
30 #include <inttypes.h>
31 #include <fcntl.h>
32
33 #include "config.h"
34 #include "libavutil/common.h"
35 #include "mpbswap.h"
36 #include "vidix.h"
37 #include "fourcc.h"
38 #include "dha.h"
39 #include "pci_ids.h"
40 #include "pci_names.h"
41 #include "mp_msg.h"
42
43 #include "mach64.h"
44
45 #define UNUSED(x) ((void)(x)) /**< Removes warning about unused arguments */
46
47 static void *mach64_mmio_base = 0;
48 static void *mach64_mem_base = 0;
49 static int32_t mach64_overlay_offset = 0;
50 static uint32_t mach64_ram_size = 0;
51 static uint32_t mach64_buffer_base[10][3];
52 static int num_mach64_buffers=-1;
53 static int supports_planar=0;
54 static int supports_lcd_v_stretch=0;
55
56 static pciinfo_t pci_info;
57 static int probed = 0;
58 static int verbosity = 0;
59
60 #define VERBOSE_LEVEL 1
61
62 typedef struct bes_registers_s
63 {
64 /* base address of yuv framebuffer */
65 uint32_t yuv_base;
66 uint32_t fourcc;
67 /* YUV BES registers */
68 uint32_t reg_load_cntl;
69 uint32_t scale_inc;
70 uint32_t y_x_start;
71 uint32_t y_x_end;
72 uint32_t vid_buf_pitch;
73 uint32_t height_width;
74
75 uint32_t scale_cntl;
76 uint32_t exclusive_horz;
77 uint32_t auto_flip_cntl;
78 uint32_t filter_cntl;
79 uint32_t key_cntl;
80 uint32_t test;
81 /* Configurable stuff */
82
83 int brightness;
84 int saturation;
85
86 int ckey_on;
87 uint32_t graphics_key_clr;
88 uint32_t graphics_key_msk;
89
90 int deinterlace_on;
91 uint32_t deinterlace_pattern;
92
93 } bes_registers_t;
94
95 static bes_registers_t besr;
96
97 typedef struct video_registers_s
98 {
99 const char * sname;
100 uint32_t name;
101 uint32_t value;
102 }video_registers_t;
103
104 /* Graphic keys */
105 static vidix_grkey_t mach64_grkey;
106
107 #define DECLARE_VREG(name) { #name, name, 0 }
108 static video_registers_t vregs[] =
109 {
110 DECLARE_VREG(OVERLAY_SCALE_INC),
111 DECLARE_VREG(OVERLAY_Y_X_START),
112 DECLARE_VREG(OVERLAY_Y_X_END),
113 DECLARE_VREG(OVERLAY_SCALE_CNTL),
114 DECLARE_VREG(OVERLAY_EXCLUSIVE_HORZ),
115 DECLARE_VREG(OVERLAY_EXCLUSIVE_VERT),
116 DECLARE_VREG(OVERLAY_TEST),
117 DECLARE_VREG(SCALER_BUF_PITCH),
118 DECLARE_VREG(SCALER_HEIGHT_WIDTH),
119 DECLARE_VREG(SCALER_BUF0_OFFSET),
120 DECLARE_VREG(SCALER_BUF0_OFFSET_U),
121 DECLARE_VREG(SCALER_BUF0_OFFSET_V),
122 DECLARE_VREG(SCALER_BUF1_OFFSET),
123 DECLARE_VREG(SCALER_BUF1_OFFSET_U),
124 DECLARE_VREG(SCALER_BUF1_OFFSET_V),
125 DECLARE_VREG(SCALER_H_COEFF0),
126 DECLARE_VREG(SCALER_H_COEFF1),
127 DECLARE_VREG(SCALER_H_COEFF2),
128 DECLARE_VREG(SCALER_H_COEFF3),
129 DECLARE_VREG(SCALER_H_COEFF4),
130 DECLARE_VREG(SCALER_COLOUR_CNTL),
131 DECLARE_VREG(SCALER_THRESHOLD),
132 DECLARE_VREG(VIDEO_FORMAT),
133 DECLARE_VREG(VIDEO_CONFIG),
134 DECLARE_VREG(VIDEO_SYNC_TEST),
135 DECLARE_VREG(VIDEO_SYNC_TEST_B)
136 };
137
138 /* have to restore it on exit */
139 static uint32_t SAVED_OVERLAY_GRAPHICS_KEY_CLR;
140
141 /* VIDIX exports */
142
143 /* MMIO space*/
144 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ))))
145 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL
146
147 #define INREG8(addr) GETREG(uint8_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2)
148 #define OUTREG8(addr,val) SETREG(uint8_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2,val)
149
INREG(uint32_t addr)150 static inline uint32_t INREG (uint32_t addr) {
151 uint32_t tmp = GETREG(uint32_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2);
152 return le2me_32(tmp);
153 }
154 #define OUTREG(addr,val) SETREG(uint32_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2,le2me_32(val))
155
156 #define OUTREGP(addr,val,mask) \
157 do { \
158 unsigned int _tmp = INREG(addr); \
159 _tmp &= (mask); \
160 _tmp |= (val); \
161 OUTREG(addr, _tmp); \
162 } while (0)
163
ATIGetMach64LCDReg(int _Index)164 static inline int ATIGetMach64LCDReg(int _Index)
165 {
166 OUTREG8(LCD_INDEX, _Index);
167 return INREG(LCD_DATA);
168 }
169
INPLL(uint32_t addr)170 static inline uint32_t INPLL(uint32_t addr)
171 {
172 uint32_t res;
173 uint32_t in;
174
175 in= INREG(CLOCK_CNTL);
176 in &= ~((PLL_WR_EN | PLL_ADDR)); //clean some stuff
177 OUTREG(CLOCK_CNTL, in | (addr<<10));
178
179 /* read the register value */
180 res = (INREG(CLOCK_CNTL)>>16)&0xFF;
181 return res;
182 }
183
OUTPLL(uint32_t addr,uint32_t val)184 static inline void OUTPLL(uint32_t addr, uint32_t val)
185 {
186 //FIXME buggy but its not used
187 /* write addr byte */
188 OUTREG8(CLOCK_CNTL + 1, (addr << 2) | PLL_WR_EN);
189 /* write the register value */
190 OUTREG(CLOCK_CNTL + 2, val);
191 OUTREG8(CLOCK_CNTL + 1, (addr << 2) & ~PLL_WR_EN);
192 }
193
194 #define OUTPLLP(addr,val,mask) \
195 do { \
196 unsigned int _tmp = INPLL(addr); \
197 _tmp &= (mask); \
198 _tmp |= (val); \
199 OUTPLL(addr, _tmp); \
200 } while (0)
201
mach64_fifo_wait(unsigned n)202 static void mach64_fifo_wait(unsigned n)
203 {
204 while ((INREG(FIFO_STAT) & 0xffff) > ((uint32_t)(0x8000 >> n)));
205 }
206
mach64_wait_for_idle(void)207 static void mach64_wait_for_idle( void )
208 {
209 mach64_fifo_wait(16);
210 while ((INREG(GUI_STAT) & 1)!= 0);
211 }
212
mach64_wait_vsync(void)213 static void mach64_wait_vsync( void )
214 {
215 int i;
216
217 for(i=0; i<2000000; i++)
218 if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK)==0 ) break;
219 for(i=0; i<2000000; i++)
220 if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK) ) break;
221
222 }
223
224 static const vidix_capability_t mach64_cap =
225 {
226 "BES driver for Mach64/3DRage cards",
227 "Nick Kurshev and Michael Niedermayer",
228 TYPE_OUTPUT,
229 { 0, 0, 0, 0 },
230 2048,
231 2048,
232 4,
233 4,
234 -1,
235 FLAG_UPSCALER|FLAG_DOWNSCALER,
236 VENDOR_ATI,
237 -1,
238 { 0, 0, 0, 0 }
239 };
240
mach64_vid_get_dbpp(void)241 static uint32_t mach64_vid_get_dbpp( void )
242 {
243 uint32_t dbpp,retval;
244 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0x7;
245 switch(dbpp)
246 {
247 case 1: retval = 4; break;
248 case 2: retval = 8; break;
249 case 3: retval = 15; break;
250 case 4: retval = 16; break;
251 case 5: retval = 24; break;
252 default: retval=32; break;
253 }
254 return retval;
255 }
256
mach64_is_dbl_scan(void)257 static int mach64_is_dbl_scan( void )
258 {
259 return INREG(CRTC_GEN_CNTL) & CRTC_DBL_SCAN_EN;
260 }
261
mach64_is_interlace(void)262 static int mach64_is_interlace( void )
263 {
264 return INREG(CRTC_GEN_CNTL) & CRTC_INTERLACE_EN;
265 }
266
mach64_get_xres(void)267 static uint32_t mach64_get_xres( void )
268 {
269 /* FIXME: currently we extract that from CRTC!!!*/
270 uint32_t xres,h_total;
271 h_total = INREG(CRTC_H_TOTAL_DISP);
272 xres = (h_total >> 16) & 0xffff;
273 return (xres + 1)*8;
274 }
275
mach64_get_yres(void)276 static uint32_t mach64_get_yres( void )
277 {
278 /* FIXME: currently we extract that from CRTC!!!*/
279 uint32_t yres,v_total;
280 v_total = INREG(CRTC_V_TOTAL_DISP);
281 yres = (v_total >> 16) & 0xffff;
282 return yres + 1;
283 }
284
285 // returns the verical stretch factor in 16.16
mach64_get_vert_stretch(void)286 static int mach64_get_vert_stretch(void)
287 {
288 int lcd_index;
289 int vert_stretching;
290 int ext_vert_stretch;
291 int ret;
292 int yres= mach64_get_yres();
293
294 if(!supports_lcd_v_stretch){
295 if(verbosity > 0) mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] vertical stretching not supported\n");
296 return 1<<16;
297 }
298
299 lcd_index= INREG(LCD_INDEX);
300
301 vert_stretching= ATIGetMach64LCDReg(LCD_VERT_STRETCHING);
302 if(!(vert_stretching&VERT_STRETCH_EN)) ret= 1<<16;
303 else
304 {
305 int panel_size;
306
307 ext_vert_stretch= ATIGetMach64LCDReg(LCD_EXT_VERT_STRETCH);
308 panel_size= (ext_vert_stretch&VERT_PANEL_SIZE)>>11;
309 panel_size++;
310
311 ret= ((yres<<16) + (panel_size>>1))/panel_size;
312 }
313
314 // lcd_gen_ctrl = ATIGetMach64LCDReg(LCD_GEN_CNTL);
315
316 OUTREG(LCD_INDEX, lcd_index);
317
318 if(verbosity > 0) mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] vertical stretching factor= %d\n", ret);
319
320 return ret;
321 }
322
mach64_vid_make_default(void)323 static void mach64_vid_make_default(void)
324 {
325 mach64_fifo_wait(5);
326 OUTREG(SCALER_COLOUR_CNTL,0x00101000);
327
328 besr.ckey_on=0;
329 besr.graphics_key_msk=0;
330 besr.graphics_key_clr=0;
331
332 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk);
333 OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr);
334 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND);
335
336 }
337
mach64_vid_dump_regs(void)338 static void mach64_vid_dump_regs( void )
339 {
340 size_t i;
341 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] *** Begin of DRIVER variables dump ***\n");
342 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] mach64_mmio_base=%p\n",mach64_mmio_base);
343 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] mach64_mem_base=%p\n",mach64_mem_base);
344 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] mach64_overlay_off=%08X\n",mach64_overlay_offset);
345 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] mach64_ram_size=%08X\n",mach64_ram_size);
346 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp());
347 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] *** Begin of OV0 registers dump ***\n");
348 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
349 {
350 mach64_wait_for_idle();
351 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] %s = %08X\n",vregs[i].sname,INREG(vregs[i].name));
352 }
353 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] *** End of OV0 registers dump ***\n");
354 }
355
356
357 static unsigned short ati_card_ids[] =
358 {
359 DEVICE_ATI_215CT_MACH64_CT,
360 DEVICE_ATI_210888CX_MACH64_CX,
361 DEVICE_ATI_210888ET_MACH64_ET,
362 DEVICE_ATI_MACH64_VT,
363 DEVICE_ATI_210888GX_MACH64_GX,
364 DEVICE_ATI_264LT_MACH64_LT,
365 DEVICE_ATI_264VT_MACH64_VT,
366 DEVICE_ATI_264VT3_MACH64_VT3,
367 DEVICE_ATI_264VT4_MACH64_VT4,
368 /**/
369 DEVICE_ATI_3D_RAGE_PRO,
370 DEVICE_ATI_3D_RAGE_PRO2,
371 DEVICE_ATI_3D_RAGE_PRO3,
372 DEVICE_ATI_3D_RAGE_PRO4,
373 DEVICE_ATI_RAGE_XC,
374 DEVICE_ATI_RAGE_XL_AGP,
375 DEVICE_ATI_RAGE_XC_AGP,
376 DEVICE_ATI_RAGE_XL,
377 DEVICE_ATI_3D_RAGE_PRO5,
378 DEVICE_ATI_3D_RAGE_PRO6,
379 DEVICE_ATI_RAGE_XL2,
380 DEVICE_ATI_RAGE_XC2,
381 DEVICE_ATI_3D_RAGE_I_II,
382 DEVICE_ATI_3D_RAGE_II,
383 DEVICE_ATI_3D_RAGE_IIC,
384 DEVICE_ATI_3D_RAGE_IIC2,
385 DEVICE_ATI_3D_RAGE_IIC3,
386 DEVICE_ATI_3D_RAGE_IIC4,
387 DEVICE_ATI_3D_RAGE_LT,
388 DEVICE_ATI_3D_RAGE_LT2,
389 DEVICE_ATI_3D_RAGE_LT_G,
390 DEVICE_ATI_3D_RAGE_LT3,
391 DEVICE_ATI_RAGE_MOBILITY_P_M,
392 DEVICE_ATI_RAGE_MOBILITY_L,
393 DEVICE_ATI_3D_RAGE_LT4,
394 DEVICE_ATI_3D_RAGE_LT5,
395 DEVICE_ATI_RAGE_MOBILITY_P_M2,
396 DEVICE_ATI_RAGE_MOBILITY_L2
397 };
398
find_chip(unsigned chip_id)399 static int find_chip(unsigned chip_id)
400 {
401 unsigned i;
402 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++)
403 {
404 if(chip_id == ati_card_ids[i]) return i;
405 }
406 return -1;
407 }
408
mach64_probe(int verbose,int force)409 static int mach64_probe(int verbose,int force)
410 {
411 pciinfo_t lst[MAX_PCI_DEVICES];
412 unsigned i,num_pci;
413 int err;
414 verbosity = verbose;
415 err = pci_scan(lst,&num_pci);
416 if(err)
417 {
418 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] Error occurred during pci scan: %s\n",strerror(err));
419 return err;
420 }
421 else
422 {
423 err = ENXIO;
424 for(i=0;i<num_pci;i++)
425 {
426 if(lst[i].vendor == VENDOR_ATI)
427 {
428 int idx;
429 const char *dname;
430 idx = find_chip(lst[i].device);
431 if(idx == -1 && force == PROBE_NORMAL) continue;
432 dname = pci_device_name(VENDOR_ATI,lst[i].device);
433 dname = dname ? dname : "Unknown chip";
434 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] Found chip: %s\n",dname);
435 #if 0
436 if ((lst[i].command & PCI_COMMAND_IO) == 0)
437 {
438 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] Device is disabled, ignoring\n");
439 continue;
440 }
441 #endif
442 if(force > PROBE_NORMAL)
443 {
444 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : "");
445 if(idx == -1)
446 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] Assuming it as Mach64\n");
447 }
448 err = 0;
449 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t));
450 probed=1;
451 break;
452 }
453 }
454 }
455 if(err && verbose) mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] Can't find chip\n");
456 return err;
457 }
458
reset_regs(void)459 static void reset_regs( void )
460 {
461 size_t i;
462 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
463 {
464 mach64_fifo_wait(2);
465 OUTREG(vregs[i].name,0);
466 }
467 }
468
469
mach64_init(void)470 static int mach64_init(void)
471 {
472 int err;
473 if(!probed)
474 {
475 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] Driver was not probed but is being initializing\n");
476 return EINTR;
477 }
478
479 if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x1000))==(void *)-1) return ENOMEM;
480 mach64_wait_for_idle();
481 mach64_ram_size = INREG(MEM_CNTL) & CTL_MEM_SIZEB;
482 if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512;
483 else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024;
484 else mach64_ram_size = (mach64_ram_size - 7) * 2048;
485 mach64_ram_size *= 0x400; /* KB -> bytes */
486 if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM;
487 memset(&besr,0,sizeof(bes_registers_t));
488 mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000);
489 err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB);
490 if(!err) mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] Set write-combining type of video memory\n");
491
492 /* save this */
493 mach64_wait_for_idle();
494 SAVED_OVERLAY_GRAPHICS_KEY_CLR = INREG(OVERLAY_GRAPHICS_KEY_CLR);
495
496 /* check if planar formats are supported */
497 supports_planar=0;
498 mach64_wait_for_idle();
499 mach64_fifo_wait(2);
500 if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1;
501 else
502 {
503 OUTREG(SCALER_BUF0_OFFSET_U, -1);
504
505 mach64_wait_vsync();
506 mach64_wait_for_idle();
507 mach64_fifo_wait(2);
508
509 if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1;
510 }
511 if(supports_planar) mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] Planar YUV formats are supported :)\n");
512 else mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] Planar YUV formats are not supported :(\n");
513
514 if( pci_info.device==DEVICE_ATI_RAGE_MOBILITY_P_M
515 || pci_info.device==DEVICE_ATI_RAGE_MOBILITY_P_M2
516 || pci_info.device==DEVICE_ATI_RAGE_MOBILITY_L
517 || pci_info.device==DEVICE_ATI_RAGE_MOBILITY_L2)
518 supports_lcd_v_stretch=1;
519 else
520 supports_lcd_v_stretch=0;
521
522 reset_regs();
523 mach64_vid_make_default();
524
525 if(verbosity > VERBOSE_LEVEL) mach64_vid_dump_regs();
526 return 0;
527 }
528
mach64_destroy(void)529 static void mach64_destroy(void)
530 {
531 /*restore this*/
532 mach64_wait_for_idle();
533 OUTREG(OVERLAY_GRAPHICS_KEY_CLR,SAVED_OVERLAY_GRAPHICS_KEY_CLR);
534
535 unmap_phys_mem(mach64_mem_base,mach64_ram_size);
536 unmap_phys_mem(mach64_mmio_base,0x1000);
537 }
538
mach64_get_caps(vidix_capability_t * to)539 static int mach64_get_caps(vidix_capability_t *to)
540 {
541 memcpy(to, &mach64_cap, sizeof(vidix_capability_t));
542 to->device_id = pci_info.device;
543 return 0;
544 }
545
mach64_query_pitch(unsigned fourcc,const vidix_yuv_t * spitch)546 static unsigned mach64_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch)
547 {
548 unsigned pitch,spy,spv,spu;
549 spy = spv = spu = 0;
550 switch(spitch->y)
551 {
552 case 16:
553 case 32:
554 case 64:
555 case 128:
556 case 256: spy = spitch->y; break;
557 default: break;
558 }
559 switch(spitch->u)
560 {
561 case 16:
562 case 32:
563 case 64:
564 case 128:
565 case 256: spu = spitch->u; break;
566 default: break;
567 }
568 switch(spitch->v)
569 {
570 case 16:
571 case 32:
572 case 64:
573 case 128:
574 case 256: spv = spitch->v; break;
575 default: break;
576 }
577 switch(fourcc)
578 {
579 /* 4:2:0 */
580 case IMGFMT_IYUV:
581 case IMGFMT_YV12:
582 case IMGFMT_I420:
583 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy;
584 else pitch = 32;
585 break;
586 case IMGFMT_YVU9:
587 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy;
588 else pitch = 64;
589 break;
590 default:
591 if(spy >= 16) pitch = spy;
592 else pitch = 16;
593 break;
594 }
595 return pitch;
596 }
597
mach64_compute_framesize(vidix_playback_t * info)598 static void mach64_compute_framesize(vidix_playback_t *info)
599 {
600 unsigned pitch,awidth;
601 pitch = mach64_query_pitch(info->fourcc,&info->src.pitch);
602 switch(info->fourcc)
603 {
604 case IMGFMT_I420:
605 case IMGFMT_YV12:
606 case IMGFMT_IYUV:
607 awidth = (info->src.w + (pitch-1)) & ~(pitch-1);
608 info->frame_size = awidth*(info->src.h+info->src.h/2);
609 break;
610 case IMGFMT_YVU9:
611 awidth = (info->src.w + (pitch-1)) & ~(pitch-1);
612 info->frame_size = awidth*(info->src.h+info->src.h/8);
613 break;
614 // case IMGFMT_RGB32:
615 case IMGFMT_BGR32:
616 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1);
617 info->frame_size = (awidth*info->src.h);
618 break;
619 /* YUY2 YVYU, RGB15, RGB16 */
620 default:
621 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1);
622 info->frame_size = (awidth*info->src.h);
623 break;
624 }
625 info->frame_size+=256; // so we have some space for alignment & such
626 info->frame_size&=~16;
627 }
628
mach64_vid_stop_video(void)629 static void mach64_vid_stop_video( void )
630 {
631 mach64_fifo_wait(14);
632 OUTREG(OVERLAY_SCALE_CNTL, 0x80000000);
633 OUTREG(OVERLAY_EXCLUSIVE_HORZ, 0);
634 OUTREG(OVERLAY_EXCLUSIVE_VERT, 0);
635 OUTREG(SCALER_H_COEFF0, 0x00002000);
636 OUTREG(SCALER_H_COEFF1, 0x0D06200D);
637 OUTREG(SCALER_H_COEFF2, 0x0D0A1C0D);
638 OUTREG(SCALER_H_COEFF3, 0x0C0E1A0C);
639 OUTREG(SCALER_H_COEFF4, 0x0C14140C);
640 OUTREG(VIDEO_FORMAT, 0xB000B);
641 OUTREG(OVERLAY_TEST, 0x0);
642 }
643
mach64_vid_display_video(void)644 static void mach64_vid_display_video( void )
645 {
646 mach64_fifo_wait(14);
647
648 OUTREG(OVERLAY_Y_X_START, besr.y_x_start);
649 OUTREG(OVERLAY_Y_X_END, besr.y_x_end);
650 OUTREG(OVERLAY_SCALE_INC, besr.scale_inc);
651 OUTREG(SCALER_BUF_PITCH, besr.vid_buf_pitch);
652 OUTREG(SCALER_HEIGHT_WIDTH, besr.height_width);
653 OUTREG(SCALER_BUF0_OFFSET, mach64_buffer_base[0][0]);
654 OUTREG(SCALER_BUF0_OFFSET_U, mach64_buffer_base[0][1]);
655 OUTREG(SCALER_BUF0_OFFSET_V, mach64_buffer_base[0][2]);
656 OUTREG(SCALER_BUF1_OFFSET, mach64_buffer_base[0][0]);
657 OUTREG(SCALER_BUF1_OFFSET_U, mach64_buffer_base[0][1]);
658 OUTREG(SCALER_BUF1_OFFSET_V, mach64_buffer_base[0][2]);
659 mach64_wait_vsync();
660
661 mach64_fifo_wait(4);
662 OUTREG(OVERLAY_SCALE_CNTL, 0xC4000003);
663 // OVERLAY_SCALE_CNTL bits & what they seem to affect
664 // bit 0 no effect
665 // bit 1 yuv2rgb coeff related
666 // bit 2 horizontal interpolation if 0
667 // bit 3 vertical interpolation if 0
668 // bit 4 chroma encoding (0-> 128=neutral / 1-> 0->neutral)
669 // bit 5-6 gamma correction
670 // bit 7 nothing visible if set
671 // bit 8-27 no effect
672 // bit 28-31 nothing interresting just crashed my system when i played with them :(
673
674 mach64_wait_for_idle();
675 INREG(VIDEO_FORMAT);
676
677 // Bits 16-19 seem to select the format
678 // 0x0 dunno behaves strange
679 // 0x1 dunno behaves strange
680 // 0x2 dunno behaves strange
681 // 0x3 BGR15
682 // 0x4 BGR16
683 // 0x5 BGR16 (hmm, that need investigation, 2 BGR16 formats, i guess 1 will have only 5bits for green)
684 // 0x6 BGR32
685 // 0x7 BGR32 with somehow mixed even / odd pixels ?
686 // 0x8 YYYYUVUV
687 // 0x9 YVU9
688 // 0xA YV12
689 // 0xB YUY2
690 // 0xC UYVY
691 // 0xD UYVY (no difference is visible if i switch between C/D for every even/odd frame)
692 // 0xE dunno behaves strange
693 // 0xF dunno behaves strange
694 // Bit 28 all values are assumed to be 7 bit with chroma=64 for black (tested with YV12 & YUY2)
695 // the remaining bits seem to have no effect
696
697
698 switch(besr.fourcc)
699 {
700 /* BGR formats */
701 case IMGFMT_BGR15: OUTREG(VIDEO_FORMAT, 0x00030000); break;
702 case IMGFMT_BGR16: OUTREG(VIDEO_FORMAT, 0x00040000); break;
703 case IMGFMT_BGR32: OUTREG(VIDEO_FORMAT, 0x00060000); break;
704 /* 4:2:0 */
705 case IMGFMT_IYUV:
706 case IMGFMT_I420:
707 case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, 0x000A0000); break;
708
709 case IMGFMT_YVU9: OUTREG(VIDEO_FORMAT, 0x00090000); break;
710 /* 4:2:2 */
711 case IMGFMT_YVYU:
712 case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, 0x000C0000); break;
713 case IMGFMT_YUY2:
714 default: OUTREG(VIDEO_FORMAT, 0x000B0000); break;
715 }
716 if(verbosity > VERBOSE_LEVEL) mach64_vid_dump_regs();
717 }
718
mach64_vid_init_video(vidix_playback_t * config)719 static int mach64_vid_init_video( vidix_playback_t *config )
720 {
721 uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,top,ecp,y_pos;
722 int is_420,best_pitch,mpitch;
723 int src_offset_y, src_offset_u, src_offset_v;
724 unsigned int i;
725
726 mach64_vid_stop_video();
727 /* warning, if left or top are != 0 this will fail, as the framesize is too small then */
728 left = config->src.x;
729 top = config->src.y;
730 src_h = config->src.h;
731 src_w = config->src.w;
732 is_420 = 0;
733 if(config->fourcc == IMGFMT_YV12 ||
734 config->fourcc == IMGFMT_I420 ||
735 config->fourcc == IMGFMT_IYUV) is_420 = 1;
736 best_pitch = mach64_query_pitch(config->fourcc,&config->src.pitch);
737 mpitch = best_pitch-1;
738 switch(config->fourcc)
739 {
740 case IMGFMT_YVU9:
741 /* 4:2:0 */
742 case IMGFMT_IYUV:
743 case IMGFMT_YV12:
744 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch;
745 config->dest.pitch.y =
746 config->dest.pitch.u =
747 config->dest.pitch.v = best_pitch;
748 besr.vid_buf_pitch= pitch;
749 break;
750 /* RGB 4:4:4:4 */
751 case IMGFMT_RGB32:
752 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch;
753 config->dest.pitch.y =
754 config->dest.pitch.u =
755 config->dest.pitch.v = best_pitch;
756 besr.vid_buf_pitch= pitch>>2;
757 break;
758 /* 4:2:2 */
759 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */
760 pitch = ((src_w*2) + mpitch) & ~mpitch;
761 config->dest.pitch.y =
762 config->dest.pitch.u =
763 config->dest.pitch.v = best_pitch;
764 besr.vid_buf_pitch= pitch>>1;
765 break;
766 }
767 dest_w = config->dest.w;
768 dest_h = config->dest.h;
769 besr.fourcc = config->fourcc;
770 ecp = (INPLL(PLL_VCLK_CNTL) & PLL_ECP_DIV) >> 4;
771
772 if(verbosity > 0) mp_msg(MSGT_VO, MSGL_STATUS, "[mach64] ecp: %d\n", ecp);
773 v_inc = src_h * mach64_get_vert_stretch();
774
775 if(mach64_is_interlace()) v_inc<<=1;
776 if(mach64_is_dbl_scan() ) v_inc>>=1;
777 v_inc>>=4; // convert 16.16 -> 20.12
778 v_inc/= dest_h;
779
780 h_inc = (src_w << (12+ecp)) / dest_w;
781 /* keep everything in 16.16 */
782 config->offsets[0] = 0;
783 for(i=1; i<config->num_frames; i++)
784 config->offsets[i] = config->offsets[i-1] + config->frame_size;
785
786 /*FIXME the left / top stuff is broken (= zoom a src rectangle from a larger one)
787 1. the framesize isn't known as the outer src rectangle dimensions aren't known
788 2. the mach64 needs aligned addresses so it can't work anyway
789 -> so we could shift the outer buffer to compensate that but that would mean
790 alignment problems for the code which writes into it
791 */
792
793 if(is_420)
794 {
795 config->offset.y= 0;
796 config->offset.u= (pitch*src_h + 15)&~15;
797 config->offset.v= (config->offset.u + (pitch*src_h>>2) + 15)&~15;
798
799 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV)
800 {
801 uint32_t tmp;
802 tmp = config->offset.u;
803 config->offset.u = config->offset.v;
804 config->offset.v = tmp;
805 }
806
807 src_offset_y= config->offset.y + top*pitch + left;
808 src_offset_u= config->offset.u + (top*pitch>>2) + (left>>1);
809 src_offset_v= config->offset.v + (top*pitch>>2) + (left>>1);
810 }
811 else if(besr.fourcc == IMGFMT_YVU9)
812 {
813 config->offset.y= 0;
814 config->offset.u= (pitch*src_h + 15)&~15;
815 config->offset.v= (config->offset.u + (pitch*src_h>>4) + 15)&~15;
816
817 src_offset_y= config->offset.y + top*pitch + left;
818 src_offset_u= config->offset.u + (top*pitch>>4) + (left>>1);
819 src_offset_v= config->offset.v + (top*pitch>>4) + (left>>1);
820 }
821 else if(besr.fourcc == IMGFMT_BGR32)
822 {
823 config->offset.y = config->offset.u = config->offset.v = 0;
824 src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 2);
825 }
826 else
827 {
828 config->offset.y = config->offset.u = config->offset.v = 0;
829 src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 1);
830 }
831
832 num_mach64_buffers= config->num_frames;
833 for(i=0; i<config->num_frames; i++)
834 {
835 mach64_buffer_base[i][0]= (mach64_overlay_offset + config->offsets[i] + src_offset_y)&~15;
836 mach64_buffer_base[i][1]= (mach64_overlay_offset + config->offsets[i] + src_offset_u)&~15;
837 mach64_buffer_base[i][2]= (mach64_overlay_offset + config->offsets[i] + src_offset_v)&~15;
838 }
839
840 left = (left >> 16) & 15;
841 besr.scale_inc = ( h_inc << 16 ) | v_inc;
842 y_pos = config->dest.y;
843 if(mach64_is_dbl_scan()) y_pos*=2;
844 else
845 if(mach64_is_interlace()) y_pos/=2;
846 besr.y_x_start = y_pos | (config->dest.x << 16);
847 y_pos =config->dest.y + dest_h;
848 if(mach64_is_dbl_scan()) y_pos*=2;
849 else
850 if(mach64_is_interlace()) y_pos/=2;
851 besr.y_x_end = y_pos | ((config->dest.x + dest_w) << 16);
852 besr.height_width = ((src_w - left)<<16) | (src_h - top);
853
854 return 0;
855 }
856
is_supported_fourcc(uint32_t fourcc)857 static int is_supported_fourcc(uint32_t fourcc)
858 {
859 switch(fourcc)
860 {
861 case IMGFMT_YV12:
862 case IMGFMT_I420:
863 case IMGFMT_YVU9:
864 case IMGFMT_IYUV:
865 return supports_planar;
866 case IMGFMT_YUY2:
867 case IMGFMT_UYVY:
868 case IMGFMT_BGR15:
869 case IMGFMT_BGR16:
870 case IMGFMT_BGR32:
871 return 1;
872 default:
873 return 0;
874 }
875 }
876
mach64_query_fourcc(vidix_fourcc_t * to)877 static int mach64_query_fourcc(vidix_fourcc_t *to)
878 {
879 if(is_supported_fourcc(to->fourcc))
880 {
881 to->depth = VID_DEPTH_ALL;
882 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
883 return 0;
884 }
885 return ENOSYS;
886 }
887
mach64_config_playback(vidix_playback_t * info)888 static int mach64_config_playback(vidix_playback_t *info)
889 {
890 if(!is_supported_fourcc(info->fourcc)) return ENOSYS;
891
892 mach64_compute_framesize(info);
893
894 if(info->num_frames>4) info->num_frames=4;
895 for(;info->num_frames>0; info->num_frames--)
896 {
897 mach64_overlay_offset = mach64_ram_size - info->frame_size*info->num_frames;
898 mach64_overlay_offset &= 0xffff0000;
899 if(mach64_overlay_offset>0) break;
900 }
901 if(info->num_frames <= 0) return EINVAL;
902
903 info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset;
904 mach64_vid_init_video(info);
905 return 0;
906 }
907
mach64_playback_on(void)908 static int mach64_playback_on(void)
909 {
910 mach64_vid_display_video();
911 return 0;
912 }
913
mach64_playback_off(void)914 static int mach64_playback_off(void)
915 {
916 mach64_vid_stop_video();
917 return 0;
918 }
919
mach64_frame_sel(unsigned int frame)920 static int mach64_frame_sel(unsigned int frame)
921 {
922 uint32_t off[6];
923 int i;
924 int last_frame= (frame-1+num_mach64_buffers) % num_mach64_buffers;
925 //mp_msg(MSGT_VO, MSGL_STATUS, "Selecting frame %d\n", frame);
926 /*
927 buf3-5 always should point onto second buffer for better
928 deinterlacing and TV-in
929 */
930 if(num_mach64_buffers==1) return 0;
931
932 for(i=0; i<3; i++)
933 {
934 off[i] = mach64_buffer_base[frame][i];
935 off[i+3]= mach64_buffer_base[last_frame][i];
936 }
937
938 mach64_wait_for_idle();
939 mach64_fifo_wait(7);
940
941 OUTREG(SCALER_BUF0_OFFSET, off[0]);
942 OUTREG(SCALER_BUF0_OFFSET_U, off[1]);
943 OUTREG(SCALER_BUF0_OFFSET_V, off[2]);
944 OUTREG(SCALER_BUF1_OFFSET, off[3]);
945 OUTREG(SCALER_BUF1_OFFSET_U, off[4]);
946 OUTREG(SCALER_BUF1_OFFSET_V, off[5]);
947 if(num_mach64_buffers==2) mach64_wait_vsync(); //only wait for vsync if we do double buffering
948
949 if(verbosity > VERBOSE_LEVEL) mach64_vid_dump_regs();
950 return 0;
951 }
952
953 static vidix_video_eq_t equal =
954 {
955 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION
956 ,
957 0, 0, 0, 0, 0, 0, 0, 0 };
958
mach64_get_eq(vidix_video_eq_t * eq)959 static int mach64_get_eq( vidix_video_eq_t * eq)
960 {
961 memcpy(eq,&equal,sizeof(vidix_video_eq_t));
962 return 0;
963 }
964
mach64_set_eq(const vidix_video_eq_t * eq)965 static int mach64_set_eq( const vidix_video_eq_t * eq)
966 {
967 int br,sat;
968 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness;
969 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast;
970 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation;
971 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue;
972 if(eq->cap & VEQ_CAP_RGB_INTENSITY)
973 {
974 equal.red_intensity = eq->red_intensity;
975 equal.green_intensity = eq->green_intensity;
976 equal.blue_intensity = eq->blue_intensity;
977 }
978 equal.flags = eq->flags;
979 br = equal.brightness * 64 / 1000;
980 if(br < -64) br = -64; if(br > 63) br = 63;
981 sat = (equal.saturation + 1000) * 16 / 1000;
982 if(sat < 0) sat = 0; if(sat > 31) sat = 31;
983 OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16));
984 return 0;
985 }
986
mach64_get_gkeys(vidix_grkey_t * grkey)987 static int mach64_get_gkeys(vidix_grkey_t *grkey)
988 {
989 memcpy(grkey, &mach64_grkey, sizeof(vidix_grkey_t));
990 return 0;
991 }
992
mach64_set_gkeys(const vidix_grkey_t * grkey)993 static int mach64_set_gkeys(const vidix_grkey_t *grkey)
994 {
995 memcpy(&mach64_grkey, grkey, sizeof(vidix_grkey_t));
996
997 if(mach64_grkey.ckey.op == CKEY_TRUE)
998 {
999 besr.ckey_on=1;
1000
1001 switch(mach64_vid_get_dbpp())
1002 {
1003 case 15:
1004 besr.graphics_key_msk=0x7FFF;
1005 besr.graphics_key_clr=
1006 ((mach64_grkey.ckey.blue &0xF8)>>3)
1007 | ((mach64_grkey.ckey.green&0xF8)<<2)
1008 | ((mach64_grkey.ckey.red &0xF8)<<7);
1009 break;
1010 case 16:
1011 besr.graphics_key_msk=0xFFFF;
1012 besr.graphics_key_clr=
1013 ((mach64_grkey.ckey.blue &0xF8)>>3)
1014 | ((mach64_grkey.ckey.green&0xFC)<<3)
1015 | ((mach64_grkey.ckey.red &0xF8)<<8);
1016 //besr.graphics_key_clr=le2me_32(besr.graphics_key_clr);
1017 break;
1018 case 24:
1019 besr.graphics_key_msk=0xFFFFFF;
1020 besr.graphics_key_clr=
1021 ((mach64_grkey.ckey.blue &0xFF))
1022 | ((mach64_grkey.ckey.green&0xFF)<<8)
1023 | ((mach64_grkey.ckey.red &0xFF)<<16);
1024 break;
1025 case 32:
1026 besr.graphics_key_msk=0xFFFFFF;
1027 besr.graphics_key_clr=
1028 ((mach64_grkey.ckey.blue &0xFF))
1029 | ((mach64_grkey.ckey.green&0xFF)<<8)
1030 | ((mach64_grkey.ckey.red &0xFF)<<16);
1031 break;
1032 default:
1033 besr.ckey_on=0;
1034 besr.graphics_key_msk=0;
1035 besr.graphics_key_clr=0;
1036 }
1037 }
1038 else
1039 {
1040 besr.ckey_on=0;
1041 besr.graphics_key_msk=0;
1042 besr.graphics_key_clr=0;
1043 }
1044
1045 mach64_fifo_wait(4);
1046 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk);
1047 OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr);
1048 // OUTREG(OVERLAY_VIDEO_KEY_MSK, 0);
1049 // OUTREG(OVERLAY_VIDEO_KEY_CLR, 0);
1050 if(besr.ckey_on)
1051 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND);
1052 else
1053 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND);
1054
1055 return 0;
1056 }
1057
1058 const VDXDriver mach64_drv = {
1059 "mach64",
1060 NULL,
1061 .probe = mach64_probe,
1062 .get_caps = mach64_get_caps,
1063 .query_fourcc = mach64_query_fourcc,
1064 .init = mach64_init,
1065 .destroy = mach64_destroy,
1066 .config_playback = mach64_config_playback,
1067 .playback_on = mach64_playback_on,
1068 .playback_off = mach64_playback_off,
1069 .frame_sel = mach64_frame_sel,
1070 .get_eq = mach64_get_eq,
1071 .set_eq = mach64_set_eq,
1072 .get_gkey = mach64_get_gkeys,
1073 .set_gkey = mach64_set_gkeys,
1074 };
1075