1 /*
2 * VIDIX driver for Matrox chipsets.
3 *
4 * Copyright (C) 2002 Alex Beregszaszi
5 * Original sources from Aaron Holtzman (C) 1999.
6 * module skeleton based on gutted agpgart module by Jeff Hartmann
7 * <slicer@ionet.net>
8 * YUY2 support and double buffering added by A'rpi/ESP-team
9 * brightness/contrast support by Nick Kurshev/Dariush Pietrzak (eyck)
10 *
11 * This file is part of MPlayer.
12 *
13 * MPlayer is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * MPlayer is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with MPlayer; if not, write to the Free Software Foundation, Inc.,
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
26 */
27
28 /* TODO:
29 * - fix memory size detection (current reading pci userconfig isn't
30 * working as requested - returns the max avail. ram on arch?)
31 * - translate all non-english comments to english
32 */
33
34 //#define CRTC2
35
36 // Set this value, if autodetection fails! (video ram size in megabytes)
37 //#define MGA_MEMORY_SIZE 16
38
39 /* No irq support in userspace implemented yet, do not enable this! */
40 /* disable irq */
41 #define MGA_ALLOW_IRQ 0
42
43 #define MGA_VSYNC_POS 2
44
45 #undef MGA_PCICONFIG_MEMDETECT
46
47 #define MGA_DEFAULT_FRAMES 4
48
49 #include <errno.h>
50 #include <stdio.h>
51 #include <stdlib.h>
52 #include <string.h>
53 #include <math.h>
54 #include <inttypes.h>
55
56 #include "vidix.h"
57 #include "fourcc.h"
58 #include "dha.h"
59 #include "pci_ids.h"
60 #include "pci_names.h"
61 #include "mp_msg.h"
62
63 #ifdef __MINGW32__
64 #define ENOTSUP 134
65 #endif
66
67 #if !defined(ENOTSUP) && defined(EOPNOTSUPP)
68 #define ENOTSUP EOPNOTSUPP
69 #endif
70
71 #define GETREG(TYPE,PTR) (*(volatile TYPE*)(PTR))
72 #define SETREG(TYPE,PTR,VAL) (*(volatile TYPE*)(PTR))=VAL
73
74 #define readb(addr) GETREG(uint8_t,addr)
75 #define writeb(val,addr) SETREG(uint8_t,addr,val)
76 #define readl(addr) GETREG(uint32_t,addr)
77 #define writel(val,addr) SETREG(uint32_t,addr,val)
78
79 static int mga_verbose = 0;
80
81 /* for device detection */
82 static int probed = 0;
83 static pciinfo_t pci_info;
84
85 /* internal booleans */
86 static int mga_vid_in_use = 0;
87 static int is_g400 = 0;
88 static int vid_src_ready = 0;
89 static int vid_overlay_on = 0;
90
91 /* mapped physical addresses */
92 static uint8_t *mga_mmio_base = 0;
93 static uint8_t *mga_mem_base = 0;
94
95 static int mga_src_base = 0; /* YUV buffer position in video memory */
96
97 static uint32_t mga_ram_size = 0; /* how much megabytes videoram we have */
98
99 /* Graphic keys */
100 static vidix_grkey_t mga_grkey;
101
102 static int colkey_saved = 0;
103 static int colkey_on = 0;
104 static unsigned char colkey_color[4];
105 static unsigned char colkey_mask[4];
106
107 /* for IRQ */
108 static int mga_irq = -1;
109
110 static int mga_next_frame = 0;
111
112 static const vidix_capability_t mga_cap =
113 {
114 "Matrox MGA G200/G4x0/G5x0 YUV Video",
115 "Aaron Holtzman, Arpad Gereoffy, Alex Beregszaszi, Nick Kurshev",
116 TYPE_OUTPUT,
117 { 0, 0, 0, 0 },
118 2048,
119 2048,
120 4,
121 4,
122 -1,
123 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER,
124 VENDOR_MATROX,
125 -1, /* will be set in vixProbe */
126 { 0, 0, 0, 0}
127 };
128
129 /* MATROX BES registers */
130 typedef struct bes_registers_s
131 {
132 //BES Control
133 uint32_t besctl;
134 //BES Global control
135 uint32_t besglobctl;
136 //Luma control (brightness and contrast)
137 uint32_t beslumactl;
138 //Line pitch
139 uint32_t bespitch;
140
141 //Buffer A-1 Chroma 3 plane org
142 uint32_t besa1c3org;
143 //Buffer A-1 Chroma org
144 uint32_t besa1corg;
145 //Buffer A-1 Luma org
146 uint32_t besa1org;
147
148 //Buffer A-2 Chroma 3 plane org
149 uint32_t besa2c3org;
150 //Buffer A-2 Chroma org
151 uint32_t besa2corg;
152 //Buffer A-2 Luma org
153 uint32_t besa2org;
154
155 //Buffer B-1 Chroma 3 plane org
156 uint32_t besb1c3org;
157 //Buffer B-1 Chroma org
158 uint32_t besb1corg;
159 //Buffer B-1 Luma org
160 uint32_t besb1org;
161
162 //Buffer B-2 Chroma 3 plane org
163 uint32_t besb2c3org;
164 //Buffer B-2 Chroma org
165 uint32_t besb2corg;
166 //Buffer B-2 Luma org
167 uint32_t besb2org;
168
169 //BES Horizontal coord
170 uint32_t beshcoord;
171 //BES Horizontal inverse scaling [5.14]
172 uint32_t beshiscal;
173 //BES Horizontal source start [10.14] (for scaling)
174 uint32_t beshsrcst;
175 //BES Horizontal source ending [10.14] (for scaling)
176 uint32_t beshsrcend;
177 //BES Horizontal source last
178 uint32_t beshsrclst;
179
180
181 //BES Vertical coord
182 uint32_t besvcoord;
183 //BES Vertical inverse scaling [5.14]
184 uint32_t besviscal;
185 //BES Field 1 vertical source last position
186 uint32_t besv1srclst;
187 //BES Field 1 weight start
188 uint32_t besv1wght;
189 //BES Field 2 vertical source last position
190 uint32_t besv2srclst;
191 //BES Field 2 weight start
192 uint32_t besv2wght;
193
194 } bes_registers_t;
195 static bes_registers_t regs;
196
197 #ifdef CRTC2
198 typedef struct crtc2_registers_s
199 {
200 uint32_t c2ctl;
201 uint32_t c2datactl;
202 uint32_t c2misc;
203 uint32_t c2hparam;
204 uint32_t c2hsync;
205 uint32_t c2offset;
206 uint32_t c2pl2startadd0;
207 uint32_t c2pl2startadd1;
208 uint32_t c2pl3startadd0;
209 uint32_t c2pl3startadd1;
210 uint32_t c2preload;
211 uint32_t c2spicstartadd0;
212 uint32_t c2spicstartadd1;
213 uint32_t c2startadd0;
214 uint32_t c2startadd1;
215 uint32_t c2subpiclut;
216 uint32_t c2vcount;
217 uint32_t c2vparam;
218 uint32_t c2vsync;
219 } crtc2_registers_t;
220 static crtc2_registers_t cregs;
221 #endif
222
223 //All register offsets are converted to word aligned offsets (32 bit)
224 //because we want all our register accesses to be 32 bits
225 #define VCOUNT 0x1e20
226
227 #define PALWTADD 0x3c00 // Index register for X_DATAREG port
228 #define X_DATAREG 0x3c0a
229
230 #define XMULCTRL 0x19
231 #define BPP_8 0x00
232 #define BPP_15 0x01
233 #define BPP_16 0x02
234 #define BPP_24 0x03
235 #define BPP_32_DIR 0x04
236 #define BPP_32_PAL 0x07
237
238 #define XCOLMSK 0x40
239 #define X_COLKEY 0x42
240 #define XKEYOPMODE 0x51
241 #define XCOLMSK0RED 0x52
242 #define XCOLMSK0GREEN 0x53
243 #define XCOLMSK0BLUE 0x54
244 #define XCOLKEY0RED 0x55
245 #define XCOLKEY0GREEN 0x56
246 #define XCOLKEY0BLUE 0x57
247
248 #ifdef CRTC2
249 /*CRTC2 registers*/
250 #define XMISCCTRL 0x1e
251 #define C2CTL 0x3c10
252 #define C2DATACTL 0x3c4c
253 #define C2MISC 0x3c44
254 #define C2HPARAM 0x3c14
255 #define C2HSYNC 0x3c18
256 #define C2OFFSET 0x3c40
257 #define C2PL2STARTADD0 0x3c30 // like BESA1CORG
258 #define C2PL2STARTADD1 0x3c34 // like BESA2CORG
259 #define C2PL3STARTADD0 0x3c38 // like BESA1C3ORG
260 #define C2PL3STARTADD1 0x3c3c // like BESA2C3ORG
261 #define C2PRELOAD 0x3c24
262 #define C2SPICSTARTADD0 0x3c54
263 #define C2SPICSTARTADD1 0x3c58
264 #define C2STARTADD0 0x3c28 // like BESA1ORG
265 #define C2STARTADD1 0x3c2c // like BESA2ORG
266 #define C2SUBPICLUT 0x3c50
267 #define C2VCOUNT 0x3c48
268 #define C2VPARAM 0x3c1c
269 #define C2VSYNC 0x3c20
270 #endif /* CRTC2 */
271
272 // Backend Scaler registers
273 #define BESCTL 0x3d20
274 #define BESGLOBCTL 0x3dc0
275 #define BESLUMACTL 0x3d40
276 #define BESPITCH 0x3d24
277
278 #define BESA1C3ORG 0x3d60
279 #define BESA1CORG 0x3d10
280 #define BESA1ORG 0x3d00
281
282 #define BESA2C3ORG 0x3d64
283 #define BESA2CORG 0x3d14
284 #define BESA2ORG 0x3d04
285
286 #define BESB1C3ORG 0x3d68
287 #define BESB1CORG 0x3d18
288 #define BESB1ORG 0x3d08
289
290 #define BESB2C3ORG 0x3d6C
291 #define BESB2CORG 0x3d1C
292 #define BESB2ORG 0x3d0C
293
294 #define BESHCOORD 0x3d28
295 #define BESHISCAL 0x3d30
296 #define BESHSRCEND 0x3d3C
297 #define BESHSRCLST 0x3d50
298 #define BESHSRCST 0x3d38
299 #define BESV1WGHT 0x3d48
300 #define BESV2WGHT 0x3d4c
301 #define BESV1SRCLST 0x3d54
302 #define BESV2SRCLST 0x3d58
303 #define BESVISCAL 0x3d34
304 #define BESVCOORD 0x3d2c
305 #define BESSTATUS 0x3dc4
306
307 #define CRTCX 0x1fd4
308 #define CRTCD 0x1fd5
309 #define IEN 0x1e1c
310 #define ICLEAR 0x1e18
311 #define STATUS 0x1e14
312
313
314 #ifdef CRTC2
crtc2_frame_sel(int frame)315 static void crtc2_frame_sel(int frame)
316 {
317 switch(frame) {
318 case 0:
319 cregs.c2pl2startadd0=regs.besa1corg;
320 cregs.c2pl3startadd0=regs.besa1c3org;
321 cregs.c2startadd0=regs.besa1org;
322 break;
323 case 1:
324 cregs.c2pl2startadd0=regs.besa2corg;
325 cregs.c2pl3startadd0=regs.besa2c3org;
326 cregs.c2startadd0=regs.besa2org;
327 break;
328 case 2:
329 cregs.c2pl2startadd0=regs.besb1corg;
330 cregs.c2pl3startadd0=regs.besb1c3org;
331 cregs.c2startadd0=regs.besb1org;
332 break;
333 case 3:
334 cregs.c2pl2startadd0=regs.besb2corg;
335 cregs.c2pl3startadd0=regs.besb2c3org;
336 cregs.c2startadd0=regs.besb2org;
337 break;
338 }
339 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0);
340 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0);
341 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0);
342 }
343 #endif
344
mga_frame_select(unsigned int frame)345 static int mga_frame_select(unsigned int frame)
346 {
347 mga_next_frame = frame;
348 if (mga_verbose>1) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] frameselect: %d\n", mga_next_frame);
349 #if MGA_ALLOW_IRQ
350 if (mga_irq == -1)
351 #endif
352 {
353 //we don't need the vcount protection as we're only hitting
354 //one register (and it doesn't seem to be double buffered)
355 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25);
356 writel( regs.besctl, mga_mmio_base + BESCTL );
357
358 // writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16),
359 writel( regs.besglobctl + (MGA_VSYNC_POS<<16),
360 mga_mmio_base + BESGLOBCTL);
361 #ifdef CRTC2
362 crtc2_frame_sel(mga_next_frame);
363 #endif
364 }
365
366 return 0;
367 }
368
369
mga_vid_write_regs(int restore)370 static void mga_vid_write_regs(int restore)
371 {
372 //Make sure internal registers don't get updated until we're done
373 writel( (readl(mga_mmio_base + VCOUNT)-1)<<16,
374 mga_mmio_base + BESGLOBCTL);
375
376 // color or coordinate keying
377
378 if(restore && colkey_saved){
379 // restore it
380 colkey_saved=0;
381
382 // Set color key registers:
383 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
384 writeb( colkey_on, mga_mmio_base + X_DATAREG);
385
386 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
387 writeb( colkey_color[0], mga_mmio_base + X_DATAREG);
388 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
389 writeb( colkey_color[1], mga_mmio_base + X_DATAREG);
390 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
391 writeb( colkey_color[2], mga_mmio_base + X_DATAREG);
392 writeb( X_COLKEY, mga_mmio_base + PALWTADD);
393 writeb( colkey_color[3], mga_mmio_base + X_DATAREG);
394
395 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
396 writeb( colkey_mask[0], mga_mmio_base + X_DATAREG);
397 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
398 writeb( colkey_mask[1], mga_mmio_base + X_DATAREG);
399 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
400 writeb( colkey_mask[2], mga_mmio_base + X_DATAREG);
401 writeb( XCOLMSK, mga_mmio_base + PALWTADD);
402 writeb( colkey_mask[3], mga_mmio_base + X_DATAREG);
403
404 } else if(!colkey_saved){
405 // save it
406 colkey_saved=1;
407 // Get color key registers:
408 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
409 colkey_on=(unsigned char)readb(mga_mmio_base + X_DATAREG) & 1;
410
411 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
412 colkey_color[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
413 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
414 colkey_color[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
415 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
416 colkey_color[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
417 writeb( X_COLKEY, mga_mmio_base + PALWTADD);
418 colkey_color[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
419
420 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
421 colkey_mask[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
422 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
423 colkey_mask[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
424 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
425 colkey_mask[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
426 writeb( XCOLMSK, mga_mmio_base + PALWTADD);
427 colkey_mask[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
428 }
429
430 if(!restore){
431 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
432 writeb( mga_grkey.ckey.op == CKEY_TRUE, mga_mmio_base + X_DATAREG);
433 if ( mga_grkey.ckey.op == CKEY_TRUE )
434 {
435 uint32_t r=0, g=0, b=0;
436
437 writeb( XMULCTRL, mga_mmio_base + PALWTADD);
438 switch (readb (mga_mmio_base + X_DATAREG))
439 {
440 case BPP_8:
441 /* Need to look up the color index, just using
442 color 0 for now. */
443 break;
444
445 case BPP_15:
446 r = mga_grkey.ckey.red >> 3;
447 g = mga_grkey.ckey.green >> 3;
448 b = mga_grkey.ckey.blue >> 3;
449 break;
450
451 case BPP_16:
452 r = mga_grkey.ckey.red >> 3;
453 g = mga_grkey.ckey.green >> 2;
454 b = mga_grkey.ckey.blue >> 3;
455 break;
456
457 case BPP_24:
458 case BPP_32_DIR:
459 case BPP_32_PAL:
460 r = mga_grkey.ckey.red;
461 g = mga_grkey.ckey.green;
462 b = mga_grkey.ckey.blue;
463 break;
464 }
465
466 // Enable colorkeying
467 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
468 writeb( 1, mga_mmio_base + X_DATAREG);
469
470 // Disable color keying on alpha channel
471 writeb( XCOLMSK, mga_mmio_base + PALWTADD);
472 writeb( 0x00, mga_mmio_base + X_DATAREG);
473 writeb( X_COLKEY, mga_mmio_base + PALWTADD);
474 writeb( 0x00, mga_mmio_base + X_DATAREG);
475
476
477 // Set up color key registers
478 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
479 writeb( r, mga_mmio_base + X_DATAREG);
480 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
481 writeb( g, mga_mmio_base + X_DATAREG);
482 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
483 writeb( b, mga_mmio_base + X_DATAREG);
484
485 // Set up color key mask registers
486 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
487 writeb( 0xff, mga_mmio_base + X_DATAREG);
488 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
489 writeb( 0xff, mga_mmio_base + X_DATAREG);
490 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
491 writeb( 0xff, mga_mmio_base + X_DATAREG);
492 }
493 else
494 {
495 // Disable colorkeying
496 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
497 writeb( 0, mga_mmio_base + X_DATAREG);
498 }
499 }
500
501 // Backend Scaler
502 writel( regs.besctl, mga_mmio_base + BESCTL);
503 if(is_g400)
504 writel( regs.beslumactl, mga_mmio_base + BESLUMACTL);
505 writel( regs.bespitch, mga_mmio_base + BESPITCH);
506
507 writel( regs.besa1org, mga_mmio_base + BESA1ORG);
508 writel( regs.besa1corg, mga_mmio_base + BESA1CORG);
509 writel( regs.besa2org, mga_mmio_base + BESA2ORG);
510 writel( regs.besa2corg, mga_mmio_base + BESA2CORG);
511 writel( regs.besb1org, mga_mmio_base + BESB1ORG);
512 writel( regs.besb1corg, mga_mmio_base + BESB1CORG);
513 writel( regs.besb2org, mga_mmio_base + BESB2ORG);
514 writel( regs.besb2corg, mga_mmio_base + BESB2CORG);
515 if(is_g400)
516 {
517 writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG);
518 writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG);
519 writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG);
520 writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG);
521 }
522
523 writel( regs.beshcoord, mga_mmio_base + BESHCOORD);
524 writel( regs.beshiscal, mga_mmio_base + BESHISCAL);
525 writel( regs.beshsrcst, mga_mmio_base + BESHSRCST);
526 writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND);
527 writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST);
528
529 writel( regs.besvcoord, mga_mmio_base + BESVCOORD);
530 writel( regs.besviscal, mga_mmio_base + BESVISCAL);
531
532 writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST);
533 writel( regs.besv1wght, mga_mmio_base + BESV1WGHT);
534 writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST);
535 writel( regs.besv2wght, mga_mmio_base + BESV2WGHT);
536
537 //update the registers somewhere between 1 and 2 frames from now.
538 writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16),
539 mga_mmio_base + BESGLOBCTL);
540
541 if (mga_verbose > 1)
542 {
543 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] wrote BES registers\n");
544 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] BESCTL = 0x%08x\n",
545 readl(mga_mmio_base + BESCTL));
546 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] BESGLOBCTL = 0x%08x\n",
547 readl(mga_mmio_base + BESGLOBCTL));
548 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] BESSTATUS= 0x%08x\n",
549 readl(mga_mmio_base + BESSTATUS));
550 }
551 #ifdef CRTC2
552 writel(((readl(mga_mmio_base + C2CTL) & ~0x03e00000) + (cregs.c2ctl & 0x03e00000)), mga_mmio_base + C2CTL);
553 writel(((readl(mga_mmio_base + C2DATACTL) & ~0x000000ff) + (cregs.c2datactl & 0x000000ff)), mga_mmio_base + C2DATACTL);
554 // ctrc2
555 // disable CRTC2 acording to specs
556 writel(cregs.c2misc, mga_mmio_base + C2MISC);
557
558 if (mga_verbose > 1) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] c2offset = %d\n",cregs.c2offset);
559
560 writel(cregs.c2offset, mga_mmio_base + C2OFFSET);
561 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0);
562 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0);
563 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0);
564 writel(cregs.c2spicstartadd0, mga_mmio_base + C2SPICSTARTADD0);
565 #endif
566 }
567
568 #if MGA_ALLOW_IRQ
enable_irq(void)569 static void enable_irq(void)
570 {
571 long int cc;
572
573 cc = readl(mga_mmio_base + IEN);
574
575 writeb( 0x11, mga_mmio_base + CRTCX);
576
577 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */
578 writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */
579 writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */
580
581 writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL);
582
583 return;
584 }
585
disable_irq(void)586 static void disable_irq(void)
587 {
588 writeb( 0x11, mga_mmio_base + CRTCX);
589 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */
590
591 return;
592 }
593
mga_handle_irq(int irq,void * dev_id)594 void mga_handle_irq(int irq, void *dev_id/*, struct pt_regs *pregs*/) {
595 long int cc;
596
597 if ( irq != -1 ) {
598
599 cc = readl(mga_mmio_base + STATUS);
600 if ( ! (cc & 0x10) ) return; /* vsyncpen */
601 }
602
603 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25);
604 writel( regs.besctl, mga_mmio_base + BESCTL );
605
606 #ifdef CRTC2
607 // sem pridat vyber obrazku !!!!
608 crtc2_frame_sel(mga_next_frame);
609 #endif
610
611 if ( irq != -1 ) {
612 writeb( 0x11, mga_mmio_base + CRTCX);
613 writeb( 0, mga_mmio_base + CRTCD );
614 writeb( 0x10, mga_mmio_base + CRTCD );
615 }
616
617 return;
618
619 }
620 #endif /* MGA_ALLOW_IRQ */
621
mga_config_playback(vidix_playback_t * config)622 static int mga_config_playback(vidix_playback_t *config)
623 {
624 unsigned int i;
625 int x, y, sw, sh, dw, dh;
626 int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights;
627 #ifdef CRTC2
628 #define right_margin 0
629 #define left_margin 18
630 #define hsync_len 46
631 #define lower_margin 10
632 #define vsync_len 4
633 #define upper_margin 39
634
635 unsigned int hdispend = (config->src.w + 31) & ~31;
636 unsigned int hsyncstart = hdispend + (right_margin & ~7);
637 unsigned int hsyncend = hsyncstart + (hsync_len & ~7);
638 unsigned int htotal = hsyncend + (left_margin & ~7);
639 unsigned int vdispend = config->src.h;
640 unsigned int vsyncstart = vdispend + lower_margin;
641 unsigned int vsyncend = vsyncstart + vsync_len;
642 unsigned int vtotal = vsyncend + upper_margin;
643 #endif
644
645 if ((config->num_frames < 1) || (config->num_frames > 4))
646 {
647 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] illegal num_frames: %d, setting to %d\n",
648 config->num_frames, MGA_DEFAULT_FRAMES);
649 config->num_frames = MGA_DEFAULT_FRAMES;
650 }
651
652 x = config->dest.x;
653 y = config->dest.y;
654 sw = config->src.w;
655 sh = config->src.h;
656 dw = config->dest.w;
657 dh = config->dest.h;
658
659 config->dest.pitch.y=32;
660 config->dest.pitch.u=config->dest.pitch.v=32;
661
662 if (mga_verbose) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Setting up a %dx%d-%dx%d video window (src %dx%d) format %X\n",
663 dw, dh, x, y, sw, sh, config->fourcc);
664
665 if ((sw < 4) || (sh < 4) || (dw < 4) || (dh < 4))
666 {
667 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Invalid src/dest dimensions\n");
668 return EINVAL;
669 }
670
671 //FIXME check that window is valid and inside desktop
672
673 sw+=sw&1;
674 switch(config->fourcc)
675 {
676 case IMGFMT_I420:
677 case IMGFMT_IYUV:
678 case IMGFMT_YV12:
679 sh+=sh&1;
680 config->frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2;
681 break;
682 case IMGFMT_YUY2:
683 case IMGFMT_UYVY:
684 config->frame_size = ((sw + 31) & ~31) * sh * 2;
685 break;
686 default:
687 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Unsupported pixel format: %x\n", config->fourcc);
688 return ENOTSUP;
689 }
690
691 config->offsets[0] = 0;
692 for (i = 1; i < config->num_frames+1; i++)
693 config->offsets[i] = i*config->frame_size;
694
695 config->offset.y=0;
696 if(config->fourcc == IMGFMT_I420 || config->fourcc == IMGFMT_IYUV)
697 {
698 config->offset.u=((sw + 31) & ~31) * sh;
699 config->offset.v=config->offset.u+((sw + 31) & ~31) * sh /4;
700 }
701 else {
702 config->offset.v=((sw + 31) & ~31) * sh;
703 config->offset.u=config->offset.v+((sw + 31) & ~31) * sh /4;
704 }
705
706 mga_src_base = (mga_ram_size*0x100000-config->num_frames*config->frame_size);
707 if (mga_src_base < 0)
708 {
709 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] not enough memory for frames!\n");
710 return EFAULT;
711 }
712 mga_src_base &= (~0xFFFF); /* 64k boundary */
713 if (mga_verbose > 1) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] YUV buffer base: %#x\n", mga_src_base);
714
715 config->dga_addr = mga_mem_base + mga_src_base;
716
717 /* for G200 set Interleaved UV planes */
718 if (!is_g400)
719 config->flags = VID_PLAY_INTERLEAVED_UV | INTERLEAVING_UV;
720
721 //Setup the BES registers for a three plane 4:2:0 video source
722
723 regs.besglobctl = 0;
724
725 switch(config->fourcc)
726 {
727 case IMGFMT_YV12:
728 case IMGFMT_I420:
729 case IMGFMT_IYUV:
730 regs.besctl = 1 // BES enabled
731 + (0<<6) // even start polarity
732 + (1<<10) // x filtering enabled
733 + (1<<11) // y filtering enabled
734 + (1<<16) // chroma upsampling
735 + (1<<17) // 4:2:0 mode
736 + (1<<18); // dither enabled
737 break;
738
739 case IMGFMT_YUY2:
740 regs.besctl = 1 // BES enabled
741 + (0<<6) // even start polarity
742 + (1<<10) // x filtering enabled
743 + (1<<11) // y filtering enabled
744 + (1<<16) // chroma upsampling
745 + (0<<17) // 4:2:2 mode
746 + (1<<18); // dither enabled
747
748 regs.besglobctl = 0; // YUY2 format selected
749 break;
750
751 case IMGFMT_UYVY:
752 regs.besctl = 1 // BES enabled
753 + (0<<6) // even start polarity
754 + (1<<10) // x filtering enabled
755 + (1<<11) // y filtering enabled
756 + (1<<16) // chroma upsampling
757 + (0<<17) // 4:2:2 mode
758 + (1<<18); // dither enabled
759
760 regs.besglobctl = 1<<6; // UYVY format selected
761 break;
762
763 }
764
765 //Disable contrast and brightness control
766 regs.besglobctl |= (1<<5) + (1<<7);
767 regs.beslumactl = (0x7f << 16) + (0x80<<0);
768 regs.beslumactl = 0x80<<0;
769
770 //Setup destination window boundaries
771 besleft = x > 0 ? x : 0;
772 bestop = y > 0 ? y : 0;
773 regs.beshcoord = (besleft<<16) + (x + dw-1);
774 regs.besvcoord = (bestop<<16) + (y + dh-1);
775
776 //Setup source dimensions
777 regs.beshsrclst = (sw - 1) << 16;
778 regs.bespitch = (sw + 31) & ~31 ;
779
780 //Setup horizontal scaling
781 ifactor = ((sw-1)<<14)/(dw-1);
782 ofsleft = besleft - x;
783
784 regs.beshiscal = ifactor<<2;
785 regs.beshsrcst = (ofsleft*ifactor)<<2;
786 regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2);
787
788 //Setup vertical scaling
789 ifactor = ((sh-1)<<14)/(dh-1);
790 ofstop = bestop - y;
791
792 regs.besviscal = ifactor<<2;
793
794 baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch;
795 regs.besa1org = (uint32_t) mga_src_base + baseadrofs;
796 regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size;
797 regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size;
798 regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size;
799
800 if(config->fourcc==IMGFMT_YV12
801 ||config->fourcc==IMGFMT_IYUV
802 ||config->fourcc==IMGFMT_I420
803 ){
804 // planar YUV frames:
805 if (is_g400)
806 baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch;
807 else
808 baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch;
809
810 if(config->fourcc==IMGFMT_YV12){
811 regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ;
812 regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh;
813 regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh;
814 regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh;
815 regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4);
816 regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4);
817 regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4);
818 regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4);
819 } else {
820 regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ;
821 regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh;
822 regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh;
823 regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh;
824 regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4);
825 regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4);
826 regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4);
827 regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4);
828 }
829
830 }
831
832 weight = ofstop * (regs.besviscal >> 2);
833 weights = weight < 0 ? 1 : 0;
834 regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2);
835 regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF);
836
837 #ifdef CRTC2
838 // pridat hlavni registry - tj. casovani ...
839
840
841 switch(config->fourcc){
842 case IMGFMT_YV12:
843 case IMGFMT_I420:
844 case IMGFMT_IYUV:
845 cregs.c2ctl = 1 // CRTC2 enabled
846 + (1<<1) // external clock
847 + (0<<2) // external clock
848 + (1<<3) // pixel clock enable - not needed ???
849 + (0<<4) // high prioryty req
850 + (1<<5) // high prioryty req
851 + (0<<6) // high prioryty req
852 + (1<<8) // high prioryty req max
853 + (0<<9) // high prioryty req max
854 + (0<<10) // high prioryty req max
855 + (0<<20) // CRTC1 to DAC
856 + (1<<21) // 420 mode
857 + (1<<22) // 420 mode
858 + (1<<23) // 420 mode
859 + (0<<24) // single chroma line for 420 mode - need to be corrected
860 + (0<<25) /*/ interlace mode - need to be corrected*/
861 + (0<<26) // field legth polariry
862 + (0<<27) // field identification polariry
863 + (1<<28) // VIDRST detection mode
864 + (0<<29) // VIDRST detection mode
865 + (1<<30) // Horizontal counter preload
866 + (1<<31) // Vertical counter preload
867 ;
868 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
869 + (1<<1) // Y filter enable
870 + (1<<2) // CbCr filter enable
871 + (0<<3) // subpicture enable (disabled)
872 + (0<<4) // NTSC enable (disabled - PAL)
873 + (0<<5) // C2 static subpicture enable (disabled)
874 + (0<<6) // C2 subpicture offset division (disabled)
875 + (0<<7) // 422 subformat selection !
876 /* + (0<<8) // 15 bpp high alpha
877 + (0<<9) // 15 bpp high alpha
878 + (0<<10) // 15 bpp high alpha
879 + (0<<11) // 15 bpp high alpha
880 + (0<<12) // 15 bpp high alpha
881 + (0<<13) // 15 bpp high alpha
882 + (0<<14) // 15 bpp high alpha
883 + (0<<15) // 15 bpp high alpha
884 + (0<<16) // 15 bpp low alpha
885 + (0<<17) // 15 bpp low alpha
886 + (0<<18) // 15 bpp low alpha
887 + (0<<19) // 15 bpp low alpha
888 + (0<<20) // 15 bpp low alpha
889 + (0<<21) // 15 bpp low alpha
890 + (0<<22) // 15 bpp low alpha
891 + (0<<23) // 15 bpp low alpha
892 + (0<<24) // static subpicture key
893 + (0<<25) // static subpicture key
894 + (0<<26) // static subpicture key
895 + (0<<27) // static subpicture key
896 + (0<<28) // static subpicture key
897 */ ;
898 break;
899
900 case IMGFMT_YUY2:
901 cregs.c2ctl = 1 // CRTC2 enabled
902 + (1<<1) // external clock
903 + (0<<2) // external clock
904 + (1<<3) // pixel clock enable - not needed ???
905 + (0<<4) // high prioryty req - acc to spec
906 + (1<<5) // high prioryty req
907 + (0<<6) // high prioryty req
908 // 7 reserved
909 + (1<<8) // high prioryty req max
910 + (0<<9) // high prioryty req max
911 + (0<<10) // high prioryty req max
912 // 11-19 reserved
913 + (0<<20) // CRTC1 to DAC
914 + (1<<21) // 422 mode
915 + (0<<22) // 422 mode
916 + (1<<23) // 422 mode
917 + (0<<24) // single chroma line for 420 mode - need to be corrected
918 + (0<<25) /*/ interlace mode - need to be corrected*/
919 + (0<<26) // field legth polariry
920 + (0<<27) // field identification polariry
921 + (1<<28) // VIDRST detection mode
922 + (0<<29) // VIDRST detection mode
923 + (1<<30) // Horizontal counter preload
924 + (1<<31) // Vertical counter preload
925 ;
926 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
927 + (1<<1) // Y filter enable
928 + (1<<2) // CbCr filter enable
929 + (0<<3) // subpicture enable (disabled)
930 + (0<<4) // NTSC enable (disabled - PAL)
931 + (0<<5) // C2 static subpicture enable (disabled)
932 + (0<<6) // C2 subpicture offset division (disabled)
933 + (0<<7) // 422 subformat selection !
934 /* + (0<<8) // 15 bpp high alpha
935 + (0<<9) // 15 bpp high alpha
936 + (0<<10) // 15 bpp high alpha
937 + (0<<11) // 15 bpp high alpha
938 + (0<<12) // 15 bpp high alpha
939 + (0<<13) // 15 bpp high alpha
940 + (0<<14) // 15 bpp high alpha
941 + (0<<15) // 15 bpp high alpha
942 + (0<<16) // 15 bpp low alpha
943 + (0<<17) // 15 bpp low alpha
944 + (0<<18) // 15 bpp low alpha
945 + (0<<19) // 15 bpp low alpha
946 + (0<<20) // 15 bpp low alpha
947 + (0<<21) // 15 bpp low alpha
948 + (0<<22) // 15 bpp low alpha
949 + (0<<23) // 15 bpp low alpha
950 + (0<<24) // static subpicture key
951 + (0<<25) // static subpicture key
952 + (0<<26) // static subpicture key
953 + (0<<27) // static subpicture key
954 + (0<<28) // static subpicture key
955 */ ;
956 break;
957
958 case IMGFMT_UYVY:
959 cregs.c2ctl = 1 // CRTC2 enabled
960 + (1<<1) // external clock
961 + (0<<2) // external clock
962 + (1<<3) // pixel clock enable - not needed ???
963 + (0<<4) // high prioryty req
964 + (1<<5) // high prioryty req
965 + (0<<6) // high prioryty req
966 + (1<<8) // high prioryty req max
967 + (0<<9) // high prioryty req max
968 + (0<<10) // high prioryty req max
969 + (0<<20) // CRTC1 to DAC
970 + (1<<21) // 422 mode
971 + (0<<22) // 422 mode
972 + (1<<23) // 422 mode
973 + (1<<24) // single chroma line for 420 mode - need to be corrected
974 + (1<<25) /*/ interlace mode - need to be corrected*/
975 + (0<<26) // field legth polariry
976 + (0<<27) // field identification polariry
977 + (1<<28) // VIDRST detection mode
978 + (0<<29) // VIDRST detection mode
979 + (1<<30) // Horizontal counter preload
980 + (1<<31) // Vertical counter preload
981 ;
982 cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode
983 + (1<<1) // Y filter enable
984 + (1<<2) // CbCr filter enable
985 + (0<<3) // subpicture enable (disabled)
986 + (0<<4) // NTSC enable (disabled - PAL)
987 + (0<<5) // C2 static subpicture enable (disabled)
988 + (0<<6) // C2 subpicture offset division (disabled)
989 + (1<<7) // 422 subformat selection !
990 /* + (0<<8) // 15 bpp high alpha
991 + (0<<9) // 15 bpp high alpha
992 + (0<<10) // 15 bpp high alpha
993 + (0<<11) // 15 bpp high alpha
994 + (0<<12) // 15 bpp high alpha
995 + (0<<13) // 15 bpp high alpha
996 + (0<<14) // 15 bpp high alpha
997 + (0<<15) // 15 bpp high alpha
998 + (0<<16) // 15 bpp low alpha
999 + (0<<17) // 15 bpp low alpha
1000 + (0<<18) // 15 bpp low alpha
1001 + (0<<19) // 15 bpp low alpha
1002 + (0<<20) // 15 bpp low alpha
1003 + (0<<21) // 15 bpp low alpha
1004 + (0<<22) // 15 bpp low alpha
1005 + (0<<23) // 15 bpp low alpha
1006 + (0<<24) // static subpicture key
1007 + (0<<25) // static subpicture key
1008 + (0<<26) // static subpicture key
1009 + (0<<27) // static subpicture key
1010 + (0<<28) // static subpicture key
1011 */ ;
1012 break;
1013 }
1014
1015 cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8);
1016 cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8);
1017
1018 cregs.c2misc=0 // CRTCV2 656 togg f0
1019 +(0<<1) // CRTCV2 656 togg f0
1020 +(0<<2) // CRTCV2 656 togg f0
1021 +(0<<4) // CRTCV2 656 togg f1
1022 +(0<<5) // CRTCV2 656 togg f1
1023 +(0<<6) // CRTCV2 656 togg f1
1024 +(0<<8) // Hsync active high
1025 +(0<<9) // Vsync active high
1026 // 16-27 c2vlinecomp - nevim co tam dat
1027 ;
1028 cregs.c2offset=(regs.bespitch << 1);
1029
1030 cregs.c2pl2startadd0=regs.besa1corg;
1031 cregs.c2pl3startadd0=regs.besa1c3org;
1032
1033 cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from
1034
1035 cregs.c2spicstartadd0=0; // not used
1036
1037 cregs.c2startadd0=regs.besa1org;
1038
1039 cregs.c2subpiclut=0; //not used
1040
1041 cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1);
1042 cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1);
1043 #endif /* CRTC2 */
1044
1045 mga_vid_write_regs(0);
1046 return 0;
1047 }
1048
mga_playback_on(void)1049 static int mga_playback_on(void)
1050 {
1051 if (mga_verbose) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] playback on\n");
1052
1053 vid_src_ready = 1;
1054 if(vid_overlay_on)
1055 {
1056 regs.besctl |= 1;
1057 mga_vid_write_regs(0);
1058 }
1059 #if MGA_ALLOW_IRQ
1060 if (mga_irq != -1)
1061 enable_irq();
1062 #endif
1063 mga_next_frame=0;
1064
1065 return 0;
1066 }
1067
mga_playback_off(void)1068 static int mga_playback_off(void)
1069 {
1070 if (mga_verbose) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] playback off\n");
1071
1072 vid_src_ready = 0;
1073 #if MGA_ALLOW_IRQ
1074 if (mga_irq != -1)
1075 disable_irq();
1076 #endif
1077 regs.besctl &= ~1;
1078 regs.besglobctl &= ~(1<<6); /* UYVY format selected */
1079 mga_vid_write_regs(0);
1080
1081 return 0;
1082 }
1083
mga_probe(int verbose,int force)1084 static int mga_probe(int verbose,int force)
1085 {
1086 pciinfo_t lst[MAX_PCI_DEVICES];
1087 unsigned int i, num_pci;
1088 int err;
1089
1090 if (verbose) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] probe\n");
1091
1092 mga_verbose = verbose;
1093
1094 is_g400 = -1;
1095
1096 err = pci_scan(lst, &num_pci);
1097 if (err)
1098 {
1099 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Error occurred during pci scan: %s\n", strerror(err));
1100 return err;
1101 }
1102
1103 if (mga_verbose)
1104 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] found %d pci devices\n", num_pci);
1105
1106 for (i = 0; i < num_pci; i++)
1107 {
1108 if (mga_verbose > 1)
1109 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] pci[%d] vendor: %d device: %d\n",
1110 i, lst[i].vendor, lst[i].device);
1111 if (lst[i].vendor == VENDOR_MATROX)
1112 {
1113 if ((lst[i].command & PCI_COMMAND_IO) == 0)
1114 {
1115 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Device seems disabled, trying anyway\n");
1116 }
1117 switch(lst[i].device)
1118 {
1119 case DEVICE_MATROX_MGA_G550_AGP:
1120 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Found MGA G550\n");
1121 is_g400 = 1;
1122 goto card_found;
1123 case DEVICE_MATROX_MGA_G400_G450:
1124 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Found MGA G400/G450\n");
1125 is_g400 = 1;
1126 goto card_found;
1127 case DEVICE_MATROX_MGA_G200_AGP:
1128 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Found MGA G200 AGP\n");
1129 is_g400 = 0;
1130 goto card_found;
1131 case DEVICE_MATROX_MGA_G200:
1132 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Found MGA G200 PCI\n");
1133 is_g400 = 0;
1134 goto card_found;
1135 }
1136 }
1137 }
1138
1139 if (is_g400 == -1)
1140 {
1141 if (verbose) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Can't find chip\n");
1142 return ENXIO;
1143 }
1144
1145 card_found:
1146 probed = 1;
1147 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
1148
1149 return 0;
1150 }
1151
mga_init(void)1152 static int mga_init(void)
1153 {
1154 unsigned int card_option = 0;
1155 int err;
1156
1157 if (mga_verbose) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] init\n");
1158
1159 mga_vid_in_use = 0;
1160
1161 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n");
1162 #ifdef CRTC2
1163 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Driver compiled with TV-out (second-head) support\n");
1164 #endif
1165
1166 if (!probed)
1167 {
1168 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] driver was not probed but is being initializing\n");
1169 return EINTR;
1170 }
1171
1172 #ifdef MGA_PCICONFIG_MEMDETECT
1173 pci_config_read(pci_info.bus, pci_info.card, pci_info.func,
1174 0x40, 4, &card_option);
1175 if (mga_verbose > 1) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] OPTION word: 0x%08X mem: 0x%02X %s\n", card_option,
1176 (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM");
1177 #endif
1178
1179 if (mga_ram_size)
1180 {
1181 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] RAMSIZE forced to %d MB\n", mga_ram_size);
1182 }
1183 else
1184 {
1185 #ifdef MGA_MEMORY_SIZE
1186 mga_ram_size = MGA_MEMORY_SIZE;
1187 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
1188 #else
1189 if (is_g400)
1190 {
1191 switch((card_option>>10)&0x17)
1192 {
1193 // SDRAM:
1194 case 0x00:
1195 case 0x04: mga_ram_size = 16; break;
1196 case 0x03: mga_ram_size = 32; break;
1197 // SGRAM:
1198 case 0x10:
1199 case 0x14: mga_ram_size = 32; break;
1200 case 0x11:
1201 case 0x12: mga_ram_size = 16; break;
1202 default:
1203 mga_ram_size = 16;
1204 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Couldn't detect RAMSIZE, assuming 16MB!\n");
1205 }
1206 }
1207 else
1208 {
1209 switch((card_option>>10)&0x17)
1210 {
1211 default: mga_ram_size = 8;
1212 }
1213 }
1214
1215 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
1216 #endif
1217 }
1218
1219 if (mga_ram_size)
1220 {
1221 if ((mga_ram_size < 4) || (mga_ram_size > 64))
1222 {
1223 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] invalid RAMSIZE: %d MB\n", mga_ram_size);
1224 return EINVAL;
1225 }
1226 }
1227
1228 if (mga_verbose > 1) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] hardware addresses: mmio: %#x, framebuffer: %#x\n",
1229 pci_info.base1, pci_info.base0);
1230
1231 mga_mmio_base = map_phys_mem(pci_info.base1,0x4000);
1232 mga_mem_base = map_phys_mem(pci_info.base0,mga_ram_size*1024*1024);
1233
1234 if (mga_verbose > 1) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] MMIO at %p, IRQ: %d, framebuffer: %p\n",
1235 mga_mmio_base, mga_irq, mga_mem_base);
1236 err = mtrr_set_type(pci_info.base0,mga_ram_size*1024*1024,MTRR_TYPE_WRCOMB);
1237 if(!err) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] Set write-combining type of video memory\n");
1238 #if MGA_ALLOW_IRQ
1239 if (mga_irq != -1)
1240 {
1241 int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq);
1242 if (tmp)
1243 {
1244 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp);
1245 mga_irq=-1;
1246 }
1247 else
1248 {
1249 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] syncfb (mga): registered irq %d\n", mga_irq);
1250 }
1251 }
1252 else
1253 {
1254 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] syncfb (mga): No valid irq was found\n");
1255 mga_irq=-1;
1256 }
1257 #else
1258 mp_msg(MSGT_VO, MSGL_STATUS, "[mga] syncfb (mga): IRQ disabled in mga_vid.c\n");
1259 mga_irq=-1;
1260 #endif
1261
1262 return 0;
1263 }
1264
mga_destroy(void)1265 static void mga_destroy(void)
1266 {
1267 if (mga_verbose) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] destroy\n");
1268
1269 /* FIXME turn off BES */
1270 vid_src_ready = 0;
1271 regs.besctl &= ~1;
1272 regs.besglobctl &= ~(1<<6); // UYVY format selected
1273 mga_vid_write_regs(1);
1274 mga_vid_in_use = 0;
1275
1276 #if MGA_ALLOW_IRQ
1277 if (mga_irq != -1)
1278 free_irq(mga_irq, &mga_irq);
1279 #endif
1280
1281 if (mga_mmio_base)
1282 unmap_phys_mem(mga_mmio_base, 0x4000);
1283 if (mga_mem_base)
1284 unmap_phys_mem(mga_mem_base, mga_ram_size);
1285 return;
1286 }
1287
mga_query_fourcc(vidix_fourcc_t * to)1288 static int mga_query_fourcc(vidix_fourcc_t *to)
1289 {
1290 if (mga_verbose) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] query fourcc (%x)\n", to->fourcc);
1291
1292 switch(to->fourcc)
1293 {
1294 case IMGFMT_YV12:
1295 case IMGFMT_IYUV:
1296 case IMGFMT_I420:
1297 case IMGFMT_YUY2:
1298 case IMGFMT_UYVY:
1299 break;
1300 default:
1301 return ENOTSUP;
1302 }
1303
1304 to->depth = VID_DEPTH_12BPP |
1305 VID_DEPTH_15BPP | VID_DEPTH_16BPP |
1306 VID_DEPTH_24BPP | VID_DEPTH_32BPP;
1307 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
1308 return 0;
1309 }
1310
mga_get_caps(vidix_capability_t * to)1311 static int mga_get_caps(vidix_capability_t *to)
1312 {
1313 memcpy(to, &mga_cap, sizeof(vidix_capability_t));
1314 to->device_id = pci_info.device; /* set device id in capabilities */
1315 return 0;
1316 }
1317
mga_get_gkeys(vidix_grkey_t * grkey)1318 static int mga_get_gkeys(vidix_grkey_t *grkey)
1319 {
1320 memcpy(grkey, &mga_grkey, sizeof(vidix_grkey_t));
1321 return 0;
1322 }
1323
mga_set_gkeys(const vidix_grkey_t * grkey)1324 static int mga_set_gkeys(const vidix_grkey_t *grkey)
1325 {
1326 memcpy(&mga_grkey, grkey, sizeof(vidix_grkey_t));
1327 mga_vid_write_regs(0);
1328 return 0;
1329 }
1330
mga_set_eq(const vidix_video_eq_t * eq)1331 static int mga_set_eq( const vidix_video_eq_t * eq)
1332 {
1333 /* contrast and brightness control isn't supported on G200 - alex */
1334 if (!is_g400)
1335 {
1336 if (mga_verbose) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] equalizer isn't supported with G200\n");
1337 return ENOTSUP;
1338 }
1339
1340 // only brightness&contrast are supported:
1341 if(!(eq->cap & (VEQ_CAP_BRIGHTNESS|VEQ_CAP_CONTRAST)))
1342 return ENOTSUP;
1343
1344 //regs.beslumactl = readl(mga_mmio_base + BESLUMACTL);
1345 if (eq->cap & VEQ_CAP_BRIGHTNESS) {
1346 regs.beslumactl &= 0xFFFF;
1347 regs.beslumactl |= (eq->brightness*255/2000)<<16;
1348 }
1349 if (eq->cap & VEQ_CAP_CONTRAST) {
1350 regs.beslumactl &= 0xFFFF0000;
1351 regs.beslumactl |= (128+eq->contrast*255/2000)&0xFFFF;
1352 }
1353 writel(regs.beslumactl,mga_mmio_base + BESLUMACTL);
1354
1355 return 0;
1356 }
1357
mga_get_eq(vidix_video_eq_t * eq)1358 static int mga_get_eq( vidix_video_eq_t * eq)
1359 {
1360 /* contrast and brightness control isn't supported on G200 - alex */
1361 if (!is_g400)
1362 {
1363 if (mga_verbose) mp_msg(MSGT_VO, MSGL_STATUS, "[mga] equalizer isn't supported with G200\n");
1364 return ENOTSUP;
1365 }
1366
1367 eq->brightness = (signed short int)(regs.beslumactl >> 16) * 1000 / 128;
1368 eq->contrast = (signed short int)(regs.beslumactl & 0xFFFF) * 1000 / 128 - 1000;
1369 eq->cap = VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST;
1370
1371 mp_msg(MSGT_VO, MSGL_STATUS, "MGA GET_EQ: br=%d c=%d \n",eq->brightness,eq->contrast);
1372
1373 return 0;
1374 }
1375
1376 #ifndef CRTC2
1377 const VDXDriver mga_drv = {
1378 "mga",
1379 #else
1380 const VDXDriver mga_crtc2_drv = {
1381 "mga_crtc2",
1382 #endif
1383 NULL,
1384
1385 .probe = mga_probe,
1386 .get_caps = mga_get_caps,
1387 .query_fourcc = mga_query_fourcc,
1388 .init = mga_init,
1389 .destroy = mga_destroy,
1390 .config_playback = mga_config_playback,
1391 .playback_on = mga_playback_on,
1392 .playback_off = mga_playback_off,
1393 .frame_sel = mga_frame_select,
1394 .get_eq = mga_get_eq,
1395 .set_eq = mga_set_eq,
1396 .get_gkey = mga_get_gkeys,
1397 .set_gkey = mga_set_gkeys,
1398 };
1399