1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * This program is used to generate definitions needed by
4 * assembly language modules.
5 *
6 * We use the technique used in the OSF Mach kernel code:
7 * generate asm statements containing #defines,
8 * compile this file to assembler, and then extract the
9 * #defines from the assembly-language output.
10 */
11
12 #define GENERATING_ASM_OFFSETS /* asm/smp.h */
13
14 #include <linux/compat.h>
15 #include <linux/signal.h>
16 #include <linux/sched.h>
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/string.h>
20 #include <linux/types.h>
21 #include <linux/mman.h>
22 #include <linux/mm.h>
23 #include <linux/suspend.h>
24 #include <linux/hrtimer.h>
25 #ifdef CONFIG_PPC64
26 #include <linux/time.h>
27 #include <linux/hardirq.h>
28 #endif
29 #include <linux/kbuild.h>
30
31 #include <asm/io.h>
32 #include <asm/page.h>
33 #include <asm/processor.h>
34 #include <asm/cputable.h>
35 #include <asm/thread_info.h>
36 #include <asm/rtas.h>
37 #include <asm/vdso_datapage.h>
38 #include <asm/dbell.h>
39 #ifdef CONFIG_PPC64
40 #include <asm/paca.h>
41 #include <asm/lppaca.h>
42 #include <asm/cache.h>
43 #include <asm/mmu.h>
44 #include <asm/hvcall.h>
45 #include <asm/xics.h>
46 #endif
47 #ifdef CONFIG_PPC_POWERNV
48 #include <asm/opal.h>
49 #endif
50 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
51 #include <linux/kvm_host.h>
52 #endif
53 #if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
54 #include <asm/kvm_book3s.h>
55 #include <asm/kvm_ppc.h>
56 #endif
57
58 #ifdef CONFIG_PPC32
59 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
60 #include "head_booke.h"
61 #endif
62 #endif
63
64 #if defined(CONFIG_PPC_FSL_BOOK3E)
65 #include "../mm/mmu_decl.h"
66 #endif
67
68 #ifdef CONFIG_PPC_8xx
69 #include <asm/fixmap.h>
70 #endif
71
72 #ifdef CONFIG_XMON
73 #include "../xmon/xmon_bpts.h"
74 #endif
75
76 #define STACK_PT_REGS_OFFSET(sym, val) \
77 DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val))
78
main(void)79 int main(void)
80 {
81 OFFSET(THREAD, task_struct, thread);
82 OFFSET(MM, task_struct, mm);
83 #ifdef CONFIG_STACKPROTECTOR
84 OFFSET(TASK_CANARY, task_struct, stack_canary);
85 #ifdef CONFIG_PPC64
86 OFFSET(PACA_CANARY, paca_struct, canary);
87 #endif
88 #endif
89 OFFSET(MMCONTEXTID, mm_struct, context.id);
90 #ifdef CONFIG_PPC64
91 DEFINE(SIGSEGV, SIGSEGV);
92 DEFINE(NMI_MASK, NMI_MASK);
93 #else
94 #ifdef CONFIG_PPC_RTAS
95 OFFSET(RTAS_SP, thread_struct, rtas_sp);
96 #endif
97 #endif /* CONFIG_PPC64 */
98 OFFSET(TASK_STACK, task_struct, stack);
99 #ifdef CONFIG_SMP
100 OFFSET(TASK_CPU, task_struct, cpu);
101 #endif
102
103 #ifdef CONFIG_LIVEPATCH
104 OFFSET(TI_livepatch_sp, thread_info, livepatch_sp);
105 #endif
106
107 OFFSET(KSP, thread_struct, ksp);
108 OFFSET(PT_REGS, thread_struct, regs);
109 #ifdef CONFIG_BOOKE
110 OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]);
111 #endif
112 #ifdef CONFIG_PPC_FPU
113 OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode);
114 OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr);
115 OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area);
116 #endif
117 OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr);
118 OFFSET(THREAD_LOAD_FP, thread_struct, load_fp);
119 #ifdef CONFIG_ALTIVEC
120 OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr);
121 OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area);
122 OFFSET(THREAD_VRSAVE, thread_struct, vrsave);
123 OFFSET(THREAD_USED_VR, thread_struct, used_vr);
124 OFFSET(VRSTATE_VSCR, thread_vr_state, vscr);
125 OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec);
126 #endif /* CONFIG_ALTIVEC */
127 #ifdef CONFIG_VSX
128 OFFSET(THREAD_USED_VSR, thread_struct, used_vsr);
129 #endif /* CONFIG_VSX */
130 #ifdef CONFIG_PPC64
131 OFFSET(KSP_VSID, thread_struct, ksp_vsid);
132 #else /* CONFIG_PPC64 */
133 OFFSET(PGDIR, thread_struct, pgdir);
134 OFFSET(SRR0, thread_struct, srr0);
135 OFFSET(SRR1, thread_struct, srr1);
136 OFFSET(DAR, thread_struct, dar);
137 OFFSET(DSISR, thread_struct, dsisr);
138 #ifdef CONFIG_PPC_BOOK3S_32
139 OFFSET(THR0, thread_struct, r0);
140 OFFSET(THR3, thread_struct, r3);
141 OFFSET(THR4, thread_struct, r4);
142 OFFSET(THR5, thread_struct, r5);
143 OFFSET(THR6, thread_struct, r6);
144 OFFSET(THR8, thread_struct, r8);
145 OFFSET(THR9, thread_struct, r9);
146 OFFSET(THR11, thread_struct, r11);
147 OFFSET(THLR, thread_struct, lr);
148 OFFSET(THCTR, thread_struct, ctr);
149 #endif
150 #ifdef CONFIG_SPE
151 OFFSET(THREAD_EVR0, thread_struct, evr[0]);
152 OFFSET(THREAD_ACC, thread_struct, acc);
153 OFFSET(THREAD_SPEFSCR, thread_struct, spefscr);
154 OFFSET(THREAD_USED_SPE, thread_struct, used_spe);
155 #endif /* CONFIG_SPE */
156 #endif /* CONFIG_PPC64 */
157 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
158 OFFSET(THREAD_DBCR0, thread_struct, debug.dbcr0);
159 #endif
160 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
161 OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu);
162 #endif
163 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
164 OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu);
165 #endif
166 #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
167 OFFSET(KUAP, thread_struct, kuap);
168 #endif
169
170 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
171 OFFSET(PACATMSCRATCH, paca_struct, tm_scratch);
172 OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar);
173 OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr);
174 OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar);
175 OFFSET(THREAD_TM_TAR, thread_struct, tm_tar);
176 OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr);
177 OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr);
178 OFFSET(THREAD_TM_AMR, thread_struct, tm_amr);
179 OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs);
180 OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr);
181 OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave);
182 OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr);
183 /* Local pt_regs on stack for Transactional Memory funcs. */
184 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
185 sizeof(struct pt_regs) + 16);
186 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
187
188 OFFSET(TI_FLAGS, thread_info, flags);
189 OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags);
190 OFFSET(TI_PREEMPT, thread_info, preempt_count);
191
192 #ifdef CONFIG_PPC64
193 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size);
194 OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size);
195 OFFSET(DCACHEL1BLOCKSPERPAGE, ppc64_caches, l1d.blocks_per_page);
196 OFFSET(ICACHEL1BLOCKSIZE, ppc64_caches, l1i.block_size);
197 OFFSET(ICACHEL1LOGBLOCKSIZE, ppc64_caches, l1i.log_block_size);
198 OFFSET(ICACHEL1BLOCKSPERPAGE, ppc64_caches, l1i.blocks_per_page);
199 /* paca */
200 DEFINE(PACA_SIZE, sizeof(struct paca_struct));
201 OFFSET(PACAPACAINDEX, paca_struct, paca_index);
202 OFFSET(PACAPROCSTART, paca_struct, cpu_start);
203 OFFSET(PACAKSAVE, paca_struct, kstack);
204 OFFSET(PACACURRENT, paca_struct, __current);
205 DEFINE(PACA_THREAD_INFO, offsetof(struct paca_struct, __current) +
206 offsetof(struct task_struct, thread_info));
207 OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
208 OFFSET(PACAR1, paca_struct, saved_r1);
209 OFFSET(PACATOC, paca_struct, kernel_toc);
210 OFFSET(PACAKBASE, paca_struct, kernelbase);
211 OFFSET(PACAKMSR, paca_struct, kernel_msr);
212 OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask);
213 OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened);
214 OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled);
215 #ifdef CONFIG_PPC_BOOK3S
216 OFFSET(PACACONTEXTID, paca_struct, mm_ctx_id);
217 #ifdef CONFIG_PPC_MM_SLICES
218 OFFSET(PACALOWSLICESPSIZE, paca_struct, mm_ctx_low_slices_psize);
219 OFFSET(PACAHIGHSLICEPSIZE, paca_struct, mm_ctx_high_slices_psize);
220 OFFSET(PACA_SLB_ADDR_LIMIT, paca_struct, mm_ctx_slb_addr_limit);
221 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
222 #endif /* CONFIG_PPC_MM_SLICES */
223 #endif
224
225 #ifdef CONFIG_PPC_BOOK3E
226 OFFSET(PACAPGD, paca_struct, pgd);
227 OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd);
228 OFFSET(PACA_EXGEN, paca_struct, exgen);
229 OFFSET(PACA_EXTLB, paca_struct, extlb);
230 OFFSET(PACA_EXMC, paca_struct, exmc);
231 OFFSET(PACA_EXCRIT, paca_struct, excrit);
232 OFFSET(PACA_EXDBG, paca_struct, exdbg);
233 OFFSET(PACA_MC_STACK, paca_struct, mc_kstack);
234 OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack);
235 OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack);
236 OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr);
237
238 OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next);
239 OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max);
240 OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first);
241 #endif /* CONFIG_PPC_BOOK3E */
242
243 #ifdef CONFIG_PPC_BOOK3S_64
244 OFFSET(PACASLBCACHE, paca_struct, slb_cache);
245 OFFSET(PACASLBCACHEPTR, paca_struct, slb_cache_ptr);
246 OFFSET(PACASTABRR, paca_struct, stab_rr);
247 OFFSET(PACAVMALLOCSLLP, paca_struct, vmalloc_sllp);
248 #ifdef CONFIG_PPC_MM_SLICES
249 OFFSET(MMUPSIZESLLP, mmu_psize_def, sllp);
250 #else
251 OFFSET(PACACONTEXTSLLP, paca_struct, mm_ctx_sllp);
252 #endif /* CONFIG_PPC_MM_SLICES */
253 OFFSET(PACA_EXGEN, paca_struct, exgen);
254 OFFSET(PACA_EXMC, paca_struct, exmc);
255 OFFSET(PACA_EXNMI, paca_struct, exnmi);
256 #ifdef CONFIG_PPC_PSERIES
257 OFFSET(PACALPPACAPTR, paca_struct, lppaca_ptr);
258 #endif
259 OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr);
260 OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid);
261 OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid);
262 OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area);
263 OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use);
264 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
265 OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use);
266 #endif
267 OFFSET(LPPACA_DTLIDX, lppaca, dtl_idx);
268 OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count);
269 OFFSET(PACA_DTL_RIDX, paca_struct, dtl_ridx);
270 #endif /* CONFIG_PPC_BOOK3S_64 */
271 OFFSET(PACAEMERGSP, paca_struct, emergency_sp);
272 #ifdef CONFIG_PPC_BOOK3S_64
273 OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp);
274 OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp);
275 OFFSET(PACA_IN_MCE, paca_struct, in_mce);
276 OFFSET(PACA_IN_NMI, paca_struct, in_nmi);
277 OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area);
278 OFFSET(PACA_EXRFI, paca_struct, exrfi);
279 OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size);
280
281 #endif
282 OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
283 OFFSET(PACAKEXECSTATE, paca_struct, kexec_state);
284 OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default);
285 #ifdef CONFIG_PPC_BOOK3E
286 OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
287 #endif
288 OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
289 #else /* CONFIG_PPC64 */
290 #endif /* CONFIG_PPC64 */
291
292 /* RTAS */
293 OFFSET(RTASBASE, rtas_t, base);
294 OFFSET(RTASENTRY, rtas_t, entry);
295
296 /* Interrupt register frame */
297 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
298 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_WITH_PT_REGS);
299 STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
300 STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
301 STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
302 STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
303 STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
304 STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
305 STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
306 STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
307 STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
308 STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
309 STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
310 STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
311 STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
312 STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
313 /*
314 * Note: these symbols include _ because they overlap with special
315 * register names
316 */
317 STACK_PT_REGS_OFFSET(_NIP, nip);
318 STACK_PT_REGS_OFFSET(_MSR, msr);
319 STACK_PT_REGS_OFFSET(_CTR, ctr);
320 STACK_PT_REGS_OFFSET(_LINK, link);
321 STACK_PT_REGS_OFFSET(_CCR, ccr);
322 STACK_PT_REGS_OFFSET(_XER, xer);
323 STACK_PT_REGS_OFFSET(_DAR, dar);
324 STACK_PT_REGS_OFFSET(_DSISR, dsisr);
325 STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3);
326 STACK_PT_REGS_OFFSET(RESULT, result);
327 STACK_PT_REGS_OFFSET(_TRAP, trap);
328 #ifndef CONFIG_PPC64
329 /*
330 * The PowerPC 400-class & Book-E processors have neither the DAR
331 * nor the DSISR SPRs. Hence, we overload them to hold the similar
332 * DEAR and ESR SPRs for such processors. For critical interrupts
333 * we use them to hold SRR0 and SRR1.
334 */
335 STACK_PT_REGS_OFFSET(_DEAR, dar);
336 STACK_PT_REGS_OFFSET(_ESR, dsisr);
337 #else /* CONFIG_PPC64 */
338 STACK_PT_REGS_OFFSET(SOFTE, softe);
339 STACK_PT_REGS_OFFSET(_PPR, ppr);
340 #endif /* CONFIG_PPC64 */
341
342 #ifdef CONFIG_PPC_PKEY
343 STACK_PT_REGS_OFFSET(STACK_REGS_AMR, amr);
344 STACK_PT_REGS_OFFSET(STACK_REGS_IAMR, iamr);
345 #endif
346 #ifdef CONFIG_PPC_KUAP
347 STACK_PT_REGS_OFFSET(STACK_REGS_KUAP, kuap);
348 #endif
349
350
351 #if defined(CONFIG_PPC32)
352 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
353 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
354 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
355 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
356 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
357 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
358 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
359 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
360 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
361 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
362 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
363 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
364 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
365 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
366 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
367 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
368 #endif
369 #endif
370
371 #ifndef CONFIG_PPC64
372 OFFSET(MM_PGD, mm_struct, pgd);
373 #endif /* ! CONFIG_PPC64 */
374
375 /* About the CPU features table */
376 OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
377 OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
378 OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
379
380 OFFSET(pbe_address, pbe, address);
381 OFFSET(pbe_orig_address, pbe, orig_address);
382 OFFSET(pbe_next, pbe, next);
383
384 #ifndef CONFIG_PPC64
385 DEFINE(TASK_SIZE, TASK_SIZE);
386 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
387 #endif /* ! CONFIG_PPC64 */
388
389 /* datapage offsets for use by vdso */
390 OFFSET(VDSO_DATA_OFFSET, vdso_arch_data, data);
391 OFFSET(CFG_TB_TICKS_PER_SEC, vdso_arch_data, tb_ticks_per_sec);
392 #ifdef CONFIG_PPC64
393 OFFSET(CFG_ICACHE_BLOCKSZ, vdso_arch_data, icache_block_size);
394 OFFSET(CFG_DCACHE_BLOCKSZ, vdso_arch_data, dcache_block_size);
395 OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_arch_data, icache_log_block_size);
396 OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_arch_data, dcache_log_block_size);
397 OFFSET(CFG_SYSCALL_MAP64, vdso_arch_data, syscall_map);
398 OFFSET(CFG_SYSCALL_MAP32, vdso_arch_data, compat_syscall_map);
399 #else
400 OFFSET(CFG_SYSCALL_MAP32, vdso_arch_data, syscall_map);
401 #endif
402
403 #ifdef CONFIG_BUG
404 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
405 #endif
406
407 #ifdef CONFIG_PPC_BOOK3S_64
408 DEFINE(PGD_TABLE_SIZE, (sizeof(pgd_t) << max(RADIX_PGD_INDEX_SIZE, H_PGD_INDEX_SIZE)));
409 #else
410 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
411 #endif
412 DEFINE(PTE_SIZE, sizeof(pte_t));
413
414 #ifdef CONFIG_KVM
415 OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
416 OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
417 OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
418 OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr);
419 OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
420 OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
421 #ifdef CONFIG_ALTIVEC
422 OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
423 #endif
424 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
425 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
426 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
427 #ifdef CONFIG_PPC_BOOK3S
428 OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
429 #endif
430 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
431 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
432 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
433 OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
434 OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
435 OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1);
436 OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0);
437 OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1);
438 OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2);
439 OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3);
440 #endif
441 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
442 OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry);
443 OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr);
444 OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit);
445 OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time);
446 OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time);
447 OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity);
448 OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start);
449 OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount);
450 OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total);
451 OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min);
452 OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max);
453 #endif
454 OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3);
455 OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4);
456 OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5);
457 OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6);
458 OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7);
459 OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid);
460 OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1);
461 OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared);
462 OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr);
463 OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr);
464 #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
465 OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian);
466 #endif
467
468 OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0);
469 OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1);
470 OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2);
471 OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3);
472 OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4);
473 OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6);
474
475 OFFSET(VCPU_KVM, kvm_vcpu, kvm);
476 OFFSET(KVM_LPID, kvm, arch.lpid);
477
478 /* book3s */
479 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
480 OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets);
481 OFFSET(KVM_SDR1, kvm, arch.sdr1);
482 OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid);
483 OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr);
484 OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1);
485 OFFSET(KVM_NEED_FLUSH, kvm, arch.need_tlb_flush.bits);
486 OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls);
487 OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v);
488 OFFSET(KVM_RADIX, kvm, arch.radix);
489 OFFSET(KVM_FWNMI, kvm, arch.fwnmi_enabled);
490 OFFSET(KVM_SECURE_GUEST, kvm, arch.secure_guest);
491 OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr);
492 OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar);
493 OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr);
494 OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty);
495 OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst);
496 OFFSET(VCPU_NESTED, kvm_vcpu, arch.nested);
497 OFFSET(VCPU_CPU, kvm_vcpu, cpu);
498 OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu);
499 #endif
500 #ifdef CONFIG_PPC_BOOK3S
501 OFFSET(VCPU_PURR, kvm_vcpu, arch.purr);
502 OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr);
503 OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
504 OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr);
505 OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
506 OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor);
507 OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr);
508 OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl);
509 OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr);
510 OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
511 OFFSET(VCPU_DAWR0, kvm_vcpu, arch.dawr0);
512 OFFSET(VCPU_DAWRX0, kvm_vcpu, arch.dawrx0);
513 OFFSET(VCPU_DAWR1, kvm_vcpu, arch.dawr1);
514 OFFSET(VCPU_DAWRX1, kvm_vcpu, arch.dawrx1);
515 OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
516 OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
517 OFFSET(VCPU_DEC, kvm_vcpu, arch.dec);
518 OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires);
519 OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions);
520 OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded);
521 OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded);
522 OFFSET(VCPU_IRQ_PENDING, kvm_vcpu, arch.irq_pending);
523 OFFSET(VCPU_DBELL_REQ, kvm_vcpu, arch.doorbell_request);
524 OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr);
525 OFFSET(VCPU_MMCRA, kvm_vcpu, arch.mmcra);
526 OFFSET(VCPU_MMCRS, kvm_vcpu, arch.mmcrs);
527 OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
528 OFFSET(VCPU_SPMC, kvm_vcpu, arch.spmc);
529 OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar);
530 OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar);
531 OFFSET(VCPU_SIER, kvm_vcpu, arch.sier);
532 OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
533 OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max);
534 OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr);
535 OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr);
536 OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar);
537 OFFSET(VCPU_FAULT_GPA, kvm_vcpu, arch.fault_gpa);
538 OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr);
539 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
540 OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap);
541 OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar);
542 OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
543 OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr);
544 OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb);
545 OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr);
546 OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr);
547 OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr);
548 OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr);
549 OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr);
550 OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr);
551 OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop);
552 OFFSET(VCPU_WORT, kvm_vcpu, arch.wort);
553 OFFSET(VCPU_TID, kvm_vcpu, arch.tid);
554 OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr);
555 OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr);
556 OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map);
557 OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest);
558 OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads);
559 OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
560 OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset);
561 OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied);
562 OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr);
563 OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
564 OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes);
565 OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
566 OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
567 OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
568 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
569 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
570 OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar);
571 OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar);
572 OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr);
573 OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr);
574 OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm);
575 OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr);
576 OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr);
577 OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm);
578 OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm);
579 OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm);
580 OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm);
581 OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm);
582 OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm);
583 OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm);
584 OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm);
585 OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm);
586 #endif
587
588 #ifdef CONFIG_PPC_BOOK3S_64
589 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
590 OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu);
591 # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
592 #else
593 # define SVCPU_FIELD(x, f)
594 #endif
595 # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
596 #else /* 32-bit */
597 # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
598 # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
599 #endif
600
601 SVCPU_FIELD(SVCPU_CR, cr);
602 SVCPU_FIELD(SVCPU_XER, xer);
603 SVCPU_FIELD(SVCPU_CTR, ctr);
604 SVCPU_FIELD(SVCPU_LR, lr);
605 SVCPU_FIELD(SVCPU_PC, pc);
606 SVCPU_FIELD(SVCPU_R0, gpr[0]);
607 SVCPU_FIELD(SVCPU_R1, gpr[1]);
608 SVCPU_FIELD(SVCPU_R2, gpr[2]);
609 SVCPU_FIELD(SVCPU_R3, gpr[3]);
610 SVCPU_FIELD(SVCPU_R4, gpr[4]);
611 SVCPU_FIELD(SVCPU_R5, gpr[5]);
612 SVCPU_FIELD(SVCPU_R6, gpr[6]);
613 SVCPU_FIELD(SVCPU_R7, gpr[7]);
614 SVCPU_FIELD(SVCPU_R8, gpr[8]);
615 SVCPU_FIELD(SVCPU_R9, gpr[9]);
616 SVCPU_FIELD(SVCPU_R10, gpr[10]);
617 SVCPU_FIELD(SVCPU_R11, gpr[11]);
618 SVCPU_FIELD(SVCPU_R12, gpr[12]);
619 SVCPU_FIELD(SVCPU_R13, gpr[13]);
620 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
621 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
622 SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
623 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
624 #ifdef CONFIG_PPC_BOOK3S_32
625 SVCPU_FIELD(SVCPU_SR, sr);
626 #endif
627 #ifdef CONFIG_PPC64
628 SVCPU_FIELD(SVCPU_SLB, slb);
629 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
630 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
631 #endif
632
633 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
634 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
635 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
636 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
637 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
638 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
639 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
640 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
641 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
642 HSTATE_FIELD(HSTATE_NAPPING, napping);
643
644 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
645 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
646 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
647 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
648 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
649 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
650 HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys);
651 HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt);
652 HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
653 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
654 HSTATE_FIELD(HSTATE_PTID, ptid);
655 HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend);
656 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
657 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
658 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
659 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
660 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
661 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
662 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
663 HSTATE_FIELD(HSTATE_MMCR3, host_mmcr[7]);
664 HSTATE_FIELD(HSTATE_SIER2, host_mmcr[8]);
665 HSTATE_FIELD(HSTATE_SIER3, host_mmcr[9]);
666 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
667 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
668 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
669 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
670 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
671 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
672 HSTATE_FIELD(HSTATE_PURR, host_purr);
673 HSTATE_FIELD(HSTATE_SPURR, host_spurr);
674 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
675 HSTATE_FIELD(HSTATE_DABR, dabr);
676 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
677 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
678 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
679 OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr);
680 OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar);
681 OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar);
682 OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap);
683 OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped);
684 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
685
686 #ifdef CONFIG_PPC_BOOK3S_64
687 HSTATE_FIELD(HSTATE_CFAR, cfar);
688 HSTATE_FIELD(HSTATE_PPR, ppr);
689 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
690 #endif /* CONFIG_PPC_BOOK3S_64 */
691
692 #else /* CONFIG_PPC_BOOK3S */
693 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
694 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
695 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
696 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
697 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
698 OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
699 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
700 OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
701 OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr);
702 OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save);
703 #endif /* CONFIG_PPC_BOOK3S */
704 #endif /* CONFIG_KVM */
705
706 #ifdef CONFIG_KVM_GUEST
707 OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1);
708 OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2);
709 OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3);
710 OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending);
711 OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr);
712 OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical);
713 OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr);
714 #endif
715
716 #ifdef CONFIG_44x
717 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
718 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
719 #endif
720 #ifdef CONFIG_PPC_FSL_BOOK3E
721 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
722 OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
723 OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
724 OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
725 OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
726 OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
727 #endif
728
729 #if defined(CONFIG_KVM) && defined(CONFIG_SPE)
730 OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]);
731 OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
732 OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr);
733 OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr);
734 #endif
735
736 #ifdef CONFIG_KVM_BOOKE_HV
737 OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4);
738 OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6);
739 #endif
740
741 #ifdef CONFIG_KVM_XICS
742 DEFINE(VCPU_XIVE_SAVED_STATE, offsetof(struct kvm_vcpu,
743 arch.xive_saved_state));
744 DEFINE(VCPU_XIVE_CAM_WORD, offsetof(struct kvm_vcpu,
745 arch.xive_cam_word));
746 DEFINE(VCPU_XIVE_PUSHED, offsetof(struct kvm_vcpu, arch.xive_pushed));
747 DEFINE(VCPU_XIVE_ESC_ON, offsetof(struct kvm_vcpu, arch.xive_esc_on));
748 DEFINE(VCPU_XIVE_ESC_RADDR, offsetof(struct kvm_vcpu, arch.xive_esc_raddr));
749 DEFINE(VCPU_XIVE_ESC_VADDR, offsetof(struct kvm_vcpu, arch.xive_esc_vaddr));
750 #endif
751
752 #ifdef CONFIG_KVM_EXIT_TIMING
753 OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu);
754 OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl);
755 OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu);
756 OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl);
757 #endif
758
759 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
760 DEFINE(PPC_DBELL_MSGTYPE, PPC_DBELL_MSGTYPE);
761
762 #ifdef CONFIG_PPC_8xx
763 DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE));
764 #endif
765
766 #ifdef CONFIG_XMON
767 DEFINE(BPT_SIZE, BPT_SIZE);
768 #endif
769
770 return 0;
771 }
772