1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
4
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/smp.h>
22 #include <linux/io.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/pgtable.h>
25
26 #include <asm/cmdline.h>
27 #include <asm/stackprotector.h>
28 #include <asm/perf_event.h>
29 #include <asm/mmu_context.h>
30 #include <asm/doublefault.h>
31 #include <asm/archrandom.h>
32 #include <asm/hypervisor.h>
33 #include <asm/processor.h>
34 #include <asm/tlbflush.h>
35 #include <asm/debugreg.h>
36 #include <asm/sections.h>
37 #include <asm/vsyscall.h>
38 #include <linux/topology.h>
39 #include <linux/cpumask.h>
40 #include <linux/atomic.h>
41 #include <asm/proto.h>
42 #include <asm/setup.h>
43 #include <asm/apic.h>
44 #include <asm/desc.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/mtrr.h>
47 #include <asm/hwcap2.h>
48 #include <linux/numa.h>
49 #include <asm/numa.h>
50 #include <asm/asm.h>
51 #include <asm/bugs.h>
52 #include <asm/cpu.h>
53 #include <asm/mce.h>
54 #include <asm/msr.h>
55 #include <asm/memtype.h>
56 #include <asm/microcode.h>
57 #include <asm/microcode_intel.h>
58 #include <asm/intel-family.h>
59 #include <asm/cpu_device_id.h>
60 #include <asm/uv/uv.h>
61
62 #include "cpu.h"
63
64 u32 elf_hwcap2 __read_mostly;
65
66 /* all of these masks are initialized in setup_cpu_local_masks() */
67 cpumask_var_t cpu_initialized_mask;
68 cpumask_var_t cpu_callout_mask;
69 cpumask_var_t cpu_callin_mask;
70
71 /* representing cpus for which sibling maps can be computed */
72 cpumask_var_t cpu_sibling_setup_mask;
73
74 /* Number of siblings per CPU package */
75 int smp_num_siblings = 1;
76 EXPORT_SYMBOL(smp_num_siblings);
77
78 /* Last level cache ID of each logical CPU */
79 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
80
81 /* correctly size the local cpu masks */
setup_cpu_local_masks(void)82 void __init setup_cpu_local_masks(void)
83 {
84 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
85 alloc_bootmem_cpumask_var(&cpu_callin_mask);
86 alloc_bootmem_cpumask_var(&cpu_callout_mask);
87 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
88 }
89
default_init(struct cpuinfo_x86 * c)90 static void default_init(struct cpuinfo_x86 *c)
91 {
92 #ifdef CONFIG_X86_64
93 cpu_detect_cache_sizes(c);
94 #else
95 /* Not much we can do here... */
96 /* Check if at least it has cpuid */
97 if (c->cpuid_level == -1) {
98 /* No cpuid. It must be an ancient CPU */
99 if (c->x86 == 4)
100 strcpy(c->x86_model_id, "486");
101 else if (c->x86 == 3)
102 strcpy(c->x86_model_id, "386");
103 }
104 #endif
105 }
106
107 static const struct cpu_dev default_cpu = {
108 .c_init = default_init,
109 .c_vendor = "Unknown",
110 .c_x86_vendor = X86_VENDOR_UNKNOWN,
111 };
112
113 static const struct cpu_dev *this_cpu = &default_cpu;
114
115 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
116 #ifdef CONFIG_X86_64
117 /*
118 * We need valid kernel segments for data and code in long mode too
119 * IRET will check the segment types kkeil 2000/10/28
120 * Also sysret mandates a special GDT layout
121 *
122 * TLS descriptors are currently at a different place compared to i386.
123 * Hopefully nobody expects them at a fixed place (Wine?)
124 */
125 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
126 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
127 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
129 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
130 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
131 #else
132 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
133 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
134 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
135 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
136 /*
137 * Segments used for calling PnP BIOS have byte granularity.
138 * They code segments and data segments have fixed 64k limits,
139 * the transfer segment sizes are set at run time.
140 */
141 /* 32-bit code */
142 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
143 /* 16-bit code */
144 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
145 /* 16-bit data */
146 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
147 /* 16-bit data */
148 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
149 /* 16-bit data */
150 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
151 /*
152 * The APM segments have byte granularity and their bases
153 * are set at run time. All have 64k limits.
154 */
155 /* 32-bit code */
156 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
157 /* 16-bit code */
158 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
159 /* data */
160 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
161
162 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
163 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
164 #endif
165 } };
166 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
167
168 #ifdef CONFIG_X86_64
x86_nopcid_setup(char * s)169 static int __init x86_nopcid_setup(char *s)
170 {
171 /* nopcid doesn't accept parameters */
172 if (s)
173 return -EINVAL;
174
175 /* do not emit a message if the feature is not present */
176 if (!boot_cpu_has(X86_FEATURE_PCID))
177 return 0;
178
179 setup_clear_cpu_cap(X86_FEATURE_PCID);
180 pr_info("nopcid: PCID feature disabled\n");
181 return 0;
182 }
183 early_param("nopcid", x86_nopcid_setup);
184 #endif
185
x86_noinvpcid_setup(char * s)186 static int __init x86_noinvpcid_setup(char *s)
187 {
188 /* noinvpcid doesn't accept parameters */
189 if (s)
190 return -EINVAL;
191
192 /* do not emit a message if the feature is not present */
193 if (!boot_cpu_has(X86_FEATURE_INVPCID))
194 return 0;
195
196 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
197 pr_info("noinvpcid: INVPCID feature disabled\n");
198 return 0;
199 }
200 early_param("noinvpcid", x86_noinvpcid_setup);
201
202 #ifdef CONFIG_X86_32
203 static int cachesize_override = -1;
204 static int disable_x86_serial_nr = 1;
205
cachesize_setup(char * str)206 static int __init cachesize_setup(char *str)
207 {
208 get_option(&str, &cachesize_override);
209 return 1;
210 }
211 __setup("cachesize=", cachesize_setup);
212
x86_sep_setup(char * s)213 static int __init x86_sep_setup(char *s)
214 {
215 setup_clear_cpu_cap(X86_FEATURE_SEP);
216 return 1;
217 }
218 __setup("nosep", x86_sep_setup);
219
220 /* Standard macro to see if a specific flag is changeable */
flag_is_changeable_p(u32 flag)221 static inline int flag_is_changeable_p(u32 flag)
222 {
223 u32 f1, f2;
224
225 /*
226 * Cyrix and IDT cpus allow disabling of CPUID
227 * so the code below may return different results
228 * when it is executed before and after enabling
229 * the CPUID. Add "volatile" to not allow gcc to
230 * optimize the subsequent calls to this function.
231 */
232 asm volatile ("pushfl \n\t"
233 "pushfl \n\t"
234 "popl %0 \n\t"
235 "movl %0, %1 \n\t"
236 "xorl %2, %0 \n\t"
237 "pushl %0 \n\t"
238 "popfl \n\t"
239 "pushfl \n\t"
240 "popl %0 \n\t"
241 "popfl \n\t"
242
243 : "=&r" (f1), "=&r" (f2)
244 : "ir" (flag));
245
246 return ((f1^f2) & flag) != 0;
247 }
248
249 /* Probe for the CPUID instruction */
have_cpuid_p(void)250 int have_cpuid_p(void)
251 {
252 return flag_is_changeable_p(X86_EFLAGS_ID);
253 }
254
squash_the_stupid_serial_number(struct cpuinfo_x86 * c)255 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
256 {
257 unsigned long lo, hi;
258
259 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
260 return;
261
262 /* Disable processor serial number: */
263
264 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
265 lo |= 0x200000;
266 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
267
268 pr_notice("CPU serial number disabled.\n");
269 clear_cpu_cap(c, X86_FEATURE_PN);
270
271 /* Disabling the serial number may affect the cpuid level */
272 c->cpuid_level = cpuid_eax(0);
273 }
274
x86_serial_nr_setup(char * s)275 static int __init x86_serial_nr_setup(char *s)
276 {
277 disable_x86_serial_nr = 0;
278 return 1;
279 }
280 __setup("serialnumber", x86_serial_nr_setup);
281 #else
flag_is_changeable_p(u32 flag)282 static inline int flag_is_changeable_p(u32 flag)
283 {
284 return 1;
285 }
squash_the_stupid_serial_number(struct cpuinfo_x86 * c)286 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
287 {
288 }
289 #endif
290
setup_disable_smep(char * arg)291 static __init int setup_disable_smep(char *arg)
292 {
293 setup_clear_cpu_cap(X86_FEATURE_SMEP);
294 return 1;
295 }
296 __setup("nosmep", setup_disable_smep);
297
setup_smep(struct cpuinfo_x86 * c)298 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
299 {
300 if (cpu_has(c, X86_FEATURE_SMEP))
301 cr4_set_bits(X86_CR4_SMEP);
302 }
303
setup_disable_smap(char * arg)304 static __init int setup_disable_smap(char *arg)
305 {
306 setup_clear_cpu_cap(X86_FEATURE_SMAP);
307 return 1;
308 }
309 __setup("nosmap", setup_disable_smap);
310
setup_smap(struct cpuinfo_x86 * c)311 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
312 {
313 unsigned long eflags = native_save_fl();
314
315 /* This should have been cleared long ago */
316 BUG_ON(eflags & X86_EFLAGS_AC);
317
318 if (cpu_has(c, X86_FEATURE_SMAP)) {
319 #ifdef CONFIG_X86_SMAP
320 cr4_set_bits(X86_CR4_SMAP);
321 #else
322 cr4_clear_bits(X86_CR4_SMAP);
323 #endif
324 }
325 }
326
setup_umip(struct cpuinfo_x86 * c)327 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
328 {
329 /* Check the boot processor, plus build option for UMIP. */
330 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
331 goto out;
332
333 /* Check the current processor's cpuid bits. */
334 if (!cpu_has(c, X86_FEATURE_UMIP))
335 goto out;
336
337 cr4_set_bits(X86_CR4_UMIP);
338
339 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
340
341 return;
342
343 out:
344 /*
345 * Make sure UMIP is disabled in case it was enabled in a
346 * previous boot (e.g., via kexec).
347 */
348 cr4_clear_bits(X86_CR4_UMIP);
349 }
350
351 /* These bits should not change their value after CPU init is finished. */
352 static const unsigned long cr4_pinned_mask =
353 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | X86_CR4_FSGSBASE;
354 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
355 static unsigned long cr4_pinned_bits __ro_after_init;
356
native_write_cr0(unsigned long val)357 void native_write_cr0(unsigned long val)
358 {
359 unsigned long bits_missing = 0;
360
361 set_register:
362 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");
363
364 if (static_branch_likely(&cr_pinning)) {
365 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
366 bits_missing = X86_CR0_WP;
367 val |= bits_missing;
368 goto set_register;
369 }
370 /* Warn after we've set the missing bits. */
371 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
372 }
373 }
374 EXPORT_SYMBOL(native_write_cr0);
375
native_write_cr4(unsigned long val)376 void native_write_cr4(unsigned long val)
377 {
378 unsigned long bits_changed = 0;
379
380 set_register:
381 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");
382
383 if (static_branch_likely(&cr_pinning)) {
384 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
385 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
386 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
387 goto set_register;
388 }
389 /* Warn after we've corrected the changed bits. */
390 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
391 bits_changed);
392 }
393 }
394 #if IS_MODULE(CONFIG_LKDTM)
395 EXPORT_SYMBOL_GPL(native_write_cr4);
396 #endif
397
cr4_update_irqsoff(unsigned long set,unsigned long clear)398 void cr4_update_irqsoff(unsigned long set, unsigned long clear)
399 {
400 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
401
402 lockdep_assert_irqs_disabled();
403
404 newval = (cr4 & ~clear) | set;
405 if (newval != cr4) {
406 this_cpu_write(cpu_tlbstate.cr4, newval);
407 __write_cr4(newval);
408 }
409 }
410 EXPORT_SYMBOL(cr4_update_irqsoff);
411
412 /* Read the CR4 shadow. */
cr4_read_shadow(void)413 unsigned long cr4_read_shadow(void)
414 {
415 return this_cpu_read(cpu_tlbstate.cr4);
416 }
417 EXPORT_SYMBOL_GPL(cr4_read_shadow);
418
cr4_init(void)419 void cr4_init(void)
420 {
421 unsigned long cr4 = __read_cr4();
422
423 if (boot_cpu_has(X86_FEATURE_PCID))
424 cr4 |= X86_CR4_PCIDE;
425 if (static_branch_likely(&cr_pinning))
426 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
427
428 __write_cr4(cr4);
429
430 /* Initialize cr4 shadow for this CPU. */
431 this_cpu_write(cpu_tlbstate.cr4, cr4);
432 }
433
434 /*
435 * Once CPU feature detection is finished (and boot params have been
436 * parsed), record any of the sensitive CR bits that are set, and
437 * enable CR pinning.
438 */
setup_cr_pinning(void)439 static void __init setup_cr_pinning(void)
440 {
441 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
442 static_key_enable(&cr_pinning.key);
443 }
444
x86_nofsgsbase_setup(char * arg)445 static __init int x86_nofsgsbase_setup(char *arg)
446 {
447 /* Require an exact match without trailing characters. */
448 if (strlen(arg))
449 return 0;
450
451 /* Do not emit a message if the feature is not present. */
452 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
453 return 1;
454
455 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
456 pr_info("FSGSBASE disabled via kernel command line\n");
457 return 1;
458 }
459 __setup("nofsgsbase", x86_nofsgsbase_setup);
460
461 /*
462 * Protection Keys are not available in 32-bit mode.
463 */
464 static bool pku_disabled;
465
setup_pku(struct cpuinfo_x86 * c)466 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
467 {
468 struct pkru_state *pk;
469
470 /* check the boot processor, plus compile options for PKU: */
471 if (!cpu_feature_enabled(X86_FEATURE_PKU))
472 return;
473 /* checks the actual processor's cpuid bits: */
474 if (!cpu_has(c, X86_FEATURE_PKU))
475 return;
476 if (pku_disabled)
477 return;
478
479 cr4_set_bits(X86_CR4_PKE);
480 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU);
481 if (pk)
482 pk->pkru = init_pkru_value;
483 /*
484 * Setting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
485 * cpuid bit to be set. We need to ensure that we
486 * update that bit in this CPU's "cpu_info".
487 */
488 set_cpu_cap(c, X86_FEATURE_OSPKE);
489 }
490
491 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
setup_disable_pku(char * arg)492 static __init int setup_disable_pku(char *arg)
493 {
494 /*
495 * Do not clear the X86_FEATURE_PKU bit. All of the
496 * runtime checks are against OSPKE so clearing the
497 * bit does nothing.
498 *
499 * This way, we will see "pku" in cpuinfo, but not
500 * "ospke", which is exactly what we want. It shows
501 * that the CPU has PKU, but the OS has not enabled it.
502 * This happens to be exactly how a system would look
503 * if we disabled the config option.
504 */
505 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
506 pku_disabled = true;
507 return 1;
508 }
509 __setup("nopku", setup_disable_pku);
510 #endif /* CONFIG_X86_64 */
511
512 /*
513 * Some CPU features depend on higher CPUID levels, which may not always
514 * be available due to CPUID level capping or broken virtualization
515 * software. Add those features to this table to auto-disable them.
516 */
517 struct cpuid_dependent_feature {
518 u32 feature;
519 u32 level;
520 };
521
522 static const struct cpuid_dependent_feature
523 cpuid_dependent_features[] = {
524 { X86_FEATURE_MWAIT, 0x00000005 },
525 { X86_FEATURE_DCA, 0x00000009 },
526 { X86_FEATURE_XSAVE, 0x0000000d },
527 { 0, 0 }
528 };
529
filter_cpuid_features(struct cpuinfo_x86 * c,bool warn)530 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
531 {
532 const struct cpuid_dependent_feature *df;
533
534 for (df = cpuid_dependent_features; df->feature; df++) {
535
536 if (!cpu_has(c, df->feature))
537 continue;
538 /*
539 * Note: cpuid_level is set to -1 if unavailable, but
540 * extended_extended_level is set to 0 if unavailable
541 * and the legitimate extended levels are all negative
542 * when signed; hence the weird messing around with
543 * signs here...
544 */
545 if (!((s32)df->level < 0 ?
546 (u32)df->level > (u32)c->extended_cpuid_level :
547 (s32)df->level > (s32)c->cpuid_level))
548 continue;
549
550 clear_cpu_cap(c, df->feature);
551 if (!warn)
552 continue;
553
554 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
555 x86_cap_flag(df->feature), df->level);
556 }
557 }
558
559 /*
560 * Naming convention should be: <Name> [(<Codename>)]
561 * This table only is used unless init_<vendor>() below doesn't set it;
562 * in particular, if CPUID levels 0x80000002..4 are supported, this
563 * isn't used
564 */
565
566 /* Look up CPU names by table lookup. */
table_lookup_model(struct cpuinfo_x86 * c)567 static const char *table_lookup_model(struct cpuinfo_x86 *c)
568 {
569 #ifdef CONFIG_X86_32
570 const struct legacy_cpu_model_info *info;
571
572 if (c->x86_model >= 16)
573 return NULL; /* Range check */
574
575 if (!this_cpu)
576 return NULL;
577
578 info = this_cpu->legacy_models;
579
580 while (info->family) {
581 if (info->family == c->x86)
582 return info->model_names[c->x86_model];
583 info++;
584 }
585 #endif
586 return NULL; /* Not found */
587 }
588
589 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
590 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
591 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
592
load_percpu_segment(int cpu)593 void load_percpu_segment(int cpu)
594 {
595 #ifdef CONFIG_X86_32
596 loadsegment(fs, __KERNEL_PERCPU);
597 #else
598 __loadsegment_simple(gs, 0);
599 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
600 #endif
601 }
602
603 #ifdef CONFIG_X86_32
604 /* The 32-bit entry code needs to find cpu_entry_area. */
605 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
606 #endif
607
608 /* Load the original GDT from the per-cpu structure */
load_direct_gdt(int cpu)609 void load_direct_gdt(int cpu)
610 {
611 struct desc_ptr gdt_descr;
612
613 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
614 gdt_descr.size = GDT_SIZE - 1;
615 load_gdt(&gdt_descr);
616 }
617 EXPORT_SYMBOL_GPL(load_direct_gdt);
618
619 /* Load a fixmap remapping of the per-cpu GDT */
load_fixmap_gdt(int cpu)620 void load_fixmap_gdt(int cpu)
621 {
622 struct desc_ptr gdt_descr;
623
624 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
625 gdt_descr.size = GDT_SIZE - 1;
626 load_gdt(&gdt_descr);
627 }
628 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
629
630 /*
631 * Current gdt points %fs at the "master" per-cpu area: after this,
632 * it's on the real one.
633 */
switch_to_new_gdt(int cpu)634 void switch_to_new_gdt(int cpu)
635 {
636 /* Load the original GDT */
637 load_direct_gdt(cpu);
638 /* Reload the per-cpu base */
639 load_percpu_segment(cpu);
640 }
641
642 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
643
get_model_name(struct cpuinfo_x86 * c)644 static void get_model_name(struct cpuinfo_x86 *c)
645 {
646 unsigned int *v;
647 char *p, *q, *s;
648
649 if (c->extended_cpuid_level < 0x80000004)
650 return;
651
652 v = (unsigned int *)c->x86_model_id;
653 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
654 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
655 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
656 c->x86_model_id[48] = 0;
657
658 /* Trim whitespace */
659 p = q = s = &c->x86_model_id[0];
660
661 while (*p == ' ')
662 p++;
663
664 while (*p) {
665 /* Note the last non-whitespace index */
666 if (!isspace(*p))
667 s = q;
668
669 *q++ = *p++;
670 }
671
672 *(s + 1) = '\0';
673 }
674
detect_num_cpu_cores(struct cpuinfo_x86 * c)675 void detect_num_cpu_cores(struct cpuinfo_x86 *c)
676 {
677 unsigned int eax, ebx, ecx, edx;
678
679 c->x86_max_cores = 1;
680 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
681 return;
682
683 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
684 if (eax & 0x1f)
685 c->x86_max_cores = (eax >> 26) + 1;
686 }
687
cpu_detect_cache_sizes(struct cpuinfo_x86 * c)688 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
689 {
690 unsigned int n, dummy, ebx, ecx, edx, l2size;
691
692 n = c->extended_cpuid_level;
693
694 if (n >= 0x80000005) {
695 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
696 c->x86_cache_size = (ecx>>24) + (edx>>24);
697 #ifdef CONFIG_X86_64
698 /* On K8 L1 TLB is inclusive, so don't count it */
699 c->x86_tlbsize = 0;
700 #endif
701 }
702
703 if (n < 0x80000006) /* Some chips just has a large L1. */
704 return;
705
706 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
707 l2size = ecx >> 16;
708
709 #ifdef CONFIG_X86_64
710 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
711 #else
712 /* do processor-specific cache resizing */
713 if (this_cpu->legacy_cache_size)
714 l2size = this_cpu->legacy_cache_size(c, l2size);
715
716 /* Allow user to override all this if necessary. */
717 if (cachesize_override != -1)
718 l2size = cachesize_override;
719
720 if (l2size == 0)
721 return; /* Again, no L2 cache is possible */
722 #endif
723
724 c->x86_cache_size = l2size;
725 }
726
727 u16 __read_mostly tlb_lli_4k[NR_INFO];
728 u16 __read_mostly tlb_lli_2m[NR_INFO];
729 u16 __read_mostly tlb_lli_4m[NR_INFO];
730 u16 __read_mostly tlb_lld_4k[NR_INFO];
731 u16 __read_mostly tlb_lld_2m[NR_INFO];
732 u16 __read_mostly tlb_lld_4m[NR_INFO];
733 u16 __read_mostly tlb_lld_1g[NR_INFO];
734
cpu_detect_tlb(struct cpuinfo_x86 * c)735 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
736 {
737 if (this_cpu->c_detect_tlb)
738 this_cpu->c_detect_tlb(c);
739
740 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
741 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
742 tlb_lli_4m[ENTRIES]);
743
744 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
745 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
746 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
747 }
748
detect_ht_early(struct cpuinfo_x86 * c)749 int detect_ht_early(struct cpuinfo_x86 *c)
750 {
751 #ifdef CONFIG_SMP
752 u32 eax, ebx, ecx, edx;
753
754 if (!cpu_has(c, X86_FEATURE_HT))
755 return -1;
756
757 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
758 return -1;
759
760 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
761 return -1;
762
763 cpuid(1, &eax, &ebx, &ecx, &edx);
764
765 smp_num_siblings = (ebx & 0xff0000) >> 16;
766 if (smp_num_siblings == 1)
767 pr_info_once("CPU0: Hyper-Threading is disabled\n");
768 #endif
769 return 0;
770 }
771
detect_ht(struct cpuinfo_x86 * c)772 void detect_ht(struct cpuinfo_x86 *c)
773 {
774 #ifdef CONFIG_SMP
775 int index_msb, core_bits;
776
777 if (detect_ht_early(c) < 0)
778 return;
779
780 index_msb = get_count_order(smp_num_siblings);
781 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
782
783 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
784
785 index_msb = get_count_order(smp_num_siblings);
786
787 core_bits = get_count_order(c->x86_max_cores);
788
789 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
790 ((1 << core_bits) - 1);
791 #endif
792 }
793
get_cpu_vendor(struct cpuinfo_x86 * c)794 static void get_cpu_vendor(struct cpuinfo_x86 *c)
795 {
796 char *v = c->x86_vendor_id;
797 int i;
798
799 for (i = 0; i < X86_VENDOR_NUM; i++) {
800 if (!cpu_devs[i])
801 break;
802
803 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
804 (cpu_devs[i]->c_ident[1] &&
805 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
806
807 this_cpu = cpu_devs[i];
808 c->x86_vendor = this_cpu->c_x86_vendor;
809 return;
810 }
811 }
812
813 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
814 "CPU: Your system may be unstable.\n", v);
815
816 c->x86_vendor = X86_VENDOR_UNKNOWN;
817 this_cpu = &default_cpu;
818 }
819
cpu_detect(struct cpuinfo_x86 * c)820 void cpu_detect(struct cpuinfo_x86 *c)
821 {
822 /* Get vendor name */
823 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
824 (unsigned int *)&c->x86_vendor_id[0],
825 (unsigned int *)&c->x86_vendor_id[8],
826 (unsigned int *)&c->x86_vendor_id[4]);
827
828 c->x86 = 4;
829 /* Intel-defined flags: level 0x00000001 */
830 if (c->cpuid_level >= 0x00000001) {
831 u32 junk, tfms, cap0, misc;
832
833 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
834 c->x86 = x86_family(tfms);
835 c->x86_model = x86_model(tfms);
836 c->x86_stepping = x86_stepping(tfms);
837
838 if (cap0 & (1<<19)) {
839 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
840 c->x86_cache_alignment = c->x86_clflush_size;
841 }
842 }
843 }
844
apply_forced_caps(struct cpuinfo_x86 * c)845 static void apply_forced_caps(struct cpuinfo_x86 *c)
846 {
847 int i;
848
849 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
850 c->x86_capability[i] &= ~cpu_caps_cleared[i];
851 c->x86_capability[i] |= cpu_caps_set[i];
852 }
853 }
854
init_speculation_control(struct cpuinfo_x86 * c)855 static void init_speculation_control(struct cpuinfo_x86 *c)
856 {
857 /*
858 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
859 * and they also have a different bit for STIBP support. Also,
860 * a hypervisor might have set the individual AMD bits even on
861 * Intel CPUs, for finer-grained selection of what's available.
862 */
863 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
864 set_cpu_cap(c, X86_FEATURE_IBRS);
865 set_cpu_cap(c, X86_FEATURE_IBPB);
866 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
867 }
868
869 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
870 set_cpu_cap(c, X86_FEATURE_STIBP);
871
872 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
873 cpu_has(c, X86_FEATURE_VIRT_SSBD))
874 set_cpu_cap(c, X86_FEATURE_SSBD);
875
876 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
877 set_cpu_cap(c, X86_FEATURE_IBRS);
878 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
879 }
880
881 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
882 set_cpu_cap(c, X86_FEATURE_IBPB);
883
884 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
885 set_cpu_cap(c, X86_FEATURE_STIBP);
886 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
887 }
888
889 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
890 set_cpu_cap(c, X86_FEATURE_SSBD);
891 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
892 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
893 }
894 }
895
get_cpu_cap(struct cpuinfo_x86 * c)896 void get_cpu_cap(struct cpuinfo_x86 *c)
897 {
898 u32 eax, ebx, ecx, edx;
899
900 /* Intel-defined flags: level 0x00000001 */
901 if (c->cpuid_level >= 0x00000001) {
902 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
903
904 c->x86_capability[CPUID_1_ECX] = ecx;
905 c->x86_capability[CPUID_1_EDX] = edx;
906 }
907
908 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
909 if (c->cpuid_level >= 0x00000006)
910 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
911
912 /* Additional Intel-defined flags: level 0x00000007 */
913 if (c->cpuid_level >= 0x00000007) {
914 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
915 c->x86_capability[CPUID_7_0_EBX] = ebx;
916 c->x86_capability[CPUID_7_ECX] = ecx;
917 c->x86_capability[CPUID_7_EDX] = edx;
918
919 /* Check valid sub-leaf index before accessing it */
920 if (eax >= 1) {
921 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
922 c->x86_capability[CPUID_7_1_EAX] = eax;
923 }
924 }
925
926 /* Extended state features: level 0x0000000d */
927 if (c->cpuid_level >= 0x0000000d) {
928 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
929
930 c->x86_capability[CPUID_D_1_EAX] = eax;
931 }
932
933 /* AMD-defined flags: level 0x80000001 */
934 eax = cpuid_eax(0x80000000);
935 c->extended_cpuid_level = eax;
936
937 if ((eax & 0xffff0000) == 0x80000000) {
938 if (eax >= 0x80000001) {
939 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
940
941 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
942 c->x86_capability[CPUID_8000_0001_EDX] = edx;
943 }
944 }
945
946 if (c->extended_cpuid_level >= 0x80000007) {
947 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
948
949 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
950 c->x86_power = edx;
951 }
952
953 if (c->extended_cpuid_level >= 0x80000008) {
954 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
955 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
956 }
957
958 if (c->extended_cpuid_level >= 0x8000000a)
959 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
960
961 if (c->extended_cpuid_level >= 0x8000001f)
962 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);
963
964 init_scattered_cpuid_features(c);
965 init_speculation_control(c);
966
967 /*
968 * Clear/Set all flags overridden by options, after probe.
969 * This needs to happen each time we re-probe, which may happen
970 * several times during CPU initialization.
971 */
972 apply_forced_caps(c);
973 }
974
get_cpu_address_sizes(struct cpuinfo_x86 * c)975 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
976 {
977 u32 eax, ebx, ecx, edx;
978
979 if (c->extended_cpuid_level >= 0x80000008) {
980 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
981
982 c->x86_virt_bits = (eax >> 8) & 0xff;
983 c->x86_phys_bits = eax & 0xff;
984 }
985 #ifdef CONFIG_X86_32
986 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
987 c->x86_phys_bits = 36;
988 #endif
989 c->x86_cache_bits = c->x86_phys_bits;
990 }
991
identify_cpu_without_cpuid(struct cpuinfo_x86 * c)992 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
993 {
994 #ifdef CONFIG_X86_32
995 int i;
996
997 /*
998 * First of all, decide if this is a 486 or higher
999 * It's a 486 if we can modify the AC flag
1000 */
1001 if (flag_is_changeable_p(X86_EFLAGS_AC))
1002 c->x86 = 4;
1003 else
1004 c->x86 = 3;
1005
1006 for (i = 0; i < X86_VENDOR_NUM; i++)
1007 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1008 c->x86_vendor_id[0] = 0;
1009 cpu_devs[i]->c_identify(c);
1010 if (c->x86_vendor_id[0]) {
1011 get_cpu_vendor(c);
1012 break;
1013 }
1014 }
1015 #endif
1016 }
1017
1018 #define NO_SPECULATION BIT(0)
1019 #define NO_MELTDOWN BIT(1)
1020 #define NO_SSB BIT(2)
1021 #define NO_L1TF BIT(3)
1022 #define NO_MDS BIT(4)
1023 #define MSBDS_ONLY BIT(5)
1024 #define NO_SWAPGS BIT(6)
1025 #define NO_ITLB_MULTIHIT BIT(7)
1026 #define NO_SPECTRE_V2 BIT(8)
1027
1028 #define VULNWL(vendor, family, model, whitelist) \
1029 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1030
1031 #define VULNWL_INTEL(model, whitelist) \
1032 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1033
1034 #define VULNWL_AMD(family, whitelist) \
1035 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1036
1037 #define VULNWL_HYGON(family, whitelist) \
1038 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1039
1040 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1041 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1042 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1043 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1044 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1045
1046 /* Intel Family 6 */
1047 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1048 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1049 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1050 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1051 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1052
1053 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1054 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1055 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1056 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1057 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1058 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1059
1060 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1061
1062 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1063 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1064
1065 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1066 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1067 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1068
1069 /*
1070 * Technically, swapgs isn't serializing on AMD (despite it previously
1071 * being documented as such in the APM). But according to AMD, %gs is
1072 * updated non-speculatively, and the issuing of %gs-relative memory
1073 * operands will be blocked until the %gs update completes, which is
1074 * good enough for our purposes.
1075 */
1076
1077 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT),
1078
1079 /* AMD Family 0xf - 0x12 */
1080 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1081 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1082 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1083 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1084
1085 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1086 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1087 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1088
1089 /* Zhaoxin Family 7 */
1090 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1091 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1092 {}
1093 };
1094
1095 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1096 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1097 INTEL_FAM6_##model, steppings, \
1098 X86_FEATURE_ANY, issues)
1099
1100 #define SRBDS BIT(0)
1101
1102 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1103 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
1104 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS),
1105 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS),
1106 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS),
1107 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS),
1108 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS),
1109 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS),
1110 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS),
1111 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0xC), SRBDS),
1112 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0xD), SRBDS),
1113 {}
1114 };
1115
cpu_matches(const struct x86_cpu_id * table,unsigned long which)1116 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1117 {
1118 const struct x86_cpu_id *m = x86_match_cpu(table);
1119
1120 return m && !!(m->driver_data & which);
1121 }
1122
x86_read_arch_cap_msr(void)1123 u64 x86_read_arch_cap_msr(void)
1124 {
1125 u64 ia32_cap = 0;
1126
1127 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1128 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1129
1130 return ia32_cap;
1131 }
1132
cpu_set_bug_bits(struct cpuinfo_x86 * c)1133 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1134 {
1135 u64 ia32_cap = x86_read_arch_cap_msr();
1136
1137 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1138 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1139 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1140 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1141
1142 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1143 return;
1144
1145 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1146
1147 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1148 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1149
1150 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1151 !(ia32_cap & ARCH_CAP_SSB_NO) &&
1152 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1153 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1154
1155 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1156 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1157
1158 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1159 !(ia32_cap & ARCH_CAP_MDS_NO)) {
1160 setup_force_cpu_bug(X86_BUG_MDS);
1161 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1162 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1163 }
1164
1165 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1166 setup_force_cpu_bug(X86_BUG_SWAPGS);
1167
1168 /*
1169 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1170 * - TSX is supported or
1171 * - TSX_CTRL is present
1172 *
1173 * TSX_CTRL check is needed for cases when TSX could be disabled before
1174 * the kernel boot e.g. kexec.
1175 * TSX_CTRL check alone is not sufficient for cases when the microcode
1176 * update is not present or running as guest that don't get TSX_CTRL.
1177 */
1178 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1179 (cpu_has(c, X86_FEATURE_RTM) ||
1180 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1181 setup_force_cpu_bug(X86_BUG_TAA);
1182
1183 /*
1184 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1185 * in the vulnerability blacklist.
1186 */
1187 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1188 cpu_has(c, X86_FEATURE_RDSEED)) &&
1189 cpu_matches(cpu_vuln_blacklist, SRBDS))
1190 setup_force_cpu_bug(X86_BUG_SRBDS);
1191
1192 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1193 return;
1194
1195 /* Rogue Data Cache Load? No! */
1196 if (ia32_cap & ARCH_CAP_RDCL_NO)
1197 return;
1198
1199 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1200
1201 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1202 return;
1203
1204 setup_force_cpu_bug(X86_BUG_L1TF);
1205 }
1206
1207 /*
1208 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1209 * unfortunately, that's not true in practice because of early VIA
1210 * chips and (more importantly) broken virtualizers that are not easy
1211 * to detect. In the latter case it doesn't even *fail* reliably, so
1212 * probing for it doesn't even work. Disable it completely on 32-bit
1213 * unless we can find a reliable way to detect all the broken cases.
1214 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1215 */
detect_nopl(void)1216 static void detect_nopl(void)
1217 {
1218 #ifdef CONFIG_X86_32
1219 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1220 #else
1221 setup_force_cpu_cap(X86_FEATURE_NOPL);
1222 #endif
1223 }
1224
1225 /*
1226 * We parse cpu parameters early because fpu__init_system() is executed
1227 * before parse_early_param().
1228 */
cpu_parse_early_param(void)1229 static void __init cpu_parse_early_param(void)
1230 {
1231 char arg[128];
1232 char *argptr = arg;
1233 int arglen, res, bit;
1234
1235 #ifdef CONFIG_X86_32
1236 if (cmdline_find_option_bool(boot_command_line, "no387"))
1237 #ifdef CONFIG_MATH_EMULATION
1238 setup_clear_cpu_cap(X86_FEATURE_FPU);
1239 #else
1240 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1241 #endif
1242
1243 if (cmdline_find_option_bool(boot_command_line, "nofxsr"))
1244 setup_clear_cpu_cap(X86_FEATURE_FXSR);
1245 #endif
1246
1247 if (cmdline_find_option_bool(boot_command_line, "noxsave"))
1248 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
1249
1250 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt"))
1251 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
1252
1253 if (cmdline_find_option_bool(boot_command_line, "noxsaves"))
1254 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
1255
1256 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg));
1257 if (arglen <= 0)
1258 return;
1259
1260 pr_info("Clearing CPUID bits:");
1261 do {
1262 res = get_option(&argptr, &bit);
1263 if (res == 0 || res == 3)
1264 break;
1265
1266 /* If the argument was too long, the last bit may be cut off */
1267 if (res == 1 && arglen >= sizeof(arg))
1268 break;
1269
1270 if (bit >= 0 && bit < NCAPINTS * 32) {
1271 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit));
1272 setup_clear_cpu_cap(bit);
1273 }
1274 } while (res == 2);
1275 pr_cont("\n");
1276 }
1277
1278 /*
1279 * Do minimum CPU detection early.
1280 * Fields really needed: vendor, cpuid_level, family, model, mask,
1281 * cache alignment.
1282 * The others are not touched to avoid unwanted side effects.
1283 *
1284 * WARNING: this function is only called on the boot CPU. Don't add code
1285 * here that is supposed to run on all CPUs.
1286 */
early_identify_cpu(struct cpuinfo_x86 * c)1287 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1288 {
1289 #ifdef CONFIG_X86_64
1290 c->x86_clflush_size = 64;
1291 c->x86_phys_bits = 36;
1292 c->x86_virt_bits = 48;
1293 #else
1294 c->x86_clflush_size = 32;
1295 c->x86_phys_bits = 32;
1296 c->x86_virt_bits = 32;
1297 #endif
1298 c->x86_cache_alignment = c->x86_clflush_size;
1299
1300 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1301 c->extended_cpuid_level = 0;
1302
1303 if (!have_cpuid_p())
1304 identify_cpu_without_cpuid(c);
1305
1306 /* cyrix could have cpuid enabled via c_identify()*/
1307 if (have_cpuid_p()) {
1308 cpu_detect(c);
1309 get_cpu_vendor(c);
1310 get_cpu_cap(c);
1311 get_cpu_address_sizes(c);
1312 setup_force_cpu_cap(X86_FEATURE_CPUID);
1313 cpu_parse_early_param();
1314
1315 if (this_cpu->c_early_init)
1316 this_cpu->c_early_init(c);
1317
1318 c->cpu_index = 0;
1319 filter_cpuid_features(c, false);
1320
1321 if (this_cpu->c_bsp_init)
1322 this_cpu->c_bsp_init(c);
1323 } else {
1324 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1325 }
1326
1327 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1328
1329 cpu_set_bug_bits(c);
1330
1331 sld_setup(c);
1332
1333 fpu__init_system(c);
1334
1335 #ifdef CONFIG_X86_32
1336 /*
1337 * Regardless of whether PCID is enumerated, the SDM says
1338 * that it can't be enabled in 32-bit mode.
1339 */
1340 setup_clear_cpu_cap(X86_FEATURE_PCID);
1341 #endif
1342
1343 /*
1344 * Later in the boot process pgtable_l5_enabled() relies on
1345 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1346 * enabled by this point we need to clear the feature bit to avoid
1347 * false-positives at the later stage.
1348 *
1349 * pgtable_l5_enabled() can be false here for several reasons:
1350 * - 5-level paging is disabled compile-time;
1351 * - it's 32-bit kernel;
1352 * - machine doesn't support 5-level paging;
1353 * - user specified 'no5lvl' in kernel command line.
1354 */
1355 if (!pgtable_l5_enabled())
1356 setup_clear_cpu_cap(X86_FEATURE_LA57);
1357
1358 detect_nopl();
1359 }
1360
early_cpu_init(void)1361 void __init early_cpu_init(void)
1362 {
1363 const struct cpu_dev *const *cdev;
1364 int count = 0;
1365
1366 #ifdef CONFIG_PROCESSOR_SELECT
1367 pr_info("KERNEL supported cpus:\n");
1368 #endif
1369
1370 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1371 const struct cpu_dev *cpudev = *cdev;
1372
1373 if (count >= X86_VENDOR_NUM)
1374 break;
1375 cpu_devs[count] = cpudev;
1376 count++;
1377
1378 #ifdef CONFIG_PROCESSOR_SELECT
1379 {
1380 unsigned int j;
1381
1382 for (j = 0; j < 2; j++) {
1383 if (!cpudev->c_ident[j])
1384 continue;
1385 pr_info(" %s %s\n", cpudev->c_vendor,
1386 cpudev->c_ident[j]);
1387 }
1388 }
1389 #endif
1390 }
1391 early_identify_cpu(&boot_cpu_data);
1392 }
1393
detect_null_seg_behavior(struct cpuinfo_x86 * c)1394 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1395 {
1396 #ifdef CONFIG_X86_64
1397 /*
1398 * Empirically, writing zero to a segment selector on AMD does
1399 * not clear the base, whereas writing zero to a segment
1400 * selector on Intel does clear the base. Intel's behavior
1401 * allows slightly faster context switches in the common case
1402 * where GS is unused by the prev and next threads.
1403 *
1404 * Since neither vendor documents this anywhere that I can see,
1405 * detect it directly instead of hard-coding the choice by
1406 * vendor.
1407 *
1408 * I've designated AMD's behavior as the "bug" because it's
1409 * counterintuitive and less friendly.
1410 */
1411
1412 unsigned long old_base, tmp;
1413 rdmsrl(MSR_FS_BASE, old_base);
1414 wrmsrl(MSR_FS_BASE, 1);
1415 loadsegment(fs, 0);
1416 rdmsrl(MSR_FS_BASE, tmp);
1417 if (tmp != 0)
1418 set_cpu_bug(c, X86_BUG_NULL_SEG);
1419 wrmsrl(MSR_FS_BASE, old_base);
1420 #endif
1421 }
1422
generic_identify(struct cpuinfo_x86 * c)1423 static void generic_identify(struct cpuinfo_x86 *c)
1424 {
1425 c->extended_cpuid_level = 0;
1426
1427 if (!have_cpuid_p())
1428 identify_cpu_without_cpuid(c);
1429
1430 /* cyrix could have cpuid enabled via c_identify()*/
1431 if (!have_cpuid_p())
1432 return;
1433
1434 cpu_detect(c);
1435
1436 get_cpu_vendor(c);
1437
1438 get_cpu_cap(c);
1439
1440 get_cpu_address_sizes(c);
1441
1442 if (c->cpuid_level >= 0x00000001) {
1443 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1444 #ifdef CONFIG_X86_32
1445 # ifdef CONFIG_SMP
1446 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1447 # else
1448 c->apicid = c->initial_apicid;
1449 # endif
1450 #endif
1451 c->phys_proc_id = c->initial_apicid;
1452 }
1453
1454 get_model_name(c); /* Default name */
1455
1456 detect_null_seg_behavior(c);
1457
1458 /*
1459 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1460 * systems that run Linux at CPL > 0 may or may not have the
1461 * issue, but, even if they have the issue, there's absolutely
1462 * nothing we can do about it because we can't use the real IRET
1463 * instruction.
1464 *
1465 * NB: For the time being, only 32-bit kernels support
1466 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1467 * whether to apply espfix using paravirt hooks. If any
1468 * non-paravirt system ever shows up that does *not* have the
1469 * ESPFIX issue, we can change this.
1470 */
1471 #ifdef CONFIG_X86_32
1472 set_cpu_bug(c, X86_BUG_ESPFIX);
1473 #endif
1474 }
1475
1476 /*
1477 * Validate that ACPI/mptables have the same information about the
1478 * effective APIC id and update the package map.
1479 */
validate_apic_and_package_id(struct cpuinfo_x86 * c)1480 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1481 {
1482 #ifdef CONFIG_SMP
1483 unsigned int apicid, cpu = smp_processor_id();
1484
1485 apicid = apic->cpu_present_to_apicid(cpu);
1486
1487 if (apicid != c->apicid) {
1488 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1489 cpu, apicid, c->initial_apicid);
1490 }
1491 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1492 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu));
1493 #else
1494 c->logical_proc_id = 0;
1495 #endif
1496 }
1497
1498 /*
1499 * This does the hard work of actually picking apart the CPU stuff...
1500 */
identify_cpu(struct cpuinfo_x86 * c)1501 static void identify_cpu(struct cpuinfo_x86 *c)
1502 {
1503 int i;
1504
1505 c->loops_per_jiffy = loops_per_jiffy;
1506 c->x86_cache_size = 0;
1507 c->x86_vendor = X86_VENDOR_UNKNOWN;
1508 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1509 c->x86_vendor_id[0] = '\0'; /* Unset */
1510 c->x86_model_id[0] = '\0'; /* Unset */
1511 c->x86_max_cores = 1;
1512 c->x86_coreid_bits = 0;
1513 c->cu_id = 0xff;
1514 #ifdef CONFIG_X86_64
1515 c->x86_clflush_size = 64;
1516 c->x86_phys_bits = 36;
1517 c->x86_virt_bits = 48;
1518 #else
1519 c->cpuid_level = -1; /* CPUID not detected */
1520 c->x86_clflush_size = 32;
1521 c->x86_phys_bits = 32;
1522 c->x86_virt_bits = 32;
1523 #endif
1524 c->x86_cache_alignment = c->x86_clflush_size;
1525 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1526 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1527 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1528 #endif
1529
1530 generic_identify(c);
1531
1532 if (this_cpu->c_identify)
1533 this_cpu->c_identify(c);
1534
1535 /* Clear/Set all flags overridden by options, after probe */
1536 apply_forced_caps(c);
1537
1538 #ifdef CONFIG_X86_64
1539 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1540 #endif
1541
1542 /*
1543 * Vendor-specific initialization. In this section we
1544 * canonicalize the feature flags, meaning if there are
1545 * features a certain CPU supports which CPUID doesn't
1546 * tell us, CPUID claiming incorrect flags, or other bugs,
1547 * we handle them here.
1548 *
1549 * At the end of this section, c->x86_capability better
1550 * indicate the features this CPU genuinely supports!
1551 */
1552 if (this_cpu->c_init)
1553 this_cpu->c_init(c);
1554
1555 /* Disable the PN if appropriate */
1556 squash_the_stupid_serial_number(c);
1557
1558 /* Set up SMEP/SMAP/UMIP */
1559 setup_smep(c);
1560 setup_smap(c);
1561 setup_umip(c);
1562
1563 /* Enable FSGSBASE instructions if available. */
1564 if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1565 cr4_set_bits(X86_CR4_FSGSBASE);
1566 elf_hwcap2 |= HWCAP2_FSGSBASE;
1567 }
1568
1569 /*
1570 * The vendor-specific functions might have changed features.
1571 * Now we do "generic changes."
1572 */
1573
1574 /* Filter out anything that depends on CPUID levels we don't have */
1575 filter_cpuid_features(c, true);
1576
1577 /* If the model name is still unset, do table lookup. */
1578 if (!c->x86_model_id[0]) {
1579 const char *p;
1580 p = table_lookup_model(c);
1581 if (p)
1582 strcpy(c->x86_model_id, p);
1583 else
1584 /* Last resort... */
1585 sprintf(c->x86_model_id, "%02x/%02x",
1586 c->x86, c->x86_model);
1587 }
1588
1589 #ifdef CONFIG_X86_64
1590 detect_ht(c);
1591 #endif
1592
1593 x86_init_rdrand(c);
1594 setup_pku(c);
1595
1596 /*
1597 * Clear/Set all flags overridden by options, need do it
1598 * before following smp all cpus cap AND.
1599 */
1600 apply_forced_caps(c);
1601
1602 /*
1603 * On SMP, boot_cpu_data holds the common feature set between
1604 * all CPUs; so make sure that we indicate which features are
1605 * common between the CPUs. The first time this routine gets
1606 * executed, c == &boot_cpu_data.
1607 */
1608 if (c != &boot_cpu_data) {
1609 /* AND the already accumulated flags with these */
1610 for (i = 0; i < NCAPINTS; i++)
1611 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1612
1613 /* OR, i.e. replicate the bug flags */
1614 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1615 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1616 }
1617
1618 /* Init Machine Check Exception if available. */
1619 mcheck_cpu_init(c);
1620
1621 select_idle_routine(c);
1622
1623 #ifdef CONFIG_NUMA
1624 numa_add_cpu(smp_processor_id());
1625 #endif
1626 }
1627
1628 /*
1629 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1630 * on 32-bit kernels:
1631 */
1632 #ifdef CONFIG_X86_32
enable_sep_cpu(void)1633 void enable_sep_cpu(void)
1634 {
1635 struct tss_struct *tss;
1636 int cpu;
1637
1638 if (!boot_cpu_has(X86_FEATURE_SEP))
1639 return;
1640
1641 cpu = get_cpu();
1642 tss = &per_cpu(cpu_tss_rw, cpu);
1643
1644 /*
1645 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1646 * see the big comment in struct x86_hw_tss's definition.
1647 */
1648
1649 tss->x86_tss.ss1 = __KERNEL_CS;
1650 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1651 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1652 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1653
1654 put_cpu();
1655 }
1656 #endif
1657
identify_boot_cpu(void)1658 void __init identify_boot_cpu(void)
1659 {
1660 identify_cpu(&boot_cpu_data);
1661 #ifdef CONFIG_X86_32
1662 sysenter_setup();
1663 enable_sep_cpu();
1664 #endif
1665 cpu_detect_tlb(&boot_cpu_data);
1666 setup_cr_pinning();
1667
1668 tsx_init();
1669 }
1670
identify_secondary_cpu(struct cpuinfo_x86 * c)1671 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1672 {
1673 BUG_ON(c == &boot_cpu_data);
1674 identify_cpu(c);
1675 #ifdef CONFIG_X86_32
1676 enable_sep_cpu();
1677 #endif
1678 mtrr_ap_init();
1679 validate_apic_and_package_id(c);
1680 x86_spec_ctrl_setup_ap();
1681 update_srbds_msr();
1682 }
1683
setup_noclflush(char * arg)1684 static __init int setup_noclflush(char *arg)
1685 {
1686 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1687 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1688 return 1;
1689 }
1690 __setup("noclflush", setup_noclflush);
1691
print_cpu_info(struct cpuinfo_x86 * c)1692 void print_cpu_info(struct cpuinfo_x86 *c)
1693 {
1694 const char *vendor = NULL;
1695
1696 if (c->x86_vendor < X86_VENDOR_NUM) {
1697 vendor = this_cpu->c_vendor;
1698 } else {
1699 if (c->cpuid_level >= 0)
1700 vendor = c->x86_vendor_id;
1701 }
1702
1703 if (vendor && !strstr(c->x86_model_id, vendor))
1704 pr_cont("%s ", vendor);
1705
1706 if (c->x86_model_id[0])
1707 pr_cont("%s", c->x86_model_id);
1708 else
1709 pr_cont("%d86", c->x86);
1710
1711 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1712
1713 if (c->x86_stepping || c->cpuid_level >= 0)
1714 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1715 else
1716 pr_cont(")\n");
1717 }
1718
1719 /*
1720 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1721 * But we need to keep a dummy __setup around otherwise it would
1722 * show up as an environment variable for init.
1723 */
setup_clearcpuid(char * arg)1724 static __init int setup_clearcpuid(char *arg)
1725 {
1726 return 1;
1727 }
1728 __setup("clearcpuid=", setup_clearcpuid);
1729
1730 #ifdef CONFIG_X86_64
1731 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
1732 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
1733 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
1734
1735 /*
1736 * The following percpu variables are hot. Align current_task to
1737 * cacheline size such that they fall in the same cacheline.
1738 */
1739 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1740 &init_task;
1741 EXPORT_PER_CPU_SYMBOL(current_task);
1742
1743 DEFINE_PER_CPU(void *, hardirq_stack_ptr);
1744 DEFINE_PER_CPU(bool, hardirq_stack_inuse);
1745
1746 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1747 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1748
1749 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK;
1750
1751 /* May not be marked __init: used by software suspend */
syscall_init(void)1752 void syscall_init(void)
1753 {
1754 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1755 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1756
1757 #ifdef CONFIG_IA32_EMULATION
1758 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1759 /*
1760 * This only works on Intel CPUs.
1761 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1762 * This does not cause SYSENTER to jump to the wrong location, because
1763 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1764 */
1765 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1766 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
1767 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1768 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1769 #else
1770 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1771 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1772 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1773 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1774 #endif
1775
1776 /* Flags to clear on syscall */
1777 wrmsrl(MSR_SYSCALL_MASK,
1778 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1779 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1780 }
1781
1782 #else /* CONFIG_X86_64 */
1783
1784 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1785 EXPORT_PER_CPU_SYMBOL(current_task);
1786 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1787 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1788
1789 /*
1790 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1791 * the top of the kernel stack. Use an extra percpu variable to track the
1792 * top of the kernel stack directly.
1793 */
1794 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1795 (unsigned long)&init_thread_union + THREAD_SIZE;
1796 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1797
1798 #ifdef CONFIG_STACKPROTECTOR
1799 DEFINE_PER_CPU(unsigned long, __stack_chk_guard);
1800 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard);
1801 #endif
1802
1803 #endif /* CONFIG_X86_64 */
1804
1805 /*
1806 * Clear all 6 debug registers:
1807 */
clear_all_debug_regs(void)1808 static void clear_all_debug_regs(void)
1809 {
1810 int i;
1811
1812 for (i = 0; i < 8; i++) {
1813 /* Ignore db4, db5 */
1814 if ((i == 4) || (i == 5))
1815 continue;
1816
1817 set_debugreg(0, i);
1818 }
1819 }
1820
1821 #ifdef CONFIG_KGDB
1822 /*
1823 * Restore debug regs if using kgdbwait and you have a kernel debugger
1824 * connection established.
1825 */
dbg_restore_debug_regs(void)1826 static void dbg_restore_debug_regs(void)
1827 {
1828 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1829 arch_kgdb_ops.correct_hw_break();
1830 }
1831 #else /* ! CONFIG_KGDB */
1832 #define dbg_restore_debug_regs()
1833 #endif /* ! CONFIG_KGDB */
1834
wait_for_master_cpu(int cpu)1835 static void wait_for_master_cpu(int cpu)
1836 {
1837 #ifdef CONFIG_SMP
1838 /*
1839 * wait for ACK from master CPU before continuing
1840 * with AP initialization
1841 */
1842 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1843 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1844 cpu_relax();
1845 #endif
1846 }
1847
1848 #ifdef CONFIG_X86_64
setup_getcpu(int cpu)1849 static inline void setup_getcpu(int cpu)
1850 {
1851 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
1852 struct desc_struct d = { };
1853
1854 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))
1855 wrmsr(MSR_TSC_AUX, cpudata, 0);
1856
1857 /* Store CPU and node number in limit. */
1858 d.limit0 = cpudata;
1859 d.limit1 = cpudata >> 16;
1860
1861 d.type = 5; /* RO data, expand down, accessed */
1862 d.dpl = 3; /* Visible to user code */
1863 d.s = 1; /* Not a system segment */
1864 d.p = 1; /* Present */
1865 d.d = 1; /* 32-bit */
1866
1867 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
1868 }
1869
ucode_cpu_init(int cpu)1870 static inline void ucode_cpu_init(int cpu)
1871 {
1872 if (cpu)
1873 load_ucode_ap();
1874 }
1875
tss_setup_ist(struct tss_struct * tss)1876 static inline void tss_setup_ist(struct tss_struct *tss)
1877 {
1878 /* Set up the per-CPU TSS IST stacks */
1879 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
1880 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
1881 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
1882 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
1883 /* Only mapped when SEV-ES is active */
1884 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
1885 }
1886
1887 #else /* CONFIG_X86_64 */
1888
setup_getcpu(int cpu)1889 static inline void setup_getcpu(int cpu) { }
1890
ucode_cpu_init(int cpu)1891 static inline void ucode_cpu_init(int cpu)
1892 {
1893 show_ucode_info_early();
1894 }
1895
tss_setup_ist(struct tss_struct * tss)1896 static inline void tss_setup_ist(struct tss_struct *tss) { }
1897
1898 #endif /* !CONFIG_X86_64 */
1899
tss_setup_io_bitmap(struct tss_struct * tss)1900 static inline void tss_setup_io_bitmap(struct tss_struct *tss)
1901 {
1902 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
1903
1904 #ifdef CONFIG_X86_IOPL_IOPERM
1905 tss->io_bitmap.prev_max = 0;
1906 tss->io_bitmap.prev_sequence = 0;
1907 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
1908 /*
1909 * Invalidate the extra array entry past the end of the all
1910 * permission bitmap as required by the hardware.
1911 */
1912 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
1913 #endif
1914 }
1915
1916 /*
1917 * Setup everything needed to handle exceptions from the IDT, including the IST
1918 * exceptions which use paranoid_entry().
1919 */
cpu_init_exception_handling(void)1920 void cpu_init_exception_handling(void)
1921 {
1922 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
1923 int cpu = raw_smp_processor_id();
1924
1925 /* paranoid_entry() gets the CPU number from the GDT */
1926 setup_getcpu(cpu);
1927
1928 /* IST vectors need TSS to be set up. */
1929 tss_setup_ist(tss);
1930 tss_setup_io_bitmap(tss);
1931 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1932
1933 load_TR_desc();
1934
1935 /* Finally load the IDT */
1936 load_current_idt();
1937 }
1938
1939 /*
1940 * cpu_init() initializes state that is per-CPU. Some data is already
1941 * initialized (naturally) in the bootstrap process, such as the GDT
1942 * and IDT. We reload them nevertheless, this function acts as a
1943 * 'CPU state barrier', nothing should get across.
1944 */
cpu_init(void)1945 void cpu_init(void)
1946 {
1947 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
1948 struct task_struct *cur = current;
1949 int cpu = raw_smp_processor_id();
1950
1951 wait_for_master_cpu(cpu);
1952
1953 ucode_cpu_init(cpu);
1954
1955 #ifdef CONFIG_NUMA
1956 if (this_cpu_read(numa_node) == 0 &&
1957 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1958 set_numa_node(early_cpu_to_node(cpu));
1959 #endif
1960 setup_getcpu(cpu);
1961
1962 pr_debug("Initializing CPU#%d\n", cpu);
1963
1964 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
1965 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
1966 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1967
1968 /*
1969 * Initialize the per-CPU GDT with the boot GDT,
1970 * and set up the GDT descriptor:
1971 */
1972 switch_to_new_gdt(cpu);
1973 load_current_idt();
1974
1975 if (IS_ENABLED(CONFIG_X86_64)) {
1976 loadsegment(fs, 0);
1977 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1978 syscall_init();
1979
1980 wrmsrl(MSR_FS_BASE, 0);
1981 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1982 barrier();
1983
1984 x2apic_setup();
1985 }
1986
1987 mmgrab(&init_mm);
1988 cur->active_mm = &init_mm;
1989 BUG_ON(cur->mm);
1990 initialize_tlbstate_and_flush();
1991 enter_lazy_tlb(&init_mm, cur);
1992
1993 /* Initialize the TSS. */
1994 tss_setup_ist(tss);
1995 tss_setup_io_bitmap(tss);
1996 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1997
1998 load_TR_desc();
1999 /*
2000 * sp0 points to the entry trampoline stack regardless of what task
2001 * is running.
2002 */
2003 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
2004
2005 load_mm_ldt(&init_mm);
2006
2007 clear_all_debug_regs();
2008 dbg_restore_debug_regs();
2009
2010 doublefault_init_cpu_tss();
2011
2012 fpu__init_cpu();
2013
2014 if (is_uv_system())
2015 uv_cpu_init();
2016
2017 load_fixmap_gdt(cpu);
2018 }
2019
2020 /*
2021 * The microcode loader calls this upon late microcode load to recheck features,
2022 * only when microcode has been updated. Caller holds microcode_mutex and CPU
2023 * hotplug lock.
2024 */
microcode_check(void)2025 void microcode_check(void)
2026 {
2027 struct cpuinfo_x86 info;
2028
2029 perf_check_microcode();
2030
2031 /* Reload CPUID max function as it might've changed. */
2032 info.cpuid_level = cpuid_eax(0);
2033
2034 /*
2035 * Copy all capability leafs to pick up the synthetic ones so that
2036 * memcmp() below doesn't fail on that. The ones coming from CPUID will
2037 * get overwritten in get_cpu_cap().
2038 */
2039 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
2040
2041 get_cpu_cap(&info);
2042
2043 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
2044 return;
2045
2046 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2047 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2048 }
2049
2050 /*
2051 * Invoked from core CPU hotplug code after hotplug operations
2052 */
arch_smt_update(void)2053 void arch_smt_update(void)
2054 {
2055 /* Handle the speculative execution misfeatures */
2056 cpu_bugs_smt_update();
2057 /* Check whether IPI broadcasting can be enabled */
2058 apic_smt_update();
2059 }
2060