1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/pci.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_ih.h"
28 #include "vid.h"
29
30 #include "oss/oss_3_0_d.h"
31 #include "oss/oss_3_0_sh_mask.h"
32
33 #include "bif/bif_5_1_d.h"
34 #include "bif/bif_5_1_sh_mask.h"
35
36 /*
37 * Interrupts
38 * Starting with r6xx, interrupts are handled via a ring buffer.
39 * Ring buffers are areas of GPU accessible memory that the GPU
40 * writes interrupt vectors into and the host reads vectors out of.
41 * There is a rptr (read pointer) that determines where the
42 * host is currently reading, and a wptr (write pointer)
43 * which determines where the GPU has written. When the
44 * pointers are equal, the ring is idle. When the GPU
45 * writes vectors to the ring buffer, it increments the
46 * wptr. When there is an interrupt, the host then starts
47 * fetching commands and processing them until the pointers are
48 * equal again at which point it updates the rptr.
49 */
50
51 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);
52
53 /**
54 * tonga_ih_enable_interrupts - Enable the interrupt ring buffer
55 *
56 * @adev: amdgpu_device pointer
57 *
58 * Enable the interrupt ring buffer (VI).
59 */
tonga_ih_enable_interrupts(struct amdgpu_device * adev)60 static void tonga_ih_enable_interrupts(struct amdgpu_device *adev)
61 {
62 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
63
64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
66 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
67 adev->irq.ih.enabled = true;
68 }
69
70 /**
71 * tonga_ih_disable_interrupts - Disable the interrupt ring buffer
72 *
73 * @adev: amdgpu_device pointer
74 *
75 * Disable the interrupt ring buffer (VI).
76 */
tonga_ih_disable_interrupts(struct amdgpu_device * adev)77 static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
78 {
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
80
81 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
83 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
84 /* set rptr, wptr to 0 */
85 WREG32(mmIH_RB_RPTR, 0);
86 WREG32(mmIH_RB_WPTR, 0);
87 adev->irq.ih.enabled = false;
88 adev->irq.ih.rptr = 0;
89 }
90
91 /**
92 * tonga_ih_irq_init - init and enable the interrupt ring
93 *
94 * @adev: amdgpu_device pointer
95 *
96 * Allocate a ring buffer for the interrupt controller,
97 * enable the RLC, disable interrupts, enable the IH
98 * ring buffer and enable it (VI).
99 * Called at device load and reume.
100 * Returns 0 for success, errors for failure.
101 */
tonga_ih_irq_init(struct amdgpu_device * adev)102 static int tonga_ih_irq_init(struct amdgpu_device *adev)
103 {
104 u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
105 struct amdgpu_ih_ring *ih = &adev->irq.ih;
106 int rb_bufsz;
107
108 /* disable irqs */
109 tonga_ih_disable_interrupts(adev);
110
111 /* setup interrupt control */
112 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
113 interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
114 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
115 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
116 */
117 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
118 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
119 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
120 WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
121
122 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
123 WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8);
124
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
126 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
128 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
131
132 if (adev->irq.msi_enabled)
133 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
134
135 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
136
137 /* set the writeback address whether it's enabled or not */
138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
140
141 /* set rptr, wptr to 0 */
142 WREG32(mmIH_RB_RPTR, 0);
143 WREG32(mmIH_RB_WPTR, 0);
144
145 ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
146 if (adev->irq.ih.use_doorbell) {
147 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
148 OFFSET, adev->irq.ih.doorbell_index);
149 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
150 ENABLE, 1);
151 } else {
152 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
153 ENABLE, 0);
154 }
155 WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
156
157 pci_set_master(adev->pdev);
158
159 /* enable interrupts */
160 tonga_ih_enable_interrupts(adev);
161
162 return 0;
163 }
164
165 /**
166 * tonga_ih_irq_disable - disable interrupts
167 *
168 * @adev: amdgpu_device pointer
169 *
170 * Disable interrupts on the hw (VI).
171 */
tonga_ih_irq_disable(struct amdgpu_device * adev)172 static void tonga_ih_irq_disable(struct amdgpu_device *adev)
173 {
174 tonga_ih_disable_interrupts(adev);
175
176 /* Wait and acknowledge irq */
177 mdelay(1);
178 }
179
180 /**
181 * tonga_ih_get_wptr - get the IH ring buffer wptr
182 *
183 * @adev: amdgpu_device pointer
184 * @ih: IH ring buffer to fetch wptr
185 *
186 * Get the IH ring buffer wptr from either the register
187 * or the writeback memory buffer (VI). Also check for
188 * ring buffer overflow and deal with it.
189 * Used by cz_irq_process(VI).
190 * Returns the value of the wptr.
191 */
tonga_ih_get_wptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)192 static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
193 struct amdgpu_ih_ring *ih)
194 {
195 u32 wptr, tmp;
196
197 wptr = le32_to_cpu(*ih->wptr_cpu);
198
199 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
200 goto out;
201
202 /* Double check that the overflow wasn't already cleared. */
203 wptr = RREG32(mmIH_RB_WPTR);
204
205 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
206 goto out;
207
208 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
209
210 /* When a ring buffer overflow happen start parsing interrupt
211 * from the last not overwritten vector (wptr + 16). Hopefully
212 * this should allow us to catchup.
213 */
214
215 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
216 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
217 ih->rptr = (wptr + 16) & ih->ptr_mask;
218 tmp = RREG32(mmIH_RB_CNTL);
219 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
220 WREG32(mmIH_RB_CNTL, tmp);
221
222 out:
223 return (wptr & ih->ptr_mask);
224 }
225
226 /**
227 * tonga_ih_decode_iv - decode an interrupt vector
228 *
229 * @adev: amdgpu_device pointer
230 * @ih: IH ring buffer to decode
231 * @entry: IV entry to place decoded information into
232 *
233 * Decodes the interrupt vector at the current rptr
234 * position and also advance the position.
235 */
tonga_ih_decode_iv(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,struct amdgpu_iv_entry * entry)236 static void tonga_ih_decode_iv(struct amdgpu_device *adev,
237 struct amdgpu_ih_ring *ih,
238 struct amdgpu_iv_entry *entry)
239 {
240 /* wptr/rptr are in bytes! */
241 u32 ring_index = ih->rptr >> 2;
242 uint32_t dw[4];
243
244 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
245 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
246 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
247 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
248
249 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
250 entry->src_id = dw[0] & 0xff;
251 entry->src_data[0] = dw[1] & 0xfffffff;
252 entry->ring_id = dw[2] & 0xff;
253 entry->vmid = (dw[2] >> 8) & 0xff;
254 entry->pasid = (dw[2] >> 16) & 0xffff;
255
256 /* wptr/rptr are in bytes! */
257 ih->rptr += 16;
258 }
259
260 /**
261 * tonga_ih_set_rptr - set the IH ring buffer rptr
262 *
263 * @adev: amdgpu_device pointer
264 * @ih: IH ring buffer to set rptr
265 *
266 * Set the IH ring buffer rptr.
267 */
tonga_ih_set_rptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)268 static void tonga_ih_set_rptr(struct amdgpu_device *adev,
269 struct amdgpu_ih_ring *ih)
270 {
271 if (ih->use_doorbell) {
272 /* XXX check if swapping is necessary on BE */
273 *ih->rptr_cpu = ih->rptr;
274 WDOORBELL32(ih->doorbell_index, ih->rptr);
275 } else {
276 WREG32(mmIH_RB_RPTR, ih->rptr);
277 }
278 }
279
tonga_ih_early_init(void * handle)280 static int tonga_ih_early_init(void *handle)
281 {
282 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
283 int ret;
284
285 ret = amdgpu_irq_add_domain(adev);
286 if (ret)
287 return ret;
288
289 tonga_ih_set_interrupt_funcs(adev);
290
291 return 0;
292 }
293
tonga_ih_sw_init(void * handle)294 static int tonga_ih_sw_init(void *handle)
295 {
296 int r;
297 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
298
299 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);
300 if (r)
301 return r;
302
303 adev->irq.ih.use_doorbell = true;
304 adev->irq.ih.doorbell_index = adev->doorbell_index.ih;
305
306 r = amdgpu_irq_init(adev);
307
308 return r;
309 }
310
tonga_ih_sw_fini(void * handle)311 static int tonga_ih_sw_fini(void *handle)
312 {
313 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
314
315 amdgpu_irq_fini(adev);
316 amdgpu_ih_ring_fini(adev, &adev->irq.ih);
317 amdgpu_irq_remove_domain(adev);
318
319 return 0;
320 }
321
tonga_ih_hw_init(void * handle)322 static int tonga_ih_hw_init(void *handle)
323 {
324 int r;
325 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
326
327 r = tonga_ih_irq_init(adev);
328 if (r)
329 return r;
330
331 return 0;
332 }
333
tonga_ih_hw_fini(void * handle)334 static int tonga_ih_hw_fini(void *handle)
335 {
336 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
337
338 tonga_ih_irq_disable(adev);
339
340 return 0;
341 }
342
tonga_ih_suspend(void * handle)343 static int tonga_ih_suspend(void *handle)
344 {
345 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
346
347 return tonga_ih_hw_fini(adev);
348 }
349
tonga_ih_resume(void * handle)350 static int tonga_ih_resume(void *handle)
351 {
352 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
353
354 return tonga_ih_hw_init(adev);
355 }
356
tonga_ih_is_idle(void * handle)357 static bool tonga_ih_is_idle(void *handle)
358 {
359 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
360 u32 tmp = RREG32(mmSRBM_STATUS);
361
362 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
363 return false;
364
365 return true;
366 }
367
tonga_ih_wait_for_idle(void * handle)368 static int tonga_ih_wait_for_idle(void *handle)
369 {
370 unsigned i;
371 u32 tmp;
372 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
373
374 for (i = 0; i < adev->usec_timeout; i++) {
375 /* read MC_STATUS */
376 tmp = RREG32(mmSRBM_STATUS);
377 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
378 return 0;
379 udelay(1);
380 }
381 return -ETIMEDOUT;
382 }
383
tonga_ih_check_soft_reset(void * handle)384 static bool tonga_ih_check_soft_reset(void *handle)
385 {
386 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
387 u32 srbm_soft_reset = 0;
388 u32 tmp = RREG32(mmSRBM_STATUS);
389
390 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
391 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
392 SOFT_RESET_IH, 1);
393
394 if (srbm_soft_reset) {
395 adev->irq.srbm_soft_reset = srbm_soft_reset;
396 return true;
397 } else {
398 adev->irq.srbm_soft_reset = 0;
399 return false;
400 }
401 }
402
tonga_ih_pre_soft_reset(void * handle)403 static int tonga_ih_pre_soft_reset(void *handle)
404 {
405 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
406
407 if (!adev->irq.srbm_soft_reset)
408 return 0;
409
410 return tonga_ih_hw_fini(adev);
411 }
412
tonga_ih_post_soft_reset(void * handle)413 static int tonga_ih_post_soft_reset(void *handle)
414 {
415 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
416
417 if (!adev->irq.srbm_soft_reset)
418 return 0;
419
420 return tonga_ih_hw_init(adev);
421 }
422
tonga_ih_soft_reset(void * handle)423 static int tonga_ih_soft_reset(void *handle)
424 {
425 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
426 u32 srbm_soft_reset;
427
428 if (!adev->irq.srbm_soft_reset)
429 return 0;
430 srbm_soft_reset = adev->irq.srbm_soft_reset;
431
432 if (srbm_soft_reset) {
433 u32 tmp;
434
435 tmp = RREG32(mmSRBM_SOFT_RESET);
436 tmp |= srbm_soft_reset;
437 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
438 WREG32(mmSRBM_SOFT_RESET, tmp);
439 tmp = RREG32(mmSRBM_SOFT_RESET);
440
441 udelay(50);
442
443 tmp &= ~srbm_soft_reset;
444 WREG32(mmSRBM_SOFT_RESET, tmp);
445 tmp = RREG32(mmSRBM_SOFT_RESET);
446
447 /* Wait a little for things to settle down */
448 udelay(50);
449 }
450
451 return 0;
452 }
453
tonga_ih_set_clockgating_state(void * handle,enum amd_clockgating_state state)454 static int tonga_ih_set_clockgating_state(void *handle,
455 enum amd_clockgating_state state)
456 {
457 return 0;
458 }
459
tonga_ih_set_powergating_state(void * handle,enum amd_powergating_state state)460 static int tonga_ih_set_powergating_state(void *handle,
461 enum amd_powergating_state state)
462 {
463 return 0;
464 }
465
466 static const struct amd_ip_funcs tonga_ih_ip_funcs = {
467 .name = "tonga_ih",
468 .early_init = tonga_ih_early_init,
469 .late_init = NULL,
470 .sw_init = tonga_ih_sw_init,
471 .sw_fini = tonga_ih_sw_fini,
472 .hw_init = tonga_ih_hw_init,
473 .hw_fini = tonga_ih_hw_fini,
474 .suspend = tonga_ih_suspend,
475 .resume = tonga_ih_resume,
476 .is_idle = tonga_ih_is_idle,
477 .wait_for_idle = tonga_ih_wait_for_idle,
478 .check_soft_reset = tonga_ih_check_soft_reset,
479 .pre_soft_reset = tonga_ih_pre_soft_reset,
480 .soft_reset = tonga_ih_soft_reset,
481 .post_soft_reset = tonga_ih_post_soft_reset,
482 .set_clockgating_state = tonga_ih_set_clockgating_state,
483 .set_powergating_state = tonga_ih_set_powergating_state,
484 };
485
486 static const struct amdgpu_ih_funcs tonga_ih_funcs = {
487 .get_wptr = tonga_ih_get_wptr,
488 .decode_iv = tonga_ih_decode_iv,
489 .set_rptr = tonga_ih_set_rptr
490 };
491
tonga_ih_set_interrupt_funcs(struct amdgpu_device * adev)492 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
493 {
494 adev->irq.ih_funcs = &tonga_ih_funcs;
495 }
496
497 const struct amdgpu_ip_block_version tonga_ih_ip_block =
498 {
499 .type = AMD_IP_BLOCK_TYPE_IH,
500 .major = 3,
501 .minor = 0,
502 .rev = 0,
503 .funcs = &tonga_ih_ip_funcs,
504 };
505