1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
3 
4 #ifndef _E1000_PHY_H_
5 #define _E1000_PHY_H_
6 
7 enum e1000_ms_type {
8 	e1000_ms_hw_default = 0,
9 	e1000_ms_force_master,
10 	e1000_ms_force_slave,
11 	e1000_ms_auto
12 };
13 
14 enum e1000_smart_speed {
15 	e1000_smart_speed_default = 0,
16 	e1000_smart_speed_on,
17 	e1000_smart_speed_off
18 };
19 
20 s32  igb_check_downshift(struct e1000_hw *hw);
21 s32  igb_check_reset_block(struct e1000_hw *hw);
22 s32  igb_copper_link_setup_igp(struct e1000_hw *hw);
23 s32  igb_copper_link_setup_m88(struct e1000_hw *hw);
24 s32  igb_copper_link_setup_m88_gen2(struct e1000_hw *hw);
25 s32  igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
26 s32  igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
27 s32  igb_get_cable_length_m88(struct e1000_hw *hw);
28 s32  igb_get_cable_length_m88_gen2(struct e1000_hw *hw);
29 s32  igb_get_cable_length_igp_2(struct e1000_hw *hw);
30 s32  igb_get_phy_id(struct e1000_hw *hw);
31 s32  igb_get_phy_info_igp(struct e1000_hw *hw);
32 s32  igb_get_phy_info_m88(struct e1000_hw *hw);
33 s32  igb_phy_sw_reset(struct e1000_hw *hw);
34 s32  igb_phy_hw_reset(struct e1000_hw *hw);
35 s32  igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
36 s32  igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
37 s32  igb_setup_copper_link(struct e1000_hw *hw);
38 s32  igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
39 s32  igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
40 				u32 usec_interval, bool *success);
41 void igb_power_up_phy_copper(struct e1000_hw *hw);
42 void igb_power_down_phy_copper(struct e1000_hw *hw);
43 s32  igb_phy_init_script_igp3(struct e1000_hw *hw);
44 s32  igb_initialize_M88E1512_phy(struct e1000_hw *hw);
45 s32  igb_initialize_M88E1543_phy(struct e1000_hw *hw);
46 s32  igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
47 s32  igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
48 s32  igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
49 s32  igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
50 s32  igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
51 s32  igb_copper_link_setup_82580(struct e1000_hw *hw);
52 s32  igb_get_phy_info_82580(struct e1000_hw *hw);
53 s32  igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);
54 s32  igb_get_cable_length_82580(struct e1000_hw *hw);
55 s32  igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data);
56 s32  igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data);
57 s32  igb_check_polarity_m88(struct e1000_hw *hw);
58 
59 /* IGP01E1000 Specific Registers */
60 #define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
61 #define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
62 #define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
63 #define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
64 #define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
65 #define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
66 #define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
67 #define IGP01E1000_PHY_POLARITY_MASK      0x0078
68 #define IGP01E1000_PSCR_AUTO_MDIX         0x1000
69 #define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
70 #define IGP01E1000_PSCFR_SMART_SPEED      0x0080
71 
72 #define I82580_ADDR_REG                   16
73 #define I82580_CFG_REG                    22
74 #define I82580_CFG_ASSERT_CRS_ON_TX       BIT(15)
75 #define I82580_CFG_ENABLE_DOWNSHIFT       (3u << 10) /* auto downshift 100/10 */
76 #define I82580_CTRL_REG                   23
77 #define I82580_CTRL_DOWNSHIFT_MASK        (7u << 10)
78 
79 /* 82580 specific PHY registers */
80 #define I82580_PHY_CTRL_2            18
81 #define I82580_PHY_LBK_CTRL          19
82 #define I82580_PHY_STATUS_2          26
83 #define I82580_PHY_DIAG_STATUS       31
84 
85 /* I82580 PHY Status 2 */
86 #define I82580_PHY_STATUS2_REV_POLARITY   0x0400
87 #define I82580_PHY_STATUS2_MDIX           0x0800
88 #define I82580_PHY_STATUS2_SPEED_MASK     0x0300
89 #define I82580_PHY_STATUS2_SPEED_1000MBPS 0x0200
90 #define I82580_PHY_STATUS2_SPEED_100MBPS  0x0100
91 
92 /* I82580 PHY Control 2 */
93 #define I82580_PHY_CTRL2_MANUAL_MDIX      0x0200
94 #define I82580_PHY_CTRL2_AUTO_MDI_MDIX    0x0400
95 #define I82580_PHY_CTRL2_MDIX_CFG_MASK    0x0600
96 
97 /* I82580 PHY Diagnostics Status */
98 #define I82580_DSTATUS_CABLE_LENGTH       0x03FC
99 #define I82580_DSTATUS_CABLE_LENGTH_SHIFT 2
100 
101 /* 82580 PHY Power Management */
102 #define E1000_82580_PHY_POWER_MGMT	0xE14
103 #define E1000_82580_PM_SPD		0x0001 /* Smart Power Down */
104 #define E1000_82580_PM_D0_LPLU		0x0002 /* For D0a states */
105 #define E1000_82580_PM_D3_LPLU		0x0004 /* For all other states */
106 #define E1000_82580_PM_GO_LINKD		0x0020 /* Go Link Disconnect */
107 
108 /* Enable flexible speed on link-up */
109 #define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
110 #define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
111 #define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
112 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
113 #define IGP01E1000_PSSR_MDIX              0x0800
114 #define IGP01E1000_PSSR_SPEED_MASK        0xC000
115 #define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
116 #define IGP02E1000_PHY_CHANNEL_NUM        4
117 #define IGP02E1000_PHY_AGC_A              0x11B1
118 #define IGP02E1000_PHY_AGC_B              0x12B1
119 #define IGP02E1000_PHY_AGC_C              0x14B1
120 #define IGP02E1000_PHY_AGC_D              0x18B1
121 #define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
122 #define IGP02E1000_AGC_LENGTH_MASK        0x7F
123 #define IGP02E1000_AGC_RANGE              15
124 
125 #define E1000_CABLE_LENGTH_UNDEFINED      0xFF
126 
127 /* SFP modules ID memory locations */
128 #define E1000_SFF_IDENTIFIER_OFFSET	0x00
129 #define E1000_SFF_IDENTIFIER_SFF	0x02
130 #define E1000_SFF_IDENTIFIER_SFP	0x03
131 
132 #define E1000_SFF_ETH_FLAGS_OFFSET	0x06
133 /* Flags for SFP modules compatible with ETH up to 1Gb */
134 struct e1000_sfp_flags {
135 	u8 e1000_base_sx:1;
136 	u8 e1000_base_lx:1;
137 	u8 e1000_base_cx:1;
138 	u8 e1000_base_t:1;
139 	u8 e100_base_lx:1;
140 	u8 e100_base_fx:1;
141 	u8 e10_base_bx10:1;
142 	u8 e10_base_px:1;
143 };
144 
145 #endif
146