1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
3
4 #ifndef _IGC_H_
5 #define _IGC_H_
6
7 #include <linux/kobject.h>
8 #include <linux/pci.h>
9 #include <linux/netdevice.h>
10 #include <linux/vmalloc.h>
11 #include <linux/ethtool.h>
12 #include <linux/sctp.h>
13 #include <linux/ptp_clock_kernel.h>
14 #include <linux/timecounter.h>
15 #include <linux/net_tstamp.h>
16
17 #include "igc_hw.h"
18
19 void igc_ethtool_set_ops(struct net_device *);
20
21 /* Transmit and receive queues */
22 #define IGC_MAX_RX_QUEUES 4
23 #define IGC_MAX_TX_QUEUES 4
24
25 #define MAX_Q_VECTORS 8
26 #define MAX_STD_JUMBO_FRAME_SIZE 9216
27
28 #define MAX_ETYPE_FILTER 8
29 #define IGC_RETA_SIZE 128
30
31 /* SDP support */
32 #define IGC_N_EXTTS 2
33 #define IGC_N_PEROUT 2
34 #define IGC_N_SDP 4
35
36 enum igc_mac_filter_type {
37 IGC_MAC_FILTER_TYPE_DST = 0,
38 IGC_MAC_FILTER_TYPE_SRC
39 };
40
41 struct igc_tx_queue_stats {
42 u64 packets;
43 u64 bytes;
44 u64 restart_queue;
45 u64 restart_queue2;
46 };
47
48 struct igc_rx_queue_stats {
49 u64 packets;
50 u64 bytes;
51 u64 drops;
52 u64 csum_err;
53 u64 alloc_failed;
54 };
55
56 struct igc_rx_packet_stats {
57 u64 ipv4_packets; /* IPv4 headers processed */
58 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
59 u64 ipv6_packets; /* IPv6 headers processed */
60 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
61 u64 tcp_packets; /* TCP headers processed */
62 u64 udp_packets; /* UDP headers processed */
63 u64 sctp_packets; /* SCTP headers processed */
64 u64 nfs_packets; /* NFS headers processe */
65 u64 other_packets;
66 };
67
68 struct igc_ring_container {
69 struct igc_ring *ring; /* pointer to linked list of rings */
70 unsigned int total_bytes; /* total bytes processed this int */
71 unsigned int total_packets; /* total packets processed this int */
72 u16 work_limit; /* total work allowed per interrupt */
73 u8 count; /* total number of rings in vector */
74 u8 itr; /* current ITR setting for ring */
75 };
76
77 struct igc_ring {
78 struct igc_q_vector *q_vector; /* backlink to q_vector */
79 struct net_device *netdev; /* back pointer to net_device */
80 struct device *dev; /* device for dma mapping */
81 union { /* array of buffer info structs */
82 struct igc_tx_buffer *tx_buffer_info;
83 struct igc_rx_buffer *rx_buffer_info;
84 };
85 void *desc; /* descriptor ring memory */
86 unsigned long flags; /* ring specific flags */
87 void __iomem *tail; /* pointer to ring tail register */
88 dma_addr_t dma; /* phys address of the ring */
89 unsigned int size; /* length of desc. ring in bytes */
90
91 u16 count; /* number of desc. in the ring */
92 u8 queue_index; /* logical index of the ring*/
93 u8 reg_idx; /* physical index of the ring */
94 bool launchtime_enable; /* true if LaunchTime is enabled */
95
96 u32 start_time;
97 u32 end_time;
98
99 /* everything past this point are written often */
100 u16 next_to_clean;
101 u16 next_to_use;
102 u16 next_to_alloc;
103
104 union {
105 /* TX */
106 struct {
107 struct igc_tx_queue_stats tx_stats;
108 struct u64_stats_sync tx_syncp;
109 struct u64_stats_sync tx_syncp2;
110 };
111 /* RX */
112 struct {
113 struct igc_rx_queue_stats rx_stats;
114 struct igc_rx_packet_stats pkt_stats;
115 struct u64_stats_sync rx_syncp;
116 struct sk_buff *skb;
117 };
118 };
119
120 struct xdp_rxq_info xdp_rxq;
121 } ____cacheline_internodealigned_in_smp;
122
123 /* Board specific private data structure */
124 struct igc_adapter {
125 struct net_device *netdev;
126
127 struct ethtool_eee eee;
128 u16 eee_advert;
129
130 unsigned long state;
131 unsigned int flags;
132 unsigned int num_q_vectors;
133
134 struct msix_entry *msix_entries;
135
136 /* TX */
137 u16 tx_work_limit;
138 u32 tx_timeout_count;
139 int num_tx_queues;
140 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
141
142 /* RX */
143 int num_rx_queues;
144 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
145
146 struct timer_list watchdog_timer;
147 struct timer_list dma_err_timer;
148 struct timer_list phy_info_timer;
149
150 u32 wol;
151 u32 en_mng_pt;
152 u16 link_speed;
153 u16 link_duplex;
154
155 u8 port_num;
156
157 u8 __iomem *io_addr;
158 /* Interrupt Throttle Rate */
159 u32 rx_itr_setting;
160 u32 tx_itr_setting;
161
162 struct work_struct reset_task;
163 struct work_struct watchdog_task;
164 struct work_struct dma_err_task;
165 bool fc_autoneg;
166
167 u8 tx_timeout_factor;
168
169 int msg_enable;
170 u32 max_frame_size;
171 u32 min_frame_size;
172
173 ktime_t base_time;
174 ktime_t cycle_time;
175
176 /* OS defined structs */
177 struct pci_dev *pdev;
178 /* lock for statistics */
179 spinlock_t stats64_lock;
180 struct rtnl_link_stats64 stats64;
181
182 /* structs defined in igc_hw.h */
183 struct igc_hw hw;
184 struct igc_hw_stats stats;
185
186 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
187 u32 eims_enable_mask;
188 u32 eims_other;
189
190 u16 tx_ring_count;
191 u16 rx_ring_count;
192
193 u32 tx_hwtstamp_timeouts;
194 u32 tx_hwtstamp_skipped;
195 u32 rx_hwtstamp_cleared;
196
197 u32 rss_queues;
198 u32 rss_indir_tbl_init;
199
200 /* Any access to elements in nfc_rule_list is protected by the
201 * nfc_rule_lock.
202 */
203 struct mutex nfc_rule_lock;
204 struct list_head nfc_rule_list;
205 unsigned int nfc_rule_count;
206
207 u8 rss_indir_tbl[IGC_RETA_SIZE];
208
209 unsigned long link_check_timeout;
210 struct igc_info ei;
211
212 u32 test_icr;
213
214 struct ptp_clock *ptp_clock;
215 struct ptp_clock_info ptp_caps;
216 struct work_struct ptp_tx_work;
217 struct sk_buff *ptp_tx_skb;
218 struct hwtstamp_config tstamp_config;
219 unsigned long ptp_tx_start;
220 unsigned int ptp_flags;
221 /* System time value lock */
222 spinlock_t tmreg_lock;
223 struct cyclecounter cc;
224 struct timecounter tc;
225 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
226 ktime_t ptp_reset_start; /* Reset time in clock mono */
227
228 char fw_version[32];
229
230 struct bpf_prog *xdp_prog;
231
232 bool pps_sys_wrap_on;
233
234 struct ptp_pin_desc sdp_config[IGC_N_SDP];
235 struct {
236 struct timespec64 start;
237 struct timespec64 period;
238 } perout[IGC_N_PEROUT];
239 };
240
241 void igc_up(struct igc_adapter *adapter);
242 void igc_down(struct igc_adapter *adapter);
243 int igc_open(struct net_device *netdev);
244 int igc_close(struct net_device *netdev);
245 int igc_setup_tx_resources(struct igc_ring *ring);
246 int igc_setup_rx_resources(struct igc_ring *ring);
247 void igc_free_tx_resources(struct igc_ring *ring);
248 void igc_free_rx_resources(struct igc_ring *ring);
249 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
250 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
251 const u32 max_rss_queues);
252 int igc_reinit_queues(struct igc_adapter *adapter);
253 void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
254 bool igc_has_link(struct igc_adapter *adapter);
255 void igc_reset(struct igc_adapter *adapter);
256 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx);
257 void igc_update_stats(struct igc_adapter *adapter);
258
259 /* igc_dump declarations */
260 void igc_rings_dump(struct igc_adapter *adapter);
261 void igc_regs_dump(struct igc_adapter *adapter);
262
263 extern char igc_driver_name[];
264
265 #define IGC_REGS_LEN 740
266
267 /* flags controlling PTP/1588 function */
268 #define IGC_PTP_ENABLED BIT(0)
269
270 /* Flags definitions */
271 #define IGC_FLAG_HAS_MSI BIT(0)
272 #define IGC_FLAG_QUEUE_PAIRS BIT(3)
273 #define IGC_FLAG_DMAC BIT(4)
274 #define IGC_FLAG_PTP BIT(8)
275 #define IGC_FLAG_WOL_SUPPORTED BIT(8)
276 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
277 #define IGC_FLAG_MEDIA_RESET BIT(10)
278 #define IGC_FLAG_MAS_ENABLE BIT(12)
279 #define IGC_FLAG_HAS_MSIX BIT(13)
280 #define IGC_FLAG_EEE BIT(14)
281 #define IGC_FLAG_VLAN_PROMISC BIT(15)
282 #define IGC_FLAG_RX_LEGACY BIT(16)
283 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
284
285 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
286 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
287
288 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
289 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
290 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
291
292 /* Interrupt defines */
293 #define IGC_START_ITR 648 /* ~6000 ints/sec */
294 #define IGC_4K_ITR 980
295 #define IGC_20K_ITR 196
296 #define IGC_70K_ITR 56
297
298 #define IGC_DEFAULT_ITR 3 /* dynamic */
299 #define IGC_MAX_ITR_USECS 10000
300 #define IGC_MIN_ITR_USECS 10
301 #define NON_Q_VECTORS 1
302 #define MAX_MSIX_ENTRIES 10
303
304 /* TX/RX descriptor defines */
305 #define IGC_DEFAULT_TXD 256
306 #define IGC_DEFAULT_TX_WORK 128
307 #define IGC_MIN_TXD 80
308 #define IGC_MAX_TXD 4096
309
310 #define IGC_DEFAULT_RXD 256
311 #define IGC_MIN_RXD 80
312 #define IGC_MAX_RXD 4096
313
314 /* Supported Rx Buffer Sizes */
315 #define IGC_RXBUFFER_256 256
316 #define IGC_RXBUFFER_2048 2048
317 #define IGC_RXBUFFER_3072 3072
318
319 #define AUTO_ALL_MODES 0
320 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256
321
322 /* Transmit and receive latency (for PTP timestamps) */
323 #define IGC_I225_TX_LATENCY_10 240
324 #define IGC_I225_TX_LATENCY_100 58
325 #define IGC_I225_TX_LATENCY_1000 80
326 #define IGC_I225_TX_LATENCY_2500 1325
327 #define IGC_I225_RX_LATENCY_10 6450
328 #define IGC_I225_RX_LATENCY_100 185
329 #define IGC_I225_RX_LATENCY_1000 300
330 #define IGC_I225_RX_LATENCY_2500 1485
331
332 /* RX and TX descriptor control thresholds.
333 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
334 * descriptors available in its onboard memory.
335 * Setting this to 0 disables RX descriptor prefetch.
336 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
337 * available in host memory.
338 * If PTHRESH is 0, this should also be 0.
339 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
340 * descriptors until either it has this many to write back, or the
341 * ITR timer expires.
342 */
343 #define IGC_RX_PTHRESH 8
344 #define IGC_RX_HTHRESH 8
345 #define IGC_TX_PTHRESH 8
346 #define IGC_TX_HTHRESH 1
347 #define IGC_RX_WTHRESH 4
348 #define IGC_TX_WTHRESH 16
349
350 #define IGC_RX_DMA_ATTR \
351 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
352
353 #define IGC_TS_HDR_LEN 16
354
355 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
356
357 #if (PAGE_SIZE < 8192)
358 #define IGC_MAX_FRAME_BUILD_SKB \
359 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
360 #else
361 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
362 #endif
363
364 /* How many Rx Buffers do we bundle into one write to the hardware ? */
365 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
366
367 /* VLAN info */
368 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
369
370 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */
igc_test_staterr(union igc_adv_rx_desc * rx_desc,const u32 stat_err_bits)371 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
372 const u32 stat_err_bits)
373 {
374 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
375 }
376
377 enum igc_state_t {
378 __IGC_TESTING,
379 __IGC_RESETTING,
380 __IGC_DOWN,
381 __IGC_PTP_TX_IN_PROGRESS,
382 };
383
384 enum igc_tx_flags {
385 /* cmd_type flags */
386 IGC_TX_FLAGS_VLAN = 0x01,
387 IGC_TX_FLAGS_TSO = 0x02,
388 IGC_TX_FLAGS_TSTAMP = 0x04,
389
390 /* olinfo flags */
391 IGC_TX_FLAGS_IPV4 = 0x10,
392 IGC_TX_FLAGS_CSUM = 0x20,
393
394 IGC_TX_FLAGS_XDP = 0x100,
395 };
396
397 enum igc_boards {
398 board_base,
399 };
400
401 /* The largest size we can write to the descriptor is 65535. In order to
402 * maintain a power of two alignment we have to limit ourselves to 32K.
403 */
404 #define IGC_MAX_TXD_PWR 15
405 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
406
407 /* Tx Descriptors needed, worst case */
408 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
409 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
410
411 /* wrapper around a pointer to a socket buffer,
412 * so a DMA handle can be stored along with the buffer
413 */
414 struct igc_tx_buffer {
415 union igc_adv_tx_desc *next_to_watch;
416 unsigned long time_stamp;
417 union {
418 struct sk_buff *skb;
419 struct xdp_frame *xdpf;
420 };
421 unsigned int bytecount;
422 u16 gso_segs;
423 __be16 protocol;
424
425 DEFINE_DMA_UNMAP_ADDR(dma);
426 DEFINE_DMA_UNMAP_LEN(len);
427 u32 tx_flags;
428 };
429
430 struct igc_rx_buffer {
431 dma_addr_t dma;
432 struct page *page;
433 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
434 __u32 page_offset;
435 #else
436 __u16 page_offset;
437 #endif
438 __u16 pagecnt_bias;
439 };
440
441 struct igc_q_vector {
442 struct igc_adapter *adapter; /* backlink */
443 void __iomem *itr_register;
444 u32 eims_value; /* EIMS mask value */
445
446 u16 itr_val;
447 u8 set_itr;
448
449 struct igc_ring_container rx, tx;
450
451 struct napi_struct napi;
452
453 struct rcu_head rcu; /* to avoid race with update stats on free */
454 char name[IFNAMSIZ + 9];
455 struct net_device poll_dev;
456
457 /* for dynamic allocation of rings associated with this q_vector */
458 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
459 };
460
461 enum igc_filter_match_flags {
462 IGC_FILTER_FLAG_ETHER_TYPE = 0x1,
463 IGC_FILTER_FLAG_VLAN_TCI = 0x2,
464 IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4,
465 IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8,
466 };
467
468 struct igc_nfc_filter {
469 u8 match_flags;
470 u16 etype;
471 u16 vlan_tci;
472 u8 src_addr[ETH_ALEN];
473 u8 dst_addr[ETH_ALEN];
474 };
475
476 struct igc_nfc_rule {
477 struct list_head list;
478 struct igc_nfc_filter filter;
479 u32 location;
480 u16 action;
481 };
482
483 /* IGC supports a total of 32 NFC rules: 16 MAC address based,, 8 VLAN priority
484 * based, and 8 ethertype based.
485 */
486 #define IGC_MAX_RXNFC_RULES 32
487
488 /* igc_desc_unused - calculate if we have unused descriptors */
igc_desc_unused(const struct igc_ring * ring)489 static inline u16 igc_desc_unused(const struct igc_ring *ring)
490 {
491 u16 ntc = ring->next_to_clean;
492 u16 ntu = ring->next_to_use;
493
494 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
495 }
496
igc_get_phy_info(struct igc_hw * hw)497 static inline s32 igc_get_phy_info(struct igc_hw *hw)
498 {
499 if (hw->phy.ops.get_phy_info)
500 return hw->phy.ops.get_phy_info(hw);
501
502 return 0;
503 }
504
igc_reset_phy(struct igc_hw * hw)505 static inline s32 igc_reset_phy(struct igc_hw *hw)
506 {
507 if (hw->phy.ops.reset)
508 return hw->phy.ops.reset(hw);
509
510 return 0;
511 }
512
txring_txq(const struct igc_ring * tx_ring)513 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
514 {
515 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
516 }
517
518 enum igc_ring_flags_t {
519 IGC_RING_FLAG_RX_3K_BUFFER,
520 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
521 IGC_RING_FLAG_RX_SCTP_CSUM,
522 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
523 IGC_RING_FLAG_TX_CTX_IDX,
524 IGC_RING_FLAG_TX_DETECT_HANG
525 };
526
527 #define ring_uses_large_buffer(ring) \
528 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
529 #define set_ring_uses_large_buffer(ring) \
530 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
531 #define clear_ring_uses_large_buffer(ring) \
532 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
533
534 #define ring_uses_build_skb(ring) \
535 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
536
igc_rx_bufsz(struct igc_ring * ring)537 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
538 {
539 #if (PAGE_SIZE < 8192)
540 if (ring_uses_large_buffer(ring))
541 return IGC_RXBUFFER_3072;
542
543 if (ring_uses_build_skb(ring))
544 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
545 #endif
546 return IGC_RXBUFFER_2048;
547 }
548
igc_rx_pg_order(struct igc_ring * ring)549 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
550 {
551 #if (PAGE_SIZE < 8192)
552 if (ring_uses_large_buffer(ring))
553 return 1;
554 #endif
555 return 0;
556 }
557
igc_read_phy_reg(struct igc_hw * hw,u32 offset,u16 * data)558 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
559 {
560 if (hw->phy.ops.read_reg)
561 return hw->phy.ops.read_reg(hw, offset, data);
562
563 return 0;
564 }
565
566 void igc_reinit_locked(struct igc_adapter *);
567 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
568 u32 location);
569 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
570 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
571
572 void igc_ptp_init(struct igc_adapter *adapter);
573 void igc_ptp_reset(struct igc_adapter *adapter);
574 void igc_ptp_suspend(struct igc_adapter *adapter);
575 void igc_ptp_stop(struct igc_adapter *adapter);
576 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
577 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
578 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
579 void igc_ptp_tx_hang(struct igc_adapter *adapter);
580 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
581
582 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
583
584 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
585
586 #define IGC_RX_DESC(R, i) \
587 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
588 #define IGC_TX_DESC(R, i) \
589 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
590 #define IGC_TX_CTXTDESC(R, i) \
591 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
592
593 #endif /* _IGC_H_ */
594