1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas Ethernet AVB device driver
3 *
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7 *
8 * Based on the SuperH Ethernet driver
9 */
10
11 #include <linux/cache.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_vlan.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/net_tstamp.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_mdio.h>
27 #include <linux/of_net.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/sys_soc.h>
32
33 #include <asm/div64.h>
34
35 #include "ravb.h"
36
37 #define RAVB_DEF_MSG_ENABLE \
38 (NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_RX_ERR | \
41 NETIF_MSG_TX_ERR)
42
43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
44 "ch0", /* RAVB_BE */
45 "ch1", /* RAVB_NC */
46 };
47
48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
49 "ch18", /* RAVB_BE */
50 "ch19", /* RAVB_NC */
51 };
52
ravb_modify(struct net_device * ndev,enum ravb_reg reg,u32 clear,u32 set)53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
54 u32 set)
55 {
56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
57 }
58
ravb_wait(struct net_device * ndev,enum ravb_reg reg,u32 mask,u32 value)59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
60 {
61 int i;
62
63 for (i = 0; i < 10000; i++) {
64 if ((ravb_read(ndev, reg) & mask) == value)
65 return 0;
66 udelay(10);
67 }
68 return -ETIMEDOUT;
69 }
70
ravb_config(struct net_device * ndev)71 static int ravb_config(struct net_device *ndev)
72 {
73 int error;
74
75 /* Set config mode */
76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
77 /* Check if the operating mode is changed to the config mode */
78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
79 if (error)
80 netdev_err(ndev, "failed to switch device to config mode\n");
81
82 return error;
83 }
84
ravb_set_rate(struct net_device * ndev)85 static void ravb_set_rate(struct net_device *ndev)
86 {
87 struct ravb_private *priv = netdev_priv(ndev);
88
89 switch (priv->speed) {
90 case 100: /* 100BASE */
91 ravb_write(ndev, GECMR_SPEED_100, GECMR);
92 break;
93 case 1000: /* 1000BASE */
94 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
95 break;
96 }
97 }
98
ravb_set_buffer_align(struct sk_buff * skb)99 static void ravb_set_buffer_align(struct sk_buff *skb)
100 {
101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
102
103 if (reserve)
104 skb_reserve(skb, RAVB_ALIGN - reserve);
105 }
106
107 /* Get MAC address from the MAC address registers
108 *
109 * Ethernet AVB device doesn't have ROM for MAC address.
110 * This function gets the MAC address that was used by a bootloader.
111 */
ravb_read_mac_address(struct device_node * np,struct net_device * ndev)112 static void ravb_read_mac_address(struct device_node *np,
113 struct net_device *ndev)
114 {
115 int ret;
116
117 ret = of_get_mac_address(np, ndev->dev_addr);
118 if (ret) {
119 u32 mahr = ravb_read(ndev, MAHR);
120 u32 malr = ravb_read(ndev, MALR);
121
122 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
123 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
124 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
125 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
126 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
127 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
128 }
129 }
130
ravb_mdio_ctrl(struct mdiobb_ctrl * ctrl,u32 mask,int set)131 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
132 {
133 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
134 mdiobb);
135
136 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
137 }
138
139 /* MDC pin control */
ravb_set_mdc(struct mdiobb_ctrl * ctrl,int level)140 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
141 {
142 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
143 }
144
145 /* Data I/O pin control */
ravb_set_mdio_dir(struct mdiobb_ctrl * ctrl,int output)146 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
147 {
148 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
149 }
150
151 /* Set data bit */
ravb_set_mdio_data(struct mdiobb_ctrl * ctrl,int value)152 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
153 {
154 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
155 }
156
157 /* Get data bit */
ravb_get_mdio_data(struct mdiobb_ctrl * ctrl)158 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
159 {
160 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
161 mdiobb);
162
163 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
164 }
165
166 /* MDIO bus control struct */
167 static const struct mdiobb_ops bb_ops = {
168 .owner = THIS_MODULE,
169 .set_mdc = ravb_set_mdc,
170 .set_mdio_dir = ravb_set_mdio_dir,
171 .set_mdio_data = ravb_set_mdio_data,
172 .get_mdio_data = ravb_get_mdio_data,
173 };
174
175 /* Free TX skb function for AVB-IP */
ravb_tx_free(struct net_device * ndev,int q,bool free_txed_only)176 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
177 {
178 struct ravb_private *priv = netdev_priv(ndev);
179 struct net_device_stats *stats = &priv->stats[q];
180 int num_tx_desc = priv->num_tx_desc;
181 struct ravb_tx_desc *desc;
182 int free_num = 0;
183 int entry;
184 u32 size;
185
186 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
187 bool txed;
188
189 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
190 num_tx_desc);
191 desc = &priv->tx_ring[q][entry];
192 txed = desc->die_dt == DT_FEMPTY;
193 if (free_txed_only && !txed)
194 break;
195 /* Descriptor type must be checked before all other reads */
196 dma_rmb();
197 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
198 /* Free the original skb. */
199 if (priv->tx_skb[q][entry / num_tx_desc]) {
200 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
201 size, DMA_TO_DEVICE);
202 /* Last packet descriptor? */
203 if (entry % num_tx_desc == num_tx_desc - 1) {
204 entry /= num_tx_desc;
205 dev_kfree_skb_any(priv->tx_skb[q][entry]);
206 priv->tx_skb[q][entry] = NULL;
207 if (txed)
208 stats->tx_packets++;
209 }
210 free_num++;
211 }
212 if (txed)
213 stats->tx_bytes += size;
214 desc->die_dt = DT_EEMPTY;
215 }
216 return free_num;
217 }
218
219 /* Free skb's and DMA buffers for Ethernet AVB */
ravb_ring_free(struct net_device * ndev,int q)220 static void ravb_ring_free(struct net_device *ndev, int q)
221 {
222 struct ravb_private *priv = netdev_priv(ndev);
223 int num_tx_desc = priv->num_tx_desc;
224 int ring_size;
225 int i;
226
227 if (priv->rx_ring[q]) {
228 for (i = 0; i < priv->num_rx_ring[q]; i++) {
229 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
230
231 if (!dma_mapping_error(ndev->dev.parent,
232 le32_to_cpu(desc->dptr)))
233 dma_unmap_single(ndev->dev.parent,
234 le32_to_cpu(desc->dptr),
235 RX_BUF_SZ,
236 DMA_FROM_DEVICE);
237 }
238 ring_size = sizeof(struct ravb_ex_rx_desc) *
239 (priv->num_rx_ring[q] + 1);
240 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
241 priv->rx_desc_dma[q]);
242 priv->rx_ring[q] = NULL;
243 }
244
245 if (priv->tx_ring[q]) {
246 ravb_tx_free(ndev, q, false);
247
248 ring_size = sizeof(struct ravb_tx_desc) *
249 (priv->num_tx_ring[q] * num_tx_desc + 1);
250 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
251 priv->tx_desc_dma[q]);
252 priv->tx_ring[q] = NULL;
253 }
254
255 /* Free RX skb ringbuffer */
256 if (priv->rx_skb[q]) {
257 for (i = 0; i < priv->num_rx_ring[q]; i++)
258 dev_kfree_skb(priv->rx_skb[q][i]);
259 }
260 kfree(priv->rx_skb[q]);
261 priv->rx_skb[q] = NULL;
262
263 /* Free aligned TX buffers */
264 kfree(priv->tx_align[q]);
265 priv->tx_align[q] = NULL;
266
267 /* Free TX skb ringbuffer.
268 * SKBs are freed by ravb_tx_free() call above.
269 */
270 kfree(priv->tx_skb[q]);
271 priv->tx_skb[q] = NULL;
272 }
273
274 /* Format skb and descriptor buffer for Ethernet AVB */
ravb_ring_format(struct net_device * ndev,int q)275 static void ravb_ring_format(struct net_device *ndev, int q)
276 {
277 struct ravb_private *priv = netdev_priv(ndev);
278 int num_tx_desc = priv->num_tx_desc;
279 struct ravb_ex_rx_desc *rx_desc;
280 struct ravb_tx_desc *tx_desc;
281 struct ravb_desc *desc;
282 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
283 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
284 num_tx_desc;
285 dma_addr_t dma_addr;
286 int i;
287
288 priv->cur_rx[q] = 0;
289 priv->cur_tx[q] = 0;
290 priv->dirty_rx[q] = 0;
291 priv->dirty_tx[q] = 0;
292
293 memset(priv->rx_ring[q], 0, rx_ring_size);
294 /* Build RX ring buffer */
295 for (i = 0; i < priv->num_rx_ring[q]; i++) {
296 /* RX descriptor */
297 rx_desc = &priv->rx_ring[q][i];
298 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
299 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
300 RX_BUF_SZ,
301 DMA_FROM_DEVICE);
302 /* We just set the data size to 0 for a failed mapping which
303 * should prevent DMA from happening...
304 */
305 if (dma_mapping_error(ndev->dev.parent, dma_addr))
306 rx_desc->ds_cc = cpu_to_le16(0);
307 rx_desc->dptr = cpu_to_le32(dma_addr);
308 rx_desc->die_dt = DT_FEMPTY;
309 }
310 rx_desc = &priv->rx_ring[q][i];
311 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
312 rx_desc->die_dt = DT_LINKFIX; /* type */
313
314 memset(priv->tx_ring[q], 0, tx_ring_size);
315 /* Build TX ring buffer */
316 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
317 i++, tx_desc++) {
318 tx_desc->die_dt = DT_EEMPTY;
319 if (num_tx_desc > 1) {
320 tx_desc++;
321 tx_desc->die_dt = DT_EEMPTY;
322 }
323 }
324 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
325 tx_desc->die_dt = DT_LINKFIX; /* type */
326
327 /* RX descriptor base address for best effort */
328 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
329 desc->die_dt = DT_LINKFIX; /* type */
330 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
331
332 /* TX descriptor base address for best effort */
333 desc = &priv->desc_bat[q];
334 desc->die_dt = DT_LINKFIX; /* type */
335 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
336 }
337
338 /* Init skb and descriptor buffer for Ethernet AVB */
ravb_ring_init(struct net_device * ndev,int q)339 static int ravb_ring_init(struct net_device *ndev, int q)
340 {
341 struct ravb_private *priv = netdev_priv(ndev);
342 int num_tx_desc = priv->num_tx_desc;
343 struct sk_buff *skb;
344 int ring_size;
345 int i;
346
347 /* Allocate RX and TX skb rings */
348 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
349 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
350 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
351 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
352 if (!priv->rx_skb[q] || !priv->tx_skb[q])
353 goto error;
354
355 for (i = 0; i < priv->num_rx_ring[q]; i++) {
356 skb = netdev_alloc_skb(ndev, RX_BUF_SZ + RAVB_ALIGN - 1);
357 if (!skb)
358 goto error;
359 ravb_set_buffer_align(skb);
360 priv->rx_skb[q][i] = skb;
361 }
362
363 if (num_tx_desc > 1) {
364 /* Allocate rings for the aligned buffers */
365 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
366 DPTR_ALIGN - 1, GFP_KERNEL);
367 if (!priv->tx_align[q])
368 goto error;
369 }
370
371 /* Allocate all RX descriptors. */
372 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
373 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
374 &priv->rx_desc_dma[q],
375 GFP_KERNEL);
376 if (!priv->rx_ring[q])
377 goto error;
378
379 priv->dirty_rx[q] = 0;
380
381 /* Allocate all TX descriptors. */
382 ring_size = sizeof(struct ravb_tx_desc) *
383 (priv->num_tx_ring[q] * num_tx_desc + 1);
384 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
385 &priv->tx_desc_dma[q],
386 GFP_KERNEL);
387 if (!priv->tx_ring[q])
388 goto error;
389
390 return 0;
391
392 error:
393 ravb_ring_free(ndev, q);
394
395 return -ENOMEM;
396 }
397
398 /* E-MAC init function */
ravb_emac_init(struct net_device * ndev)399 static void ravb_emac_init(struct net_device *ndev)
400 {
401 /* Receive frame limit set register */
402 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
403
404 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
405 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
406 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
407 ECMR_TE | ECMR_RE, ECMR);
408
409 ravb_set_rate(ndev);
410
411 /* Set MAC address */
412 ravb_write(ndev,
413 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
414 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
415 ravb_write(ndev,
416 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
417
418 /* E-MAC status register clear */
419 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
420
421 /* E-MAC interrupt enable register */
422 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
423 }
424
425 /* Device init function for Ethernet AVB */
ravb_dmac_init(struct net_device * ndev)426 static int ravb_dmac_init(struct net_device *ndev)
427 {
428 struct ravb_private *priv = netdev_priv(ndev);
429 int error;
430
431 /* Set CONFIG mode */
432 error = ravb_config(ndev);
433 if (error)
434 return error;
435
436 error = ravb_ring_init(ndev, RAVB_BE);
437 if (error)
438 return error;
439 error = ravb_ring_init(ndev, RAVB_NC);
440 if (error) {
441 ravb_ring_free(ndev, RAVB_BE);
442 return error;
443 }
444
445 /* Descriptor format */
446 ravb_ring_format(ndev, RAVB_BE);
447 ravb_ring_format(ndev, RAVB_NC);
448
449 /* Set AVB RX */
450 ravb_write(ndev,
451 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
452
453 /* Set FIFO size */
454 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
455
456 /* Timestamp enable */
457 ravb_write(ndev, TCCR_TFEN, TCCR);
458
459 /* Interrupt init: */
460 if (priv->chip_id == RCAR_GEN3) {
461 /* Clear DIL.DPLx */
462 ravb_write(ndev, 0, DIL);
463 /* Set queue specific interrupt */
464 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
465 }
466 /* Frame receive */
467 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
468 /* Disable FIFO full warning */
469 ravb_write(ndev, 0, RIC1);
470 /* Receive FIFO full error, descriptor empty */
471 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
472 /* Frame transmitted, timestamp FIFO updated */
473 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
474
475 /* Setting the control will start the AVB-DMAC process. */
476 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
477
478 return 0;
479 }
480
ravb_get_tx_tstamp(struct net_device * ndev)481 static void ravb_get_tx_tstamp(struct net_device *ndev)
482 {
483 struct ravb_private *priv = netdev_priv(ndev);
484 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
485 struct skb_shared_hwtstamps shhwtstamps;
486 struct sk_buff *skb;
487 struct timespec64 ts;
488 u16 tag, tfa_tag;
489 int count;
490 u32 tfa2;
491
492 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
493 while (count--) {
494 tfa2 = ravb_read(ndev, TFA2);
495 tfa_tag = (tfa2 & TFA2_TST) >> 16;
496 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
497 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
498 ravb_read(ndev, TFA1);
499 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
500 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
501 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
502 list) {
503 skb = ts_skb->skb;
504 tag = ts_skb->tag;
505 list_del(&ts_skb->list);
506 kfree(ts_skb);
507 if (tag == tfa_tag) {
508 skb_tstamp_tx(skb, &shhwtstamps);
509 dev_consume_skb_any(skb);
510 break;
511 } else {
512 dev_kfree_skb_any(skb);
513 }
514 }
515 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
516 }
517 }
518
ravb_rx_csum(struct sk_buff * skb)519 static void ravb_rx_csum(struct sk_buff *skb)
520 {
521 u8 *hw_csum;
522
523 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
524 * appended to packet data
525 */
526 if (unlikely(skb->len < sizeof(__sum16)))
527 return;
528 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
529 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
530 skb->ip_summed = CHECKSUM_COMPLETE;
531 skb_trim(skb, skb->len - sizeof(__sum16));
532 }
533
534 /* Packet receive function for Ethernet AVB */
ravb_rx(struct net_device * ndev,int * quota,int q)535 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
536 {
537 struct ravb_private *priv = netdev_priv(ndev);
538 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
539 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
540 priv->cur_rx[q];
541 struct net_device_stats *stats = &priv->stats[q];
542 struct ravb_ex_rx_desc *desc;
543 struct sk_buff *skb;
544 dma_addr_t dma_addr;
545 struct timespec64 ts;
546 u8 desc_status;
547 u16 pkt_len;
548 int limit;
549
550 boguscnt = min(boguscnt, *quota);
551 limit = boguscnt;
552 desc = &priv->rx_ring[q][entry];
553 while (desc->die_dt != DT_FEMPTY) {
554 /* Descriptor type must be checked before all other reads */
555 dma_rmb();
556 desc_status = desc->msc;
557 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
558
559 if (--boguscnt < 0)
560 break;
561
562 /* We use 0-byte descriptors to mark the DMA mapping errors */
563 if (!pkt_len)
564 continue;
565
566 if (desc_status & MSC_MC)
567 stats->multicast++;
568
569 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
570 MSC_CEEF)) {
571 stats->rx_errors++;
572 if (desc_status & MSC_CRC)
573 stats->rx_crc_errors++;
574 if (desc_status & MSC_RFE)
575 stats->rx_frame_errors++;
576 if (desc_status & (MSC_RTLF | MSC_RTSF))
577 stats->rx_length_errors++;
578 if (desc_status & MSC_CEEF)
579 stats->rx_missed_errors++;
580 } else {
581 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
582
583 skb = priv->rx_skb[q][entry];
584 priv->rx_skb[q][entry] = NULL;
585 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
586 RX_BUF_SZ,
587 DMA_FROM_DEVICE);
588 get_ts &= (q == RAVB_NC) ?
589 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
590 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
591 if (get_ts) {
592 struct skb_shared_hwtstamps *shhwtstamps;
593
594 shhwtstamps = skb_hwtstamps(skb);
595 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
596 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
597 32) | le32_to_cpu(desc->ts_sl);
598 ts.tv_nsec = le32_to_cpu(desc->ts_n);
599 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
600 }
601
602 skb_put(skb, pkt_len);
603 skb->protocol = eth_type_trans(skb, ndev);
604 if (ndev->features & NETIF_F_RXCSUM)
605 ravb_rx_csum(skb);
606 napi_gro_receive(&priv->napi[q], skb);
607 stats->rx_packets++;
608 stats->rx_bytes += pkt_len;
609 }
610
611 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
612 desc = &priv->rx_ring[q][entry];
613 }
614
615 /* Refill the RX ring buffers. */
616 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
617 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
618 desc = &priv->rx_ring[q][entry];
619 desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
620
621 if (!priv->rx_skb[q][entry]) {
622 skb = netdev_alloc_skb(ndev,
623 RX_BUF_SZ +
624 RAVB_ALIGN - 1);
625 if (!skb)
626 break; /* Better luck next round. */
627 ravb_set_buffer_align(skb);
628 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
629 le16_to_cpu(desc->ds_cc),
630 DMA_FROM_DEVICE);
631 skb_checksum_none_assert(skb);
632 /* We just set the data size to 0 for a failed mapping
633 * which should prevent DMA from happening...
634 */
635 if (dma_mapping_error(ndev->dev.parent, dma_addr))
636 desc->ds_cc = cpu_to_le16(0);
637 desc->dptr = cpu_to_le32(dma_addr);
638 priv->rx_skb[q][entry] = skb;
639 }
640 /* Descriptor type must be set after all the above writes */
641 dma_wmb();
642 desc->die_dt = DT_FEMPTY;
643 }
644
645 *quota -= limit - (++boguscnt);
646
647 return boguscnt <= 0;
648 }
649
ravb_rcv_snd_disable(struct net_device * ndev)650 static void ravb_rcv_snd_disable(struct net_device *ndev)
651 {
652 /* Disable TX and RX */
653 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
654 }
655
ravb_rcv_snd_enable(struct net_device * ndev)656 static void ravb_rcv_snd_enable(struct net_device *ndev)
657 {
658 /* Enable TX and RX */
659 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
660 }
661
662 /* function for waiting dma process finished */
ravb_stop_dma(struct net_device * ndev)663 static int ravb_stop_dma(struct net_device *ndev)
664 {
665 int error;
666
667 /* Wait for stopping the hardware TX process */
668 error = ravb_wait(ndev, TCCR,
669 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
670 if (error)
671 return error;
672
673 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
674 0);
675 if (error)
676 return error;
677
678 /* Stop the E-MAC's RX/TX processes. */
679 ravb_rcv_snd_disable(ndev);
680
681 /* Wait for stopping the RX DMA process */
682 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
683 if (error)
684 return error;
685
686 /* Stop AVB-DMAC process */
687 return ravb_config(ndev);
688 }
689
690 /* E-MAC interrupt handler */
ravb_emac_interrupt_unlocked(struct net_device * ndev)691 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
692 {
693 struct ravb_private *priv = netdev_priv(ndev);
694 u32 ecsr, psr;
695
696 ecsr = ravb_read(ndev, ECSR);
697 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
698
699 if (ecsr & ECSR_MPD)
700 pm_wakeup_event(&priv->pdev->dev, 0);
701 if (ecsr & ECSR_ICD)
702 ndev->stats.tx_carrier_errors++;
703 if (ecsr & ECSR_LCHNG) {
704 /* Link changed */
705 if (priv->no_avb_link)
706 return;
707 psr = ravb_read(ndev, PSR);
708 if (priv->avb_link_active_low)
709 psr ^= PSR_LMON;
710 if (!(psr & PSR_LMON)) {
711 /* DIsable RX and TX */
712 ravb_rcv_snd_disable(ndev);
713 } else {
714 /* Enable RX and TX */
715 ravb_rcv_snd_enable(ndev);
716 }
717 }
718 }
719
ravb_emac_interrupt(int irq,void * dev_id)720 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
721 {
722 struct net_device *ndev = dev_id;
723 struct ravb_private *priv = netdev_priv(ndev);
724
725 spin_lock(&priv->lock);
726 ravb_emac_interrupt_unlocked(ndev);
727 spin_unlock(&priv->lock);
728 return IRQ_HANDLED;
729 }
730
731 /* Error interrupt handler */
ravb_error_interrupt(struct net_device * ndev)732 static void ravb_error_interrupt(struct net_device *ndev)
733 {
734 struct ravb_private *priv = netdev_priv(ndev);
735 u32 eis, ris2;
736
737 eis = ravb_read(ndev, EIS);
738 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
739 if (eis & EIS_QFS) {
740 ris2 = ravb_read(ndev, RIS2);
741 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED),
742 RIS2);
743
744 /* Receive Descriptor Empty int */
745 if (ris2 & RIS2_QFF0)
746 priv->stats[RAVB_BE].rx_over_errors++;
747
748 /* Receive Descriptor Empty int */
749 if (ris2 & RIS2_QFF1)
750 priv->stats[RAVB_NC].rx_over_errors++;
751
752 /* Receive FIFO Overflow int */
753 if (ris2 & RIS2_RFFF)
754 priv->rx_fifo_errors++;
755 }
756 }
757
ravb_queue_interrupt(struct net_device * ndev,int q)758 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
759 {
760 struct ravb_private *priv = netdev_priv(ndev);
761 u32 ris0 = ravb_read(ndev, RIS0);
762 u32 ric0 = ravb_read(ndev, RIC0);
763 u32 tis = ravb_read(ndev, TIS);
764 u32 tic = ravb_read(ndev, TIC);
765
766 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
767 if (napi_schedule_prep(&priv->napi[q])) {
768 /* Mask RX and TX interrupts */
769 if (priv->chip_id == RCAR_GEN2) {
770 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
771 ravb_write(ndev, tic & ~BIT(q), TIC);
772 } else {
773 ravb_write(ndev, BIT(q), RID0);
774 ravb_write(ndev, BIT(q), TID);
775 }
776 __napi_schedule(&priv->napi[q]);
777 } else {
778 netdev_warn(ndev,
779 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
780 ris0, ric0);
781 netdev_warn(ndev,
782 " tx status 0x%08x, tx mask 0x%08x.\n",
783 tis, tic);
784 }
785 return true;
786 }
787 return false;
788 }
789
ravb_timestamp_interrupt(struct net_device * ndev)790 static bool ravb_timestamp_interrupt(struct net_device *ndev)
791 {
792 u32 tis = ravb_read(ndev, TIS);
793
794 if (tis & TIS_TFUF) {
795 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
796 ravb_get_tx_tstamp(ndev);
797 return true;
798 }
799 return false;
800 }
801
ravb_interrupt(int irq,void * dev_id)802 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
803 {
804 struct net_device *ndev = dev_id;
805 struct ravb_private *priv = netdev_priv(ndev);
806 irqreturn_t result = IRQ_NONE;
807 u32 iss;
808
809 spin_lock(&priv->lock);
810 /* Get interrupt status */
811 iss = ravb_read(ndev, ISS);
812
813 /* Received and transmitted interrupts */
814 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
815 int q;
816
817 /* Timestamp updated */
818 if (ravb_timestamp_interrupt(ndev))
819 result = IRQ_HANDLED;
820
821 /* Network control and best effort queue RX/TX */
822 for (q = RAVB_NC; q >= RAVB_BE; q--) {
823 if (ravb_queue_interrupt(ndev, q))
824 result = IRQ_HANDLED;
825 }
826 }
827
828 /* E-MAC status summary */
829 if (iss & ISS_MS) {
830 ravb_emac_interrupt_unlocked(ndev);
831 result = IRQ_HANDLED;
832 }
833
834 /* Error status summary */
835 if (iss & ISS_ES) {
836 ravb_error_interrupt(ndev);
837 result = IRQ_HANDLED;
838 }
839
840 /* gPTP interrupt status summary */
841 if (iss & ISS_CGIS) {
842 ravb_ptp_interrupt(ndev);
843 result = IRQ_HANDLED;
844 }
845
846 spin_unlock(&priv->lock);
847 return result;
848 }
849
850 /* Timestamp/Error/gPTP interrupt handler */
ravb_multi_interrupt(int irq,void * dev_id)851 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
852 {
853 struct net_device *ndev = dev_id;
854 struct ravb_private *priv = netdev_priv(ndev);
855 irqreturn_t result = IRQ_NONE;
856 u32 iss;
857
858 spin_lock(&priv->lock);
859 /* Get interrupt status */
860 iss = ravb_read(ndev, ISS);
861
862 /* Timestamp updated */
863 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
864 result = IRQ_HANDLED;
865
866 /* Error status summary */
867 if (iss & ISS_ES) {
868 ravb_error_interrupt(ndev);
869 result = IRQ_HANDLED;
870 }
871
872 /* gPTP interrupt status summary */
873 if (iss & ISS_CGIS) {
874 ravb_ptp_interrupt(ndev);
875 result = IRQ_HANDLED;
876 }
877
878 spin_unlock(&priv->lock);
879 return result;
880 }
881
ravb_dma_interrupt(int irq,void * dev_id,int q)882 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
883 {
884 struct net_device *ndev = dev_id;
885 struct ravb_private *priv = netdev_priv(ndev);
886 irqreturn_t result = IRQ_NONE;
887
888 spin_lock(&priv->lock);
889
890 /* Network control/Best effort queue RX/TX */
891 if (ravb_queue_interrupt(ndev, q))
892 result = IRQ_HANDLED;
893
894 spin_unlock(&priv->lock);
895 return result;
896 }
897
ravb_be_interrupt(int irq,void * dev_id)898 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
899 {
900 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
901 }
902
ravb_nc_interrupt(int irq,void * dev_id)903 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
904 {
905 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
906 }
907
ravb_poll(struct napi_struct * napi,int budget)908 static int ravb_poll(struct napi_struct *napi, int budget)
909 {
910 struct net_device *ndev = napi->dev;
911 struct ravb_private *priv = netdev_priv(ndev);
912 unsigned long flags;
913 int q = napi - priv->napi;
914 int mask = BIT(q);
915 int quota = budget;
916
917 /* Processing RX Descriptor Ring */
918 /* Clear RX interrupt */
919 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
920 if (ravb_rx(ndev, "a, q))
921 goto out;
922
923 /* Processing RX Descriptor Ring */
924 spin_lock_irqsave(&priv->lock, flags);
925 /* Clear TX interrupt */
926 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
927 ravb_tx_free(ndev, q, true);
928 netif_wake_subqueue(ndev, q);
929 spin_unlock_irqrestore(&priv->lock, flags);
930
931 napi_complete(napi);
932
933 /* Re-enable RX/TX interrupts */
934 spin_lock_irqsave(&priv->lock, flags);
935 if (priv->chip_id == RCAR_GEN2) {
936 ravb_modify(ndev, RIC0, mask, mask);
937 ravb_modify(ndev, TIC, mask, mask);
938 } else {
939 ravb_write(ndev, mask, RIE0);
940 ravb_write(ndev, mask, TIE);
941 }
942 spin_unlock_irqrestore(&priv->lock, flags);
943
944 /* Receive error message handling */
945 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
946 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
947 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
948 ndev->stats.rx_over_errors = priv->rx_over_errors;
949 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
950 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
951 out:
952 return budget - quota;
953 }
954
955 /* PHY state control function */
ravb_adjust_link(struct net_device * ndev)956 static void ravb_adjust_link(struct net_device *ndev)
957 {
958 struct ravb_private *priv = netdev_priv(ndev);
959 struct phy_device *phydev = ndev->phydev;
960 bool new_state = false;
961 unsigned long flags;
962
963 spin_lock_irqsave(&priv->lock, flags);
964
965 /* Disable TX and RX right over here, if E-MAC change is ignored */
966 if (priv->no_avb_link)
967 ravb_rcv_snd_disable(ndev);
968
969 if (phydev->link) {
970 if (phydev->speed != priv->speed) {
971 new_state = true;
972 priv->speed = phydev->speed;
973 ravb_set_rate(ndev);
974 }
975 if (!priv->link) {
976 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
977 new_state = true;
978 priv->link = phydev->link;
979 }
980 } else if (priv->link) {
981 new_state = true;
982 priv->link = 0;
983 priv->speed = 0;
984 }
985
986 /* Enable TX and RX right over here, if E-MAC change is ignored */
987 if (priv->no_avb_link && phydev->link)
988 ravb_rcv_snd_enable(ndev);
989
990 spin_unlock_irqrestore(&priv->lock, flags);
991
992 if (new_state && netif_msg_link(priv))
993 phy_print_status(phydev);
994 }
995
996 static const struct soc_device_attribute r8a7795es10[] = {
997 { .soc_id = "r8a7795", .revision = "ES1.0", },
998 { /* sentinel */ }
999 };
1000
1001 /* PHY init function */
ravb_phy_init(struct net_device * ndev)1002 static int ravb_phy_init(struct net_device *ndev)
1003 {
1004 struct device_node *np = ndev->dev.parent->of_node;
1005 struct ravb_private *priv = netdev_priv(ndev);
1006 struct phy_device *phydev;
1007 struct device_node *pn;
1008 phy_interface_t iface;
1009 int err;
1010
1011 priv->link = 0;
1012 priv->speed = 0;
1013
1014 /* Try connecting to PHY */
1015 pn = of_parse_phandle(np, "phy-handle", 0);
1016 if (!pn) {
1017 /* In the case of a fixed PHY, the DT node associated
1018 * to the PHY is the Ethernet MAC DT node.
1019 */
1020 if (of_phy_is_fixed_link(np)) {
1021 err = of_phy_register_fixed_link(np);
1022 if (err)
1023 return err;
1024 }
1025 pn = of_node_get(np);
1026 }
1027
1028 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII
1029 : priv->phy_interface;
1030 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface);
1031 of_node_put(pn);
1032 if (!phydev) {
1033 netdev_err(ndev, "failed to connect PHY\n");
1034 err = -ENOENT;
1035 goto err_deregister_fixed_link;
1036 }
1037
1038 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1039 * at this time.
1040 */
1041 if (soc_device_match(r8a7795es10)) {
1042 err = phy_set_max_speed(phydev, SPEED_100);
1043 if (err) {
1044 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1045 goto err_phy_disconnect;
1046 }
1047
1048 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1049 }
1050
1051 /* 10BASE, Pause and Asym Pause is not supported */
1052 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1053 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1054 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1055 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1056
1057 /* Half Duplex is not supported */
1058 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1059 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1060
1061 phy_attached_info(phydev);
1062
1063 return 0;
1064
1065 err_phy_disconnect:
1066 phy_disconnect(phydev);
1067 err_deregister_fixed_link:
1068 if (of_phy_is_fixed_link(np))
1069 of_phy_deregister_fixed_link(np);
1070
1071 return err;
1072 }
1073
1074 /* PHY control start function */
ravb_phy_start(struct net_device * ndev)1075 static int ravb_phy_start(struct net_device *ndev)
1076 {
1077 int error;
1078
1079 error = ravb_phy_init(ndev);
1080 if (error)
1081 return error;
1082
1083 phy_start(ndev->phydev);
1084
1085 return 0;
1086 }
1087
ravb_get_msglevel(struct net_device * ndev)1088 static u32 ravb_get_msglevel(struct net_device *ndev)
1089 {
1090 struct ravb_private *priv = netdev_priv(ndev);
1091
1092 return priv->msg_enable;
1093 }
1094
ravb_set_msglevel(struct net_device * ndev,u32 value)1095 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1096 {
1097 struct ravb_private *priv = netdev_priv(ndev);
1098
1099 priv->msg_enable = value;
1100 }
1101
1102 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1103 "rx_queue_0_current",
1104 "tx_queue_0_current",
1105 "rx_queue_0_dirty",
1106 "tx_queue_0_dirty",
1107 "rx_queue_0_packets",
1108 "tx_queue_0_packets",
1109 "rx_queue_0_bytes",
1110 "tx_queue_0_bytes",
1111 "rx_queue_0_mcast_packets",
1112 "rx_queue_0_errors",
1113 "rx_queue_0_crc_errors",
1114 "rx_queue_0_frame_errors",
1115 "rx_queue_0_length_errors",
1116 "rx_queue_0_missed_errors",
1117 "rx_queue_0_over_errors",
1118
1119 "rx_queue_1_current",
1120 "tx_queue_1_current",
1121 "rx_queue_1_dirty",
1122 "tx_queue_1_dirty",
1123 "rx_queue_1_packets",
1124 "tx_queue_1_packets",
1125 "rx_queue_1_bytes",
1126 "tx_queue_1_bytes",
1127 "rx_queue_1_mcast_packets",
1128 "rx_queue_1_errors",
1129 "rx_queue_1_crc_errors",
1130 "rx_queue_1_frame_errors",
1131 "rx_queue_1_length_errors",
1132 "rx_queue_1_missed_errors",
1133 "rx_queue_1_over_errors",
1134 };
1135
1136 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1137
ravb_get_sset_count(struct net_device * netdev,int sset)1138 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1139 {
1140 switch (sset) {
1141 case ETH_SS_STATS:
1142 return RAVB_STATS_LEN;
1143 default:
1144 return -EOPNOTSUPP;
1145 }
1146 }
1147
ravb_get_ethtool_stats(struct net_device * ndev,struct ethtool_stats * estats,u64 * data)1148 static void ravb_get_ethtool_stats(struct net_device *ndev,
1149 struct ethtool_stats *estats, u64 *data)
1150 {
1151 struct ravb_private *priv = netdev_priv(ndev);
1152 int i = 0;
1153 int q;
1154
1155 /* Device-specific stats */
1156 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1157 struct net_device_stats *stats = &priv->stats[q];
1158
1159 data[i++] = priv->cur_rx[q];
1160 data[i++] = priv->cur_tx[q];
1161 data[i++] = priv->dirty_rx[q];
1162 data[i++] = priv->dirty_tx[q];
1163 data[i++] = stats->rx_packets;
1164 data[i++] = stats->tx_packets;
1165 data[i++] = stats->rx_bytes;
1166 data[i++] = stats->tx_bytes;
1167 data[i++] = stats->multicast;
1168 data[i++] = stats->rx_errors;
1169 data[i++] = stats->rx_crc_errors;
1170 data[i++] = stats->rx_frame_errors;
1171 data[i++] = stats->rx_length_errors;
1172 data[i++] = stats->rx_missed_errors;
1173 data[i++] = stats->rx_over_errors;
1174 }
1175 }
1176
ravb_get_strings(struct net_device * ndev,u32 stringset,u8 * data)1177 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1178 {
1179 switch (stringset) {
1180 case ETH_SS_STATS:
1181 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1182 break;
1183 }
1184 }
1185
ravb_get_ringparam(struct net_device * ndev,struct ethtool_ringparam * ring)1186 static void ravb_get_ringparam(struct net_device *ndev,
1187 struct ethtool_ringparam *ring)
1188 {
1189 struct ravb_private *priv = netdev_priv(ndev);
1190
1191 ring->rx_max_pending = BE_RX_RING_MAX;
1192 ring->tx_max_pending = BE_TX_RING_MAX;
1193 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1194 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1195 }
1196
ravb_set_ringparam(struct net_device * ndev,struct ethtool_ringparam * ring)1197 static int ravb_set_ringparam(struct net_device *ndev,
1198 struct ethtool_ringparam *ring)
1199 {
1200 struct ravb_private *priv = netdev_priv(ndev);
1201 int error;
1202
1203 if (ring->tx_pending > BE_TX_RING_MAX ||
1204 ring->rx_pending > BE_RX_RING_MAX ||
1205 ring->tx_pending < BE_TX_RING_MIN ||
1206 ring->rx_pending < BE_RX_RING_MIN)
1207 return -EINVAL;
1208 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1209 return -EINVAL;
1210
1211 if (netif_running(ndev)) {
1212 netif_device_detach(ndev);
1213 /* Stop PTP Clock driver */
1214 if (priv->chip_id == RCAR_GEN2)
1215 ravb_ptp_stop(ndev);
1216 /* Wait for DMA stopping */
1217 error = ravb_stop_dma(ndev);
1218 if (error) {
1219 netdev_err(ndev,
1220 "cannot set ringparam! Any AVB processes are still running?\n");
1221 return error;
1222 }
1223 synchronize_irq(ndev->irq);
1224
1225 /* Free all the skb's in the RX queue and the DMA buffers. */
1226 ravb_ring_free(ndev, RAVB_BE);
1227 ravb_ring_free(ndev, RAVB_NC);
1228 }
1229
1230 /* Set new parameters */
1231 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1232 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1233
1234 if (netif_running(ndev)) {
1235 error = ravb_dmac_init(ndev);
1236 if (error) {
1237 netdev_err(ndev,
1238 "%s: ravb_dmac_init() failed, error %d\n",
1239 __func__, error);
1240 return error;
1241 }
1242
1243 ravb_emac_init(ndev);
1244
1245 /* Initialise PTP Clock driver */
1246 if (priv->chip_id == RCAR_GEN2)
1247 ravb_ptp_init(ndev, priv->pdev);
1248
1249 netif_device_attach(ndev);
1250 }
1251
1252 return 0;
1253 }
1254
ravb_get_ts_info(struct net_device * ndev,struct ethtool_ts_info * info)1255 static int ravb_get_ts_info(struct net_device *ndev,
1256 struct ethtool_ts_info *info)
1257 {
1258 struct ravb_private *priv = netdev_priv(ndev);
1259
1260 info->so_timestamping =
1261 SOF_TIMESTAMPING_TX_SOFTWARE |
1262 SOF_TIMESTAMPING_RX_SOFTWARE |
1263 SOF_TIMESTAMPING_SOFTWARE |
1264 SOF_TIMESTAMPING_TX_HARDWARE |
1265 SOF_TIMESTAMPING_RX_HARDWARE |
1266 SOF_TIMESTAMPING_RAW_HARDWARE;
1267 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1268 info->rx_filters =
1269 (1 << HWTSTAMP_FILTER_NONE) |
1270 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1271 (1 << HWTSTAMP_FILTER_ALL);
1272 info->phc_index = ptp_clock_index(priv->ptp.clock);
1273
1274 return 0;
1275 }
1276
ravb_get_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)1277 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1278 {
1279 struct ravb_private *priv = netdev_priv(ndev);
1280
1281 wol->supported = WAKE_MAGIC;
1282 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1283 }
1284
ravb_set_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)1285 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1286 {
1287 struct ravb_private *priv = netdev_priv(ndev);
1288
1289 if (wol->wolopts & ~WAKE_MAGIC)
1290 return -EOPNOTSUPP;
1291
1292 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1293
1294 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1295
1296 return 0;
1297 }
1298
1299 static const struct ethtool_ops ravb_ethtool_ops = {
1300 .nway_reset = phy_ethtool_nway_reset,
1301 .get_msglevel = ravb_get_msglevel,
1302 .set_msglevel = ravb_set_msglevel,
1303 .get_link = ethtool_op_get_link,
1304 .get_strings = ravb_get_strings,
1305 .get_ethtool_stats = ravb_get_ethtool_stats,
1306 .get_sset_count = ravb_get_sset_count,
1307 .get_ringparam = ravb_get_ringparam,
1308 .set_ringparam = ravb_set_ringparam,
1309 .get_ts_info = ravb_get_ts_info,
1310 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1311 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1312 .get_wol = ravb_get_wol,
1313 .set_wol = ravb_set_wol,
1314 };
1315
ravb_hook_irq(unsigned int irq,irq_handler_t handler,struct net_device * ndev,struct device * dev,const char * ch)1316 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1317 struct net_device *ndev, struct device *dev,
1318 const char *ch)
1319 {
1320 char *name;
1321 int error;
1322
1323 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1324 if (!name)
1325 return -ENOMEM;
1326 error = request_irq(irq, handler, 0, name, ndev);
1327 if (error)
1328 netdev_err(ndev, "cannot request IRQ %s\n", name);
1329
1330 return error;
1331 }
1332
1333 /* Network device open function for Ethernet AVB */
ravb_open(struct net_device * ndev)1334 static int ravb_open(struct net_device *ndev)
1335 {
1336 struct ravb_private *priv = netdev_priv(ndev);
1337 struct platform_device *pdev = priv->pdev;
1338 struct device *dev = &pdev->dev;
1339 int error;
1340
1341 napi_enable(&priv->napi[RAVB_BE]);
1342 napi_enable(&priv->napi[RAVB_NC]);
1343
1344 if (priv->chip_id == RCAR_GEN2) {
1345 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1346 ndev->name, ndev);
1347 if (error) {
1348 netdev_err(ndev, "cannot request IRQ\n");
1349 goto out_napi_off;
1350 }
1351 } else {
1352 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1353 dev, "ch22:multi");
1354 if (error)
1355 goto out_napi_off;
1356 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1357 dev, "ch24:emac");
1358 if (error)
1359 goto out_free_irq;
1360 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1361 ndev, dev, "ch0:rx_be");
1362 if (error)
1363 goto out_free_irq_emac;
1364 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1365 ndev, dev, "ch18:tx_be");
1366 if (error)
1367 goto out_free_irq_be_rx;
1368 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1369 ndev, dev, "ch1:rx_nc");
1370 if (error)
1371 goto out_free_irq_be_tx;
1372 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1373 ndev, dev, "ch19:tx_nc");
1374 if (error)
1375 goto out_free_irq_nc_rx;
1376 }
1377
1378 /* Device init */
1379 error = ravb_dmac_init(ndev);
1380 if (error)
1381 goto out_free_irq_nc_tx;
1382 ravb_emac_init(ndev);
1383
1384 /* Initialise PTP Clock driver */
1385 if (priv->chip_id == RCAR_GEN2)
1386 ravb_ptp_init(ndev, priv->pdev);
1387
1388 netif_tx_start_all_queues(ndev);
1389
1390 /* PHY control start */
1391 error = ravb_phy_start(ndev);
1392 if (error)
1393 goto out_ptp_stop;
1394
1395 return 0;
1396
1397 out_ptp_stop:
1398 /* Stop PTP Clock driver */
1399 if (priv->chip_id == RCAR_GEN2)
1400 ravb_ptp_stop(ndev);
1401 out_free_irq_nc_tx:
1402 if (priv->chip_id == RCAR_GEN2)
1403 goto out_free_irq;
1404 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1405 out_free_irq_nc_rx:
1406 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1407 out_free_irq_be_tx:
1408 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1409 out_free_irq_be_rx:
1410 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1411 out_free_irq_emac:
1412 free_irq(priv->emac_irq, ndev);
1413 out_free_irq:
1414 free_irq(ndev->irq, ndev);
1415 out_napi_off:
1416 napi_disable(&priv->napi[RAVB_NC]);
1417 napi_disable(&priv->napi[RAVB_BE]);
1418 return error;
1419 }
1420
1421 /* Timeout function for Ethernet AVB */
ravb_tx_timeout(struct net_device * ndev,unsigned int txqueue)1422 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1423 {
1424 struct ravb_private *priv = netdev_priv(ndev);
1425
1426 netif_err(priv, tx_err, ndev,
1427 "transmit timed out, status %08x, resetting...\n",
1428 ravb_read(ndev, ISS));
1429
1430 /* tx_errors count up */
1431 ndev->stats.tx_errors++;
1432
1433 schedule_work(&priv->work);
1434 }
1435
ravb_tx_timeout_work(struct work_struct * work)1436 static void ravb_tx_timeout_work(struct work_struct *work)
1437 {
1438 struct ravb_private *priv = container_of(work, struct ravb_private,
1439 work);
1440 struct net_device *ndev = priv->ndev;
1441 int error;
1442
1443 netif_tx_stop_all_queues(ndev);
1444
1445 /* Stop PTP Clock driver */
1446 if (priv->chip_id == RCAR_GEN2)
1447 ravb_ptp_stop(ndev);
1448
1449 /* Wait for DMA stopping */
1450 if (ravb_stop_dma(ndev)) {
1451 /* If ravb_stop_dma() fails, the hardware is still operating
1452 * for TX and/or RX. So, this should not call the following
1453 * functions because ravb_dmac_init() is possible to fail too.
1454 * Also, this should not retry ravb_stop_dma() again and again
1455 * here because it's possible to wait forever. So, this just
1456 * re-enables the TX and RX and skip the following
1457 * re-initialization procedure.
1458 */
1459 ravb_rcv_snd_enable(ndev);
1460 goto out;
1461 }
1462
1463 ravb_ring_free(ndev, RAVB_BE);
1464 ravb_ring_free(ndev, RAVB_NC);
1465
1466 /* Device init */
1467 error = ravb_dmac_init(ndev);
1468 if (error) {
1469 /* If ravb_dmac_init() fails, descriptors are freed. So, this
1470 * should return here to avoid re-enabling the TX and RX in
1471 * ravb_emac_init().
1472 */
1473 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
1474 __func__, error);
1475 return;
1476 }
1477 ravb_emac_init(ndev);
1478
1479 out:
1480 /* Initialise PTP Clock driver */
1481 if (priv->chip_id == RCAR_GEN2)
1482 ravb_ptp_init(ndev, priv->pdev);
1483
1484 netif_tx_start_all_queues(ndev);
1485 }
1486
1487 /* Packet transmit function for Ethernet AVB */
ravb_start_xmit(struct sk_buff * skb,struct net_device * ndev)1488 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1489 {
1490 struct ravb_private *priv = netdev_priv(ndev);
1491 int num_tx_desc = priv->num_tx_desc;
1492 u16 q = skb_get_queue_mapping(skb);
1493 struct ravb_tstamp_skb *ts_skb;
1494 struct ravb_tx_desc *desc;
1495 unsigned long flags;
1496 u32 dma_addr;
1497 void *buffer;
1498 u32 entry;
1499 u32 len;
1500
1501 spin_lock_irqsave(&priv->lock, flags);
1502 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1503 num_tx_desc) {
1504 netif_err(priv, tx_queued, ndev,
1505 "still transmitting with the full ring!\n");
1506 netif_stop_subqueue(ndev, q);
1507 spin_unlock_irqrestore(&priv->lock, flags);
1508 return NETDEV_TX_BUSY;
1509 }
1510
1511 if (skb_put_padto(skb, ETH_ZLEN))
1512 goto exit;
1513
1514 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
1515 priv->tx_skb[q][entry / num_tx_desc] = skb;
1516
1517 if (num_tx_desc > 1) {
1518 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1519 entry / num_tx_desc * DPTR_ALIGN;
1520 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1521
1522 /* Zero length DMA descriptors are problematic as they seem
1523 * to terminate DMA transfers. Avoid them by simply using a
1524 * length of DPTR_ALIGN (4) when skb data is aligned to
1525 * DPTR_ALIGN.
1526 *
1527 * As skb is guaranteed to have at least ETH_ZLEN (60)
1528 * bytes of data by the call to skb_put_padto() above this
1529 * is safe with respect to both the length of the first DMA
1530 * descriptor (len) overflowing the available data and the
1531 * length of the second DMA descriptor (skb->len - len)
1532 * being negative.
1533 */
1534 if (len == 0)
1535 len = DPTR_ALIGN;
1536
1537 memcpy(buffer, skb->data, len);
1538 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1539 DMA_TO_DEVICE);
1540 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1541 goto drop;
1542
1543 desc = &priv->tx_ring[q][entry];
1544 desc->ds_tagl = cpu_to_le16(len);
1545 desc->dptr = cpu_to_le32(dma_addr);
1546
1547 buffer = skb->data + len;
1548 len = skb->len - len;
1549 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1550 DMA_TO_DEVICE);
1551 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1552 goto unmap;
1553
1554 desc++;
1555 } else {
1556 desc = &priv->tx_ring[q][entry];
1557 len = skb->len;
1558 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
1559 DMA_TO_DEVICE);
1560 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1561 goto drop;
1562 }
1563 desc->ds_tagl = cpu_to_le16(len);
1564 desc->dptr = cpu_to_le32(dma_addr);
1565
1566 /* TX timestamp required */
1567 if (q == RAVB_NC) {
1568 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1569 if (!ts_skb) {
1570 if (num_tx_desc > 1) {
1571 desc--;
1572 dma_unmap_single(ndev->dev.parent, dma_addr,
1573 len, DMA_TO_DEVICE);
1574 }
1575 goto unmap;
1576 }
1577 ts_skb->skb = skb_get(skb);
1578 ts_skb->tag = priv->ts_skb_tag++;
1579 priv->ts_skb_tag &= 0x3ff;
1580 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1581
1582 /* TAG and timestamp required flag */
1583 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1584 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1585 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
1586 }
1587
1588 skb_tx_timestamp(skb);
1589 /* Descriptor type must be set after all the above writes */
1590 dma_wmb();
1591 if (num_tx_desc > 1) {
1592 desc->die_dt = DT_FEND;
1593 desc--;
1594 desc->die_dt = DT_FSTART;
1595 } else {
1596 desc->die_dt = DT_FSINGLE;
1597 }
1598 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1599
1600 priv->cur_tx[q] += num_tx_desc;
1601 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1602 (priv->num_tx_ring[q] - 1) * num_tx_desc &&
1603 !ravb_tx_free(ndev, q, true))
1604 netif_stop_subqueue(ndev, q);
1605
1606 exit:
1607 spin_unlock_irqrestore(&priv->lock, flags);
1608 return NETDEV_TX_OK;
1609
1610 unmap:
1611 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1612 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1613 drop:
1614 dev_kfree_skb_any(skb);
1615 priv->tx_skb[q][entry / num_tx_desc] = NULL;
1616 goto exit;
1617 }
1618
ravb_select_queue(struct net_device * ndev,struct sk_buff * skb,struct net_device * sb_dev)1619 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1620 struct net_device *sb_dev)
1621 {
1622 /* If skb needs TX timestamp, it is handled in network control queue */
1623 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1624 RAVB_BE;
1625
1626 }
1627
ravb_get_stats(struct net_device * ndev)1628 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1629 {
1630 struct ravb_private *priv = netdev_priv(ndev);
1631 struct net_device_stats *nstats, *stats0, *stats1;
1632
1633 nstats = &ndev->stats;
1634 stats0 = &priv->stats[RAVB_BE];
1635 stats1 = &priv->stats[RAVB_NC];
1636
1637 if (priv->chip_id == RCAR_GEN3) {
1638 nstats->tx_dropped += ravb_read(ndev, TROCR);
1639 ravb_write(ndev, 0, TROCR); /* (write clear) */
1640 }
1641
1642 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1643 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1644 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1645 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1646 nstats->multicast = stats0->multicast + stats1->multicast;
1647 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1648 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1649 nstats->rx_frame_errors =
1650 stats0->rx_frame_errors + stats1->rx_frame_errors;
1651 nstats->rx_length_errors =
1652 stats0->rx_length_errors + stats1->rx_length_errors;
1653 nstats->rx_missed_errors =
1654 stats0->rx_missed_errors + stats1->rx_missed_errors;
1655 nstats->rx_over_errors =
1656 stats0->rx_over_errors + stats1->rx_over_errors;
1657
1658 return nstats;
1659 }
1660
1661 /* Update promiscuous bit */
ravb_set_rx_mode(struct net_device * ndev)1662 static void ravb_set_rx_mode(struct net_device *ndev)
1663 {
1664 struct ravb_private *priv = netdev_priv(ndev);
1665 unsigned long flags;
1666
1667 spin_lock_irqsave(&priv->lock, flags);
1668 ravb_modify(ndev, ECMR, ECMR_PRM,
1669 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1670 spin_unlock_irqrestore(&priv->lock, flags);
1671 }
1672
1673 /* Device close function for Ethernet AVB */
ravb_close(struct net_device * ndev)1674 static int ravb_close(struct net_device *ndev)
1675 {
1676 struct device_node *np = ndev->dev.parent->of_node;
1677 struct ravb_private *priv = netdev_priv(ndev);
1678 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1679
1680 netif_tx_stop_all_queues(ndev);
1681
1682 /* Disable interrupts by clearing the interrupt masks. */
1683 ravb_write(ndev, 0, RIC0);
1684 ravb_write(ndev, 0, RIC2);
1685 ravb_write(ndev, 0, TIC);
1686
1687 /* Stop PTP Clock driver */
1688 if (priv->chip_id == RCAR_GEN2)
1689 ravb_ptp_stop(ndev);
1690
1691 /* Set the config mode to stop the AVB-DMAC's processes */
1692 if (ravb_stop_dma(ndev) < 0)
1693 netdev_err(ndev,
1694 "device will be stopped after h/w processes are done.\n");
1695
1696 /* Clear the timestamp list */
1697 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1698 list_del(&ts_skb->list);
1699 kfree_skb(ts_skb->skb);
1700 kfree(ts_skb);
1701 }
1702
1703 /* PHY disconnect */
1704 if (ndev->phydev) {
1705 phy_stop(ndev->phydev);
1706 phy_disconnect(ndev->phydev);
1707 if (of_phy_is_fixed_link(np))
1708 of_phy_deregister_fixed_link(np);
1709 }
1710
1711 if (priv->chip_id != RCAR_GEN2) {
1712 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1713 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1714 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1715 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1716 free_irq(priv->emac_irq, ndev);
1717 }
1718 free_irq(ndev->irq, ndev);
1719
1720 napi_disable(&priv->napi[RAVB_NC]);
1721 napi_disable(&priv->napi[RAVB_BE]);
1722
1723 /* Free all the skb's in the RX queue and the DMA buffers. */
1724 ravb_ring_free(ndev, RAVB_BE);
1725 ravb_ring_free(ndev, RAVB_NC);
1726
1727 return 0;
1728 }
1729
ravb_hwtstamp_get(struct net_device * ndev,struct ifreq * req)1730 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1731 {
1732 struct ravb_private *priv = netdev_priv(ndev);
1733 struct hwtstamp_config config;
1734
1735 config.flags = 0;
1736 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1737 HWTSTAMP_TX_OFF;
1738 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) {
1739 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT:
1740 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1741 break;
1742 case RAVB_RXTSTAMP_TYPE_ALL:
1743 config.rx_filter = HWTSTAMP_FILTER_ALL;
1744 break;
1745 default:
1746 config.rx_filter = HWTSTAMP_FILTER_NONE;
1747 }
1748
1749 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1750 -EFAULT : 0;
1751 }
1752
1753 /* Control hardware time stamping */
ravb_hwtstamp_set(struct net_device * ndev,struct ifreq * req)1754 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1755 {
1756 struct ravb_private *priv = netdev_priv(ndev);
1757 struct hwtstamp_config config;
1758 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1759 u32 tstamp_tx_ctrl;
1760
1761 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1762 return -EFAULT;
1763
1764 /* Reserved for future extensions */
1765 if (config.flags)
1766 return -EINVAL;
1767
1768 switch (config.tx_type) {
1769 case HWTSTAMP_TX_OFF:
1770 tstamp_tx_ctrl = 0;
1771 break;
1772 case HWTSTAMP_TX_ON:
1773 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1774 break;
1775 default:
1776 return -ERANGE;
1777 }
1778
1779 switch (config.rx_filter) {
1780 case HWTSTAMP_FILTER_NONE:
1781 tstamp_rx_ctrl = 0;
1782 break;
1783 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1784 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1785 break;
1786 default:
1787 config.rx_filter = HWTSTAMP_FILTER_ALL;
1788 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1789 }
1790
1791 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1792 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1793
1794 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1795 -EFAULT : 0;
1796 }
1797
1798 /* ioctl to device function */
ravb_do_ioctl(struct net_device * ndev,struct ifreq * req,int cmd)1799 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1800 {
1801 struct phy_device *phydev = ndev->phydev;
1802
1803 if (!netif_running(ndev))
1804 return -EINVAL;
1805
1806 if (!phydev)
1807 return -ENODEV;
1808
1809 switch (cmd) {
1810 case SIOCGHWTSTAMP:
1811 return ravb_hwtstamp_get(ndev, req);
1812 case SIOCSHWTSTAMP:
1813 return ravb_hwtstamp_set(ndev, req);
1814 }
1815
1816 return phy_mii_ioctl(phydev, req, cmd);
1817 }
1818
ravb_change_mtu(struct net_device * ndev,int new_mtu)1819 static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
1820 {
1821 struct ravb_private *priv = netdev_priv(ndev);
1822
1823 ndev->mtu = new_mtu;
1824
1825 if (netif_running(ndev)) {
1826 synchronize_irq(priv->emac_irq);
1827 ravb_emac_init(ndev);
1828 }
1829
1830 netdev_update_features(ndev);
1831
1832 return 0;
1833 }
1834
ravb_set_rx_csum(struct net_device * ndev,bool enable)1835 static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
1836 {
1837 struct ravb_private *priv = netdev_priv(ndev);
1838 unsigned long flags;
1839
1840 spin_lock_irqsave(&priv->lock, flags);
1841
1842 /* Disable TX and RX */
1843 ravb_rcv_snd_disable(ndev);
1844
1845 /* Modify RX Checksum setting */
1846 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
1847
1848 /* Enable TX and RX */
1849 ravb_rcv_snd_enable(ndev);
1850
1851 spin_unlock_irqrestore(&priv->lock, flags);
1852 }
1853
ravb_set_features(struct net_device * ndev,netdev_features_t features)1854 static int ravb_set_features(struct net_device *ndev,
1855 netdev_features_t features)
1856 {
1857 netdev_features_t changed = ndev->features ^ features;
1858
1859 if (changed & NETIF_F_RXCSUM)
1860 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
1861
1862 ndev->features = features;
1863
1864 return 0;
1865 }
1866
1867 static const struct net_device_ops ravb_netdev_ops = {
1868 .ndo_open = ravb_open,
1869 .ndo_stop = ravb_close,
1870 .ndo_start_xmit = ravb_start_xmit,
1871 .ndo_select_queue = ravb_select_queue,
1872 .ndo_get_stats = ravb_get_stats,
1873 .ndo_set_rx_mode = ravb_set_rx_mode,
1874 .ndo_tx_timeout = ravb_tx_timeout,
1875 .ndo_do_ioctl = ravb_do_ioctl,
1876 .ndo_change_mtu = ravb_change_mtu,
1877 .ndo_validate_addr = eth_validate_addr,
1878 .ndo_set_mac_address = eth_mac_addr,
1879 .ndo_set_features = ravb_set_features,
1880 };
1881
1882 /* MDIO bus init function */
ravb_mdio_init(struct ravb_private * priv)1883 static int ravb_mdio_init(struct ravb_private *priv)
1884 {
1885 struct platform_device *pdev = priv->pdev;
1886 struct device *dev = &pdev->dev;
1887 int error;
1888
1889 /* Bitbang init */
1890 priv->mdiobb.ops = &bb_ops;
1891
1892 /* MII controller setting */
1893 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1894 if (!priv->mii_bus)
1895 return -ENOMEM;
1896
1897 /* Hook up MII support for ethtool */
1898 priv->mii_bus->name = "ravb_mii";
1899 priv->mii_bus->parent = dev;
1900 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1901 pdev->name, pdev->id);
1902
1903 /* Register MDIO bus */
1904 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1905 if (error)
1906 goto out_free_bus;
1907
1908 return 0;
1909
1910 out_free_bus:
1911 free_mdio_bitbang(priv->mii_bus);
1912 return error;
1913 }
1914
1915 /* MDIO bus release function */
ravb_mdio_release(struct ravb_private * priv)1916 static int ravb_mdio_release(struct ravb_private *priv)
1917 {
1918 /* Unregister mdio bus */
1919 mdiobus_unregister(priv->mii_bus);
1920
1921 /* Free bitbang info */
1922 free_mdio_bitbang(priv->mii_bus);
1923
1924 return 0;
1925 }
1926
1927 static const struct of_device_id ravb_match_table[] = {
1928 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1929 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1930 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1931 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1932 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1933 { }
1934 };
1935 MODULE_DEVICE_TABLE(of, ravb_match_table);
1936
ravb_set_gti(struct net_device * ndev)1937 static int ravb_set_gti(struct net_device *ndev)
1938 {
1939 struct ravb_private *priv = netdev_priv(ndev);
1940 struct device *dev = ndev->dev.parent;
1941 unsigned long rate;
1942 uint64_t inc;
1943
1944 rate = clk_get_rate(priv->clk);
1945 if (!rate)
1946 return -EINVAL;
1947
1948 inc = 1000000000ULL << 20;
1949 do_div(inc, rate);
1950
1951 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1952 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1953 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1954 return -EINVAL;
1955 }
1956
1957 ravb_write(ndev, inc, GTI);
1958
1959 return 0;
1960 }
1961
ravb_set_config_mode(struct net_device * ndev)1962 static void ravb_set_config_mode(struct net_device *ndev)
1963 {
1964 struct ravb_private *priv = netdev_priv(ndev);
1965
1966 if (priv->chip_id == RCAR_GEN2) {
1967 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1968 /* Set CSEL value */
1969 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1970 } else {
1971 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1972 CCC_GAC | CCC_CSEL_HPB);
1973 }
1974 }
1975
1976 static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = {
1977 { .soc_id = "r8a774c0" },
1978 { .soc_id = "r8a77990" },
1979 { .soc_id = "r8a77995" },
1980 { /* sentinel */ }
1981 };
1982
1983 /* Set tx and rx clock internal delay modes */
ravb_parse_delay_mode(struct device_node * np,struct net_device * ndev)1984 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev)
1985 {
1986 struct ravb_private *priv = netdev_priv(ndev);
1987 bool explicit_delay = false;
1988 u32 delay;
1989
1990 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) {
1991 /* Valid values are 0 and 1800, according to DT bindings */
1992 priv->rxcidm = !!delay;
1993 explicit_delay = true;
1994 }
1995 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) {
1996 /* Valid values are 0 and 2000, according to DT bindings */
1997 priv->txcidm = !!delay;
1998 explicit_delay = true;
1999 }
2000
2001 if (explicit_delay)
2002 return;
2003
2004 /* Fall back to legacy rgmii-*id behavior */
2005 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2006 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) {
2007 priv->rxcidm = 1;
2008 priv->rgmii_override = 1;
2009 }
2010
2011 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2012 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
2013 if (!WARN(soc_device_match(ravb_delay_mode_quirk_match),
2014 "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree",
2015 phy_modes(priv->phy_interface))) {
2016 priv->txcidm = 1;
2017 priv->rgmii_override = 1;
2018 }
2019 }
2020 }
2021
ravb_set_delay_mode(struct net_device * ndev)2022 static void ravb_set_delay_mode(struct net_device *ndev)
2023 {
2024 struct ravb_private *priv = netdev_priv(ndev);
2025 u32 set = 0;
2026
2027 if (priv->rxcidm)
2028 set |= APSR_RDM;
2029 if (priv->txcidm)
2030 set |= APSR_TDM;
2031 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set);
2032 }
2033
ravb_probe(struct platform_device * pdev)2034 static int ravb_probe(struct platform_device *pdev)
2035 {
2036 struct device_node *np = pdev->dev.of_node;
2037 struct ravb_private *priv;
2038 enum ravb_chip_id chip_id;
2039 struct net_device *ndev;
2040 int error, irq, q;
2041 struct resource *res;
2042 int i;
2043
2044 if (!np) {
2045 dev_err(&pdev->dev,
2046 "this driver is required to be instantiated from device tree\n");
2047 return -EINVAL;
2048 }
2049
2050 /* Get base address */
2051 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2052 if (!res) {
2053 dev_err(&pdev->dev, "invalid resource\n");
2054 return -EINVAL;
2055 }
2056
2057 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2058 NUM_TX_QUEUE, NUM_RX_QUEUE);
2059 if (!ndev)
2060 return -ENOMEM;
2061
2062 ndev->features = NETIF_F_RXCSUM;
2063 ndev->hw_features = NETIF_F_RXCSUM;
2064
2065 pm_runtime_enable(&pdev->dev);
2066 pm_runtime_get_sync(&pdev->dev);
2067
2068 /* The Ether-specific entries in the device structure. */
2069 ndev->base_addr = res->start;
2070
2071 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
2072
2073 if (chip_id == RCAR_GEN3)
2074 irq = platform_get_irq_byname(pdev, "ch22");
2075 else
2076 irq = platform_get_irq(pdev, 0);
2077 if (irq < 0) {
2078 error = irq;
2079 goto out_release;
2080 }
2081 ndev->irq = irq;
2082
2083 SET_NETDEV_DEV(ndev, &pdev->dev);
2084
2085 priv = netdev_priv(ndev);
2086 priv->ndev = ndev;
2087 priv->pdev = pdev;
2088 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2089 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2090 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2091 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2092 priv->addr = devm_ioremap_resource(&pdev->dev, res);
2093 if (IS_ERR(priv->addr)) {
2094 error = PTR_ERR(priv->addr);
2095 goto out_release;
2096 }
2097
2098 spin_lock_init(&priv->lock);
2099 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2100
2101 error = of_get_phy_mode(np, &priv->phy_interface);
2102 if (error && error != -ENODEV)
2103 goto out_release;
2104
2105 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2106 priv->avb_link_active_low =
2107 of_property_read_bool(np, "renesas,ether-link-active-low");
2108
2109 if (chip_id == RCAR_GEN3) {
2110 irq = platform_get_irq_byname(pdev, "ch24");
2111 if (irq < 0) {
2112 error = irq;
2113 goto out_release;
2114 }
2115 priv->emac_irq = irq;
2116 for (i = 0; i < NUM_RX_QUEUE; i++) {
2117 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2118 if (irq < 0) {
2119 error = irq;
2120 goto out_release;
2121 }
2122 priv->rx_irqs[i] = irq;
2123 }
2124 for (i = 0; i < NUM_TX_QUEUE; i++) {
2125 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2126 if (irq < 0) {
2127 error = irq;
2128 goto out_release;
2129 }
2130 priv->tx_irqs[i] = irq;
2131 }
2132 }
2133
2134 priv->chip_id = chip_id;
2135
2136 priv->clk = devm_clk_get(&pdev->dev, NULL);
2137 if (IS_ERR(priv->clk)) {
2138 error = PTR_ERR(priv->clk);
2139 goto out_release;
2140 }
2141
2142 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk");
2143 if (IS_ERR(priv->refclk)) {
2144 error = PTR_ERR(priv->refclk);
2145 goto out_release;
2146 }
2147 clk_prepare_enable(priv->refclk);
2148
2149 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2150 ndev->min_mtu = ETH_MIN_MTU;
2151
2152 priv->num_tx_desc = chip_id == RCAR_GEN2 ?
2153 NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3;
2154
2155 /* Set function */
2156 ndev->netdev_ops = &ravb_netdev_ops;
2157 ndev->ethtool_ops = &ravb_ethtool_ops;
2158
2159 /* Set AVB config mode */
2160 ravb_set_config_mode(ndev);
2161
2162 /* Set GTI value */
2163 error = ravb_set_gti(ndev);
2164 if (error)
2165 goto out_disable_refclk;
2166
2167 /* Request GTI loading */
2168 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2169
2170 if (priv->chip_id != RCAR_GEN2) {
2171 ravb_parse_delay_mode(np, ndev);
2172 ravb_set_delay_mode(ndev);
2173 }
2174
2175 /* Allocate descriptor base address table */
2176 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2177 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2178 &priv->desc_bat_dma, GFP_KERNEL);
2179 if (!priv->desc_bat) {
2180 dev_err(&pdev->dev,
2181 "Cannot allocate desc base address table (size %d bytes)\n",
2182 priv->desc_bat_size);
2183 error = -ENOMEM;
2184 goto out_disable_refclk;
2185 }
2186 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2187 priv->desc_bat[q].die_dt = DT_EOS;
2188 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2189
2190 /* Initialise HW timestamp list */
2191 INIT_LIST_HEAD(&priv->ts_skb_list);
2192
2193 /* Initialise PTP Clock driver */
2194 if (chip_id != RCAR_GEN2)
2195 ravb_ptp_init(ndev, pdev);
2196
2197 /* Debug message level */
2198 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2199
2200 /* Read and set MAC address */
2201 ravb_read_mac_address(np, ndev);
2202 if (!is_valid_ether_addr(ndev->dev_addr)) {
2203 dev_warn(&pdev->dev,
2204 "no valid MAC address supplied, using a random one\n");
2205 eth_hw_addr_random(ndev);
2206 }
2207
2208 /* MDIO bus init */
2209 error = ravb_mdio_init(priv);
2210 if (error) {
2211 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2212 goto out_dma_free;
2213 }
2214
2215 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2216 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2217
2218 /* Network device register */
2219 error = register_netdev(ndev);
2220 if (error)
2221 goto out_napi_del;
2222
2223 device_set_wakeup_capable(&pdev->dev, 1);
2224
2225 /* Print device information */
2226 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2227 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2228
2229 platform_set_drvdata(pdev, ndev);
2230
2231 return 0;
2232
2233 out_napi_del:
2234 netif_napi_del(&priv->napi[RAVB_NC]);
2235 netif_napi_del(&priv->napi[RAVB_BE]);
2236 ravb_mdio_release(priv);
2237 out_dma_free:
2238 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2239 priv->desc_bat_dma);
2240
2241 /* Stop PTP Clock driver */
2242 if (chip_id != RCAR_GEN2)
2243 ravb_ptp_stop(ndev);
2244 out_disable_refclk:
2245 clk_disable_unprepare(priv->refclk);
2246 out_release:
2247 free_netdev(ndev);
2248
2249 pm_runtime_put(&pdev->dev);
2250 pm_runtime_disable(&pdev->dev);
2251 return error;
2252 }
2253
ravb_remove(struct platform_device * pdev)2254 static int ravb_remove(struct platform_device *pdev)
2255 {
2256 struct net_device *ndev = platform_get_drvdata(pdev);
2257 struct ravb_private *priv = netdev_priv(ndev);
2258
2259 /* Stop PTP Clock driver */
2260 if (priv->chip_id != RCAR_GEN2)
2261 ravb_ptp_stop(ndev);
2262
2263 clk_disable_unprepare(priv->refclk);
2264
2265 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2266 priv->desc_bat_dma);
2267 /* Set reset mode */
2268 ravb_write(ndev, CCC_OPC_RESET, CCC);
2269 pm_runtime_put_sync(&pdev->dev);
2270 unregister_netdev(ndev);
2271 netif_napi_del(&priv->napi[RAVB_NC]);
2272 netif_napi_del(&priv->napi[RAVB_BE]);
2273 ravb_mdio_release(priv);
2274 pm_runtime_disable(&pdev->dev);
2275 free_netdev(ndev);
2276 platform_set_drvdata(pdev, NULL);
2277
2278 return 0;
2279 }
2280
ravb_wol_setup(struct net_device * ndev)2281 static int ravb_wol_setup(struct net_device *ndev)
2282 {
2283 struct ravb_private *priv = netdev_priv(ndev);
2284
2285 /* Disable interrupts by clearing the interrupt masks. */
2286 ravb_write(ndev, 0, RIC0);
2287 ravb_write(ndev, 0, RIC2);
2288 ravb_write(ndev, 0, TIC);
2289
2290 /* Only allow ECI interrupts */
2291 synchronize_irq(priv->emac_irq);
2292 napi_disable(&priv->napi[RAVB_NC]);
2293 napi_disable(&priv->napi[RAVB_BE]);
2294 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2295
2296 /* Enable MagicPacket */
2297 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2298
2299 return enable_irq_wake(priv->emac_irq);
2300 }
2301
ravb_wol_restore(struct net_device * ndev)2302 static int ravb_wol_restore(struct net_device *ndev)
2303 {
2304 struct ravb_private *priv = netdev_priv(ndev);
2305 int ret;
2306
2307 napi_enable(&priv->napi[RAVB_NC]);
2308 napi_enable(&priv->napi[RAVB_BE]);
2309
2310 /* Disable MagicPacket */
2311 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2312
2313 ret = ravb_close(ndev);
2314 if (ret < 0)
2315 return ret;
2316
2317 return disable_irq_wake(priv->emac_irq);
2318 }
2319
ravb_suspend(struct device * dev)2320 static int __maybe_unused ravb_suspend(struct device *dev)
2321 {
2322 struct net_device *ndev = dev_get_drvdata(dev);
2323 struct ravb_private *priv = netdev_priv(ndev);
2324 int ret;
2325
2326 if (!netif_running(ndev))
2327 return 0;
2328
2329 netif_device_detach(ndev);
2330
2331 if (priv->wol_enabled)
2332 ret = ravb_wol_setup(ndev);
2333 else
2334 ret = ravb_close(ndev);
2335
2336 return ret;
2337 }
2338
ravb_resume(struct device * dev)2339 static int __maybe_unused ravb_resume(struct device *dev)
2340 {
2341 struct net_device *ndev = dev_get_drvdata(dev);
2342 struct ravb_private *priv = netdev_priv(ndev);
2343 int ret = 0;
2344
2345 /* If WoL is enabled set reset mode to rearm the WoL logic */
2346 if (priv->wol_enabled)
2347 ravb_write(ndev, CCC_OPC_RESET, CCC);
2348
2349 /* All register have been reset to default values.
2350 * Restore all registers which where setup at probe time and
2351 * reopen device if it was running before system suspended.
2352 */
2353
2354 /* Set AVB config mode */
2355 ravb_set_config_mode(ndev);
2356
2357 /* Set GTI value */
2358 ret = ravb_set_gti(ndev);
2359 if (ret)
2360 return ret;
2361
2362 /* Request GTI loading */
2363 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2364
2365 if (priv->chip_id != RCAR_GEN2)
2366 ravb_set_delay_mode(ndev);
2367
2368 /* Restore descriptor base address table */
2369 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2370
2371 if (netif_running(ndev)) {
2372 if (priv->wol_enabled) {
2373 ret = ravb_wol_restore(ndev);
2374 if (ret)
2375 return ret;
2376 }
2377 ret = ravb_open(ndev);
2378 if (ret < 0)
2379 return ret;
2380 netif_device_attach(ndev);
2381 }
2382
2383 return ret;
2384 }
2385
ravb_runtime_nop(struct device * dev)2386 static int __maybe_unused ravb_runtime_nop(struct device *dev)
2387 {
2388 /* Runtime PM callback shared between ->runtime_suspend()
2389 * and ->runtime_resume(). Simply returns success.
2390 *
2391 * This driver re-initializes all registers after
2392 * pm_runtime_get_sync() anyway so there is no need
2393 * to save and restore registers here.
2394 */
2395 return 0;
2396 }
2397
2398 static const struct dev_pm_ops ravb_dev_pm_ops = {
2399 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2400 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2401 };
2402
2403 static struct platform_driver ravb_driver = {
2404 .probe = ravb_probe,
2405 .remove = ravb_remove,
2406 .driver = {
2407 .name = "ravb",
2408 .pm = &ravb_dev_pm_ops,
2409 .of_match_table = ravb_match_table,
2410 },
2411 };
2412
2413 module_platform_driver(ravb_driver);
2414
2415 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2416 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2417 MODULE_LICENSE("GPL v2");
2418