1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/*
7 * VScom OnRISC
8 * http://www.vscom.de
9 */
10
11/dts-v1/;
12
13#include "am335x-baltos.dtsi"
14#include "am335x-baltos-leds.dtsi"
15
16/ {
17	model = "OnRISC Baltos iR 3220";
18};
19
20&am33xx_pinmux {
21	tca6416_pins: pinmux_tca6416_pins {
22		pinctrl-single,pins = <
23			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7)      /* xdma_event_intr1.gpio0[20] tca6416 stuff */
24		>;
25	};
26
27	uart1_pins: pinmux_uart1_pins {
28		pinctrl-single,pins = <
29			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
30			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)
31			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
32			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
33			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
34			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
35			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
36			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
37		>;
38	};
39
40	uart2_pins: pinmux_uart2_pins {
41		pinctrl-single,pins = <
42			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)      /* spi0_sclk.uart2_rxd_mux3 */
43			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)      /* spi0_d0.uart2_txd_mux3 */
44			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* i2c0_sda.uart2_ctsn_mux0 */
45			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* i2c0_scl.uart2_rtsn_mux0 */
46			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad12.gpio1[12] DTR */
47			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad13.gpio1[13] DSR */
48			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad14.gpio1[14] DCD */
49			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad15.gpio1[15] RI */
50
51			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7)      /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
52		>;
53	};
54
55	mmc1_pins: pinmux_mmc1_pins {
56		pinctrl-single,pins = <
57			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7)     /* MMC1 CD */
58		>;
59	};
60};
61
62&uart1 {
63	pinctrl-names = "default";
64	pinctrl-0 = <&uart1_pins>;
65	dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
66	dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
67	dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
68	rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
69
70	status = "okay";
71};
72
73&uart2 {
74	pinctrl-names = "default";
75	pinctrl-0 = <&uart2_pins>;
76	dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
77	dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
78	dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
79	rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
80
81	status = "okay";
82};
83
84&i2c1 {
85	tca6416: gpio@20 {
86		compatible = "ti,tca6416";
87		reg = <0x20>;
88		gpio-controller;
89		#gpio-cells = <2>;
90		interrupt-parent = <&gpio0>;
91		interrupts = <20 IRQ_TYPE_EDGE_RISING>;
92		pinctrl-names = "default";
93		pinctrl-0 = <&tca6416_pins>;
94	};
95};
96
97&usb0_phy {
98	status = "okay";
99};
100
101&usb0 {
102	status = "okay";
103	dr_mode = "host";
104};
105
106&cpsw_emac0 {
107	phy-mode = "rmii";
108	dual_emac_res_vlan = <1>;
109	fixed-link {
110		speed = <100>;
111		full-duplex;
112	};
113};
114
115&cpsw_emac1 {
116	phy-mode = "rgmii-id";
117	dual_emac_res_vlan = <2>;
118	phy-handle = <&phy1>;
119};
120
121&mmc1 {
122	pinctrl-names = "default";
123	pinctrl-0 = <&mmc1_pins>;
124	cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
125};
126