1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/ { 7 cpus { 8 cpu@0 { 9 cpu0-supply = <&dcdc2_reg>; 10 }; 11 }; 12 13 memory@80000000 { 14 device_type = "memory"; 15 reg = <0x80000000 0x10000000>; /* 256 MB */ 16 }; 17 18 chosen { 19 stdout-path = &uart0; 20 }; 21 22 leds { 23 pinctrl-names = "default"; 24 pinctrl-0 = <&user_leds_s0>; 25 26 compatible = "gpio-leds"; 27 28 led2 { 29 label = "beaglebone:green:heartbeat"; 30 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 31 linux,default-trigger = "heartbeat"; 32 default-state = "off"; 33 }; 34 35 led3 { 36 label = "beaglebone:green:mmc0"; 37 gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; 38 linux,default-trigger = "mmc0"; 39 default-state = "off"; 40 }; 41 42 led4 { 43 label = "beaglebone:green:usr2"; 44 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; 45 linux,default-trigger = "cpu0"; 46 default-state = "off"; 47 }; 48 49 led5 { 50 label = "beaglebone:green:usr3"; 51 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; 52 linux,default-trigger = "mmc1"; 53 default-state = "off"; 54 }; 55 }; 56 57 vmmcsd_fixed: fixedregulator0 { 58 compatible = "regulator-fixed"; 59 regulator-name = "vmmcsd_fixed"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 }; 63}; 64 65&am33xx_pinmux { 66 pinctrl-names = "default"; 67 pinctrl-0 = <&clkout2_pin>; 68 69 user_leds_s0: user_leds_s0 { 70 pinctrl-single,pins = < 71 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ 72 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ 73 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ 74 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ 75 >; 76 }; 77 78 i2c0_pins: pinmux_i2c0_pins { 79 pinctrl-single,pins = < 80 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ 81 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ 82 >; 83 }; 84 85 i2c2_pins: pinmux_i2c2_pins { 86 pinctrl-single,pins = < 87 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ 88 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ 89 >; 90 }; 91 92 uart0_pins: pinmux_uart0_pins { 93 pinctrl-single,pins = < 94 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 95 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 96 >; 97 }; 98 99 clkout2_pin: pinmux_clkout2_pin { 100 pinctrl-single,pins = < 101 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ 102 >; 103 }; 104 105 cpsw_default: cpsw_default { 106 pinctrl-single,pins = < 107 /* Slave 1 */ 108 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) 109 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 110 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) 111 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 112 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 113 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 114 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 115 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 116 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 117 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) 118 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) 119 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) 120 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) 121 >; 122 }; 123 124 cpsw_sleep: cpsw_sleep { 125 pinctrl-single,pins = < 126 /* Slave 1 reset value */ 127 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) 128 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 129 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) 130 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 131 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 132 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 133 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 134 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 135 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 136 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 137 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 138 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 139 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 140 >; 141 }; 142 143 davinci_mdio_default: davinci_mdio_default { 144 pinctrl-single,pins = < 145 /* MDIO */ 146 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 147 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 148 >; 149 }; 150 151 davinci_mdio_sleep: davinci_mdio_sleep { 152 pinctrl-single,pins = < 153 /* MDIO reset value */ 154 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) 155 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) 156 >; 157 }; 158 159 mmc1_pins: pinmux_mmc1_pins { 160 pinctrl-single,pins = < 161 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */ 162 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) 163 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) 164 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) 165 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) 166 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) 167 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 168 >; 169 }; 170 171 emmc_pins: pinmux_emmc_pins { 172 pinctrl-single,pins = < 173 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ 174 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ 175 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ 176 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ 177 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ 178 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ 179 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ 180 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ 181 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ 182 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ 183 >; 184 }; 185}; 186 187&uart0 { 188 pinctrl-names = "default"; 189 pinctrl-0 = <&uart0_pins>; 190 191 status = "okay"; 192}; 193 194&usb0 { 195 dr_mode = "peripheral"; 196 interrupts-extended = <&intc 18 &tps 0>; 197 interrupt-names = "mc", "vbus"; 198}; 199 200&usb1 { 201 dr_mode = "host"; 202}; 203 204&i2c0 { 205 pinctrl-names = "default"; 206 pinctrl-0 = <&i2c0_pins>; 207 208 status = "okay"; 209 clock-frequency = <400000>; 210 211 tps: tps@24 { 212 reg = <0x24>; 213 }; 214 215 baseboard_eeprom: baseboard_eeprom@50 { 216 compatible = "atmel,24c256"; 217 reg = <0x50>; 218 219 #address-cells = <1>; 220 #size-cells = <1>; 221 baseboard_data: baseboard_data@0 { 222 reg = <0 0x100>; 223 }; 224 }; 225}; 226 227&i2c2 { 228 pinctrl-names = "default"; 229 pinctrl-0 = <&i2c2_pins>; 230 231 status = "okay"; 232 clock-frequency = <100000>; 233 234 cape_eeprom0: cape_eeprom0@54 { 235 compatible = "atmel,24c256"; 236 reg = <0x54>; 237 #address-cells = <1>; 238 #size-cells = <1>; 239 cape0_data: cape_data@0 { 240 reg = <0 0x100>; 241 }; 242 }; 243 244 cape_eeprom1: cape_eeprom1@55 { 245 compatible = "atmel,24c256"; 246 reg = <0x55>; 247 #address-cells = <1>; 248 #size-cells = <1>; 249 cape1_data: cape_data@0 { 250 reg = <0 0x100>; 251 }; 252 }; 253 254 cape_eeprom2: cape_eeprom2@56 { 255 compatible = "atmel,24c256"; 256 reg = <0x56>; 257 #address-cells = <1>; 258 #size-cells = <1>; 259 cape2_data: cape_data@0 { 260 reg = <0 0x100>; 261 }; 262 }; 263 264 cape_eeprom3: cape_eeprom3@57 { 265 compatible = "atmel,24c256"; 266 reg = <0x57>; 267 #address-cells = <1>; 268 #size-cells = <1>; 269 cape3_data: cape_data@0 { 270 reg = <0 0x100>; 271 }; 272 }; 273}; 274 275 276/include/ "tps65217.dtsi" 277 278&tps { 279 /* 280 * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only 281 * mode") at poweroff. Most BeagleBone versions do not support RTC-only 282 * mode and risk hardware damage if this mode is entered. 283 * 284 * For details, see linux-omap mailing list May 2015 thread 285 * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller 286 * In particular, messages: 287 * http://www.spinics.net/lists/linux-omap/msg118585.html 288 * http://www.spinics.net/lists/linux-omap/msg118615.html 289 * 290 * You can override this later with 291 * &tps { /delete-property/ ti,pmic-shutdown-controller; } 292 * if you want to use RTC-only mode and made sure you are not affected 293 * by the hardware problems. (Tip: double-check by performing a current 294 * measurement after shutdown: it should be less than 1 mA.) 295 */ 296 297 interrupts = <7>; /* NMI */ 298 interrupt-parent = <&intc>; 299 300 ti,pmic-shutdown-controller; 301 302 charger { 303 status = "okay"; 304 }; 305 306 pwrbutton { 307 status = "okay"; 308 }; 309 310 regulators { 311 dcdc1_reg: regulator@0 { 312 regulator-name = "vdds_dpr"; 313 regulator-always-on; 314 }; 315 316 dcdc2_reg: regulator@1 { 317 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 318 regulator-name = "vdd_mpu"; 319 regulator-min-microvolt = <925000>; 320 regulator-max-microvolt = <1351500>; 321 regulator-boot-on; 322 regulator-always-on; 323 }; 324 325 dcdc3_reg: regulator@2 { 326 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 327 regulator-name = "vdd_core"; 328 regulator-min-microvolt = <925000>; 329 regulator-max-microvolt = <1150000>; 330 regulator-boot-on; 331 regulator-always-on; 332 }; 333 334 ldo1_reg: regulator@3 { 335 regulator-name = "vio,vrtc,vdds"; 336 regulator-always-on; 337 }; 338 339 ldo2_reg: regulator@4 { 340 regulator-name = "vdd_3v3aux"; 341 regulator-always-on; 342 }; 343 344 ldo3_reg: regulator@5 { 345 regulator-name = "vdd_1v8"; 346 regulator-always-on; 347 }; 348 349 ldo4_reg: regulator@6 { 350 regulator-name = "vdd_3v3a"; 351 regulator-always-on; 352 }; 353 }; 354}; 355 356&cpsw_emac0 { 357 phy-handle = <ðphy0>; 358 phy-mode = "mii"; 359}; 360 361&mac { 362 slaves = <1>; 363 pinctrl-names = "default", "sleep"; 364 pinctrl-0 = <&cpsw_default>; 365 pinctrl-1 = <&cpsw_sleep>; 366 status = "okay"; 367}; 368 369&davinci_mdio { 370 pinctrl-names = "default", "sleep"; 371 pinctrl-0 = <&davinci_mdio_default>; 372 pinctrl-1 = <&davinci_mdio_sleep>; 373 status = "okay"; 374 375 ethphy0: ethernet-phy@0 { 376 reg = <0>; 377 }; 378}; 379 380&mmc1 { 381 status = "okay"; 382 bus-width = <0x4>; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&mmc1_pins>; 385 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 386}; 387 388&aes { 389 status = "okay"; 390}; 391 392&sham { 393 status = "okay"; 394}; 395 396&rtc { 397 clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 398 clock-names = "ext-clk", "int-clk"; 399}; 400