1// SPDX-License-Identifier: GPL-2.0-or-later 2/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */ 3 4/* Based on code by myc_c335x.dts, MYiRtech.com */ 5/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ 6 7/dts-v1/; 8 9#include "am33xx.dtsi" 10 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/leds/common.h> 13 14/ { 15 model = "MYIR MYC-AM335X"; 16 compatible = "myir,myc-am335x", "ti,am33xx"; 17 18 cpus { 19 cpu@0 { 20 cpu0-supply = <&vdd_core>; 21 voltage-tolerance = <2>; 22 }; 23 }; 24 25 memory@80000000 { 26 device_type = "memory"; 27 reg = <0x80000000 0x10000000>; 28 }; 29 30 vdd_mod: vdd_mod_reg { 31 compatible = "regulator-fixed"; 32 regulator-name = "vdd-mod"; 33 regulator-always-on; 34 regulator-boot-on; 35 }; 36 37 vdd_core: vdd_core_reg { 38 compatible = "regulator-fixed"; 39 regulator-name = "vdd-core"; 40 regulator-always-on; 41 regulator-boot-on; 42 vin-supply = <&vdd_mod>; 43 }; 44 45 leds: leds { 46 compatible = "gpio-leds"; 47 pinctrl-names = "default"; 48 pinctrl-0 = <&led_mod_pins>; 49 50 led_mod: led_mod { 51 label = "module:user"; 52 gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; 53 color = <LED_COLOR_ID_GREEN>; 54 default-state = "off"; 55 panic-indicator; 56 }; 57 }; 58}; 59 60&cpsw_emac0 { 61 phy-handle = <&phy0>; 62 phy-mode = "rgmii-id"; 63}; 64 65&davinci_mdio { 66 pinctrl-names = "default", "sleep"; 67 pinctrl-0 = <&mdio_pins_default>; 68 pinctrl-1 = <&mdio_pins_sleep>; 69 status = "okay"; 70 71 phy0: ethernet-phy@4 { 72 reg = <4>; 73 }; 74}; 75 76&elm { 77 status = "okay"; 78}; 79 80&gpmc { 81 pinctrl-names = "default", "sleep"; 82 pinctrl-0 = <&nand_pins_default>; 83 pinctrl-1 = <&nand_pins_sleep>; 84 ranges = <0 0 0x8000000 0x1000000>; 85 status = "okay"; 86 87 nand0: nand@0,0 { 88 compatible = "ti,omap2-nand"; 89 reg = <0 0 4>; 90 interrupt-parent = <&gpmc>; 91 interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE_NONE>; 92 nand-bus-width = <8>; 93 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; 94 gpmc,device-width = <1>; 95 gpmc,sync-clk-ps = <0>; 96 gpmc,cs-on-ns = <0>; 97 gpmc,cs-rd-off-ns = <44>; 98 gpmc,cs-wr-off-ns = <44>; 99 gpmc,adv-on-ns = <6>; 100 gpmc,adv-rd-off-ns = <34>; 101 gpmc,adv-wr-off-ns = <44>; 102 gpmc,we-on-ns = <0>; 103 gpmc,we-off-ns = <40>; 104 gpmc,oe-on-ns = <0>; 105 gpmc,oe-off-ns = <54>; 106 gpmc,access-ns = <64>; 107 gpmc,rd-cycle-ns = <82>; 108 gpmc,wr-cycle-ns = <82>; 109 gpmc,bus-turnaround-ns = <0>; 110 gpmc,cycle2cycle-delay-ns = <0>; 111 gpmc,clk-activation-ns = <0>; 112 gpmc,wr-access-ns = <40>; 113 gpmc,wr-data-mux-bus-ns = <0>; 114 ti,elm-id = <&elm>; 115 ti,nand-ecc-opt = "bch8"; 116 117 #address-cells = <1>; 118 #size-cells = <1>; 119 }; 120}; 121 122&i2c0 { 123 pinctrl-names = "default", "gpio", "sleep"; 124 pinctrl-0 = <&i2c0_pins_default>; 125 pinctrl-1 = <&i2c0_pins_gpio>; 126 pinctrl-2 = <&i2c0_pins_sleep>; 127 clock-frequency = <400000>; 128 scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 129 sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 130 status = "okay"; 131 132 eeprom: eeprom@50 { 133 compatible = "atmel,24c32"; 134 reg = <0x50>; 135 pagesize = <32>; 136 vcc-supply = <&vdd_mod>; 137 }; 138}; 139 140&mac { 141 pinctrl-names = "default", "sleep"; 142 pinctrl-0 = <ð_slave1_pins_default>; 143 pinctrl-1 = <ð_slave1_pins_sleep>; 144 slaves = <1>; 145 status = "okay"; 146}; 147 148&rtc { 149 system-power-controller; 150}; 151 152&am33xx_pinmux { 153 mdio_pins_default: pinmux_mdio_pins_default { 154 pinctrl-single,pins = < 155 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data */ 156 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk */ 157 >; 158 }; 159 160 mdio_pins_sleep: pinmux_mdio_pins_sleep { 161 pinctrl-single,pins = < 162 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) 163 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) 164 >; 165 }; 166 167 eth_slave1_pins_default: pinmux_eth_slave1_pins_default { 168 pinctrl-single,pins = < 169 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tctl */ 170 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rctl */ 171 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td3 */ 172 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td2 */ 173 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td1 */ 174 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td0 */ 175 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tclk */ 176 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rclk */ 177 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd3 */ 178 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd2 */ 179 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd1 */ 180 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd0 */ 181 >; 182 }; 183 184 eth_slave1_pins_sleep: pinmux_eth_slave1_pins_sleep { 185 pinctrl-single,pins = < 186 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 187 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) 188 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 189 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 190 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 191 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 192 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 193 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 194 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 195 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 196 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 197 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 198 >; 199 }; 200 201 i2c0_pins_default: pinmux_i2c0_pins_default { 202 pinctrl-single,pins = < 203 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SDA */ 204 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SCL */ 205 >; 206 }; 207 208 i2c0_pins_gpio: pinmux_i2c0_pins_gpio { 209 pinctrl-single,pins = < 210 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE7) /* gpio3[5] */ 211 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE7) /* gpio3[6] */ 212 >; 213 }; 214 215 i2c0_pins_sleep: pinmux_i2c0_pins_sleep { 216 pinctrl-single,pins = < 217 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE7) 218 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE7) 219 >; 220 }; 221 222 led_mod_pins: pinmux_led_mod_pins { 223 pinctrl-single,pins = < 224 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpio3[18] */ 225 >; 226 }; 227 228 nand_pins_default: pinmux_nand_pins_default { 229 pinctrl-single,pins = < 230 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0 */ 231 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1 */ 232 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2 */ 233 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3 */ 234 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4 */ 235 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5 */ 236 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6 */ 237 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7 */ 238 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0 */ 239 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio0[31] */ 240 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0 */ 241 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale */ 242 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren */ 243 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen */ 244 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle */ 245 >; 246 }; 247 248 nand_pins_sleep: pinmux_nand_pins_sleep { 249 pinctrl-single,pins = < 250 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 251 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 252 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 253 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 254 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE7) 255 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE7) 256 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE7) 257 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE7) 258 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) 259 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) 260 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT_PULLDOWN, MUX_MODE7) 261 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) 262 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) 263 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT_PULLDOWN, MUX_MODE7) 264 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) 265 >; 266 }; 267}; 268