1&l4_wkup { /* 0x44c00000 */ 2 compatible = "ti,am33xx-l4-wkup", "simple-pm-bus"; 3 power-domains = <&prm_wkup>; 4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; 5 clock-names = "fck"; 6 reg = <0x44c00000 0x800>, 7 <0x44c00800 0x800>, 8 <0x44c01000 0x400>, 9 <0x44c01400 0x400>; 10 reg-names = "ap", "la", "ia0", "ia1"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 16 17 segment@0 { /* 0x44c00000 */ 18 compatible = "simple-pm-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 22 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 23 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 24 <0x00001400 0x00001400 0x000400>; /* ap 3 */ 25 }; 26 27 segment@100000 { /* 0x44d00000 */ 28 compatible = "simple-pm-bus"; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ 32 <0x00004000 0x00104000 0x001000>, /* ap 5 */ 33 <0x00080000 0x00180000 0x002000>, /* ap 6 */ 34 <0x00082000 0x00182000 0x001000>; /* ap 7 */ 35 36 target-module@0 { /* 0x44d00000, ap 4 28.0 */ 37 compatible = "ti,sysc-omap4", "ti,sysc"; 38 reg = <0x0 0x4>; 39 reg-names = "rev"; 40 clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; 41 clock-names = "fck"; 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges = <0x00000000 0x00000000 0x4000>, 45 <0x00080000 0x00080000 0x2000>; 46 47 wkup_m3: cpu@0 { 48 compatible = "ti,am3352-wkup-m3"; 49 reg = <0x00000000 0x4000>, 50 <0x00080000 0x2000>; 51 reg-names = "umem", "dmem"; 52 resets = <&prm_wkup 3>; 53 reset-names = "rstctrl"; 54 ti,pm-firmware = "am335x-pm-firmware.elf"; 55 }; 56 }; 57 }; 58 59 segment@200000 { /* 0x44e00000 */ 60 compatible = "simple-pm-bus"; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ 64 <0x00002000 0x00202000 0x001000>, /* ap 9 */ 65 <0x00003000 0x00203000 0x001000>, /* ap 10 */ 66 <0x00004000 0x00204000 0x001000>, /* ap 11 */ 67 <0x00005000 0x00205000 0x001000>, /* ap 12 */ 68 <0x00006000 0x00206000 0x001000>, /* ap 13 */ 69 <0x00007000 0x00207000 0x001000>, /* ap 14 */ 70 <0x00008000 0x00208000 0x001000>, /* ap 15 */ 71 <0x00009000 0x00209000 0x001000>, /* ap 16 */ 72 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ 73 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ 74 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ 75 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ 76 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ 77 <0x00010000 0x00210000 0x010000>, /* ap 22 */ 78 <0x00020000 0x00220000 0x010000>, /* ap 23 */ 79 <0x00030000 0x00230000 0x001000>, /* ap 24 */ 80 <0x00031000 0x00231000 0x001000>, /* ap 25 */ 81 <0x00032000 0x00232000 0x001000>, /* ap 26 */ 82 <0x00033000 0x00233000 0x001000>, /* ap 27 */ 83 <0x00034000 0x00234000 0x001000>, /* ap 28 */ 84 <0x00035000 0x00235000 0x001000>, /* ap 29 */ 85 <0x00036000 0x00236000 0x001000>, /* ap 30 */ 86 <0x00037000 0x00237000 0x001000>, /* ap 31 */ 87 <0x00038000 0x00238000 0x001000>, /* ap 32 */ 88 <0x00039000 0x00239000 0x001000>, /* ap 33 */ 89 <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ 90 <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ 91 <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ 92 <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ 93 <0x00040000 0x00240000 0x040000>, /* ap 38 */ 94 <0x00080000 0x00280000 0x001000>; /* ap 39 */ 95 96 target-module@0 { /* 0x44e00000, ap 8 58.0 */ 97 compatible = "ti,sysc-omap4", "ti,sysc"; 98 reg = <0 0x4>; 99 reg-names = "rev"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges = <0x0 0x0 0x2000>; 103 104 prcm: prcm@0 { 105 compatible = "ti,am3-prcm", "simple-bus"; 106 reg = <0 0x2000>; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges = <0 0 0x2000>; 110 111 prcm_clocks: clocks { 112 #address-cells = <1>; 113 #size-cells = <0>; 114 }; 115 116 prcm_clockdomains: clockdomains { 117 }; 118 }; 119 }; 120 121 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ 122 compatible = "ti,sysc"; 123 status = "disabled"; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 ranges = <0x0 0x3000 0x1000>; 127 }; 128 129 target-module@5000 { /* 0x44e05000, ap 12 30.0 */ 130 compatible = "ti,sysc"; 131 status = "disabled"; 132 #address-cells = <1>; 133 #size-cells = <1>; 134 ranges = <0x0 0x5000 0x1000>; 135 }; 136 137 gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ 138 compatible = "ti,sysc-omap2", "ti,sysc"; 139 reg = <0x7000 0x4>, 140 <0x7010 0x4>, 141 <0x7114 0x4>; 142 reg-names = "rev", "sysc", "syss"; 143 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 144 SYSC_OMAP2_SOFTRESET | 145 SYSC_OMAP2_AUTOIDLE)>; 146 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 147 <SYSC_IDLE_NO>, 148 <SYSC_IDLE_SMART>, 149 <SYSC_IDLE_SMART_WKUP>; 150 ti,syss-mask = <1>; 151 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 152 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, 153 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; 154 clock-names = "fck", "dbclk"; 155 #address-cells = <1>; 156 #size-cells = <1>; 157 ranges = <0x0 0x7000 0x1000>; 158 159 gpio0: gpio@0 { 160 compatible = "ti,omap4-gpio"; 161 gpio-ranges = <&am33xx_pinmux 0 82 8>, 162 <&am33xx_pinmux 8 52 4>, 163 <&am33xx_pinmux 12 94 4>, 164 <&am33xx_pinmux 16 71 2>, 165 <&am33xx_pinmux 18 135 1>, 166 <&am33xx_pinmux 19 108 2>, 167 <&am33xx_pinmux 21 73 1>, 168 <&am33xx_pinmux 22 8 2>, 169 <&am33xx_pinmux 26 10 2>, 170 <&am33xx_pinmux 28 74 1>, 171 <&am33xx_pinmux 29 81 1>, 172 <&am33xx_pinmux 30 28 2>; 173 gpio-controller; 174 #gpio-cells = <2>; 175 interrupt-controller; 176 #interrupt-cells = <2>; 177 reg = <0x0 0x1000>; 178 interrupts = <96>; 179 }; 180 }; 181 182 target-module@9000 { /* 0x44e09000, ap 16 04.0 */ 183 compatible = "ti,sysc-omap2", "ti,sysc"; 184 reg = <0x9050 0x4>, 185 <0x9054 0x4>, 186 <0x9058 0x4>; 187 reg-names = "rev", "sysc", "syss"; 188 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 189 SYSC_OMAP2_SOFTRESET | 190 SYSC_OMAP2_AUTOIDLE)>; 191 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 192 <SYSC_IDLE_NO>, 193 <SYSC_IDLE_SMART>, 194 <SYSC_IDLE_SMART_WKUP>; 195 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 196 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; 197 clock-names = "fck"; 198 #address-cells = <1>; 199 #size-cells = <1>; 200 ranges = <0x0 0x9000 0x1000>; 201 202 uart0: serial@0 { 203 compatible = "ti,am3352-uart", "ti,omap3-uart"; 204 clock-frequency = <48000000>; 205 reg = <0x0 0x1000>; 206 interrupts = <72>; 207 status = "disabled"; 208 dmas = <&edma 26 0>, <&edma 27 0>; 209 dma-names = "tx", "rx"; 210 }; 211 }; 212 213 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ 214 compatible = "ti,sysc-omap2", "ti,sysc"; 215 reg = <0xb000 0x8>, 216 <0xb010 0x8>, 217 <0xb090 0x8>; 218 reg-names = "rev", "sysc", "syss"; 219 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 220 SYSC_OMAP2_ENAWAKEUP | 221 SYSC_OMAP2_SOFTRESET | 222 SYSC_OMAP2_AUTOIDLE)>; 223 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 224 <SYSC_IDLE_NO>, 225 <SYSC_IDLE_SMART>, 226 <SYSC_IDLE_SMART_WKUP>; 227 ti,syss-mask = <1>; 228 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 229 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; 230 clock-names = "fck"; 231 #address-cells = <1>; 232 #size-cells = <1>; 233 ranges = <0x0 0xb000 0x1000>; 234 235 i2c0: i2c@0 { 236 compatible = "ti,omap4-i2c"; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 reg = <0x0 0x1000>; 240 interrupts = <70>; 241 status = "disabled"; 242 }; 243 }; 244 245 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ 246 compatible = "ti,sysc-omap4", "ti,sysc"; 247 reg = <0xd000 0x4>, 248 <0xd010 0x4>; 249 reg-names = "rev", "sysc"; 250 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 251 <SYSC_IDLE_NO>, 252 <SYSC_IDLE_SMART>, 253 <SYSC_IDLE_SMART_WKUP>; 254 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 255 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; 256 clock-names = "fck"; 257 #address-cells = <1>; 258 #size-cells = <1>; 259 ranges = <0x00000000 0x0000d000 0x00001000>, 260 <0x00001000 0x0000e000 0x00001000>; 261 262 tscadc: tscadc@0 { 263 compatible = "ti,am3359-tscadc"; 264 reg = <0x0 0x1000>; 265 interrupts = <16>; 266 status = "disabled"; 267 dmas = <&edma 53 0>, <&edma 57 0>; 268 dma-names = "fifo0", "fifo1"; 269 270 tsc { 271 compatible = "ti,am3359-tsc"; 272 }; 273 am335x_adc: adc { 274 #io-channel-cells = <1>; 275 compatible = "ti,am3359-adc"; 276 }; 277 }; 278 }; 279 280 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ 281 compatible = "ti,sysc-omap4", "ti,sysc"; 282 reg = <0x10000 0x4>; 283 reg-names = "rev"; 284 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_CONTROL_CLKCTRL 0>; 285 clock-names = "fck"; 286 ti,no-idle; 287 #address-cells = <1>; 288 #size-cells = <1>; 289 ranges = <0x00000000 0x00010000 0x00010000>, 290 <0x00010000 0x00020000 0x00010000>; 291 292 scm: scm@0 { 293 compatible = "ti,am3-scm", "simple-bus"; 294 reg = <0x0 0x2000>; 295 #address-cells = <1>; 296 #size-cells = <1>; 297 #pinctrl-cells = <1>; 298 ranges = <0 0 0x2000>; 299 300 am33xx_pinmux: pinmux@800 { 301 compatible = "pinctrl-single"; 302 reg = <0x800 0x238>; 303 #pinctrl-cells = <2>; 304 pinctrl-single,register-width = <32>; 305 pinctrl-single,function-mask = <0x7f>; 306 }; 307 308 scm_conf: scm_conf@0 { 309 compatible = "syscon", "simple-bus"; 310 reg = <0x0 0x800>; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 ranges = <0 0 0x800>; 314 315 phy_gmii_sel: phy-gmii-sel { 316 compatible = "ti,am3352-phy-gmii-sel"; 317 reg = <0x650 0x4>; 318 #phy-cells = <2>; 319 }; 320 321 scm_clocks: clocks { 322 #address-cells = <1>; 323 #size-cells = <0>; 324 }; 325 }; 326 327 usb_ctrl_mod: control@620 { 328 compatible = "ti,am335x-usb-ctrl-module"; 329 reg = <0x620 0x10>, 330 <0x648 0x4>; 331 reg-names = "phy_ctrl", "wakeup"; 332 }; 333 334 wkup_m3_ipc: wkup_m3_ipc@1324 { 335 compatible = "ti,am3352-wkup-m3-ipc"; 336 reg = <0x1324 0x24>; 337 interrupts = <78>; 338 ti,rproc = <&wkup_m3>; 339 mboxes = <&mailbox &mbox_wkupm3>; 340 }; 341 342 edma_xbar: dma-router@f90 { 343 compatible = "ti,am335x-edma-crossbar"; 344 reg = <0xf90 0x40>; 345 #dma-cells = <3>; 346 dma-requests = <32>; 347 dma-masters = <&edma>; 348 }; 349 350 scm_clockdomains: clockdomains { 351 }; 352 }; 353 }; 354 355 timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */ 356 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 357 reg = <0x31000 0x4>, 358 <0x31010 0x4>, 359 <0x31014 0x4>; 360 reg-names = "rev", "sysc", "syss"; 361 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 362 SYSC_OMAP2_SOFTRESET | 363 SYSC_OMAP2_AUTOIDLE)>; 364 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 365 <SYSC_IDLE_NO>, 366 <SYSC_IDLE_SMART>; 367 ti,syss-mask = <1>; 368 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 369 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; 370 clock-names = "fck"; 371 #address-cells = <1>; 372 #size-cells = <1>; 373 ranges = <0x0 0x31000 0x1000>; 374 375 timer1: timer@0 { 376 compatible = "ti,am335x-timer-1ms"; 377 reg = <0x0 0x400>; 378 interrupts = <67>; 379 ti,timer-alwon; 380 clocks = <&timer1_fck>; 381 clock-names = "fck"; 382 }; 383 }; 384 385 target-module@33000 { /* 0x44e33000, ap 27 18.0 */ 386 compatible = "ti,sysc"; 387 status = "disabled"; 388 #address-cells = <1>; 389 #size-cells = <1>; 390 ranges = <0x0 0x33000 0x1000>; 391 }; 392 393 target-module@35000 { /* 0x44e35000, ap 29 50.0 */ 394 compatible = "ti,sysc-omap2", "ti,sysc"; 395 reg = <0x35000 0x4>, 396 <0x35010 0x4>, 397 <0x35014 0x4>; 398 reg-names = "rev", "sysc", "syss"; 399 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 400 SYSC_OMAP2_SOFTRESET)>; 401 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 402 <SYSC_IDLE_NO>, 403 <SYSC_IDLE_SMART>, 404 <SYSC_IDLE_SMART_WKUP>; 405 ti,syss-mask = <1>; 406 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 407 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; 408 clock-names = "fck"; 409 #address-cells = <1>; 410 #size-cells = <1>; 411 ranges = <0x0 0x35000 0x1000>; 412 413 wdt2: wdt@0 { 414 compatible = "ti,omap3-wdt"; 415 reg = <0x0 0x1000>; 416 interrupts = <91>; 417 }; 418 }; 419 420 target-module@37000 { /* 0x44e37000, ap 31 08.0 */ 421 compatible = "ti,sysc"; 422 status = "disabled"; 423 #address-cells = <1>; 424 #size-cells = <1>; 425 ranges = <0x0 0x37000 0x1000>; 426 }; 427 428 target-module@39000 { /* 0x44e39000, ap 33 02.0 */ 429 compatible = "ti,sysc"; 430 status = "disabled"; 431 #address-cells = <1>; 432 #size-cells = <1>; 433 ranges = <0x0 0x39000 0x1000>; 434 }; 435 436 target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ 437 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 438 reg = <0x3e074 0x4>, 439 <0x3e078 0x4>; 440 reg-names = "rev", "sysc"; 441 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 442 <SYSC_IDLE_NO>, 443 <SYSC_IDLE_SMART>, 444 <SYSC_IDLE_SMART_WKUP>; 445 /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ 446 power-domains = <&prm_rtc>; 447 clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; 448 clock-names = "fck"; 449 #address-cells = <1>; 450 #size-cells = <1>; 451 ranges = <0x0 0x3e000 0x1000>; 452 453 rtc: rtc@0 { 454 compatible = "ti,am3352-rtc", "ti,da830-rtc"; 455 reg = <0x0 0x1000>; 456 interrupts = <75 457 76>; 458 }; 459 }; 460 461 target-module@40000 { /* 0x44e40000, ap 38 68.0 */ 462 compatible = "ti,sysc"; 463 status = "disabled"; 464 #address-cells = <1>; 465 #size-cells = <1>; 466 ranges = <0x0 0x40000 0x40000>; 467 }; 468 }; 469}; 470 471&l4_fw { /* 0x47c00000 */ 472 compatible = "ti,am33xx-l4-fw", "simple-bus"; 473 reg = <0x47c00000 0x800>, 474 <0x47c00800 0x800>, 475 <0x47c01000 0x400>; 476 reg-names = "ap", "la", "ia0"; 477 #address-cells = <1>; 478 #size-cells = <1>; 479 ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ 480 481 segment@0 { /* 0x47c00000 */ 482 compatible = "simple-bus"; 483 #address-cells = <1>; 484 #size-cells = <1>; 485 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 486 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 487 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 488 <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ 489 <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ 490 <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ 491 <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ 492 <0x00010000 0x00010000 0x001000>, /* ap 7 */ 493 <0x00011000 0x00011000 0x001000>, /* ap 8 */ 494 <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ 495 <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ 496 <0x00024000 0x00024000 0x001000>, /* ap 11 */ 497 <0x00025000 0x00025000 0x001000>, /* ap 12 */ 498 <0x00026000 0x00026000 0x001000>, /* ap 13 */ 499 <0x00027000 0x00027000 0x001000>, /* ap 14 */ 500 <0x00030000 0x00030000 0x001000>, /* ap 15 */ 501 <0x00031000 0x00031000 0x001000>, /* ap 16 */ 502 <0x00038000 0x00038000 0x001000>, /* ap 17 */ 503 <0x00039000 0x00039000 0x001000>, /* ap 18 */ 504 <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ 505 <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ 506 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 507 <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ 508 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ 509 <0x00040000 0x00040000 0x001000>, /* ap 24 */ 510 <0x00046000 0x00046000 0x001000>, /* ap 25 */ 511 <0x00047000 0x00047000 0x001000>, /* ap 26 */ 512 <0x00044000 0x00044000 0x001000>, /* ap 27 */ 513 <0x00045000 0x00045000 0x001000>, /* ap 28 */ 514 <0x00028000 0x00028000 0x001000>, /* ap 29 */ 515 <0x00029000 0x00029000 0x001000>, /* ap 30 */ 516 <0x00032000 0x00032000 0x001000>, /* ap 31 */ 517 <0x00033000 0x00033000 0x001000>, /* ap 32 */ 518 <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ 519 <0x00041000 0x00041000 0x001000>, /* ap 34 */ 520 <0x00042000 0x00042000 0x001000>, /* ap 35 */ 521 <0x00043000 0x00043000 0x001000>, /* ap 36 */ 522 <0x00014000 0x00014000 0x001000>, /* ap 37 */ 523 <0x00015000 0x00015000 0x001000>; /* ap 38 */ 524 525 target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ 526 compatible = "ti,sysc"; 527 status = "disabled"; 528 #address-cells = <1>; 529 #size-cells = <1>; 530 ranges = <0x0 0xc000 0x1000>; 531 }; 532 533 target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ 534 compatible = "ti,sysc"; 535 status = "disabled"; 536 #address-cells = <1>; 537 #size-cells = <1>; 538 ranges = <0x0 0xe000 0x1000>; 539 }; 540 541 target-module@10000 { /* 0x47c10000, ap 7 20.0 */ 542 compatible = "ti,sysc"; 543 status = "disabled"; 544 #address-cells = <1>; 545 #size-cells = <1>; 546 ranges = <0x0 0x10000 0x1000>; 547 }; 548 549 target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ 550 compatible = "ti,sysc"; 551 status = "disabled"; 552 #address-cells = <1>; 553 #size-cells = <1>; 554 ranges = <0x0 0x14000 0x1000>; 555 }; 556 557 target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ 558 compatible = "ti,sysc"; 559 status = "disabled"; 560 #address-cells = <1>; 561 #size-cells = <1>; 562 ranges = <0x0 0x1a000 0x1000>; 563 }; 564 565 target-module@24000 { /* 0x47c24000, ap 11 28.0 */ 566 compatible = "ti,sysc"; 567 status = "disabled"; 568 #address-cells = <1>; 569 #size-cells = <1>; 570 ranges = <0x0 0x24000 0x1000>; 571 }; 572 573 target-module@26000 { /* 0x47c26000, ap 13 30.0 */ 574 compatible = "ti,sysc"; 575 status = "disabled"; 576 #address-cells = <1>; 577 #size-cells = <1>; 578 ranges = <0x0 0x26000 0x1000>; 579 }; 580 581 target-module@28000 { /* 0x47c28000, ap 29 40.0 */ 582 compatible = "ti,sysc"; 583 status = "disabled"; 584 #address-cells = <1>; 585 #size-cells = <1>; 586 ranges = <0x0 0x28000 0x1000>; 587 }; 588 589 target-module@30000 { /* 0x47c30000, ap 15 14.0 */ 590 compatible = "ti,sysc"; 591 status = "disabled"; 592 #address-cells = <1>; 593 #size-cells = <1>; 594 ranges = <0x0 0x30000 0x1000>; 595 }; 596 597 target-module@32000 { /* 0x47c32000, ap 31 06.0 */ 598 compatible = "ti,sysc"; 599 status = "disabled"; 600 #address-cells = <1>; 601 #size-cells = <1>; 602 ranges = <0x0 0x32000 0x1000>; 603 }; 604 605 target-module@38000 { /* 0x47c38000, ap 17 18.0 */ 606 compatible = "ti,sysc"; 607 status = "disabled"; 608 #address-cells = <1>; 609 #size-cells = <1>; 610 ranges = <0x0 0x38000 0x1000>; 611 }; 612 613 target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ 614 compatible = "ti,sysc"; 615 status = "disabled"; 616 #address-cells = <1>; 617 #size-cells = <1>; 618 ranges = <0x0 0x3a000 0x1000>; 619 }; 620 621 target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ 622 compatible = "ti,sysc"; 623 status = "disabled"; 624 #address-cells = <1>; 625 #size-cells = <1>; 626 ranges = <0x0 0x3c000 0x1000>; 627 }; 628 629 target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ 630 compatible = "ti,sysc"; 631 status = "disabled"; 632 #address-cells = <1>; 633 #size-cells = <1>; 634 ranges = <0x0 0x3e000 0x1000>; 635 }; 636 637 target-module@40000 { /* 0x47c40000, ap 24 02.0 */ 638 compatible = "ti,sysc"; 639 status = "disabled"; 640 #address-cells = <1>; 641 #size-cells = <1>; 642 ranges = <0x0 0x40000 0x1000>; 643 }; 644 645 target-module@42000 { /* 0x47c42000, ap 35 34.0 */ 646 compatible = "ti,sysc"; 647 status = "disabled"; 648 #address-cells = <1>; 649 #size-cells = <1>; 650 ranges = <0x0 0x42000 0x1000>; 651 }; 652 653 target-module@44000 { /* 0x47c44000, ap 27 24.0 */ 654 compatible = "ti,sysc"; 655 status = "disabled"; 656 #address-cells = <1>; 657 #size-cells = <1>; 658 ranges = <0x0 0x44000 0x1000>; 659 }; 660 661 target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ 662 compatible = "ti,sysc"; 663 status = "disabled"; 664 #address-cells = <1>; 665 #size-cells = <1>; 666 ranges = <0x0 0x46000 0x1000>; 667 }; 668 }; 669}; 670 671&l4_fast { /* 0x4a000000 */ 672 compatible = "ti,am33xx-l4-fast", "simple-pm-bus"; 673 power-domains = <&prm_per>; 674 clocks = <&l4hs_clkctrl AM3_L4HS_L4_HS_CLKCTRL 0>; 675 clock-names = "fck"; 676 reg = <0x4a000000 0x800>, 677 <0x4a000800 0x800>, 678 <0x4a001000 0x400>; 679 reg-names = "ap", "la", "ia0"; 680 #address-cells = <1>; 681 #size-cells = <1>; 682 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ 683 684 segment@0 { /* 0x4a000000 */ 685 compatible = "simple-pm-bus"; 686 #address-cells = <1>; 687 #size-cells = <1>; 688 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 689 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 690 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 691 <0x00100000 0x00100000 0x008000>, /* ap 3 */ 692 <0x00108000 0x00108000 0x001000>, /* ap 4 */ 693 <0x00180000 0x00180000 0x020000>, /* ap 5 */ 694 <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ 695 <0x00200000 0x00200000 0x080000>, /* ap 7 */ 696 <0x00280000 0x00280000 0x001000>, /* ap 8 */ 697 <0x00300000 0x00300000 0x080000>, /* ap 9 */ 698 <0x00380000 0x00380000 0x001000>; /* ap 10 */ 699 700 target-module@100000 { /* 0x4a100000, ap 3 08.0 */ 701 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 702 reg = <0x101200 0x4>, 703 <0x101208 0x4>, 704 <0x101204 0x4>; 705 reg-names = "rev", "sysc", "syss"; 706 ti,sysc-mask = <0>; 707 ti,sysc-midle = <SYSC_IDLE_FORCE>, 708 <SYSC_IDLE_NO>; 709 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 710 <SYSC_IDLE_NO>; 711 ti,syss-mask = <1>; 712 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 713 clock-names = "fck"; 714 #address-cells = <1>; 715 #size-cells = <1>; 716 ranges = <0x0 0x100000 0x8000>; 717 718 mac: ethernet@0 { 719 compatible = "ti,am335x-cpsw","ti,cpsw"; 720 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; 721 clock-names = "fck", "cpts"; 722 cpdma_channels = <8>; 723 ale_entries = <1024>; 724 bd_ram_size = <0x2000>; 725 mac_control = <0x20>; 726 slaves = <2>; 727 active_slave = <0>; 728 cpts_clock_mult = <0x80000000>; 729 cpts_clock_shift = <29>; 730 reg = <0x0 0x800 731 0x1200 0x100>; 732 #address-cells = <1>; 733 #size-cells = <1>; 734 /* 735 * c0_rx_thresh_pend 736 * c0_rx_pend 737 * c0_tx_pend 738 * c0_misc_pend 739 */ 740 interrupts = <40 41 42 43>; 741 ranges = <0 0 0x8000>; 742 syscon = <&scm_conf>; 743 status = "disabled"; 744 745 davinci_mdio: mdio@1000 { 746 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 747 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 748 clock-names = "fck"; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 bus_freq = <1000000>; 752 reg = <0x1000 0x100>; 753 status = "disabled"; 754 }; 755 756 cpsw_emac0: slave@200 { 757 /* Filled in by U-Boot */ 758 mac-address = [ 00 00 00 00 00 00 ]; 759 phys = <&phy_gmii_sel 1 1>; 760 }; 761 762 cpsw_emac1: slave@300 { 763 /* Filled in by U-Boot */ 764 mac-address = [ 00 00 00 00 00 00 ]; 765 phys = <&phy_gmii_sel 2 1>; 766 }; 767 }; 768 769 mac_sw: switch@0 { 770 compatible = "ti,am335x-cpsw-switch", "ti,cpsw-switch"; 771 reg = <0x0 0x4000>; 772 ranges = <0 0 0x4000>; 773 clocks = <&cpsw_125mhz_gclk>; 774 clock-names = "fck"; 775 #address-cells = <1>; 776 #size-cells = <1>; 777 syscon = <&scm_conf>; 778 status = "disabled"; 779 780 interrupts = <40 41 42 43>; 781 interrupt-names = "rx_thresh", "rx", "tx", "misc"; 782 783 ethernet-ports { 784 #address-cells = <1>; 785 #size-cells = <0>; 786 787 cpsw_port1: port@1 { 788 reg = <1>; 789 label = "port1"; 790 mac-address = [ 00 00 00 00 00 00 ]; 791 phys = <&phy_gmii_sel 1 1>; 792 }; 793 794 cpsw_port2: port@2 { 795 reg = <2>; 796 label = "port2"; 797 mac-address = [ 00 00 00 00 00 00 ]; 798 phys = <&phy_gmii_sel 2 1>; 799 }; 800 }; 801 802 davinci_mdio_sw: mdio@1000 { 803 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 804 clocks = <&cpsw_125mhz_gclk>; 805 clock-names = "fck"; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 bus_freq = <1000000>; 809 reg = <0x1000 0x100>; 810 }; 811 812 cpts { 813 clocks = <&cpsw_cpts_rft_clk>; 814 clock-names = "cpts"; 815 }; 816 }; 817 }; 818 819 target-module@180000 { /* 0x4a180000, ap 5 10.0 */ 820 compatible = "ti,sysc"; 821 status = "disabled"; 822 #address-cells = <1>; 823 #size-cells = <1>; 824 ranges = <0x0 0x180000 0x20000>; 825 }; 826 827 target-module@200000 { /* 0x4a200000, ap 7 02.0 */ 828 compatible = "ti,sysc"; 829 status = "disabled"; 830 #address-cells = <1>; 831 #size-cells = <1>; 832 ranges = <0x0 0x200000 0x80000>; 833 }; 834 835 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ 836 compatible = "ti,sysc-pruss", "ti,sysc"; 837 reg = <0x326000 0x4>, 838 <0x326004 0x4>; 839 reg-names = "rev", "sysc"; 840 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | 841 SYSC_PRUSS_SUB_MWAIT)>; 842 ti,sysc-midle = <SYSC_IDLE_FORCE>, 843 <SYSC_IDLE_NO>, 844 <SYSC_IDLE_SMART>; 845 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 846 <SYSC_IDLE_NO>, 847 <SYSC_IDLE_SMART>; 848 clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>; 849 clock-names = "fck"; 850 resets = <&prm_per 1>; 851 reset-names = "rstctrl"; 852 #address-cells = <1>; 853 #size-cells = <1>; 854 ranges = <0x0 0x300000 0x80000>; 855 status = "disabled"; 856 }; 857 }; 858}; 859 860&l4_mpuss { /* 0x4b140000 */ 861 compatible = "ti,am33xx-l4-mpuss", "simple-bus"; 862 reg = <0x4b144400 0x100>, 863 <0x4b144800 0x400>; 864 reg-names = "la", "ap"; 865 #address-cells = <1>; 866 #size-cells = <1>; 867 ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ 868 869 segment@0 { /* 0x4b140000 */ 870 compatible = "simple-bus"; 871 #address-cells = <1>; 872 #size-cells = <1>; 873 ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ 874 <0x00001000 0x00001000 0x001000>, /* ap 1 */ 875 <0x00002000 0x00002000 0x001000>, /* ap 2 */ 876 <0x00004000 0x00004000 0x000400>, /* ap 3 */ 877 <0x00005000 0x00005000 0x000400>, /* ap 4 */ 878 <0x00000000 0x00000000 0x001000>, /* ap 5 */ 879 <0x00003000 0x00003000 0x001000>, /* ap 6 */ 880 <0x00000800 0x00000800 0x000800>; /* ap 7 */ 881 882 target-module@0 { /* 0x4b140000, ap 5 02.2 */ 883 compatible = "ti,sysc"; 884 status = "disabled"; 885 #address-cells = <1>; 886 #size-cells = <1>; 887 ranges = <0x00000000 0x00000000 0x00001000>, 888 <0x00001000 0x00001000 0x00001000>, 889 <0x00002000 0x00002000 0x00001000>; 890 }; 891 892 target-module@3000 { /* 0x4b143000, ap 6 04.0 */ 893 compatible = "ti,sysc"; 894 status = "disabled"; 895 #address-cells = <1>; 896 #size-cells = <1>; 897 ranges = <0x0 0x3000 0x1000>; 898 }; 899 }; 900}; 901 902&l4_per { /* 0x48000000 */ 903 compatible = "ti,am33xx-l4-per", "simple-pm-bus"; 904 power-domains = <&prm_per>; 905 clocks = <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; 906 clock-names = "fck"; 907 reg = <0x48000000 0x800>, 908 <0x48000800 0x800>, 909 <0x48001000 0x400>, 910 <0x48001400 0x400>, 911 <0x48001800 0x400>, 912 <0x48001c00 0x400>; 913 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 914 #address-cells = <1>; 915 #size-cells = <1>; 916 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ 917 <0x00100000 0x48100000 0x100000>, /* segment 1 */ 918 <0x00200000 0x48200000 0x100000>, /* segment 2 */ 919 <0x00300000 0x48300000 0x100000>, /* segment 3 */ 920 <0x46000000 0x46000000 0x400000>, /* l3 data port */ 921 <0x46400000 0x46400000 0x400000>; /* l3 data port */ 922 923 segment@0 { /* 0x48000000 */ 924 compatible = "simple-pm-bus"; 925 #address-cells = <1>; 926 #size-cells = <1>; 927 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 928 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 929 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 930 <0x00001400 0x00001400 0x000400>, /* ap 3 */ 931 <0x00001800 0x00001800 0x000400>, /* ap 4 */ 932 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ 933 <0x00008000 0x00008000 0x001000>, /* ap 6 */ 934 <0x00009000 0x00009000 0x001000>, /* ap 7 */ 935 <0x00016000 0x00016000 0x001000>, /* ap 8 */ 936 <0x00017000 0x00017000 0x001000>, /* ap 9 */ 937 <0x00022000 0x00022000 0x001000>, /* ap 10 */ 938 <0x00023000 0x00023000 0x001000>, /* ap 11 */ 939 <0x00024000 0x00024000 0x001000>, /* ap 12 */ 940 <0x00025000 0x00025000 0x001000>, /* ap 13 */ 941 <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ 942 <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ 943 <0x00038000 0x00038000 0x002000>, /* ap 16 */ 944 <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ 945 <0x00014000 0x00014000 0x001000>, /* ap 18 */ 946 <0x00015000 0x00015000 0x001000>, /* ap 19 */ 947 <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ 948 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 949 <0x00040000 0x00040000 0x001000>, /* ap 22 */ 950 <0x00041000 0x00041000 0x001000>, /* ap 23 */ 951 <0x00042000 0x00042000 0x001000>, /* ap 24 */ 952 <0x00043000 0x00043000 0x001000>, /* ap 25 */ 953 <0x00044000 0x00044000 0x001000>, /* ap 26 */ 954 <0x00045000 0x00045000 0x001000>, /* ap 27 */ 955 <0x00046000 0x00046000 0x001000>, /* ap 28 */ 956 <0x00047000 0x00047000 0x001000>, /* ap 29 */ 957 <0x00048000 0x00048000 0x001000>, /* ap 30 */ 958 <0x00049000 0x00049000 0x001000>, /* ap 31 */ 959 <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ 960 <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ 961 <0x00050000 0x00050000 0x002000>, /* ap 34 */ 962 <0x00052000 0x00052000 0x001000>, /* ap 35 */ 963 <0x00060000 0x00060000 0x001000>, /* ap 36 */ 964 <0x00061000 0x00061000 0x001000>, /* ap 37 */ 965 <0x00080000 0x00080000 0x010000>, /* ap 38 */ 966 <0x00090000 0x00090000 0x001000>, /* ap 39 */ 967 <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ 968 <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ 969 <0x00030000 0x00030000 0x001000>, /* ap 77 */ 970 <0x00031000 0x00031000 0x001000>, /* ap 78 */ 971 <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ 972 <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ 973 <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ 974 <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ 975 <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ 976 <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ 977 <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ 978 <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ 979 <0x46000000 0x46000000 0x400000>, /* l3 data port */ 980 <0x46400000 0x46400000 0x400000>; /* l3 data port */ 981 982 target-module@8000 { /* 0x48008000, ap 6 10.0 */ 983 compatible = "ti,sysc"; 984 status = "disabled"; 985 #address-cells = <1>; 986 #size-cells = <1>; 987 ranges = <0x0 0x8000 0x1000>; 988 }; 989 990 target-module@14000 { /* 0x48014000, ap 18 58.0 */ 991 compatible = "ti,sysc"; 992 status = "disabled"; 993 #address-cells = <1>; 994 #size-cells = <1>; 995 ranges = <0x0 0x14000 0x1000>; 996 }; 997 998 target-module@16000 { /* 0x48016000, ap 8 3c.0 */ 999 compatible = "ti,sysc"; 1000 status = "disabled"; 1001 #address-cells = <1>; 1002 #size-cells = <1>; 1003 ranges = <0x0 0x16000 0x1000>; 1004 }; 1005 1006 target-module@22000 { /* 0x48022000, ap 10 12.0 */ 1007 compatible = "ti,sysc-omap2", "ti,sysc"; 1008 reg = <0x22050 0x4>, 1009 <0x22054 0x4>, 1010 <0x22058 0x4>; 1011 reg-names = "rev", "sysc", "syss"; 1012 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1013 SYSC_OMAP2_SOFTRESET | 1014 SYSC_OMAP2_AUTOIDLE)>; 1015 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1016 <SYSC_IDLE_NO>, 1017 <SYSC_IDLE_SMART>, 1018 <SYSC_IDLE_SMART_WKUP>; 1019 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1020 clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; 1021 clock-names = "fck"; 1022 #address-cells = <1>; 1023 #size-cells = <1>; 1024 ranges = <0x0 0x22000 0x1000>; 1025 1026 uart1: serial@0 { 1027 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1028 clock-frequency = <48000000>; 1029 reg = <0x0 0x1000>; 1030 interrupts = <73>; 1031 status = "disabled"; 1032 dmas = <&edma 28 0>, <&edma 29 0>; 1033 dma-names = "tx", "rx"; 1034 }; 1035 }; 1036 1037 target-module@24000 { /* 0x48024000, ap 12 14.0 */ 1038 compatible = "ti,sysc-omap2", "ti,sysc"; 1039 reg = <0x24050 0x4>, 1040 <0x24054 0x4>, 1041 <0x24058 0x4>; 1042 reg-names = "rev", "sysc", "syss"; 1043 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1044 SYSC_OMAP2_SOFTRESET | 1045 SYSC_OMAP2_AUTOIDLE)>; 1046 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1047 <SYSC_IDLE_NO>, 1048 <SYSC_IDLE_SMART>, 1049 <SYSC_IDLE_SMART_WKUP>; 1050 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1051 clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; 1052 clock-names = "fck"; 1053 #address-cells = <1>; 1054 #size-cells = <1>; 1055 ranges = <0x0 0x24000 0x1000>; 1056 1057 uart2: serial@0 { 1058 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1059 clock-frequency = <48000000>; 1060 reg = <0x0 0x1000>; 1061 interrupts = <74>; 1062 status = "disabled"; 1063 dmas = <&edma 30 0>, <&edma 31 0>; 1064 dma-names = "tx", "rx"; 1065 }; 1066 }; 1067 1068 target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ 1069 compatible = "ti,sysc-omap2", "ti,sysc"; 1070 reg = <0x2a000 0x8>, 1071 <0x2a010 0x8>, 1072 <0x2a090 0x8>; 1073 reg-names = "rev", "sysc", "syss"; 1074 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1075 SYSC_OMAP2_ENAWAKEUP | 1076 SYSC_OMAP2_SOFTRESET | 1077 SYSC_OMAP2_AUTOIDLE)>; 1078 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1079 <SYSC_IDLE_NO>, 1080 <SYSC_IDLE_SMART>, 1081 <SYSC_IDLE_SMART_WKUP>; 1082 ti,syss-mask = <1>; 1083 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1084 clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; 1085 clock-names = "fck"; 1086 #address-cells = <1>; 1087 #size-cells = <1>; 1088 ranges = <0x0 0x2a000 0x1000>; 1089 1090 i2c1: i2c@0 { 1091 compatible = "ti,omap4-i2c"; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 reg = <0x0 0x1000>; 1095 interrupts = <71>; 1096 status = "disabled"; 1097 }; 1098 }; 1099 1100 target-module@30000 { /* 0x48030000, ap 77 08.0 */ 1101 compatible = "ti,sysc-omap2", "ti,sysc"; 1102 reg = <0x30000 0x4>, 1103 <0x30110 0x4>, 1104 <0x30114 0x4>; 1105 reg-names = "rev", "sysc", "syss"; 1106 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1107 SYSC_OMAP2_SOFTRESET | 1108 SYSC_OMAP2_AUTOIDLE)>; 1109 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1110 <SYSC_IDLE_NO>, 1111 <SYSC_IDLE_SMART>; 1112 ti,syss-mask = <1>; 1113 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1114 clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; 1115 clock-names = "fck"; 1116 #address-cells = <1>; 1117 #size-cells = <1>; 1118 ranges = <0x0 0x30000 0x1000>; 1119 1120 spi0: spi@0 { 1121 compatible = "ti,omap4-mcspi"; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 reg = <0x0 0x400>; 1125 interrupts = <65>; 1126 ti,spi-num-cs = <2>; 1127 dmas = <&edma 16 0 1128 &edma 17 0 1129 &edma 18 0 1130 &edma 19 0>; 1131 dma-names = "tx0", "rx0", "tx1", "rx1"; 1132 status = "disabled"; 1133 }; 1134 }; 1135 1136 target-module@38000 { /* 0x48038000, ap 16 02.0 */ 1137 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1138 reg = <0x38000 0x4>, 1139 <0x38004 0x4>; 1140 reg-names = "rev", "sysc"; 1141 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1142 <SYSC_IDLE_NO>, 1143 <SYSC_IDLE_SMART>; 1144 /* Domains (P, C): per_pwrdm, l3s_clkdm */ 1145 clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; 1146 clock-names = "fck"; 1147 #address-cells = <1>; 1148 #size-cells = <1>; 1149 ranges = <0x0 0x38000 0x2000>, 1150 <0x46000000 0x46000000 0x400000>; 1151 1152 mcasp0: mcasp@0 { 1153 compatible = "ti,am33xx-mcasp-audio"; 1154 reg = <0x0 0x2000>, 1155 <0x46000000 0x400000>; 1156 reg-names = "mpu", "dat"; 1157 interrupts = <80>, <81>; 1158 interrupt-names = "tx", "rx"; 1159 status = "disabled"; 1160 dmas = <&edma 8 2>, 1161 <&edma 9 2>; 1162 dma-names = "tx", "rx"; 1163 }; 1164 }; 1165 1166 target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ 1167 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1168 reg = <0x3c000 0x4>, 1169 <0x3c004 0x4>; 1170 reg-names = "rev", "sysc"; 1171 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1172 <SYSC_IDLE_NO>, 1173 <SYSC_IDLE_SMART>; 1174 /* Domains (P, C): per_pwrdm, l3s_clkdm */ 1175 clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; 1176 clock-names = "fck"; 1177 #address-cells = <1>; 1178 #size-cells = <1>; 1179 ranges = <0x0 0x3c000 0x2000>, 1180 <0x46400000 0x46400000 0x400000>; 1181 1182 mcasp1: mcasp@0 { 1183 compatible = "ti,am33xx-mcasp-audio"; 1184 reg = <0x0 0x2000>, 1185 <0x46400000 0x400000>; 1186 reg-names = "mpu", "dat"; 1187 interrupts = <82>, <83>; 1188 interrupt-names = "tx", "rx"; 1189 status = "disabled"; 1190 dmas = <&edma 10 2>, 1191 <&edma 11 2>; 1192 dma-names = "tx", "rx"; 1193 }; 1194 }; 1195 1196 timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */ 1197 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1198 reg = <0x40000 0x4>, 1199 <0x40010 0x4>, 1200 <0x40014 0x4>; 1201 reg-names = "rev", "sysc", "syss"; 1202 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1203 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1204 <SYSC_IDLE_NO>, 1205 <SYSC_IDLE_SMART>, 1206 <SYSC_IDLE_SMART_WKUP>; 1207 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1208 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; 1209 clock-names = "fck"; 1210 #address-cells = <1>; 1211 #size-cells = <1>; 1212 ranges = <0x0 0x40000 0x1000>; 1213 1214 timer2: timer@0 { 1215 compatible = "ti,am335x-timer"; 1216 reg = <0x0 0x400>; 1217 interrupts = <68>; 1218 clocks = <&timer2_fck>; 1219 clock-names = "fck"; 1220 }; 1221 }; 1222 1223 target-module@42000 { /* 0x48042000, ap 24 1c.0 */ 1224 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1225 reg = <0x42000 0x4>, 1226 <0x42010 0x4>, 1227 <0x42014 0x4>; 1228 reg-names = "rev", "sysc", "syss"; 1229 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1230 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1231 <SYSC_IDLE_NO>, 1232 <SYSC_IDLE_SMART>, 1233 <SYSC_IDLE_SMART_WKUP>; 1234 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1235 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; 1236 clock-names = "fck"; 1237 #address-cells = <1>; 1238 #size-cells = <1>; 1239 ranges = <0x0 0x42000 0x1000>; 1240 1241 timer3: timer@0 { 1242 compatible = "ti,am335x-timer"; 1243 reg = <0x0 0x400>; 1244 interrupts = <69>; 1245 }; 1246 }; 1247 1248 target-module@44000 { /* 0x48044000, ap 26 26.0 */ 1249 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1250 reg = <0x44000 0x4>, 1251 <0x44010 0x4>, 1252 <0x44014 0x4>; 1253 reg-names = "rev", "sysc", "syss"; 1254 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1255 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1256 <SYSC_IDLE_NO>, 1257 <SYSC_IDLE_SMART>, 1258 <SYSC_IDLE_SMART_WKUP>; 1259 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1260 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; 1261 clock-names = "fck"; 1262 #address-cells = <1>; 1263 #size-cells = <1>; 1264 ranges = <0x0 0x44000 0x1000>; 1265 1266 timer4: timer@0 { 1267 compatible = "ti,am335x-timer"; 1268 reg = <0x0 0x400>; 1269 interrupts = <92>; 1270 ti,timer-pwm; 1271 }; 1272 }; 1273 1274 target-module@46000 { /* 0x48046000, ap 28 28.0 */ 1275 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1276 reg = <0x46000 0x4>, 1277 <0x46010 0x4>, 1278 <0x46014 0x4>; 1279 reg-names = "rev", "sysc", "syss"; 1280 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1281 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1282 <SYSC_IDLE_NO>, 1283 <SYSC_IDLE_SMART>, 1284 <SYSC_IDLE_SMART_WKUP>; 1285 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1286 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; 1287 clock-names = "fck"; 1288 #address-cells = <1>; 1289 #size-cells = <1>; 1290 ranges = <0x0 0x46000 0x1000>; 1291 1292 timer5: timer@0 { 1293 compatible = "ti,am335x-timer"; 1294 reg = <0x0 0x400>; 1295 interrupts = <93>; 1296 ti,timer-pwm; 1297 }; 1298 }; 1299 1300 target-module@48000 { /* 0x48048000, ap 30 22.0 */ 1301 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1302 reg = <0x48000 0x4>, 1303 <0x48010 0x4>, 1304 <0x48014 0x4>; 1305 reg-names = "rev", "sysc", "syss"; 1306 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1307 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1308 <SYSC_IDLE_NO>, 1309 <SYSC_IDLE_SMART>, 1310 <SYSC_IDLE_SMART_WKUP>; 1311 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1312 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; 1313 clock-names = "fck"; 1314 #address-cells = <1>; 1315 #size-cells = <1>; 1316 ranges = <0x0 0x48000 0x1000>; 1317 1318 timer6: timer@0 { 1319 compatible = "ti,am335x-timer"; 1320 reg = <0x0 0x400>; 1321 interrupts = <94>; 1322 ti,timer-pwm; 1323 }; 1324 }; 1325 1326 target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ 1327 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1328 reg = <0x4a000 0x4>, 1329 <0x4a010 0x4>, 1330 <0x4a014 0x4>; 1331 reg-names = "rev", "sysc", "syss"; 1332 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1333 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1334 <SYSC_IDLE_NO>, 1335 <SYSC_IDLE_SMART>, 1336 <SYSC_IDLE_SMART_WKUP>; 1337 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1338 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; 1339 clock-names = "fck"; 1340 #address-cells = <1>; 1341 #size-cells = <1>; 1342 ranges = <0x0 0x4a000 0x1000>; 1343 1344 timer7: timer@0 { 1345 compatible = "ti,am335x-timer"; 1346 reg = <0x0 0x400>; 1347 interrupts = <95>; 1348 ti,timer-pwm; 1349 }; 1350 }; 1351 1352 target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ 1353 compatible = "ti,sysc-omap2", "ti,sysc"; 1354 reg = <0x4c000 0x4>, 1355 <0x4c010 0x4>, 1356 <0x4c114 0x4>; 1357 reg-names = "rev", "sysc", "syss"; 1358 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1359 SYSC_OMAP2_SOFTRESET | 1360 SYSC_OMAP2_AUTOIDLE)>; 1361 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1362 <SYSC_IDLE_NO>, 1363 <SYSC_IDLE_SMART>, 1364 <SYSC_IDLE_SMART_WKUP>; 1365 ti,syss-mask = <1>; 1366 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1367 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, 1368 <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; 1369 clock-names = "fck", "dbclk"; 1370 #address-cells = <1>; 1371 #size-cells = <1>; 1372 ranges = <0x0 0x4c000 0x1000>; 1373 1374 gpio1: gpio@0 { 1375 compatible = "ti,omap4-gpio"; 1376 gpio-ranges = <&am33xx_pinmux 0 0 8>, 1377 <&am33xx_pinmux 8 90 4>, 1378 <&am33xx_pinmux 12 12 16>, 1379 <&am33xx_pinmux 28 30 4>; 1380 gpio-controller; 1381 #gpio-cells = <2>; 1382 interrupt-controller; 1383 #interrupt-cells = <2>; 1384 reg = <0x0 0x1000>; 1385 interrupts = <98>; 1386 }; 1387 }; 1388 1389 target-module@50000 { /* 0x48050000, ap 34 2c.0 */ 1390 compatible = "ti,sysc"; 1391 status = "disabled"; 1392 #address-cells = <1>; 1393 #size-cells = <1>; 1394 ranges = <0x0 0x50000 0x2000>; 1395 }; 1396 1397 target-module@60000 { /* 0x48060000, ap 36 0c.0 */ 1398 compatible = "ti,sysc-omap2", "ti,sysc"; 1399 reg = <0x602fc 0x4>, 1400 <0x60110 0x4>, 1401 <0x60114 0x4>; 1402 reg-names = "rev", "sysc", "syss"; 1403 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1404 SYSC_OMAP2_ENAWAKEUP | 1405 SYSC_OMAP2_SOFTRESET | 1406 SYSC_OMAP2_AUTOIDLE)>; 1407 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1408 <SYSC_IDLE_NO>, 1409 <SYSC_IDLE_SMART>; 1410 ti,syss-mask = <1>; 1411 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1412 clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; 1413 clock-names = "fck"; 1414 #address-cells = <1>; 1415 #size-cells = <1>; 1416 ranges = <0x0 0x60000 0x1000>; 1417 1418 mmc1: mmc@0 { 1419 compatible = "ti,am335-sdhci"; 1420 ti,needs-special-reset; 1421 dmas = <&edma_xbar 24 0 0 1422 &edma_xbar 25 0 0>; 1423 dma-names = "tx", "rx"; 1424 interrupts = <64>; 1425 reg = <0x0 0x1000>; 1426 status = "disabled"; 1427 }; 1428 }; 1429 1430 target-module@80000 { /* 0x48080000, ap 38 18.0 */ 1431 compatible = "ti,sysc-omap2", "ti,sysc"; 1432 reg = <0x80000 0x4>, 1433 <0x80010 0x4>, 1434 <0x80014 0x4>; 1435 reg-names = "rev", "sysc", "syss"; 1436 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1437 SYSC_OMAP2_SOFTRESET | 1438 SYSC_OMAP2_AUTOIDLE)>; 1439 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1440 <SYSC_IDLE_NO>, 1441 <SYSC_IDLE_SMART>; 1442 ti,syss-mask = <1>; 1443 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1444 clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; 1445 clock-names = "fck"; 1446 #address-cells = <1>; 1447 #size-cells = <1>; 1448 ranges = <0x0 0x80000 0x10000>; 1449 1450 elm: elm@0 { 1451 compatible = "ti,am3352-elm"; 1452 reg = <0x0 0x2000>; 1453 interrupts = <4>; 1454 status = "disabled"; 1455 }; 1456 }; 1457 1458 target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ 1459 compatible = "ti,sysc"; 1460 status = "disabled"; 1461 #address-cells = <1>; 1462 #size-cells = <1>; 1463 ranges = <0x0 0xa0000 0x10000>; 1464 }; 1465 1466 target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ 1467 compatible = "ti,sysc-omap4", "ti,sysc"; 1468 reg = <0xc8000 0x4>, 1469 <0xc8010 0x4>; 1470 reg-names = "rev", "sysc"; 1471 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1472 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1473 <SYSC_IDLE_NO>, 1474 <SYSC_IDLE_SMART>; 1475 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1476 clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; 1477 clock-names = "fck"; 1478 #address-cells = <1>; 1479 #size-cells = <1>; 1480 ranges = <0x0 0xc8000 0x1000>; 1481 1482 mailbox: mailbox@0 { 1483 compatible = "ti,omap4-mailbox"; 1484 reg = <0x0 0x200>; 1485 interrupts = <77>; 1486 #mbox-cells = <1>; 1487 ti,mbox-num-users = <4>; 1488 ti,mbox-num-fifos = <8>; 1489 mbox_wkupm3: wkup_m3 { 1490 ti,mbox-send-noirq; 1491 ti,mbox-tx = <0 0 0>; 1492 ti,mbox-rx = <0 0 3>; 1493 }; 1494 }; 1495 }; 1496 1497 target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ 1498 compatible = "ti,sysc-omap2", "ti,sysc"; 1499 reg = <0xca000 0x4>, 1500 <0xca010 0x4>, 1501 <0xca014 0x4>; 1502 reg-names = "rev", "sysc", "syss"; 1503 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1504 SYSC_OMAP2_ENAWAKEUP | 1505 SYSC_OMAP2_SOFTRESET | 1506 SYSC_OMAP2_AUTOIDLE)>; 1507 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1508 <SYSC_IDLE_NO>, 1509 <SYSC_IDLE_SMART>; 1510 ti,syss-mask = <1>; 1511 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1512 clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; 1513 clock-names = "fck"; 1514 #address-cells = <1>; 1515 #size-cells = <1>; 1516 ranges = <0x0 0xca000 0x1000>; 1517 1518 hwspinlock: spinlock@0 { 1519 compatible = "ti,omap4-hwspinlock"; 1520 reg = <0x0 0x1000>; 1521 #hwlock-cells = <1>; 1522 }; 1523 }; 1524 1525 target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ 1526 compatible = "ti,sysc"; 1527 status = "disabled"; 1528 #address-cells = <1>; 1529 #size-cells = <1>; 1530 ranges = <0x0 0xcc000 0x1000>; 1531 }; 1532 }; 1533 1534 segment@100000 { /* 0x48100000 */ 1535 compatible = "simple-pm-bus"; 1536 #address-cells = <1>; 1537 #size-cells = <1>; 1538 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ 1539 <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ 1540 <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ 1541 <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ 1542 <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ 1543 <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ 1544 <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ 1545 <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ 1546 <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ 1547 <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ 1548 <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ 1549 <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ 1550 <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ 1551 <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ 1552 <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ 1553 <0x000af000 0x001af000 0x001000>, /* ap 57 */ 1554 <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ 1555 <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ 1556 <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ 1557 <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ 1558 <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ 1559 <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ 1560 <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ 1561 <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ 1562 <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ 1563 <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ 1564 <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ 1565 <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ 1566 <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ 1567 <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ 1568 1569 target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ 1570 compatible = "ti,sysc"; 1571 status = "disabled"; 1572 #address-cells = <1>; 1573 #size-cells = <1>; 1574 ranges = <0x0 0x8c000 0x1000>; 1575 }; 1576 1577 target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ 1578 compatible = "ti,sysc"; 1579 status = "disabled"; 1580 #address-cells = <1>; 1581 #size-cells = <1>; 1582 ranges = <0x0 0x8e000 0x1000>; 1583 }; 1584 1585 target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ 1586 compatible = "ti,sysc-omap2", "ti,sysc"; 1587 reg = <0x9c000 0x8>, 1588 <0x9c010 0x8>, 1589 <0x9c090 0x8>; 1590 reg-names = "rev", "sysc", "syss"; 1591 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1592 SYSC_OMAP2_ENAWAKEUP | 1593 SYSC_OMAP2_SOFTRESET | 1594 SYSC_OMAP2_AUTOIDLE)>; 1595 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1596 <SYSC_IDLE_NO>, 1597 <SYSC_IDLE_SMART>, 1598 <SYSC_IDLE_SMART_WKUP>; 1599 ti,syss-mask = <1>; 1600 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1601 clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; 1602 clock-names = "fck"; 1603 #address-cells = <1>; 1604 #size-cells = <1>; 1605 ranges = <0x0 0x9c000 0x1000>; 1606 1607 i2c2: i2c@0 { 1608 compatible = "ti,omap4-i2c"; 1609 #address-cells = <1>; 1610 #size-cells = <0>; 1611 reg = <0x0 0x1000>; 1612 interrupts = <30>; 1613 status = "disabled"; 1614 }; 1615 }; 1616 1617 target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ 1618 compatible = "ti,sysc-omap2", "ti,sysc"; 1619 reg = <0xa0000 0x4>, 1620 <0xa0110 0x4>, 1621 <0xa0114 0x4>; 1622 reg-names = "rev", "sysc", "syss"; 1623 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1624 SYSC_OMAP2_SOFTRESET | 1625 SYSC_OMAP2_AUTOIDLE)>; 1626 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1627 <SYSC_IDLE_NO>, 1628 <SYSC_IDLE_SMART>; 1629 ti,syss-mask = <1>; 1630 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1631 clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; 1632 clock-names = "fck"; 1633 #address-cells = <1>; 1634 #size-cells = <1>; 1635 ranges = <0x0 0xa0000 0x1000>; 1636 1637 spi1: spi@0 { 1638 compatible = "ti,omap4-mcspi"; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 reg = <0x0 0x400>; 1642 interrupts = <125>; 1643 ti,spi-num-cs = <2>; 1644 dmas = <&edma 42 0 1645 &edma 43 0 1646 &edma 44 0 1647 &edma 45 0>; 1648 dma-names = "tx0", "rx0", "tx1", "rx1"; 1649 status = "disabled"; 1650 }; 1651 }; 1652 1653 target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ 1654 compatible = "ti,sysc"; 1655 status = "disabled"; 1656 #address-cells = <1>; 1657 #size-cells = <1>; 1658 ranges = <0x0 0xa2000 0x1000>; 1659 }; 1660 1661 target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ 1662 compatible = "ti,sysc"; 1663 status = "disabled"; 1664 #address-cells = <1>; 1665 #size-cells = <1>; 1666 ranges = <0x0 0xa4000 0x1000>; 1667 }; 1668 1669 target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ 1670 compatible = "ti,sysc-omap2", "ti,sysc"; 1671 reg = <0xa6050 0x4>, 1672 <0xa6054 0x4>, 1673 <0xa6058 0x4>; 1674 reg-names = "rev", "sysc", "syss"; 1675 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1676 SYSC_OMAP2_SOFTRESET | 1677 SYSC_OMAP2_AUTOIDLE)>; 1678 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1679 <SYSC_IDLE_NO>, 1680 <SYSC_IDLE_SMART>, 1681 <SYSC_IDLE_SMART_WKUP>; 1682 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1683 clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; 1684 clock-names = "fck"; 1685 #address-cells = <1>; 1686 #size-cells = <1>; 1687 ranges = <0x0 0xa6000 0x1000>; 1688 1689 uart3: serial@0 { 1690 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1691 clock-frequency = <48000000>; 1692 reg = <0x0 0x1000>; 1693 interrupts = <44>; 1694 status = "disabled"; 1695 }; 1696 }; 1697 1698 target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ 1699 compatible = "ti,sysc-omap2", "ti,sysc"; 1700 reg = <0xa8050 0x4>, 1701 <0xa8054 0x4>, 1702 <0xa8058 0x4>; 1703 reg-names = "rev", "sysc", "syss"; 1704 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1705 SYSC_OMAP2_SOFTRESET | 1706 SYSC_OMAP2_AUTOIDLE)>; 1707 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1708 <SYSC_IDLE_NO>, 1709 <SYSC_IDLE_SMART>, 1710 <SYSC_IDLE_SMART_WKUP>; 1711 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1712 clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; 1713 clock-names = "fck"; 1714 #address-cells = <1>; 1715 #size-cells = <1>; 1716 ranges = <0x0 0xa8000 0x1000>; 1717 1718 uart4: serial@0 { 1719 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1720 clock-frequency = <48000000>; 1721 reg = <0x0 0x1000>; 1722 interrupts = <45>; 1723 status = "disabled"; 1724 }; 1725 }; 1726 1727 target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ 1728 compatible = "ti,sysc-omap2", "ti,sysc"; 1729 reg = <0xaa050 0x4>, 1730 <0xaa054 0x4>, 1731 <0xaa058 0x4>; 1732 reg-names = "rev", "sysc", "syss"; 1733 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1734 SYSC_OMAP2_SOFTRESET | 1735 SYSC_OMAP2_AUTOIDLE)>; 1736 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1737 <SYSC_IDLE_NO>, 1738 <SYSC_IDLE_SMART>, 1739 <SYSC_IDLE_SMART_WKUP>; 1740 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1741 clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; 1742 clock-names = "fck"; 1743 #address-cells = <1>; 1744 #size-cells = <1>; 1745 ranges = <0x0 0xaa000 0x1000>; 1746 1747 uart5: serial@0 { 1748 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1749 clock-frequency = <48000000>; 1750 reg = <0x0 0x1000>; 1751 interrupts = <46>; 1752 status = "disabled"; 1753 }; 1754 }; 1755 1756 target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ 1757 compatible = "ti,sysc-omap2", "ti,sysc"; 1758 reg = <0xac000 0x4>, 1759 <0xac010 0x4>, 1760 <0xac114 0x4>; 1761 reg-names = "rev", "sysc", "syss"; 1762 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1763 SYSC_OMAP2_SOFTRESET | 1764 SYSC_OMAP2_AUTOIDLE)>; 1765 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1766 <SYSC_IDLE_NO>, 1767 <SYSC_IDLE_SMART>, 1768 <SYSC_IDLE_SMART_WKUP>; 1769 ti,syss-mask = <1>; 1770 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1771 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, 1772 <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; 1773 clock-names = "fck", "dbclk"; 1774 #address-cells = <1>; 1775 #size-cells = <1>; 1776 ranges = <0x0 0xac000 0x1000>; 1777 1778 gpio2: gpio@0 { 1779 compatible = "ti,omap4-gpio"; 1780 gpio-ranges = <&am33xx_pinmux 0 34 18>, 1781 <&am33xx_pinmux 18 77 4>, 1782 <&am33xx_pinmux 22 56 10>; 1783 gpio-controller; 1784 #gpio-cells = <2>; 1785 interrupt-controller; 1786 #interrupt-cells = <2>; 1787 reg = <0x0 0x1000>; 1788 interrupts = <32>; 1789 }; 1790 }; 1791 1792 target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ 1793 compatible = "ti,sysc-omap2", "ti,sysc"; 1794 reg = <0xae000 0x4>, 1795 <0xae010 0x4>, 1796 <0xae114 0x4>; 1797 reg-names = "rev", "sysc", "syss"; 1798 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1799 SYSC_OMAP2_SOFTRESET | 1800 SYSC_OMAP2_AUTOIDLE)>; 1801 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1802 <SYSC_IDLE_NO>, 1803 <SYSC_IDLE_SMART>, 1804 <SYSC_IDLE_SMART_WKUP>; 1805 ti,syss-mask = <1>; 1806 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1807 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, 1808 <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; 1809 clock-names = "fck", "dbclk"; 1810 #address-cells = <1>; 1811 #size-cells = <1>; 1812 ranges = <0x0 0xae000 0x1000>; 1813 1814 gpio3: gpio@0 { 1815 compatible = "ti,omap4-gpio"; 1816 gpio-ranges = <&am33xx_pinmux 0 66 5>, 1817 <&am33xx_pinmux 5 98 2>, 1818 <&am33xx_pinmux 7 75 2>, 1819 <&am33xx_pinmux 13 141 1>, 1820 <&am33xx_pinmux 14 100 8>; 1821 gpio-controller; 1822 #gpio-cells = <2>; 1823 interrupt-controller; 1824 #interrupt-cells = <2>; 1825 reg = <0x0 0x1000>; 1826 interrupts = <62>; 1827 }; 1828 }; 1829 1830 target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ 1831 compatible = "ti,sysc"; 1832 status = "disabled"; 1833 #address-cells = <1>; 1834 #size-cells = <1>; 1835 ranges = <0x0 0xb0000 0x10000>; 1836 }; 1837 1838 target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ 1839 compatible = "ti,sysc-omap4", "ti,sysc"; 1840 reg = <0xcc020 0x4>; 1841 reg-names = "rev"; 1842 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1843 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, 1844 <&dcan0_fck>; 1845 clock-names = "fck", "osc"; 1846 #address-cells = <1>; 1847 #size-cells = <1>; 1848 ranges = <0x0 0xcc000 0x2000>; 1849 1850 dcan0: can@0 { 1851 compatible = "ti,am3352-d_can"; 1852 reg = <0x0 0x2000>; 1853 clocks = <&dcan0_fck>; 1854 clock-names = "fck"; 1855 syscon-raminit = <&scm_conf 0x644 0>; 1856 interrupts = <52>; 1857 status = "disabled"; 1858 }; 1859 }; 1860 1861 target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ 1862 compatible = "ti,sysc-omap4", "ti,sysc"; 1863 reg = <0xd0020 0x4>; 1864 reg-names = "rev"; 1865 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1866 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>, 1867 <&dcan1_fck>; 1868 clock-names = "fck", "osc"; 1869 #address-cells = <1>; 1870 #size-cells = <1>; 1871 ranges = <0x0 0xd0000 0x2000>; 1872 1873 dcan1: can@0 { 1874 compatible = "ti,am3352-d_can"; 1875 reg = <0x0 0x2000>; 1876 clocks = <&dcan1_fck>; 1877 clock-names = "fck"; 1878 syscon-raminit = <&scm_conf 0x644 1>; 1879 interrupts = <55>; 1880 status = "disabled"; 1881 }; 1882 }; 1883 1884 target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ 1885 compatible = "ti,sysc-omap2", "ti,sysc"; 1886 reg = <0xd82fc 0x4>, 1887 <0xd8110 0x4>, 1888 <0xd8114 0x4>; 1889 reg-names = "rev", "sysc", "syss"; 1890 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1891 SYSC_OMAP2_ENAWAKEUP | 1892 SYSC_OMAP2_SOFTRESET | 1893 SYSC_OMAP2_AUTOIDLE)>; 1894 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1895 <SYSC_IDLE_NO>, 1896 <SYSC_IDLE_SMART>; 1897 ti,syss-mask = <1>; 1898 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1899 clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; 1900 clock-names = "fck"; 1901 #address-cells = <1>; 1902 #size-cells = <1>; 1903 ranges = <0x0 0xd8000 0x1000>; 1904 1905 mmc2: mmc@0 { 1906 compatible = "ti,am335-sdhci"; 1907 ti,needs-special-reset; 1908 dmas = <&edma 2 0 1909 &edma 3 0>; 1910 dma-names = "tx", "rx"; 1911 interrupts = <28>; 1912 reg = <0x0 0x1000>; 1913 status = "disabled"; 1914 }; 1915 }; 1916 }; 1917 1918 segment@200000 { /* 0x48200000 */ 1919 compatible = "simple-pm-bus"; 1920 #address-cells = <1>; 1921 #size-cells = <1>; 1922 ranges = <0x00000000 0x00200000 0x010000>; 1923 1924 target-module@0 { 1925 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1926 power-domains = <&prm_mpu>; 1927 clocks = <&mpu_clkctrl AM3_MPU_MPU_CLKCTRL 0>; 1928 clock-names = "fck"; 1929 ti,no-idle; 1930 #address-cells = <1>; 1931 #size-cells = <1>; 1932 ranges = <0 0 0x10000>; 1933 1934 mpu@0 { 1935 compatible = "ti,omap3-mpu"; 1936 pm-sram = <&pm_sram_code 1937 &pm_sram_data>; 1938 }; 1939 }; 1940 }; 1941 1942 segment@300000 { /* 0x48300000 */ 1943 compatible = "simple-pm-bus"; 1944 #address-cells = <1>; 1945 #size-cells = <1>; 1946 ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ 1947 <0x00001000 0x00301000 0x001000>, /* ap 67 */ 1948 <0x00002000 0x00302000 0x001000>, /* ap 68 */ 1949 <0x00003000 0x00303000 0x001000>, /* ap 69 */ 1950 <0x00004000 0x00304000 0x001000>, /* ap 70 */ 1951 <0x00005000 0x00305000 0x001000>, /* ap 71 */ 1952 <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ 1953 <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ 1954 <0x00018000 0x00318000 0x004000>, /* ap 74 */ 1955 <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ 1956 <0x00010000 0x00310000 0x002000>, /* ap 76 */ 1957 <0x00012000 0x00312000 0x001000>, /* ap 93 */ 1958 <0x00015000 0x00315000 0x001000>, /* ap 94 */ 1959 <0x00016000 0x00316000 0x001000>, /* ap 95 */ 1960 <0x00017000 0x00317000 0x001000>, /* ap 96 */ 1961 <0x00013000 0x00313000 0x001000>, /* ap 97 */ 1962 <0x00014000 0x00314000 0x001000>, /* ap 98 */ 1963 <0x00020000 0x00320000 0x001000>, /* ap 99 */ 1964 <0x00021000 0x00321000 0x001000>, /* ap 100 */ 1965 <0x00022000 0x00322000 0x001000>, /* ap 101 */ 1966 <0x00023000 0x00323000 0x001000>, /* ap 102 */ 1967 <0x00024000 0x00324000 0x001000>, /* ap 103 */ 1968 <0x00025000 0x00325000 0x001000>; /* ap 104 */ 1969 1970 target-module@0 { /* 0x48300000, ap 66 48.0 */ 1971 compatible = "ti,sysc-omap4", "ti,sysc"; 1972 reg = <0x0 0x4>, 1973 <0x4 0x4>; 1974 reg-names = "rev", "sysc"; 1975 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1976 <SYSC_IDLE_NO>, 1977 <SYSC_IDLE_SMART>, 1978 <SYSC_IDLE_SMART_WKUP>; 1979 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1980 <SYSC_IDLE_NO>, 1981 <SYSC_IDLE_SMART>, 1982 <SYSC_IDLE_SMART_WKUP>; 1983 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1984 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; 1985 clock-names = "fck"; 1986 #address-cells = <1>; 1987 #size-cells = <1>; 1988 ranges = <0x0 0x0 0x1000>; 1989 1990 epwmss0: epwmss@0 { 1991 compatible = "ti,am33xx-pwmss"; 1992 reg = <0x0 0x10>; 1993 #address-cells = <1>; 1994 #size-cells = <1>; 1995 status = "disabled"; 1996 ranges = <0 0 0x1000>; 1997 1998 ecap0: ecap@100 { 1999 compatible = "ti,am3352-ecap", 2000 "ti,am33xx-ecap"; 2001 #pwm-cells = <3>; 2002 reg = <0x100 0x80>; 2003 clocks = <&l4ls_gclk>; 2004 clock-names = "fck"; 2005 interrupts = <31>; 2006 interrupt-names = "ecap0"; 2007 status = "disabled"; 2008 }; 2009 2010 eqep0: counter@180 { 2011 compatible = "ti,am3352-eqep"; 2012 reg = <0x180 0x80>; 2013 clocks = <&l4ls_gclk>; 2014 clock-names = "sysclkout"; 2015 interrupts = <79>; 2016 status = "disabled"; 2017 }; 2018 2019 ehrpwm0: pwm@200 { 2020 compatible = "ti,am3352-ehrpwm", 2021 "ti,am33xx-ehrpwm"; 2022 #pwm-cells = <3>; 2023 reg = <0x200 0x80>; 2024 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; 2025 clock-names = "tbclk", "fck"; 2026 status = "disabled"; 2027 }; 2028 }; 2029 }; 2030 2031 target-module@2000 { /* 0x48302000, ap 68 52.0 */ 2032 compatible = "ti,sysc-omap4", "ti,sysc"; 2033 reg = <0x2000 0x4>, 2034 <0x2004 0x4>; 2035 reg-names = "rev", "sysc"; 2036 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2037 <SYSC_IDLE_NO>, 2038 <SYSC_IDLE_SMART>, 2039 <SYSC_IDLE_SMART_WKUP>; 2040 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2041 <SYSC_IDLE_NO>, 2042 <SYSC_IDLE_SMART>, 2043 <SYSC_IDLE_SMART_WKUP>; 2044 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2045 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; 2046 clock-names = "fck"; 2047 #address-cells = <1>; 2048 #size-cells = <1>; 2049 ranges = <0x0 0x2000 0x1000>; 2050 2051 epwmss1: epwmss@0 { 2052 compatible = "ti,am33xx-pwmss"; 2053 reg = <0x0 0x10>; 2054 #address-cells = <1>; 2055 #size-cells = <1>; 2056 status = "disabled"; 2057 ranges = <0 0 0x1000>; 2058 2059 ecap1: ecap@100 { 2060 compatible = "ti,am3352-ecap", 2061 "ti,am33xx-ecap"; 2062 #pwm-cells = <3>; 2063 reg = <0x100 0x80>; 2064 clocks = <&l4ls_gclk>; 2065 clock-names = "fck"; 2066 interrupts = <47>; 2067 interrupt-names = "ecap1"; 2068 status = "disabled"; 2069 }; 2070 2071 eqep1: counter@180 { 2072 compatible = "ti,am3352-eqep"; 2073 reg = <0x180 0x80>; 2074 clocks = <&l4ls_gclk>; 2075 clock-names = "sysclkout"; 2076 interrupts = <88>; 2077 status = "disabled"; 2078 }; 2079 2080 ehrpwm1: pwm@200 { 2081 compatible = "ti,am3352-ehrpwm", 2082 "ti,am33xx-ehrpwm"; 2083 #pwm-cells = <3>; 2084 reg = <0x200 0x80>; 2085 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; 2086 clock-names = "tbclk", "fck"; 2087 status = "disabled"; 2088 }; 2089 }; 2090 }; 2091 2092 target-module@4000 { /* 0x48304000, ap 70 44.0 */ 2093 compatible = "ti,sysc-omap4", "ti,sysc"; 2094 reg = <0x4000 0x4>, 2095 <0x4004 0x4>; 2096 reg-names = "rev", "sysc"; 2097 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2098 <SYSC_IDLE_NO>, 2099 <SYSC_IDLE_SMART>, 2100 <SYSC_IDLE_SMART_WKUP>; 2101 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2102 <SYSC_IDLE_NO>, 2103 <SYSC_IDLE_SMART>, 2104 <SYSC_IDLE_SMART_WKUP>; 2105 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2106 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; 2107 clock-names = "fck"; 2108 #address-cells = <1>; 2109 #size-cells = <1>; 2110 ranges = <0x0 0x4000 0x1000>; 2111 2112 epwmss2: epwmss@0 { 2113 compatible = "ti,am33xx-pwmss"; 2114 reg = <0x0 0x10>; 2115 #address-cells = <1>; 2116 #size-cells = <1>; 2117 status = "disabled"; 2118 ranges = <0 0 0x1000>; 2119 2120 ecap2: ecap@100 { 2121 compatible = "ti,am3352-ecap", 2122 "ti,am33xx-ecap"; 2123 #pwm-cells = <3>; 2124 reg = <0x100 0x80>; 2125 clocks = <&l4ls_gclk>; 2126 clock-names = "fck"; 2127 interrupts = <61>; 2128 interrupt-names = "ecap2"; 2129 status = "disabled"; 2130 }; 2131 2132 eqep2: counter@180 { 2133 compatible = "ti,am3352-eqep"; 2134 reg = <0x180 0x80>; 2135 clocks = <&l4ls_gclk>; 2136 clock-names = "sysclkout"; 2137 interrupts = <89>; 2138 status = "disabled"; 2139 }; 2140 2141 ehrpwm2: pwm@200 { 2142 compatible = "ti,am3352-ehrpwm", 2143 "ti,am33xx-ehrpwm"; 2144 #pwm-cells = <3>; 2145 reg = <0x200 0x80>; 2146 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; 2147 clock-names = "tbclk", "fck"; 2148 status = "disabled"; 2149 }; 2150 }; 2151 }; 2152 2153 target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ 2154 compatible = "ti,sysc-omap4", "ti,sysc"; 2155 reg = <0xe000 0x4>, 2156 <0xe054 0x4>; 2157 reg-names = "rev", "sysc"; 2158 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2159 <SYSC_IDLE_NO>, 2160 <SYSC_IDLE_SMART>; 2161 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2162 <SYSC_IDLE_NO>, 2163 <SYSC_IDLE_SMART>; 2164 /* Domains (P, C): per_pwrdm, lcdc_clkdm */ 2165 clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; 2166 clock-names = "fck"; 2167 #address-cells = <1>; 2168 #size-cells = <1>; 2169 ranges = <0x0 0xe000 0x1000>; 2170 2171 lcdc: lcdc@0 { 2172 compatible = "ti,am33xx-tilcdc"; 2173 reg = <0x0 0x1000>; 2174 interrupts = <36>; 2175 status = "disabled"; 2176 }; 2177 }; 2178 2179 target-module@10000 { /* 0x48310000, ap 76 4e.1 */ 2180 compatible = "ti,sysc-omap2", "ti,sysc"; 2181 reg = <0x11fe0 0x4>, 2182 <0x11fe4 0x4>; 2183 reg-names = "rev", "sysc"; 2184 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; 2185 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2186 <SYSC_IDLE_NO>; 2187 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2188 clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; 2189 clock-names = "fck"; 2190 #address-cells = <1>; 2191 #size-cells = <1>; 2192 ranges = <0x0 0x10000 0x2000>; 2193 2194 rng: rng@0 { 2195 compatible = "ti,omap4-rng"; 2196 reg = <0x0 0x2000>; 2197 interrupts = <111>; 2198 }; 2199 }; 2200 2201 target-module@13000 { /* 0x48313000, ap 97 62.0 */ 2202 compatible = "ti,sysc"; 2203 status = "disabled"; 2204 #address-cells = <1>; 2205 #size-cells = <1>; 2206 ranges = <0x0 0x13000 0x1000>; 2207 }; 2208 2209 target-module@15000 { /* 0x48315000, ap 94 56.0 */ 2210 compatible = "ti,sysc"; 2211 status = "disabled"; 2212 #address-cells = <1>; 2213 #size-cells = <1>; 2214 ranges = <0x00000000 0x00015000 0x00001000>, 2215 <0x00001000 0x00016000 0x00001000>; 2216 }; 2217 2218 target-module@18000 { /* 0x48318000, ap 74 4c.0 */ 2219 compatible = "ti,sysc"; 2220 status = "disabled"; 2221 #address-cells = <1>; 2222 #size-cells = <1>; 2223 ranges = <0x0 0x18000 0x4000>; 2224 }; 2225 2226 target-module@20000 { /* 0x48320000, ap 99 34.0 */ 2227 compatible = "ti,sysc"; 2228 status = "disabled"; 2229 #address-cells = <1>; 2230 #size-cells = <1>; 2231 ranges = <0x0 0x20000 0x1000>; 2232 }; 2233 2234 target-module@22000 { /* 0x48322000, ap 101 3e.0 */ 2235 compatible = "ti,sysc"; 2236 status = "disabled"; 2237 #address-cells = <1>; 2238 #size-cells = <1>; 2239 ranges = <0x0 0x22000 0x1000>; 2240 }; 2241 2242 target-module@24000 { /* 0x48324000, ap 103 68.0 */ 2243 compatible = "ti,sysc"; 2244 status = "disabled"; 2245 #address-cells = <1>; 2246 #size-cells = <1>; 2247 ranges = <0x0 0x24000 0x1000>; 2248 }; 2249 }; 2250}; 2251 2252