1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device tree for Winterland IceBoard 4 * 5 * https://mcgillcosmology.com 6 * https://threespeedlogic.com 7 * 8 * This is an ARM + FPGA instrumentation board used at telescopes in 9 * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO 10 * observatory in British Columbia (CHIME). 11 * 12 * Copyright (c) 2019 Three-Speed Logic, Inc. <gsmecher@threespeedlogic.com> 13 */ 14 15/dts-v1/; 16 17#include "dm814x.dtsi" 18#include <dt-bindings/interrupt-controller/irq.h> 19 20/ { 21 model = "Winterland IceBoard"; 22 compatible = "ti,dm8148", "ti,dm814"; 23 24 chosen { 25 stdout-path = "serial1:115200n8"; 26 bootargs = "earlycon"; 27 }; 28 29 memory@80000000 { 30 device_type = "memory"; 31 reg = <0x80000000 0x40000000>; /* 1 GB */ 32 }; 33 34 vmmcsd_fixed: fixedregulator0 { 35 compatible = "regulator-fixed"; 36 regulator-name = "vmmcsd_fixed"; 37 regulator-min-microvolt = <3300000>; 38 regulator-max-microvolt = <3300000>; 39 regulator-always-on; 40 }; 41}; 42 43/* The MAC provides internal delay for the transmit path ONLY, which is enabled 44 * provided no -id/-txid/-rxid suffix is provided to "phy-mode". 45 * 46 * The receive path is delayed at the PHY. The recommended register settings 47 * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the 48 * conversion code in the kernel lies: the PHY's registers are 120 ps per tap, 49 * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to 50 * obtain the correct register settings. 51 */ 52&mac { dual_emac = <1>; }; 53&cpsw_emac0 { 54 phy-handle = <ðphy0>; 55 phy-mode = "rgmii"; 56 dual_emac_res_vlan = <1>; 57}; 58&cpsw_emac1 { 59 phy-handle = <ðphy1>; 60 phy-mode = "rgmii"; 61 dual_emac_res_vlan = <2>; 62}; 63 64&davinci_mdio { 65 ethphy0: ethernet-phy@0 { 66 reg = <0x2>; 67 68 rxc-skew-ps = <3000>; 69 rxdv-skew-ps = <0>; 70 71 rxd3-skew-ps = <0>; 72 rxd2-skew-ps = <0>; 73 rxd1-skew-ps = <0>; 74 rxd0-skew-ps = <0>; 75 76 phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; 77 }; 78 79 ethphy1: ethernet-phy@1 { 80 reg = <0x1>; 81 82 rxc-skew-ps = <3000>; 83 rxdv-skew-ps = <0>; 84 85 rxd3-skew-ps = <0>; 86 rxd2-skew-ps = <0>; 87 rxd1-skew-ps = <0>; 88 rxd0-skew-ps = <0>; 89 90 phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 91 }; 92}; 93 94&mmc1 { status = "disabled"; }; 95&mmc2 { 96 pinctrl-names = "default"; 97 pinctrl-0 = <&mmc2_pins>; 98 vmmc-supply = <&vmmcsd_fixed>; 99 bus-width = <4>; 100}; 101&mmc3 { status = "disabled"; }; 102 103&i2c1 { 104 /* Most I2C activity happens through this port, with the sole exception 105 * of the backplane. Since there are multiply assigned addresses, the 106 * "i2c-mux-idle-disconnect" is important. 107 */ 108 109 pca9548@70 { 110 compatible = "nxp,pca9548"; 111 reg = <0x70>; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 i2c-mux-idle-disconnect; 115 116 i2c@0 { 117 /* FMC A */ 118 #address-cells = <1>; 119 #size-cells = <0>; 120 reg = <0>; 121 }; 122 123 i2c@1 { 124 /* FMC B */ 125 #address-cells = <1>; 126 #size-cells = <0>; 127 reg = <1>; 128 }; 129 130 i2c@2 { 131 /* QSFP A */ 132 #address-cells = <1>; 133 #size-cells = <0>; 134 reg = <2>; 135 }; 136 137 i2c@3 { 138 /* QSFP B */ 139 #address-cells = <1>; 140 #size-cells = <0>; 141 reg = <3>; 142 }; 143 144 i2c@4 { 145 /* SFP */ 146 #address-cells = <1>; 147 #size-cells = <0>; 148 reg = <4>; 149 }; 150 151 i2c@5 { 152 #address-cells = <1>; 153 #size-cells = <0>; 154 reg = <5>; 155 156 ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; }; 157 ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; }; 158 ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; }; 159 160 ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; }; 161 ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; }; 162 ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; }; 163 164 ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; }; 165 ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; }; 166 ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; }; 167 ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; }; 168 ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; }; 169 ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; }; 170 ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; }; 171 ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; }; 172 ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; }; 173 }; 174 175 i2c@6 { 176 /* Backplane */ 177 #address-cells = <1>; 178 #size-cells = <0>; 179 reg = <6>; 180 }; 181 182 i2c@7 { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 reg = <7>; 186 187 u41: pca9575@20 { 188 compatible = "nxp,pca9575"; 189 reg = <0x20>; 190 gpio-controller; 191 #gpio-cells = <2>; 192 193 gpio-line-names = 194 "FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C", 195 "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS", 196 "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C", 197 "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL"; 198 reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; 199 }; 200 201 u42: pca9575@21 { 202 compatible = "nxp,pca9575"; 203 reg = <0x21>; 204 gpio-controller; 205 #gpio-cells = <2>; 206 gpio-line-names = 207 "QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL", 208 "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL", 209 "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1", 210 "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR"; 211 reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; 212 }; 213 214 u48: pca9575@22 { 215 compatible = "nxp,pca9575"; 216 reg=<0x22>; 217 gpio-controller; 218 #gpio-cells = <2>; 219 220 sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>, 221 <&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>; 222 led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>, 223 <&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>; 224 225 gpio-line-names = 226 "GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4", 227 "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8", 228 "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5", 229 "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1"; 230 reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; 231 }; 232 233 u59: pca9575@23 { 234 compatible = "nxp,pca9575"; 235 reg=<0x23>; 236 gpio-controller; 237 #gpio-cells = <2>; 238 gpio-line-names = 239 "GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12", 240 "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault", 241 "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3", 242 "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17"; 243 reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; 244 }; 245 246 tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; }; 247 tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; }; 248 tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; }; 249 tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; }; 250 251 /* EEPROM bank and serial number are treated as separate devices */ 252 at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; }; 253 at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; }; 254 }; 255 }; 256}; 257 258&i2c2 { 259 pca9548@71 { 260 compatible = "nxp,pca9548"; 261 reg = <0x71>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 265 i2c@6 { 266 /* Backplane */ 267 #address-cells = <1>; 268 #size-cells = <0>; 269 reg = <6>; 270 multi-master; 271 272 /* All backplanes should have this -- it's how we know they're there. */ 273 at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; }; 274 at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; }; 275 276 /* 16 slot backplane */ 277 tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; }; 278 tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; }; 279 ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; }; 280 amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; }; 281 282 /* Single slot backplane */ 283 }; 284 }; 285}; 286 287&pincntl { 288 mmc2_pins: pinmux_mmc2_pins { 289 pinctrl-single,pins = < 290 DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ 291 DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ 292 DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ 293 DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ 294 DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ 295 DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ 296 DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40) /* SD1_POW */ 297 DM814X_IOPAD(0x0928, PIN_INPUT | 0x40) /* SD1_SDWP */ 298 DM814X_IOPAD(0x093C, PIN_INPUT | 0x2) /* SD1_SDCD */ 299 >; 300 }; 301 302 usb0_pins: pinmux_usb0_pins { 303 pinctrl-single,pins = < 304 DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ 305 >; 306 }; 307 308 usb1_pins: pinmux_usb1_pins { 309 pinctrl-single,pins = < 310 DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ 311 >; 312 }; 313 314 gpio1_pins: pinmux_gpio1_pins { 315 pinctrl-single,pins = < 316 DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */ 317 DM814X_IOPAD(0x0820, PIN_INPUT | 0x80) /* INIT_B */ 318 DM814X_IOPAD(0x0824, PIN_INPUT | 0x80) /* DONE */ 319 320 DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */ 321 DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */ 322 DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */ 323 DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */ 324 DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */ 325 326 DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */ 327 DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */ 328 DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */ 329 DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */ 330 DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */ 331 332 DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */ 333 DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */ 334 DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */ 335 DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */ 336 >; 337 }; 338 339 gpio2_pins: pinmux_gpio2_pins { 340 pinctrl-single,pins = < 341 DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */ 342 DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */ 343 DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */ 344 DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */ 345 346 //DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */ 347 //DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */ 348 DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */ 349 >; 350 }; 351 352 gpio4_pins: pinmux_gpio4_pins { 353 pinctrl-single,pins = < 354 /* The PLL doesn't react well to the SPI controller reset, so 355 * we force the CS lines to pull up as GPIOs until we're ready. 356 * See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3 357 */ 358 DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */ 359 DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */ 360 DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */ 361 DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */ 362 DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */ 363 DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */ 364 >; 365 }; 366 367 spi2_pins: pinmux_spi2_pins { 368 pinctrl-single,pins = < 369 DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */ 370 DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */ 371 >; 372 }; 373 374 spi4_pins: pinmux_spi4_pins { 375 pinctrl-single,pins = < 376 DM814X_IOPAD(0x0a7c, 0x20) 377 DM814X_IOPAD(0x0b74, 0x20) 378 DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20) 379 DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20) 380 DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20) 381 >; 382 }; 383}; 384 385&gpio1 { 386 pinctrl-names = "default"; 387 pinctrl-0 = <&gpio1_pins>; 388 gpio-line-names = 389 "", "PROGRAM_B", "INIT_B", "DONE", /* 0-3 */ 390 "", "", "", "", /* 4-7 */ 391 "FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI", /* 8-11 */ 392 "", "", "", "FMCA_TRST", /* 12-15 */ 393 "FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI", /* 16-19 */ 394 "FMCB_TRST", "", "", "", /* 20-23 */ 395 "FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI", /* 24-27 */ 396 "", "", "", ""; /* 28-31 */ 397}; 398 399&gpio2 { 400 pinctrl-names = "default"; 401 pinctrl-0 = <&gpio2_pins>; 402 gpio-line-names = 403 "PHYA_IRQ_N", "PHYA_RESET_N", "", "", /* 0-3 */ 404 "", "", "", "PHYB_IRQ_N", /* 4-7 */ 405 "PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", ""; /* 8-11 */ 406}; 407 408&gpio3 { 409 pinctrl-names = "default"; 410 /*pinctrl-0 = <&gpio3_pins>;*/ 411 gpio-line-names = 412 "", "", "ARMClkSel0", "", /* 0-3 */ 413 "EnFPGARef", "", "", "ARMClkSel1"; /* 4-7 */ 414}; 415 416&gpio4 { 417 pinctrl-names = "default"; 418 pinctrl-0 = <&gpio4_pins>; 419 gpio-line-names = 420 "BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3", 421 "BP_ARM_GPIO4", "BP_ARM_GPIO5"; 422}; 423 424&usb0 { 425 pinctrl-names = "default"; 426 pinctrl-0 = <&usb0_pins>; 427 dr_mode = "host"; 428}; 429 430&usb1 { 431 pinctrl-names = "default"; 432 pinctrl-0 = <&usb1_pins>; 433 dr_mode = "host"; 434}; 435 436&mcspi1 { 437 s25fl256@0 { 438 #address-cells = <1>; 439 #size-cells = <1>; 440 compatible = "jedec,spi-nor"; 441 reg = <0>; 442 spi-max-frequency = <40000000>; 443 444 fsbl@0 { 445 /* 256 kB */ 446 label = "U-Boot-min"; 447 reg = <0 0x40000>; 448 }; 449 ssbl@1 { 450 /* 512 kB */ 451 label = "U-Boot"; 452 reg = <0x40000 0x80000>; 453 }; 454 bootenv@2 { 455 /* 256 kB */ 456 label = "U-Boot Env"; 457 reg = <0xc0000 0x40000>; 458 }; 459 kernel@3 { 460 /* 4 MB */ 461 label = "Kernel"; 462 reg = <0x100000 0x400000>; 463 }; 464 ipmi@4 { 465 label = "IPMI FRU"; 466 reg = <0x500000 0x40000>; 467 }; 468 fs@5 { 469 label = "File System"; 470 reg = <0x540000 0x1ac0000>; 471 }; 472 }; 473}; 474 475&mcspi3 { 476 /* DMA event numbers stolen from MCASP */ 477 dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17 478 &edma_xbar 10 0 18 &edma_xbar 11 0 19>; 479 dma-names = "tx0", "rx0", "tx1", "rx1"; 480}; 481 482&mcspi4 { 483 pinctrl-names = "default"; 484 pinctrl-0 = <&spi4_pins>; 485 486 /* DMA event numbers stolen from MCASP, MCBSP */ 487 dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>; 488 dma-names = "tx0", "rx0"; 489}; 490