1/* 2 * Device Tree Source for AM4372 SoC 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/bus/ti-sysc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/clock/am4.h> 15 16/ { 17 compatible = "ti,am4372", "ti,am43"; 18 interrupt-parent = <&wakeupgen>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 chosen { }; 22 23 memory@0 { 24 device_type = "memory"; 25 reg = <0 0>; 26 }; 27 28 aliases { 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 ethernet0 = &cpsw_port1; 39 ethernet1 = &cpsw_port2; 40 spi0 = &qspi; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu: cpu@0 { 47 compatible = "arm,cortex-a9"; 48 enable-method = "ti,am4372"; 49 device_type = "cpu"; 50 reg = <0>; 51 52 clocks = <&dpll_mpu_ck>; 53 clock-names = "cpu"; 54 55 operating-points-v2 = <&cpu0_opp_table>; 56 57 clock-latency = <300000>; /* From omap-cpufreq driver */ 58 cpu-idle-states = <&mpu_gate>; 59 }; 60 61 idle-states { 62 mpu_gate: mpu_gate { 63 compatible = "arm,idle-state"; 64 entry-latency-us = <40>; 65 exit-latency-us = <100>; 66 min-residency-us = <300>; 67 local-timer-stop; 68 }; 69 }; 70 }; 71 72 cpu0_opp_table: opp-table { 73 compatible = "operating-points-v2-ti-cpu"; 74 syscon = <&scm_conf>; 75 76 opp50-300000000 { 77 opp-hz = /bits/ 64 <300000000>; 78 opp-microvolt = <950000 931000 969000>; 79 opp-supported-hw = <0xFF 0x01>; 80 opp-suspend; 81 }; 82 83 opp100-600000000 { 84 opp-hz = /bits/ 64 <600000000>; 85 opp-microvolt = <1100000 1078000 1122000>; 86 opp-supported-hw = <0xFF 0x04>; 87 }; 88 89 opp120-720000000 { 90 opp-hz = /bits/ 64 <720000000>; 91 opp-microvolt = <1200000 1176000 1224000>; 92 opp-supported-hw = <0xFF 0x08>; 93 }; 94 95 oppturbo-800000000 { 96 opp-hz = /bits/ 64 <800000000>; 97 opp-microvolt = <1260000 1234800 1285200>; 98 opp-supported-hw = <0xFF 0x10>; 99 }; 100 101 oppnitro-1000000000 { 102 opp-hz = /bits/ 64 <1000000000>; 103 opp-microvolt = <1325000 1298500 1351500>; 104 opp-supported-hw = <0xFF 0x20>; 105 }; 106 }; 107 108 soc { 109 compatible = "ti,omap-infra"; 110 }; 111 112 gic: interrupt-controller@48241000 { 113 compatible = "arm,cortex-a9-gic"; 114 interrupt-controller; 115 #interrupt-cells = <3>; 116 reg = <0x48241000 0x1000>, 117 <0x48240100 0x0100>; 118 interrupt-parent = <&gic>; 119 }; 120 121 wakeupgen: interrupt-controller@48281000 { 122 compatible = "ti,omap4-wugen-mpu"; 123 interrupt-controller; 124 #interrupt-cells = <3>; 125 reg = <0x48281000 0x1000>; 126 interrupt-parent = <&gic>; 127 }; 128 129 scu: scu@48240000 { 130 compatible = "arm,cortex-a9-scu"; 131 reg = <0x48240000 0x100>; 132 }; 133 134 global_timer: timer@48240200 { 135 compatible = "arm,cortex-a9-global-timer"; 136 reg = <0x48240200 0x100>; 137 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 138 interrupt-parent = <&gic>; 139 clocks = <&mpu_periphclk>; 140 }; 141 142 local_timer: timer@48240600 { 143 compatible = "arm,cortex-a9-twd-timer"; 144 reg = <0x48240600 0x100>; 145 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>; 146 interrupt-parent = <&gic>; 147 clocks = <&mpu_periphclk>; 148 }; 149 150 cache-controller@48242000 { 151 compatible = "arm,pl310-cache"; 152 reg = <0x48242000 0x1000>; 153 cache-unified; 154 cache-level = <2>; 155 }; 156 157 ocp@44000000 { 158 compatible = "simple-pm-bus"; 159 power-domains = <&prm_per>; 160 clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>; 161 clock-names = "fck"; 162 #address-cells = <1>; 163 #size-cells = <1>; 164 ranges; 165 ti,no-idle; 166 167 l3-noc@44000000 { 168 compatible = "ti,am4372-l3-noc"; 169 reg = <0x44000000 0x400000>, 170 <0x44800000 0x400000>; 171 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 173 }; 174 175 l4_wkup: interconnect@44c00000 { 176 }; 177 l4_per: interconnect@48000000 { 178 }; 179 l4_fast: interconnect@4a000000 { 180 }; 181 182 target-module@4c000000 { 183 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 184 reg = <0x4c000000 0x4>; 185 reg-names = "rev"; 186 clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>; 187 clock-names = "fck"; 188 ti,no-idle; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 ranges = <0x0 0x4c000000 0x1000000>; 192 193 emif: emif@0 { 194 compatible = "ti,emif-am4372"; 195 reg = <0 0x1000000>; 196 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 197 sram = <&pm_sram_code 198 &pm_sram_data>; 199 }; 200 }; 201 202 target-module@49000000 { 203 compatible = "ti,sysc-omap4", "ti,sysc"; 204 reg = <0x49000000 0x4>; 205 reg-names = "rev"; 206 clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>; 207 clock-names = "fck"; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges = <0x0 0x49000000 0x10000>; 211 212 edma: dma@0 { 213 compatible = "ti,edma3-tpcc"; 214 reg = <0 0x10000>; 215 reg-names = "edma3_cc"; 216 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 219 interrupt-names = "edma3_ccint", "edma3_mperr", 220 "edma3_ccerrint"; 221 dma-requests = <64>; 222 #dma-cells = <2>; 223 224 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, 225 <&edma_tptc2 0>; 226 227 ti,edma-memcpy-channels = <58 59>; 228 }; 229 }; 230 231 target-module@49800000 { 232 compatible = "ti,sysc-omap4", "ti,sysc"; 233 reg = <0x49800000 0x4>, 234 <0x49800010 0x4>; 235 reg-names = "rev", "sysc"; 236 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 237 ti,sysc-midle = <SYSC_IDLE_FORCE>; 238 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 239 <SYSC_IDLE_SMART>; 240 clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>; 241 clock-names = "fck"; 242 #address-cells = <1>; 243 #size-cells = <1>; 244 ranges = <0x0 0x49800000 0x100000>; 245 246 edma_tptc0: dma@0 { 247 compatible = "ti,edma3-tptc"; 248 reg = <0 0x100000>; 249 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 250 interrupt-names = "edma3_tcerrint"; 251 }; 252 }; 253 254 target-module@49900000 { 255 compatible = "ti,sysc-omap4", "ti,sysc"; 256 reg = <0x49900000 0x4>, 257 <0x49900010 0x4>; 258 reg-names = "rev", "sysc"; 259 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 260 ti,sysc-midle = <SYSC_IDLE_FORCE>; 261 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 262 <SYSC_IDLE_SMART>; 263 clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>; 264 clock-names = "fck"; 265 #address-cells = <1>; 266 #size-cells = <1>; 267 ranges = <0x0 0x49900000 0x100000>; 268 269 edma_tptc1: dma@0 { 270 compatible = "ti,edma3-tptc"; 271 reg = <0 0x100000>; 272 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 273 interrupt-names = "edma3_tcerrint"; 274 }; 275 }; 276 277 target-module@49a00000 { 278 compatible = "ti,sysc-omap4", "ti,sysc"; 279 reg = <0x49a00000 0x4>, 280 <0x49a00010 0x4>; 281 reg-names = "rev", "sysc"; 282 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 283 ti,sysc-midle = <SYSC_IDLE_FORCE>; 284 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 285 <SYSC_IDLE_SMART>; 286 clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>; 287 clock-names = "fck"; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 ranges = <0x0 0x49a00000 0x100000>; 291 292 edma_tptc2: dma@0 { 293 compatible = "ti,edma3-tptc"; 294 reg = <0 0x100000>; 295 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 296 interrupt-names = "edma3_tcerrint"; 297 }; 298 }; 299 300 target-module@47810000 { 301 compatible = "ti,sysc-omap2", "ti,sysc"; 302 reg = <0x478102fc 0x4>, 303 <0x47810110 0x4>, 304 <0x47810114 0x4>; 305 reg-names = "rev", "sysc", "syss"; 306 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 307 SYSC_OMAP2_ENAWAKEUP | 308 SYSC_OMAP2_SOFTRESET | 309 SYSC_OMAP2_AUTOIDLE)>; 310 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 311 <SYSC_IDLE_NO>, 312 <SYSC_IDLE_SMART>; 313 ti,syss-mask = <1>; 314 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>; 315 clock-names = "fck"; 316 #address-cells = <1>; 317 #size-cells = <1>; 318 ranges = <0x0 0x47810000 0x1000>; 319 320 mmc3: mmc@0 { 321 compatible = "ti,am437-sdhci"; 322 ti,needs-special-reset; 323 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 324 reg = <0x0 0x1000>; 325 status = "disabled"; 326 }; 327 }; 328 329 sham_target: target-module@53100000 { 330 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 331 reg = <0x53100100 0x4>, 332 <0x53100110 0x4>, 333 <0x53100114 0x4>; 334 reg-names = "rev", "sysc", "syss"; 335 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 336 SYSC_OMAP2_AUTOIDLE)>; 337 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 338 <SYSC_IDLE_NO>, 339 <SYSC_IDLE_SMART>; 340 ti,syss-mask = <1>; 341 /* Domains (P, C): per_pwrdm, l3_clkdm */ 342 clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>; 343 clock-names = "fck"; 344 #address-cells = <1>; 345 #size-cells = <1>; 346 ranges = <0x0 0x53100000 0x1000>; 347 348 sham: sham@0 { 349 compatible = "ti,omap5-sham"; 350 reg = <0 0x300>; 351 dmas = <&edma 36 0>; 352 dma-names = "rx"; 353 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 354 }; 355 }; 356 357 aes_target: target-module@53501000 { 358 compatible = "ti,sysc-omap2", "ti,sysc"; 359 reg = <0x53501080 0x4>, 360 <0x53501084 0x4>, 361 <0x53501088 0x4>; 362 reg-names = "rev", "sysc", "syss"; 363 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 364 SYSC_OMAP2_AUTOIDLE)>; 365 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 366 <SYSC_IDLE_NO>, 367 <SYSC_IDLE_SMART>, 368 <SYSC_IDLE_SMART_WKUP>; 369 ti,syss-mask = <1>; 370 /* Domains (P, C): per_pwrdm, l3_clkdm */ 371 clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>; 372 clock-names = "fck"; 373 #address-cells = <1>; 374 #size-cells = <1>; 375 ranges = <0x0 0x53501000 0x1000>; 376 377 aes: aes@0 { 378 compatible = "ti,omap4-aes"; 379 reg = <0 0xa0>; 380 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 381 dmas = <&edma 6 0>, 382 <&edma 5 0>; 383 dma-names = "tx", "rx"; 384 }; 385 }; 386 387 des_target: target-module@53701000 { 388 compatible = "ti,sysc-omap2", "ti,sysc"; 389 reg = <0x53701030 0x4>, 390 <0x53701034 0x4>, 391 <0x53701038 0x4>; 392 reg-names = "rev", "sysc", "syss"; 393 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 394 SYSC_OMAP2_AUTOIDLE)>; 395 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 396 <SYSC_IDLE_NO>, 397 <SYSC_IDLE_SMART>, 398 <SYSC_IDLE_SMART_WKUP>; 399 ti,syss-mask = <1>; 400 /* Domains (P, C): per_pwrdm, l3_clkdm */ 401 clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>; 402 clock-names = "fck"; 403 #address-cells = <1>; 404 #size-cells = <1>; 405 ranges = <0 0x53701000 0x1000>; 406 407 des: des@0 { 408 compatible = "ti,omap4-des"; 409 reg = <0 0xa0>; 410 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 411 dmas = <&edma 34 0>, 412 <&edma 33 0>; 413 dma-names = "tx", "rx"; 414 }; 415 }; 416 417 pruss_tm: target-module@54400000 { 418 compatible = "ti,sysc-pruss", "ti,sysc"; 419 reg = <0x54426000 0x4>, 420 <0x54426004 0x4>; 421 reg-names = "rev", "sysc"; 422 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | 423 SYSC_PRUSS_SUB_MWAIT)>; 424 ti,sysc-midle = <SYSC_IDLE_FORCE>, 425 <SYSC_IDLE_NO>, 426 <SYSC_IDLE_SMART>; 427 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 428 <SYSC_IDLE_NO>, 429 <SYSC_IDLE_SMART>; 430 clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>; 431 clock-names = "fck"; 432 resets = <&prm_per 1>; 433 reset-names = "rstctrl"; 434 #address-cells = <1>; 435 #size-cells = <1>; 436 ranges = <0x0 0x54400000 0x80000>; 437 }; 438 439 target-module@50000000 { 440 compatible = "ti,sysc-omap2", "ti,sysc"; 441 reg = <0x50000000 4>, 442 <0x50000010 4>, 443 <0x50000014 4>; 444 reg-names = "rev", "sysc", "syss"; 445 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 446 <SYSC_IDLE_NO>, 447 <SYSC_IDLE_SMART>; 448 ti,syss-mask = <1>; 449 clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>; 450 clock-names = "fck"; 451 #address-cells = <1>; 452 #size-cells = <1>; 453 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ 454 <0x00000000 0x00000000 0x40000000>; /* data */ 455 456 gpmc: gpmc@50000000 { 457 compatible = "ti,am3352-gpmc"; 458 dmas = <&edma 52 0>; 459 dma-names = "rxtx"; 460 clocks = <&l3s_gclk>; 461 clock-names = "fck"; 462 reg = <0x50000000 0x2000>; 463 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 464 gpmc,num-cs = <7>; 465 gpmc,num-waitpins = <2>; 466 #address-cells = <2>; 467 #size-cells = <1>; 468 interrupt-controller; 469 #interrupt-cells = <2>; 470 gpio-controller; 471 #gpio-cells = <2>; 472 status = "disabled"; 473 }; 474 }; 475 476 target-module@47900000 { 477 compatible = "ti,sysc-omap4", "ti,sysc"; 478 reg = <0x47900000 0x4>, 479 <0x47900010 0x4>; 480 reg-names = "rev", "sysc"; 481 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 482 <SYSC_IDLE_NO>, 483 <SYSC_IDLE_SMART>, 484 <SYSC_IDLE_SMART_WKUP>; 485 clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>; 486 clock-names = "fck"; 487 #address-cells = <1>; 488 #size-cells = <1>; 489 ranges = <0x0 0x47900000 0x1000>, 490 <0x30000000 0x30000000 0x4000000>; 491 492 qspi: spi@0 { 493 compatible = "ti,am4372-qspi"; 494 reg = <0 0x100>, 495 <0x30000000 0x4000000>; 496 reg-names = "qspi_base", "qspi_mmap"; 497 clocks = <&dpll_per_m2_div4_ck>; 498 clock-names = "fck"; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 interrupts = <0 138 0x4>; 502 num-cs = <4>; 503 }; 504 }; 505 506 target-module@40300000 { 507 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 508 clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>; 509 clock-names = "fck"; 510 ti,no-idle; 511 #address-cells = <1>; 512 #size-cells = <1>; 513 ranges = <0 0x40300000 0x40000>; 514 515 ocmcram: sram@0 { 516 compatible = "mmio-sram"; 517 reg = <0 0x40000>; /* 256k */ 518 ranges = <0 0 0x40000>; 519 #address-cells = <1>; 520 #size-cells = <1>; 521 522 pm_sram_code: pm-code-sram@0 { 523 compatible = "ti,sram"; 524 reg = <0x0 0x1000>; 525 protect-exec; 526 }; 527 528 pm_sram_data: pm-data-sram@1000 { 529 compatible = "ti,sram"; 530 reg = <0x1000 0x1000>; 531 pool; 532 }; 533 }; 534 }; 535 536 target-module@56000000 { 537 compatible = "ti,sysc-omap4", "ti,sysc"; 538 reg = <0x5600fe00 0x4>, 539 <0x5600fe10 0x4>; 540 reg-names = "rev", "sysc"; 541 ti,sysc-midle = <SYSC_IDLE_FORCE>, 542 <SYSC_IDLE_NO>, 543 <SYSC_IDLE_SMART>; 544 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 545 <SYSC_IDLE_NO>, 546 <SYSC_IDLE_SMART>; 547 clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>; 548 clock-names = "fck"; 549 power-domains = <&prm_gfx>; 550 resets = <&prm_gfx 0>; 551 reset-names = "rstctrl"; 552 #address-cells = <1>; 553 #size-cells = <1>; 554 ranges = <0 0x56000000 0x1000000>; 555 }; 556 }; 557}; 558 559#include "am437x-l4.dtsi" 560#include "am43xx-clocks.dtsi" 561 562&prcm { 563 prm_mpu: prm@300 { 564 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 565 reg = <0x300 0x100>; 566 #power-domain-cells = <0>; 567 }; 568 569 prm_gfx: prm@400 { 570 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 571 reg = <0x400 0x100>; 572 #power-domain-cells = <0>; 573 #reset-cells = <1>; 574 }; 575 576 prm_rtc: prm@500 { 577 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 578 reg = <0x500 0x100>; 579 #power-domain-cells = <0>; 580 }; 581 582 prm_tamper: prm@600 { 583 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 584 reg = <0x600 0x100>; 585 #power-domain-cells = <0>; 586 }; 587 588 prm_cefuse: prm@700 { 589 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 590 reg = <0x700 0x100>; 591 #power-domain-cells = <0>; 592 }; 593 594 prm_per: prm@800 { 595 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 596 reg = <0x800 0x100>; 597 #reset-cells = <1>; 598 #power-domain-cells = <0>; 599 }; 600 601 prm_wkup: prm@2000 { 602 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 603 reg = <0x2000 0x100>; 604 #reset-cells = <1>; 605 #power-domain-cells = <0>; 606 }; 607 608 prm_device: prm@4000 { 609 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 610 reg = <0x4000 0x100>; 611 #reset-cells = <1>; 612 }; 613}; 614 615/* Preferred always-on timer for clocksource */ 616&timer1_target { 617 ti,no-reset-on-init; 618 ti,no-idle; 619 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>, 620 <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; 621 clock-names = "fck", "ick"; 622 timer@0 { 623 assigned-clocks = <&timer1_fck>; 624 assigned-clock-parents = <&sys_clkin_ck>; 625 }; 626}; 627 628/* Preferred timer for clockevent */ 629&timer2_target { 630 ti,no-reset-on-init; 631 ti,no-idle; 632 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>, 633 <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>; 634 clock-names = "fck", "ick"; 635 timer@0 { 636 assigned-clocks = <&timer2_fck>; 637 assigned-clock-parents = <&sys_clkin_ck>; 638 }; 639}; 640