1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/* AM43x EPOS EVM */
7
8/dts-v1/;
9
10#include "am4372.dtsi"
11#include <dt-bindings/pinctrl/am43xx.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/pwm/pwm.h>
14#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
15
16/ {
17	model = "TI AM43x EPOS EVM";
18	compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43";
19
20	aliases {
21		display0 = &lcd0;
22	};
23
24	chosen {
25		stdout-path = &uart0;
26	};
27
28	vmmcsd_fixed: fixedregulator-sd {
29		compatible = "regulator-fixed";
30		regulator-name = "vmmcsd_fixed";
31		regulator-min-microvolt = <3300000>;
32		regulator-max-microvolt = <3300000>;
33		enable-active-high;
34	};
35
36	vbat: fixedregulator0 {
37		compatible = "regulator-fixed";
38		regulator-name = "vbat";
39		regulator-min-microvolt = <5000000>;
40		regulator-max-microvolt = <5000000>;
41		regulator-boot-on;
42	};
43
44	lcd0: display {
45		compatible = "osddisplays,osd070t1718-19ts", "panel-dpi";
46		label = "lcd";
47
48		backlight = <&lcd_bl>;
49
50		port {
51			lcd_in: endpoint {
52				remote-endpoint = <&dpi_out>;
53			};
54		};
55	};
56
57	matrix_keypad: matrix_keypad0 {
58		compatible = "gpio-matrix-keypad";
59		debounce-delay-ms = <5>;
60		col-scan-delay-us = <2>;
61		pinctrl-names = "default", "sleep";
62		pinctrl-0 = <&matrix_keypad_default>;
63		pinctrl-1 = <&matrix_keypad_sleep>;
64		wakeup-source;
65
66		row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH		/* Bank0, pin12 */
67			     &gpio0 13 GPIO_ACTIVE_HIGH		/* Bank0, pin13 */
68			     &gpio0 14 GPIO_ACTIVE_HIGH		/* Bank0, pin14 */
69			     &gpio0 15 GPIO_ACTIVE_HIGH>;	/* Bank0, pin15 */
70
71		col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH		/* Bank3, pin9 */
72			     &gpio3 10 GPIO_ACTIVE_HIGH		/* Bank3, pin10 */
73			     &gpio2 18 GPIO_ACTIVE_HIGH		/* Bank2, pin18 */
74			     &gpio2 19 GPIO_ACTIVE_HIGH>;	/* Bank2, pin19 */
75
76		linux,keymap = <0x00000201	/* P1 */
77			0x01000204	/* P4 */
78			0x02000207	/* P7 */
79			0x0300020a	/* NUMERIC_STAR */
80			0x00010202	/* P2 */
81			0x01010205	/* P5 */
82			0x02010208	/* P8 */
83			0x03010200	/* P0 */
84			0x00020203	/* P3 */
85			0x01020206	/* P6 */
86			0x02020209	/* P9 */
87			0x0302020b	/* NUMERIC_POUND */
88			0x00030067	/* UP */
89			0x0103006a	/* RIGHT */
90			0x0203006c	/* DOWN */
91			0x03030069>;	/* LEFT */
92	};
93
94	lcd_bl: backlight {
95		compatible = "pwm-backlight";
96		pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
97		brightness-levels = <0 51 53 56 62 75 101 152 255>;
98		default-brightness-level = <8>;
99	};
100
101	sound0: sound0 {
102		compatible = "simple-audio-card";
103		simple-audio-card,name = "AM43-EPOS-EVM";
104		simple-audio-card,widgets =
105			"Microphone", "Microphone Jack",
106			"Headphone", "Headphone Jack",
107			"Speaker", "Speaker";
108		simple-audio-card,routing =
109			"MIC1LP", "Microphone Jack",
110			"MIC1RP", "Microphone Jack",
111			"MIC1LP", "MICBIAS",
112			"MIC1RP", "MICBIAS",
113			"Headphone Jack", "HPL",
114			"Headphone Jack", "HPR",
115			"Speaker", "SPL",
116			"Speaker", "SPR";
117		simple-audio-card,format = "dsp_b";
118		simple-audio-card,bitclock-master = <&sound0_master>;
119		simple-audio-card,frame-master = <&sound0_master>;
120		simple-audio-card,bitclock-inversion;
121
122		simple-audio-card,cpu {
123			sound-dai = <&mcasp1>;
124			system-clock-frequency = <12000000>;
125		};
126
127		sound0_master: simple-audio-card,codec {
128			sound-dai = <&tlv320aic3111>;
129			system-clock-frequency = <12000000>;
130		};
131	};
132
133	audio_mstrclk: clock {
134		compatible = "fixed-clock";
135		#clock-cells = <0>;
136		clock-frequency = <12000000>;
137	};
138};
139
140&am43xx_pinmux {
141		pinctrl-names = "default";
142		pinctrl-0 = <&unused_pins>;
143
144		unused_pins: unused_pins {
145			pinctrl-single,pins = <
146				AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
147				AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
148				AM4372_IOPAD(0x858, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
149				AM4372_IOPAD(0x860, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
150				AM4372_IOPAD(0x864, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
151				AM4372_IOPAD(0x868, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
152				AM4372_IOPAD(0x86c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
153				AM4372_IOPAD(0x878, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
154				AM4372_IOPAD(0x908, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7)
155				AM4372_IOPAD(0x91c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
156				AM4372_IOPAD(0x920, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
157				AM4372_IOPAD(0x9e0, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7)
158				AM4372_IOPAD(0xA0c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
159				AM4372_IOPAD(0xA38, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
160				AM4372_IOPAD(0xA3c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
161				AM4372_IOPAD(0xA40, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
162				AM4372_IOPAD(0xA44, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
163				AM4372_IOPAD(0xA48, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
164				AM4372_IOPAD(0xA4c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
165				AM4372_IOPAD(0xA50, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
166				AM4372_IOPAD(0xA54, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
167				AM4372_IOPAD(0xA58, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
168				AM4372_IOPAD(0xA5c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
169				AM4372_IOPAD(0xA60, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
170				AM4372_IOPAD(0xA64, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
171				AM4372_IOPAD(0xA68, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
172				AM4372_IOPAD(0xA6C, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
173				AM4372_IOPAD(0xA74, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7)
174				AM4372_IOPAD(0xA78, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
175			>;
176		};
177
178		cpsw_default: cpsw_default {
179			pinctrl-single,pins = <
180				/* Slave 1 */
181				AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_crs.rmii1_crs */
182				AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
183				AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txen.rmii1_txen */
184				AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxdv.rmii1_rxdv */
185				AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd1.rmii1_txd1 */
186				AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd0.rmii1_txd0 */
187				AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd1.rmii1_rxd1 */
188				AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd0.rmii1_rxd0 */
189				AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_refclk.rmii1_refclk */
190			>;
191		};
192
193		cpsw_sleep: cpsw_sleep {
194			pinctrl-single,pins = <
195				/* Slave 1 reset value */
196				AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
197				AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
198				AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
199				AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
200				AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
201				AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
202				AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
203				AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
204				AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
205			>;
206		};
207
208		davinci_mdio_default: davinci_mdio_default {
209			pinctrl-single,pins = <
210				/* MDIO */
211				AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
212				AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
213			>;
214		};
215
216		davinci_mdio_sleep: davinci_mdio_sleep {
217			pinctrl-single,pins = <
218				/* MDIO reset value */
219				AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
220				AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
221			>;
222		};
223
224		i2c0_pins: pinmux_i2c0_pins {
225			pinctrl-single,pins = <
226				AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
227				AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
228			>;
229		};
230
231		nand_flash_x8_default: nand_flash_x8_default {
232			pinctrl-single,pins = <
233				AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a0.SELQSPIorNAND/GPIO */
234				AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
235				AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
236				AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
237				AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
238				AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
239				AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
240				AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
241				AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
242				AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
243				AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpmc_wpn */
244				AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
245				AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
246				AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
247				AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
248				AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
249			>;
250		};
251
252		nand_flash_x8_sleep: nand_flash_x8_sleep {
253			pinctrl-single,pins = <
254				AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
255				AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
256				AM4372_IOPAD(0x804, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
257				AM4372_IOPAD(0x808, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
258				AM4372_IOPAD(0x80c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
259				AM4372_IOPAD(0x810, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
260				AM4372_IOPAD(0x814, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
261				AM4372_IOPAD(0x818, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
262				AM4372_IOPAD(0x81c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
263				AM4372_IOPAD(0x870, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
264				AM4372_IOPAD(0x874, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
265				AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
266				AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
267				AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
268				AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
269				AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
270			>;
271		};
272
273		ecap0_pins_default: backlight_pins_default {
274			pinctrl-single,pins = <
275				AM4372_IOPAD(0x964, MUX_MODE0)         /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
276			>;
277		};
278
279		ecap0_pins_sleep: backlight_pins_sleep {
280			pinctrl-single,pins = <
281				AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
282			>;
283		};
284
285		i2c2_pins: pinmux_i2c2_pins {
286			pinctrl-single,pins = <
287				AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_sda.i2c2_sda */
288				AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_scl.i2c2_scl */
289			>;
290		};
291
292		spi0_pins_default: pinmux_spi0_pins_default {
293			pinctrl-single,pins = <
294				AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0)           /* spi0_clk.spi0_clk */
295				AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0)           /* spi0_d0.spi0_d0 */
296				AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0)           /* spi0_d1.spi0_d1 */
297				AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0)          /* spi0_cs0.spi0_cs0 */
298			>;
299		};
300
301		spi0_pins_sleep: pinmux_spi0_pins_sleep {
302			pinctrl-single,pins = <
303				AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
304				AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
305				AM4372_IOPAD(0x958, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
306				AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
307			>;
308		};
309
310		spi1_pins_default: pinmux_spi1_pins_default {
311			pinctrl-single,pins = <
312				AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3)           /* mcasp0_aclkx.spi1_clk */
313				AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3)           /* mcasp0_fsx.spi1_d0 */
314				AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3)           /* mcasp0_axr0.spi1_d1 */
315				AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3)          /* mcasp0_ahclkr.spi1_cs0 */
316			>;
317		};
318
319		spi1_pins_sleep: pinmux_spi1_pins_sleep {
320			pinctrl-single,pins = <
321				AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
322				AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
323				AM4372_IOPAD(0x998, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
324				AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
325			>;
326		};
327
328		mmc1_pins_default: pinmux_mmc1_pins_default {
329			pinctrl-single,pins = <
330				AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
331			>;
332		};
333
334		mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
335			pinctrl-single,pins = <
336				AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7)
337			>;
338		};
339
340		matrix_keypad_default: matrix_keypad_default {
341			pinctrl-single,pins = <
342				 AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7)          /* mii1_tx_clk.gpio3_9 */
343				 AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7)          /* mii1_rx_clk.gpio3_10 */
344				 AM4372_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7)          /* mii1_rxd3.gpio2_18 */
345				 AM4372_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7)          /* mii1_rxd2.gpio2_19 */
346				 AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7)  /* uart1_ctsn.gpio0_12 */
347				 AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7)  /* uart1_rtsn.gpio0_13 */
348				 AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7)  /* uart1_rxd.gpio0_14 */
349				 AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7)  /* uart1_txd.gpio0_15 */
350			>;
351		};
352
353		matrix_keypad_sleep: matrix_keypad_sleep {
354			pinctrl-single,pins = <
355				AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7)
356				AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7)
357				AM4372_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE7)
358				AM4372_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE7)
359				AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7)
360				AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7)
361				AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7)
362				AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7)
363			>;
364		};
365
366		qspi1_pins_default: qspi1_pins_default {
367			pinctrl-single,pins = <
368				AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3)
369				AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2)
370				AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3)
371				AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3)
372				AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3)
373				AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3)
374			>;
375		};
376
377		qspi1_pins_sleep: qspi1_pins_sleep {
378			pinctrl-single,pins = <
379				AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
380				AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
381				AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
382				AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
383				AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
384				AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
385			>;
386		};
387
388		pixcir_ts_pins_default: pixcir_ts_pins_default {
389			pinctrl-single,pins = <
390				AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_a1.gpio1_17 */
391			>;
392		};
393
394		pixcir_ts_pins_sleep: pixcir_ts_pins_sleep {
395			pinctrl-single,pins = <
396				AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_a1.gpio1_17 */
397			>;
398		};
399
400		hdq_pins: pinmux_hdq_pins {
401			pinctrl-single,pins = <
402				AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1)    /* cam1_wen.hdq_gpio */
403			>;
404		};
405
406		dss_pins: dss_pins {
407			pinctrl-single,pins = <
408				AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
409				AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
410				AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
411				AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
412				AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
413				AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
414				AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
415				AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
416				AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
417				AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
418				AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
419				AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
420				AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
421				AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
422				AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0)
423				AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
424				AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
425				AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
426				AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
427				AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
428				AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
429				AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
430				AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
431				AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
432				AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
433				AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
434				AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
435				AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
436			>;
437		};
438
439		display_mux_pins: display_mux_pins {
440			pinctrl-single,pins = <
441				/* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
442				AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7)
443			>;
444		};
445
446		vpfe1_pins_default: vpfe1_pins_default {
447			pinctrl-single,pins = <
448				AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0 */
449				AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0 */
450				AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0 */
451				AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0 */
452				AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0 */
453				AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0 */
454				AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0 */
455				AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0 */
456				AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0 */
457				AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0 */
458				AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0 */
459				AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0 */
460				AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0 */
461			>;
462		};
463
464		vpfe1_pins_sleep: vpfe1_pins_sleep {
465			pinctrl-single,pins = <
466				AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
467				AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
468				AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
469				AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
470				AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
471				AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
472				AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
473				AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
474				AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
475				AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
476				AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
477				AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
478				AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
479			>;
480		};
481
482		uart0_pins_default: uart0_pins_default {
483			pinctrl-single,pins = <
484				AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
485				AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
486				AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
487				AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0)	/* uart0_txd.uart0_txd */
488			>;
489		};
490
491		uart0_pins_sleep: uart0_pins_sleep {
492			pinctrl-single,pins = <
493				AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
494				AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
495				AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0)
496				AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0)
497			>;
498		};
499
500		usb2_phy1_default: usb2_phy1_default {
501			pinctrl-single,pins = <
502				AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0)
503			>;
504		};
505
506		usb2_phy1_sleep: usb2_phy1_sleep {
507			pinctrl-single,pins = <
508				AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
509			>;
510		};
511
512		usb2_phy2_default: usb2_phy2_default {
513			pinctrl-single,pins = <
514				AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0)
515			>;
516		};
517
518		usb2_phy2_sleep: usb2_phy2_sleep {
519			pinctrl-single,pins = <
520				AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
521			>;
522		};
523
524		mcasp1_pins: mcasp1_pins {
525			pinctrl-single,pins = <
526				AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */
527				AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */
528				AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */
529				AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */
530			>;
531		};
532
533		mcasp1_sleep_pins: mcasp1_sleep_pins {
534			pinctrl-single,pins = <
535				AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
536				AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7)
537				AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
538				AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7)
539			>;
540		};
541};
542
543&mmc1 {
544	status = "okay";
545	vmmc-supply = <&vmmcsd_fixed>;
546	bus-width = <4>;
547	pinctrl-names = "default", "sleep";
548	pinctrl-0 = <&mmc1_pins_default>;
549	pinctrl-1 = <&mmc1_pins_sleep>;
550	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
551};
552
553&mac_sw {
554	pinctrl-names = "default", "sleep";
555	pinctrl-0 = <&cpsw_default>;
556	pinctrl-1 = <&cpsw_sleep>;
557	status = "okay";
558};
559
560&davinci_mdio_sw {
561	pinctrl-names = "default", "sleep";
562	pinctrl-0 = <&davinci_mdio_default>;
563	pinctrl-1 = <&davinci_mdio_sleep>;
564
565	ethphy0: ethernet-phy@16 {
566		reg = <16>;
567	};
568};
569
570&cpsw_port1 {
571	phy-handle = <&ethphy0>;
572	phy-mode = "rmii";
573	phys = <&phy_gmii_sel 1 1>;
574	ti,dual-emac-pvid = <1>;
575};
576
577&cpsw_port2 {
578	status = "disabled";
579};
580
581&i2c0 {
582	status = "okay";
583	pinctrl-names = "default";
584	pinctrl-0 = <&i2c0_pins>;
585	clock-frequency = <400000>;
586
587	tps65218: tps65218@24 {
588		reg = <0x24>;
589		compatible = "ti,tps65218";
590		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */
591		interrupt-controller;
592		#interrupt-cells = <2>;
593
594		dcdc1: regulator-dcdc1 {
595			regulator-name = "vdd_core";
596			regulator-min-microvolt = <912000>;
597			regulator-max-microvolt = <1144000>;
598			regulator-boot-on;
599			regulator-always-on;
600		};
601
602		dcdc2: regulator-dcdc2 {
603			regulator-name = "vdd_mpu";
604			regulator-min-microvolt = <912000>;
605			regulator-max-microvolt = <1378000>;
606			regulator-boot-on;
607			regulator-always-on;
608		};
609
610		dcdc3: regulator-dcdc3 {
611			regulator-name = "vdcdc3";
612			regulator-boot-on;
613			regulator-always-on;
614			regulator-state-mem {
615				regulator-on-in-suspend;
616			};
617			regulator-state-disk {
618				regulator-off-in-suspend;
619			};
620		};
621
622		dcdc4: regulator-dcdc4 {
623			regulator-name = "vdcdc4";
624			regulator-min-microvolt = <3300000>;
625			regulator-max-microvolt = <3300000>;
626			regulator-boot-on;
627			regulator-always-on;
628		};
629
630		dcdc5: regulator-dcdc5 {
631			regulator-name = "v1_0bat";
632			regulator-min-microvolt = <1000000>;
633			regulator-max-microvolt = <1000000>;
634			regulator-boot-on;
635			regulator-always-on;
636		};
637
638		dcdc6: regulator-dcdc6 {
639			regulator-name = "v1_8bat";
640			regulator-min-microvolt = <1800000>;
641			regulator-max-microvolt = <1800000>;
642			regulator-boot-on;
643			regulator-always-on;
644		};
645
646		ldo1: regulator-ldo1 {
647			regulator-min-microvolt = <1800000>;
648			regulator-max-microvolt = <1800000>;
649			regulator-boot-on;
650			regulator-always-on;
651		};
652	};
653
654	at24@50 {
655		compatible = "atmel,24c256";
656		pagesize = <64>;
657		reg = <0x50>;
658	};
659
660	pixcir_ts@5c {
661		compatible = "pixcir,pixcir_tangoc";
662		pinctrl-names = "default", "sleep";
663		pinctrl-0 = <&pixcir_ts_pins_default>;
664		pinctrl-1 = <&pixcir_ts_pins_sleep>;
665
666		reg = <0x5c>;
667		interrupt-parent = <&gpio1>;
668		interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
669
670		attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
671
672		touchscreen-size-x = <1024>;
673		touchscreen-size-y = <600>;
674	};
675
676	tlv320aic3111: tlv320aic3111@18 {
677		#sound-dai-cells = <0>;
678		compatible = "ti,tlv320aic3111";
679		reg = <0x18>;
680		status = "okay";
681
682		ai31xx-micbias-vg = <MICBIAS_2_0V>;
683
684		/* Regulators */
685		HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
686		SPRVDD-supply = <&vbat>; /* vbat */
687		SPLVDD-supply = <&vbat>; /* vbat */
688		AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
689		IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
690		DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
691	};
692
693	ov2659@30 {
694		compatible = "ovti,ov2659";
695		reg = <0x30>;
696
697		clocks = <&audio_mstrclk>;
698		clock-names = "xvclk";
699
700		port {
701			ov2659_1: endpoint {
702				remote-endpoint = <&vpfe1_ep>;
703				link-frequencies = /bits/ 64 <70000000>;
704			};
705		};
706	};
707};
708
709&i2c2 {
710	pinctrl-names = "default";
711	pinctrl-0 = <&i2c2_pins>;
712	status = "okay";
713};
714
715&gpio0 {
716	status = "okay";
717};
718
719&gpio1 {
720	status = "okay";
721};
722
723&gpio2 {
724	pinctrl-names = "default";
725	pinctrl-0 = <&display_mux_pins>;
726	status = "okay";
727
728	p1 {
729		/*
730		 * SelLCDorHDMI selects between display and audio paths:
731		 * Low: HDMI display with audio via HDMI
732		 * High: LCD display with analog audio via aic3111 codec
733		 */
734		gpio-hog;
735		gpios = <1 GPIO_ACTIVE_HIGH>;
736		output-high;
737		line-name = "SelLCDorHDMI";
738	};
739};
740
741&gpio3 {
742	status = "okay";
743};
744
745&elm {
746	status = "okay";
747};
748
749&gpmc {
750	status = "okay";	/* Disable QSPI when enabling GPMC (NAND) */
751	pinctrl-names = "default", "sleep";
752	pinctrl-0 = <&nand_flash_x8_default>;
753	pinctrl-1 = <&nand_flash_x8_sleep>;
754	ranges = <0 0 0x08000000 0x01000000>;	/* CS0 space. Min partition = 16MB */
755	nand@0,0 {
756		compatible = "ti,omap2-nand";
757		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
758		interrupt-parent = <&gpmc>;
759		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
760			     <1 IRQ_TYPE_NONE>;	/* termcount */
761		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;	/* gpmc_wait0 */
762		ti,nand-xfer-type = "prefetch-dma";
763		ti,nand-ecc-opt = "bch16";
764		ti,elm-id = <&elm>;
765		nand-bus-width = <8>;
766		gpmc,device-width = <1>;
767		gpmc,sync-clk-ps = <0>;
768		gpmc,cs-on-ns = <0>;
769		gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
770		gpmc,cs-wr-off-ns = <40>;
771		gpmc,adv-on-ns = <0>;  /* cs-on-ns */
772		gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
773		gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
774		gpmc,we-on-ns = <0>;   /* cs-on-ns */
775		gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
776		gpmc,oe-on-ns = <3>;  /* cs-on-ns + tRR + 2 */
777		gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
778		gpmc,access-ns = <30>; /* tCEA + 4*/
779		gpmc,rd-cycle-ns = <40>;
780		gpmc,wr-cycle-ns = <40>;
781		gpmc,bus-turnaround-ns = <0>;
782		gpmc,cycle2cycle-delay-ns = <0>;
783		gpmc,clk-activation-ns = <0>;
784		gpmc,wr-access-ns = <40>;
785		gpmc,wr-data-mux-bus-ns = <0>;
786		/* MTD partition table */
787		/* All SPL-* partitions are sized to minimal length
788		 * which can be independently programmable. For
789		 * NAND flash this is equal to size of erase-block */
790		#address-cells = <1>;
791		#size-cells = <1>;
792		partition@0 {
793			label = "NAND.SPL";
794			reg = <0x00000000 0x00040000>;
795		};
796		partition@1 {
797			label = "NAND.SPL.backup1";
798			reg = <0x00040000 0x00040000>;
799		};
800		partition@2 {
801			label = "NAND.SPL.backup2";
802			reg = <0x00080000 0x00040000>;
803		};
804		partition@3 {
805			label = "NAND.SPL.backup3";
806			reg = <0x000C0000 0x00040000>;
807		};
808		partition@4 {
809			label = "NAND.u-boot-spl-os";
810			reg = <0x00100000 0x00080000>;
811		};
812		partition@5 {
813			label = "NAND.u-boot";
814			reg = <0x00180000 0x00100000>;
815		};
816		partition@6 {
817			label = "NAND.u-boot-env";
818			reg = <0x00280000 0x00040000>;
819		};
820		partition@7 {
821			label = "NAND.u-boot-env.backup1";
822			reg = <0x002C0000 0x00040000>;
823		};
824		partition@8 {
825			label = "NAND.kernel";
826			reg = <0x00300000 0x00700000>;
827		};
828		partition@9 {
829			label = "NAND.file-system";
830			reg = <0x00a00000 0x1f600000>;
831		};
832	};
833};
834
835&epwmss0 {
836	status = "okay";
837};
838
839&rtc_target {
840	status = "disabled";
841};
842
843&tscadc {
844	status = "okay";
845
846	adc {
847		ti,adc-channels = <0 1 2 3 4 5 6 7>;
848	};
849};
850
851&ecap0 {
852		status = "okay";
853		pinctrl-names = "default", "sleep";
854		pinctrl-0 = <&ecap0_pins_default>;
855		pinctrl-1 = <&ecap0_pins_sleep>;
856};
857
858&spi0 {
859	status = "okay";
860	pinctrl-names = "default", "sleep";
861	pinctrl-0 = <&spi0_pins_default>;
862	pinctrl-1 = <&spi0_pins_sleep>;
863	ti,pindir-d0-out-d1-in = <1>;
864};
865
866&spi1 {
867	status = "okay";
868	pinctrl-names = "default", "sleep";
869	pinctrl-0 = <&spi1_pins_default>;
870	pinctrl-1 = <&spi1_pins_sleep>;
871	ti,pindir-d0-out-d1-in = <1>;
872};
873
874&usb2_phy1 {
875	status = "okay";
876	pinctrl-names = "default", "sleep";
877	pinctrl-0 = <&usb2_phy1_default>;
878	pinctrl-1 = <&usb2_phy1_sleep>;
879};
880
881&usb1 {
882	dr_mode = "otg";
883	status = "okay";
884};
885
886&usb2_phy2 {
887	status = "okay";
888	pinctrl-names = "default", "sleep";
889	pinctrl-0 = <&usb2_phy2_default>;
890	pinctrl-1 = <&usb2_phy2_sleep>;
891};
892
893&usb2 {
894	dr_mode = "host";
895	status = "okay";
896};
897
898&qspi {
899	status = "disabled";	/* Disable GPMC (NAND) when enabling QSPI */
900	pinctrl-names = "default", "sleep";
901	pinctrl-0 = <&qspi1_pins_default>;
902	pinctrl-1 = <&qspi1_pins_sleep>;
903
904	spi-max-frequency = <48000000>;
905	m25p80@0 {
906		compatible = "mx66l51235l";
907		spi-max-frequency = <48000000>;
908		reg = <0>;
909		spi-cpol;
910		spi-cpha;
911		spi-tx-bus-width = <1>;
912		spi-rx-bus-width = <4>;
913		#address-cells = <1>;
914		#size-cells = <1>;
915
916		/* MTD partition table.
917		 * The ROM checks the first 512KiB
918		 * for a valid file to boot(XIP).
919		 */
920		partition@0 {
921			label = "QSPI.U_BOOT";
922			reg = <0x00000000 0x000080000>;
923		};
924		partition@1 {
925			label = "QSPI.U_BOOT.backup";
926			reg = <0x00080000 0x00080000>;
927		};
928		partition@2 {
929			label = "QSPI.U-BOOT-SPL_OS";
930			reg = <0x00100000 0x00010000>;
931		};
932		partition@3 {
933			label = "QSPI.U_BOOT_ENV";
934			reg = <0x00110000 0x00010000>;
935		};
936		partition@4 {
937			label = "QSPI.U-BOOT-ENV.backup";
938			reg = <0x00120000 0x00010000>;
939		};
940		partition@5 {
941			label = "QSPI.KERNEL";
942			reg = <0x00130000 0x0800000>;
943		};
944		partition@6 {
945			label = "QSPI.FILESYSTEM";
946			reg = <0x00930000 0x36D0000>;
947		};
948	};
949};
950
951&hdq {
952	status = "okay";
953	pinctrl-names = "default";
954	pinctrl-0 = <&hdq_pins>;
955};
956
957&dss {
958	status = "okay";
959
960	pinctrl-names = "default";
961	pinctrl-0 = <&dss_pins>;
962
963	port {
964		dpi_out: endpoint {
965			remote-endpoint = <&lcd_in>;
966			data-lines = <24>;
967		};
968	};
969};
970
971&vpfe1 {
972	status = "okay";
973	pinctrl-names = "default", "sleep";
974	pinctrl-0 = <&vpfe1_pins_default>;
975	pinctrl-1 = <&vpfe1_pins_sleep>;
976
977	port {
978		vpfe1_ep: endpoint {
979			remote-endpoint = <&ov2659_1>;
980			ti,am437x-vpfe-interface = <0>;
981			bus-width = <8>;
982			hsync-active = <0>;
983			vsync-active = <0>;
984		};
985	};
986};
987
988&uart0 {
989	status = "okay";
990	pinctrl-names = "default", "sleep";
991	pinctrl-0 = <&uart0_pins_default>;
992	pinctrl-1 = <&uart0_pins_sleep>;
993};
994
995&mcasp1 {
996	#sound-dai-cells = <0>;
997	pinctrl-names = "default", "sleep";
998	pinctrl-0 = <&mcasp1_pins>;
999	pinctrl-1 = <&mcasp1_sleep_pins>;
1000
1001	status = "okay";
1002
1003	op-mode = <0>;          /* MCASP_IIS_MODE */
1004	tdm-slots = <2>;
1005	/* 4 serializer */
1006	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
1007		1 2 0 0
1008	>;
1009	tx-num-evt = <32>;
1010	rx-num-evt = <32>;
1011};
1012
1013&mux_synctimer32k_ck {
1014	assigned-clocks = <&mux_synctimer32k_ck>;
1015	assigned-clock-parents = <&clkdiv32k_ick>;
1016};
1017
1018&cpu {
1019	cpu0-supply = <&dcdc2>;
1020};
1021