1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3
4/ {
5	#address-cells = <2>;
6	#size-cells = <2>;
7	model = "Broadcom STB (bcm7445)";
8	compatible = "brcm,bcm7445", "brcm,brcmstb";
9	interrupt-parent = <&gic>;
10
11	chosen {
12		bootargs = "console=ttyS0,115200 earlyprintk";
13	};
14
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu@0 {
20			compatible = "brcm,brahma-b15";
21			device_type = "cpu";
22			enable-method = "brcm,brahma-b15";
23			reg = <0>;
24		};
25
26		cpu@1 {
27			compatible = "brcm,brahma-b15";
28			device_type = "cpu";
29			enable-method = "brcm,brahma-b15";
30			reg = <1>;
31		};
32
33		cpu@2 {
34			compatible = "brcm,brahma-b15";
35			device_type = "cpu";
36			enable-method = "brcm,brahma-b15";
37			reg = <2>;
38		};
39
40		cpu@3 {
41			compatible = "brcm,brahma-b15";
42			device_type = "cpu";
43			enable-method = "brcm,brahma-b15";
44			reg = <3>;
45		};
46	};
47
48	gic: interrupt-controller@ffd00000 {
49		compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic";
50		reg = <0x00 0xffd01000 0x00 0x1000>,
51		      <0x00 0xffd02000 0x00 0x2000>,
52		      <0x00 0xffd04000 0x00 0x2000>,
53		      <0x00 0xffd06000 0x00 0x2000>;
54		interrupt-controller;
55		#interrupt-cells = <3>;
56	};
57
58	timer {
59		compatible = "arm,armv7-timer";
60		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
61			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
62			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
63			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
64	};
65
66	rdb@f0000000 {
67		#address-cells = <1>;
68		#size-cells = <1>;
69		compatible = "simple-bus";
70		ranges = <0 0x00 0xf0000000 0x1000000>;
71
72		serial@40ab00 {
73			compatible = "ns16550a";
74			reg = <0x40ab00 0x20>;
75			reg-shift = <2>;
76			reg-io-width = <4>;
77			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
78			clock-frequency = <81000000>;
79		};
80
81		sun_top_ctrl: syscon@404000 {
82			compatible = "brcm,bcm7445-sun-top-ctrl",
83				     "syscon";
84			reg = <0x404000 0x51c>;
85		};
86
87		hif_cpubiuctrl: syscon@3e2400 {
88			compatible = "brcm,bcm7445-hif-cpubiuctrl",
89				     "syscon";
90			reg = <0x3e2400 0x5b4>;
91		};
92
93		hif_continuation: syscon@452000 {
94			compatible = "brcm,bcm7445-hif-continuation",
95				     "syscon";
96			reg = <0x452000 0x100>;
97		};
98
99		irq0_intc: interrupt-controller@40a780 {
100			compatible = "brcm,bcm7120-l2-intc";
101			interrupt-parent = <&gic>;
102			#interrupt-cells = <1>;
103			reg = <0x40a780 0x8>;
104			interrupt-controller;
105			interrupts = <GIC_SPI 0x45 0x0>,
106				     <GIC_SPI 0x43 0x0>;
107			brcm,int-map-mask = <0x25c>, <0x7000000>;
108			brcm,int-fwd-mask = <0x70000>;
109		};
110
111		irq0_aon_intc: interrupt-controller@417280 {
112			compatible = "brcm,bcm7120-l2-intc";
113			reg = <0x417280 0x8>;
114			interrupt-parent = <&gic>;
115			#interrupt-cells = <1>;
116			interrupt-controller;
117			interrupts = <GIC_SPI 0x46 0x0>,
118				     <GIC_SPI 0x44 0x0>,
119				     <GIC_SPI 0x49 0x0>;
120			brcm,int-map-mask = <0x1e3 0x18000000 0x100000>;
121			brcm,int-fwd-mask = <0x0>;
122			brcm,irq-can-wake;
123		};
124
125		hif_intr2_intc: interrupt-controller@3e1000 {
126			compatible = "brcm,l2-intc";
127			reg = <0x3e1000 0x30>;
128			interrupt-controller;
129			#interrupt-cells = <1>;
130			interrupts = <GIC_SPI 0x20 0x0>;
131			interrupt-parent = <&gic>;
132			interrupt-names = "hif";
133		};
134
135                aon_pm_l2_intc: interrupt-controller@410640 {
136			compatible = "brcm,l2-intc";
137			reg = <0x410640 0x30>;
138			interrupt-controller;
139			#interrupt-cells = <1>;
140			interrupts = <GIC_SPI 0x40 0x0>;
141			interrupt-parent = <&gic>;
142			brcm,irq-can-wake;
143		};
144
145		aon-ctrl@410000 {
146			compatible = "brcm,brcmstb-aon-ctrl";
147			reg = <0x410000 0x200>, <0x410200 0x400>;
148			reg-names = "aon-ctrl", "aon-sram";
149		};
150
151		nand: nand@3e2800 {
152			status = "disabled";
153			#address-cells = <1>;
154			#size-cells = <0>;
155			compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
156			reg-names = "nand", "flash-dma";
157			reg = <0x3e2800 0x600>, <0x3e3000 0x2c>;
158			interrupt-parent = <&hif_intr2_intc>;
159			interrupts = <24>, <4>;
160			interrupt-names = "nand_ctlrdy", "flash_dma_done";
161		};
162
163		sata@45a000 {
164			compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
165			reg-names = "ahci", "top-ctrl";
166			reg = <0x45a000 0xa9c>, <0x458040 0x24>;
167			interrupts = <GIC_SPI 30 0>;
168			#address-cells = <1>;
169			#size-cells = <0>;
170
171			sata0: sata-port@0 {
172				reg = <0>;
173				phys = <&sata_phy0>;
174			};
175
176			sata1: sata-port@1 {
177				reg = <1>;
178				phys = <&sata_phy1>;
179			};
180		};
181
182		sata_phy: sata-phy@458100 {
183			compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
184			reg = <0x458100 0x1f00>;
185			reg-names = "phy";
186			#address-cells = <0x1>;
187			#size-cells = <0x0>;
188
189			sata_phy0: sata-phy@0 {
190				reg = <0>;
191				#phy-cells = <0>;
192			};
193
194			sata_phy1: sata-phy@1 {
195				reg = <1>;
196				#phy-cells = <0>;
197			};
198		};
199
200		upg_gio: gpio@40a700 {
201			compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
202			reg = <0x40a700 0x80>;
203			#gpio-cells = <2>;
204			#interrupt-cells = <2>;
205			gpio-controller;
206			interrupt-controller;
207			interrupt-parent = <&irq0_intc>;
208			interrupts = <6>;
209			brcm,gpio-bank-widths = <32 32 32 24>;
210		};
211
212		upg_gio_aon: gpio@4172c0 {
213			compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
214			reg = <0x4172c0 0x40>;
215			#gpio-cells = <2>;
216			#interrupt-cells = <2>;
217			gpio-controller;
218			interrupt-controller;
219			interrupts-extended = <&irq0_aon_intc 0x6>,
220					      <&aon_pm_l2_intc 0x5>;
221			wakeup-source;
222			brcm,gpio-bank-widths = <18 4>;
223		};
224
225	};
226
227	memory_controllers@f1100000 {
228		compatible = "simple-bus";
229		ranges = <0x0 0x0 0xf1100000 0x200000>;
230		#address-cells = <1>;
231		#size-cells = <1>;
232
233		memc@0 {
234			compatible = "brcm,brcmstb-memc", "simple-bus";
235			#address-cells = <1>;
236			#size-cells = <1>;
237			ranges = <0x0 0x0 0x80000>;
238
239			memc-ddr@2000 {
240				compatible = "brcm,brcmstb-memc-ddr";
241				reg = <0x2000 0x800>;
242			};
243
244			ddr-phy@6000 {
245				compatible = "brcm,brcmstb-ddr-phy-v240.1";
246				reg = <0x6000 0x21c>;
247				};
248
249			shimphy@8000 {
250				compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
251				reg = <0x8000 0xe4>;
252			};
253		};
254
255		memc@80000 {
256			compatible = "brcm,brcmstb-memc", "simple-bus";
257			#address-cells = <1>;
258			#size-cells = <1>;
259			ranges = <0x0 0x80000 0x80000>;
260
261			memc-ddr@2000 {
262				compatible = "brcm,brcmstb-memc-ddr";
263				reg = <0x2000 0x800>;
264			};
265
266			ddr-phy@6000 {
267				compatible = "brcm,brcmstb-ddr-phy-v240.1";
268				reg = <0x6000 0x21c>;
269			};
270
271			shimphy@8000 {
272				compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
273				reg = <0x8000 0xe4>;
274			};
275		};
276
277		memc@100000 {
278			compatible = "brcm,brcmstb-memc", "simple-bus";
279			#address-cells = <1>;
280			#size-cells = <1>;
281			ranges = <0x0 0x100000 0x80000>;
282
283			memc-ddr@2000 {
284				compatible = "brcm,brcmstb-memc-ddr";
285				reg = <0x2000 0x800>;
286			};
287
288			ddr-phy@6000 {
289				compatible = "brcm,brcmstb-ddr-phy-v240.1";
290				reg = <0x6000 0x21c>;
291			};
292
293			shimphy@8000 {
294				compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
295				reg = <0x8000 0xe4>;
296			};
297		};
298	};
299
300	sram@ffe00000 {
301		compatible = "brcm,boot-sram", "mmio-sram";
302		reg = <0x0 0xffe00000 0x0 0x10000>;
303	};
304
305	smpboot {
306		compatible = "brcm,brcmstb-smpboot";
307		syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
308		syscon-cont = <&hif_continuation>;
309	};
310
311	reboot {
312		compatible = "brcm,brcmstb-reboot";
313		syscon = <&sun_top_ctrl 0x304 0x308>;
314	};
315};
316