1/* 2 * This file is licensed under the terms of the GNU General Public License 3 * version 2. This program is licensed "as is" without any warranty of any 4 * kind, whether express or implied. 5 */ 6 7#include <dt-bindings/bus/ti-sysc.h> 8#include <dt-bindings/clock/dm816.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/pinctrl/omap.h> 11 12/ { 13 compatible = "ti,dm816"; 14 interrupt-parent = <&intc>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 chosen { }; 18 19 aliases { 20 i2c0 = &i2c1; 21 i2c1 = &i2c2; 22 serial0 = &uart1; 23 serial1 = &uart2; 24 serial2 = &uart3; 25 ethernet0 = ð0; 26 ethernet1 = ð1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 cpu@0 { 33 compatible = "arm,cortex-a8"; 34 device_type = "cpu"; 35 reg = <0>; 36 }; 37 }; 38 39 pmu { 40 compatible = "arm,cortex-a8-pmu"; 41 interrupts = <3>; 42 }; 43 44 /* 45 * The soc node represents the soc top level view. It is used for IPs 46 * that are not memory mapped in the MPU view or for the MPU itself. 47 */ 48 soc { 49 compatible = "ti,omap-infra"; 50 mpu { 51 compatible = "ti,omap3-mpu"; 52 ti,hwmods = "mpu"; 53 }; 54 }; 55 56 /* 57 * XXX: Use a flat representation of the dm816x interconnect. 58 * The real dm816x interconnect network is quite complex. Since 59 * it will not bring real advantage to represent that in DT 60 * for the moment, just use a fake OCP bus entry to represent 61 * the whole bus hierarchy. 62 */ 63 ocp { 64 compatible = "simple-bus"; 65 reg = <0x44000000 0x10000>; 66 interrupts = <9 10>; 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges; 70 71 prcm: prcm@48180000 { 72 compatible = "ti,dm816-prcm", "simple-bus"; 73 reg = <0x48180000 0x4000>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges = <0 0x48180000 0x4000>; 77 78 prcm_clocks: clocks { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 }; 82 83 prcm_clockdomains: clockdomains { 84 }; 85 }; 86 87 scrm: scrm@48140000 { 88 compatible = "ti,dm816-scrm", "simple-bus"; 89 reg = <0x48140000 0x21000>; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 #pinctrl-cells = <1>; 93 ranges = <0 0x48140000 0x21000>; 94 95 dm816x_pinmux: pinmux@800 { 96 compatible = "pinctrl-single"; 97 reg = <0x800 0x50a>; 98 #address-cells = <1>; 99 #size-cells = <0>; 100 #pinctrl-cells = <1>; 101 pinctrl-single,register-width = <16>; 102 pinctrl-single,function-mask = <0xf>; 103 }; 104 105 /* Device Configuration Registers */ 106 scm_conf: syscon@600 { 107 compatible = "syscon", "simple-bus"; 108 reg = <0x600 0x110>; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0 0x600 0x110>; 112 113 usb_phy0: usb-phy@20 { 114 compatible = "ti,dm8168-usb-phy"; 115 reg = <0x20 0x8>; 116 reg-names = "phy"; 117 clocks = <&main_fapll 6>; 118 clock-names = "refclk"; 119 #phy-cells = <0>; 120 syscon = <&scm_conf>; 121 }; 122 123 usb_phy1: usb-phy@28 { 124 compatible = "ti,dm8168-usb-phy"; 125 reg = <0x28 0x8>; 126 reg-names = "phy"; 127 clocks = <&main_fapll 6>; 128 clock-names = "refclk"; 129 #phy-cells = <0>; 130 syscon = <&scm_conf>; 131 }; 132 }; 133 134 scrm_clocks: clocks { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 }; 138 139 scrm_clockdomains: clockdomains { 140 }; 141 }; 142 143 target-module@49000000 { 144 compatible = "ti,sysc-omap4", "ti,sysc"; 145 reg = <0x49000000 0x4>; 146 reg-names = "rev"; 147 clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>; 148 clock-names = "fck"; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 ranges = <0x0 0x49000000 0x10000>; 152 153 edma: dma@0 { 154 compatible = "ti,edma3-tpcc"; 155 reg = <0 0x10000>; 156 reg-names = "edma3_cc"; 157 interrupts = <12 13 14>; 158 interrupt-names = "edma3_ccint", "edma3_mperr", 159 "edma3_ccerrint"; 160 dma-requests = <64>; 161 #dma-cells = <2>; 162 163 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, 164 <&edma_tptc2 3>, <&edma_tptc3 0>; 165 166 ti,edma-memcpy-channels = <20 21>; 167 }; 168 }; 169 170 target-module@49800000 { 171 compatible = "ti,sysc-omap4", "ti,sysc"; 172 reg = <0x49800000 0x4>, 173 <0x49800010 0x4>; 174 reg-names = "rev", "sysc"; 175 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 176 ti,sysc-midle = <SYSC_IDLE_FORCE>; 177 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 178 <SYSC_IDLE_SMART>; 179 clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>; 180 clock-names = "fck"; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 ranges = <0x0 0x49800000 0x100000>; 184 185 edma_tptc0: dma@0 { 186 compatible = "ti,edma3-tptc"; 187 reg = <0 0x100000>; 188 interrupts = <112>; 189 interrupt-names = "edma3_tcerrint"; 190 }; 191 }; 192 193 target-module@49900000 { 194 compatible = "ti,sysc-omap4", "ti,sysc"; 195 reg = <0x49900000 0x4>, 196 <0x49900010 0x4>; 197 reg-names = "rev", "sysc"; 198 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 199 ti,sysc-midle = <SYSC_IDLE_FORCE>; 200 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 201 <SYSC_IDLE_SMART>; 202 clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>; 203 clock-names = "fck"; 204 #address-cells = <1>; 205 #size-cells = <1>; 206 ranges = <0x0 0x49900000 0x100000>; 207 208 edma_tptc1: dma@0 { 209 compatible = "ti,edma3-tptc"; 210 reg = <0 0x100000>; 211 interrupts = <113>; 212 interrupt-names = "edma3_tcerrint"; 213 }; 214 }; 215 216 target-module@49a00000 { 217 compatible = "ti,sysc-omap4", "ti,sysc"; 218 reg = <0x49a00000 0x4>, 219 <0x49a00010 0x4>; 220 reg-names = "rev", "sysc"; 221 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 222 ti,sysc-midle = <SYSC_IDLE_FORCE>; 223 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 224 <SYSC_IDLE_SMART>; 225 clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>; 226 clock-names = "fck"; 227 #address-cells = <1>; 228 #size-cells = <1>; 229 ranges = <0x0 0x49a00000 0x100000>; 230 231 edma_tptc2: dma@0 { 232 compatible = "ti,edma3-tptc"; 233 reg = <0 0x100000>; 234 interrupts = <114>; 235 interrupt-names = "edma3_tcerrint"; 236 }; 237 }; 238 239 target-module@49b00000 { 240 compatible = "ti,sysc-omap4", "ti,sysc"; 241 reg = <0x49b00000 0x4>, 242 <0x49b00010 0x4>; 243 reg-names = "rev", "sysc"; 244 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 245 ti,sysc-midle = <SYSC_IDLE_FORCE>; 246 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 247 <SYSC_IDLE_SMART>; 248 clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>; 249 clock-names = "fck"; 250 #address-cells = <1>; 251 #size-cells = <1>; 252 ranges = <0x0 0x49b00000 0x100000>; 253 254 edma_tptc3: dma@0 { 255 compatible = "ti,edma3-tptc"; 256 reg = <0 0x100000>; 257 interrupts = <115>; 258 interrupt-names = "edma3_tcerrint"; 259 }; 260 }; 261 262 elm: elm@48080000 { 263 compatible = "ti,am3352-elm"; 264 ti,hwmods = "elm"; 265 reg = <0x48080000 0x2000>; 266 interrupts = <4>; 267 }; 268 269 gpio1: gpio@48032000 { 270 compatible = "ti,omap4-gpio"; 271 ti,hwmods = "gpio1"; 272 ti,gpio-always-on; 273 reg = <0x48032000 0x1000>; 274 interrupts = <96>; 275 gpio-controller; 276 #gpio-cells = <2>; 277 interrupt-controller; 278 #interrupt-cells = <2>; 279 }; 280 281 gpio2: gpio@4804c000 { 282 compatible = "ti,omap4-gpio"; 283 ti,hwmods = "gpio2"; 284 ti,gpio-always-on; 285 reg = <0x4804c000 0x1000>; 286 interrupts = <98>; 287 gpio-controller; 288 #gpio-cells = <2>; 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 }; 292 293 gpmc: gpmc@50000000 { 294 compatible = "ti,am3352-gpmc"; 295 ti,hwmods = "gpmc"; 296 reg = <0x50000000 0x2000>; 297 #address-cells = <2>; 298 #size-cells = <1>; 299 interrupts = <100>; 300 dmas = <&edma 52 0>; 301 dma-names = "rxtx"; 302 gpmc,num-cs = <6>; 303 gpmc,num-waitpins = <2>; 304 interrupt-controller; 305 #interrupt-cells = <2>; 306 gpio-controller; 307 #gpio-cells = <2>; 308 }; 309 310 i2c1: i2c@48028000 { 311 compatible = "ti,omap4-i2c"; 312 ti,hwmods = "i2c1"; 313 reg = <0x48028000 0x1000>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 interrupts = <70>; 317 dmas = <&edma 58 0 &edma 59 0>; 318 dma-names = "tx", "rx"; 319 }; 320 321 i2c2: i2c@4802a000 { 322 compatible = "ti,omap4-i2c"; 323 ti,hwmods = "i2c2"; 324 reg = <0x4802a000 0x1000>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 interrupts = <71>; 328 dmas = <&edma 60 0 &edma 61 0>; 329 dma-names = "tx", "rx"; 330 }; 331 332 intc: interrupt-controller@48200000 { 333 compatible = "ti,dm816-intc"; 334 interrupt-controller; 335 #interrupt-cells = <1>; 336 reg = <0x48200000 0x1000>; 337 }; 338 339 rtc: rtc@480c0000 { 340 compatible = "ti,am3352-rtc", "ti,da830-rtc"; 341 reg = <0x480c0000 0x1000>; 342 interrupts = <75 76>; 343 ti,hwmods = "rtc"; 344 }; 345 346 mailbox: mailbox@480c8000 { 347 compatible = "ti,omap4-mailbox"; 348 reg = <0x480c8000 0x2000>; 349 interrupts = <77>; 350 ti,hwmods = "mailbox"; 351 #mbox-cells = <1>; 352 ti,mbox-num-users = <4>; 353 ti,mbox-num-fifos = <12>; 354 mbox_dsp: mbox_dsp { 355 ti,mbox-tx = <3 0 0>; 356 ti,mbox-rx = <0 0 0>; 357 }; 358 }; 359 360 spinbox: spinbox@480ca000 { 361 compatible = "ti,omap4-hwspinlock"; 362 reg = <0x480ca000 0x2000>; 363 ti,hwmods = "spinbox"; 364 #hwlock-cells = <1>; 365 }; 366 367 mdio: mdio@4a100800 { 368 compatible = "ti,davinci_mdio"; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 reg = <0x4a100800 0x100>; 372 ti,hwmods = "davinci_mdio"; 373 bus_freq = <1000000>; 374 phy0: ethernet-phy@0 { 375 reg = <1>; 376 }; 377 phy1: ethernet-phy@1 { 378 reg = <2>; 379 }; 380 }; 381 382 eth0: ethernet@4a100000 { 383 compatible = "ti,dm816-emac"; 384 ti,hwmods = "emac0"; 385 reg = <0x4a100000 0x800 386 0x4a100900 0x3700>; 387 clocks = <&sysclk24_ck>; 388 syscon = <&scm_conf>; 389 ti,davinci-ctrl-reg-offset = <0>; 390 ti,davinci-ctrl-mod-reg-offset = <0x900>; 391 ti,davinci-ctrl-ram-offset = <0x2000>; 392 ti,davinci-ctrl-ram-size = <0x2000>; 393 interrupts = <40 41 42 43>; 394 phy-handle = <&phy0>; 395 }; 396 397 eth1: ethernet@4a120000 { 398 compatible = "ti,dm816-emac"; 399 ti,hwmods = "emac1"; 400 reg = <0x4a120000 0x4000>; 401 clocks = <&sysclk24_ck>; 402 syscon = <&scm_conf>; 403 ti,davinci-ctrl-reg-offset = <0>; 404 ti,davinci-ctrl-mod-reg-offset = <0x900>; 405 ti,davinci-ctrl-ram-offset = <0x2000>; 406 ti,davinci-ctrl-ram-size = <0x2000>; 407 interrupts = <44 45 46 47>; 408 phy-handle = <&phy1>; 409 }; 410 411 sata: sata@4a140000 { 412 compatible = "ti,dm816-ahci"; 413 reg = <0x4a140000 0x10000>; 414 interrupts = <16>; 415 ti,hwmods = "sata"; 416 }; 417 418 mcspi1: spi@48030000 { 419 compatible = "ti,omap4-mcspi"; 420 reg = <0x48030000 0x1000>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 interrupts = <65>; 424 ti,spi-num-cs = <4>; 425 ti,hwmods = "mcspi1"; 426 dmas = <&edma 16 0 &edma 17 0 427 &edma 18 0 &edma 19 0 428 &edma 20 0 &edma 21 0 429 &edma 22 0 &edma 23 0>; 430 dma-names = "tx0", "rx0", "tx1", "rx1", 431 "tx2", "rx2", "tx3", "rx3"; 432 }; 433 434 mmc1: mmc@48060000 { 435 compatible = "ti,omap4-hsmmc"; 436 reg = <0x48060000 0x11000>; 437 ti,hwmods = "mmc1"; 438 interrupts = <64>; 439 dmas = <&edma 24 0 &edma 25 0>; 440 dma-names = "tx", "rx"; 441 }; 442 443 timer1_target: target-module@4802e000 { 444 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 445 reg = <0x4802e000 0x4>, 446 <0x4802e010 0x4>; 447 reg-names = "rev", "sysc"; 448 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 449 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 450 <SYSC_IDLE_NO>, 451 <SYSC_IDLE_SMART>, 452 <SYSC_IDLE_SMART_WKUP>; 453 clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; 454 clock-names = "fck"; 455 #address-cells = <1>; 456 #size-cells = <1>; 457 ranges = <0x0 0x4802e000 0x1000>; 458 459 timer1: timer@0 { 460 compatible = "ti,dm816-timer"; 461 reg = <0 0x1000>; 462 interrupts = <67>; 463 ti,timer-alwon; 464 clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; 465 clock-names = "fck"; 466 }; 467 }; 468 469 timer2_target: target-module@48040000 { 470 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 471 reg = <0x48040000 0x4>, 472 <0x48040010 0x4>; 473 reg-names = "rev", "sysc"; 474 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 475 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 476 <SYSC_IDLE_NO>, 477 <SYSC_IDLE_SMART>, 478 <SYSC_IDLE_SMART_WKUP>; 479 clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; 480 clock-names = "fck"; 481 #address-cells = <1>; 482 #size-cells = <1>; 483 ranges = <0x0 0x48040000 0x1000>; 484 485 timer2: timer@0 { 486 compatible = "ti,dm816-timer"; 487 reg = <0 0x1000>; 488 interrupts = <68>; 489 clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; 490 clock-names = "fck"; 491 }; 492 }; 493 494 timer3: timer@48042000 { 495 compatible = "ti,dm816-timer"; 496 reg = <0x48042000 0x2000>; 497 interrupts = <69>; 498 ti,hwmods = "timer3"; 499 }; 500 501 timer4: timer@48044000 { 502 compatible = "ti,dm816-timer"; 503 reg = <0x48044000 0x2000>; 504 interrupts = <92>; 505 ti,hwmods = "timer4"; 506 ti,timer-pwm; 507 }; 508 509 timer5: timer@48046000 { 510 compatible = "ti,dm816-timer"; 511 reg = <0x48046000 0x2000>; 512 interrupts = <93>; 513 ti,hwmods = "timer5"; 514 ti,timer-pwm; 515 }; 516 517 timer6: timer@48048000 { 518 compatible = "ti,dm816-timer"; 519 reg = <0x48048000 0x2000>; 520 interrupts = <94>; 521 ti,hwmods = "timer6"; 522 ti,timer-pwm; 523 }; 524 525 timer7: timer@4804a000 { 526 compatible = "ti,dm816-timer"; 527 reg = <0x4804a000 0x2000>; 528 interrupts = <95>; 529 ti,hwmods = "timer7"; 530 ti,timer-pwm; 531 }; 532 533 uart1: uart@48020000 { 534 compatible = "ti,am3352-uart", "ti,omap3-uart"; 535 ti,hwmods = "uart1"; 536 reg = <0x48020000 0x2000>; 537 clock-frequency = <48000000>; 538 interrupts = <72>; 539 dmas = <&edma 26 0 &edma 27 0>; 540 dma-names = "tx", "rx"; 541 }; 542 543 uart2: uart@48022000 { 544 compatible = "ti,am3352-uart", "ti,omap3-uart"; 545 ti,hwmods = "uart2"; 546 reg = <0x48022000 0x2000>; 547 clock-frequency = <48000000>; 548 interrupts = <73>; 549 dmas = <&edma 28 0 &edma 29 0>; 550 dma-names = "tx", "rx"; 551 }; 552 553 uart3: uart@48024000 { 554 compatible = "ti,am3352-uart", "ti,omap3-uart"; 555 ti,hwmods = "uart3"; 556 reg = <0x48024000 0x2000>; 557 clock-frequency = <48000000>; 558 interrupts = <74>; 559 dmas = <&edma 30 0 &edma 31 0>; 560 dma-names = "tx", "rx"; 561 }; 562 563 /* NOTE: USB needs a transceiver driver for phys to work */ 564 usb: usb_otg_hs@47401000 { 565 compatible = "ti,am33xx-usb"; 566 reg = <0x47401000 0x400000>; 567 ranges; 568 #address-cells = <1>; 569 #size-cells = <1>; 570 ti,hwmods = "usb_otg_hs"; 571 572 usb0: usb@47401000 { 573 compatible = "ti,musb-dm816"; 574 reg = <0x47401400 0x400 575 0x47401000 0x200>; 576 reg-names = "mc", "control"; 577 interrupts = <18>; 578 interrupt-names = "mc"; 579 dr_mode = "host"; 580 interface-type = <0>; 581 phys = <&usb_phy0>; 582 phy-names = "usb2-phy"; 583 mentor,multipoint = <1>; 584 mentor,num-eps = <16>; 585 mentor,ram-bits = <12>; 586 mentor,power = <500>; 587 588 dmas = <&cppi41dma 0 0 &cppi41dma 1 0 589 &cppi41dma 2 0 &cppi41dma 3 0 590 &cppi41dma 4 0 &cppi41dma 5 0 591 &cppi41dma 6 0 &cppi41dma 7 0 592 &cppi41dma 8 0 &cppi41dma 9 0 593 &cppi41dma 10 0 &cppi41dma 11 0 594 &cppi41dma 12 0 &cppi41dma 13 0 595 &cppi41dma 14 0 &cppi41dma 0 1 596 &cppi41dma 1 1 &cppi41dma 2 1 597 &cppi41dma 3 1 &cppi41dma 4 1 598 &cppi41dma 5 1 &cppi41dma 6 1 599 &cppi41dma 7 1 &cppi41dma 8 1 600 &cppi41dma 9 1 &cppi41dma 10 1 601 &cppi41dma 11 1 &cppi41dma 12 1 602 &cppi41dma 13 1 &cppi41dma 14 1>; 603 dma-names = 604 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", 605 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", 606 "rx14", "rx15", 607 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 608 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", 609 "tx14", "tx15"; 610 }; 611 612 usb1: usb@47401800 { 613 compatible = "ti,musb-dm816"; 614 reg = <0x47401c00 0x400 615 0x47401800 0x200>; 616 reg-names = "mc", "control"; 617 interrupts = <19>; 618 interrupt-names = "mc"; 619 dr_mode = "host"; 620 interface-type = <0>; 621 phys = <&usb_phy1>; 622 phy-names = "usb2-phy"; 623 mentor,multipoint = <1>; 624 mentor,num-eps = <16>; 625 mentor,ram-bits = <12>; 626 mentor,power = <500>; 627 628 dmas = <&cppi41dma 15 0 &cppi41dma 16 0 629 &cppi41dma 17 0 &cppi41dma 18 0 630 &cppi41dma 19 0 &cppi41dma 20 0 631 &cppi41dma 21 0 &cppi41dma 22 0 632 &cppi41dma 23 0 &cppi41dma 24 0 633 &cppi41dma 25 0 &cppi41dma 26 0 634 &cppi41dma 27 0 &cppi41dma 28 0 635 &cppi41dma 29 0 &cppi41dma 15 1 636 &cppi41dma 16 1 &cppi41dma 17 1 637 &cppi41dma 18 1 &cppi41dma 19 1 638 &cppi41dma 20 1 &cppi41dma 21 1 639 &cppi41dma 22 1 &cppi41dma 23 1 640 &cppi41dma 24 1 &cppi41dma 25 1 641 &cppi41dma 26 1 &cppi41dma 27 1 642 &cppi41dma 28 1 &cppi41dma 29 1>; 643 dma-names = 644 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", 645 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", 646 "rx14", "rx15", 647 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 648 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", 649 "tx14", "tx15"; 650 }; 651 652 cppi41dma: dma-controller@47402000 { 653 compatible = "ti,am3359-cppi41"; 654 reg = <0x47400000 0x1000 655 0x47402000 0x1000 656 0x47403000 0x1000 657 0x47404000 0x4000>; 658 reg-names = "glue", "controller", "scheduler", "queuemgr"; 659 interrupts = <17>; 660 interrupt-names = "glue"; 661 #dma-cells = <2>; 662 #dma-channels = <30>; 663 #dma-requests = <256>; 664 }; 665 }; 666 667 wd_timer2: wd_timer@480c2000 { 668 compatible = "ti,omap3-wdt"; 669 ti,hwmods = "wd_timer"; 670 reg = <0x480c2000 0x1000>; 671 interrupts = <0>; 672 }; 673 }; 674}; 675 676#include "dm816x-clocks.dtsi" 677 678/* Preferred always-on timer for clocksource */ 679&timer1_target { 680 ti,no-reset-on-init; 681 ti,no-idle; 682 timer@0 { 683 assigned-clocks = <&timer1_fck>; 684 assigned-clock-parents = <&sys_clkin_ck>; 685 }; 686}; 687 688/* Preferred timer for clockevent */ 689&timer2_target { 690 ti,no-reset-on-init; 691 ti,no-idle; 692 timer@0 { 693 assigned-clocks = <&timer2_fck>; 694 assigned-clock-parents = <&sys_clkin_ck>; 695 }; 696}; 697