1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4210 SoC device tree source
4 *
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 *		http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
8 *		www.linaro.org
9 *
10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
11 * based board files can include this file and provide values for board specific
12 * bindings.
13 *
14 * Note: This file does not include device nodes for all the controllers in
15 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
16 * nodes can be added to this file.
17 */
18
19#include "exynos4.dtsi"
20#include "exynos4-cpu-thermal.dtsi"
21
22/ {
23	compatible = "samsung,exynos4210", "samsung,exynos4";
24
25	aliases {
26		pinctrl0 = &pinctrl_0;
27		pinctrl1 = &pinctrl_1;
28		pinctrl2 = &pinctrl_2;
29	};
30
31	cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34
35		cpu0: cpu@900 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a9";
38			reg = <0x900>;
39			clocks = <&clock CLK_ARM_CLK>;
40			clock-names = "cpu";
41			clock-latency = <160000>;
42
43			operating-points = <
44				1200000 1250000
45				1000000 1150000
46				800000	1075000
47				500000	975000
48				400000	975000
49				200000	950000
50			>;
51			#cooling-cells = <2>; /* min followed by max */
52		};
53
54		cpu1: cpu@901 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a9";
57			reg = <0x901>;
58			clocks = <&clock CLK_ARM_CLK>;
59			clock-names = "cpu";
60			clock-latency = <160000>;
61
62			operating-points = <
63				1200000 1250000
64				1000000 1150000
65				800000	1075000
66				500000	975000
67				400000	975000
68				200000	950000
69			>;
70			#cooling-cells = <2>; /* min followed by max */
71		};
72	};
73
74	soc: soc {
75		sysram: sram@2020000 {
76			compatible = "mmio-sram";
77			reg = <0x02020000 0x20000>;
78			#address-cells = <1>;
79			#size-cells = <1>;
80			ranges = <0 0x02020000 0x20000>;
81
82			smp-sram@0 {
83				compatible = "samsung,exynos4210-sysram";
84				reg = <0x0 0x1000>;
85			};
86
87			smp-sram@1f000 {
88				compatible = "samsung,exynos4210-sysram-ns";
89				reg = <0x1f000 0x1000>;
90			};
91		};
92
93		pd_lcd1: power-domain@10023ca0 {
94			compatible = "samsung,exynos4210-pd";
95			reg = <0x10023CA0 0x20>;
96			#power-domain-cells = <0>;
97			label = "LCD1";
98		};
99
100		l2c: cache-controller@10502000 {
101			compatible = "arm,pl310-cache";
102			reg = <0x10502000 0x1000>;
103			cache-unified;
104			cache-level = <2>;
105			prefetch-data = <1>;
106			prefetch-instr = <1>;
107			arm,tag-latency = <2 2 1>;
108			arm,data-latency = <2 2 1>;
109		};
110
111		mct: timer@10050000 {
112			compatible = "samsung,exynos4210-mct";
113			reg = <0x10050000 0x800>;
114			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
115			clock-names = "fin_pll", "mct";
116			interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
117					      <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
118					      <&combiner 12 6>,
119					      <&combiner 12 7>,
120					      <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
121					      <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
122		};
123
124		watchdog: watchdog@10060000 {
125			compatible = "samsung,s3c6410-wdt";
126			reg = <0x10060000 0x100>;
127			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
128			clocks = <&clock CLK_WDT>;
129			clock-names = "watchdog";
130		};
131
132		clock: clock-controller@10030000 {
133			compatible = "samsung,exynos4210-clock";
134			reg = <0x10030000 0x20000>;
135			#clock-cells = <1>;
136		};
137
138		pinctrl_0: pinctrl@11400000 {
139			compatible = "samsung,exynos4210-pinctrl";
140			reg = <0x11400000 0x1000>;
141			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
142		};
143
144		pinctrl_1: pinctrl@11000000 {
145			compatible = "samsung,exynos4210-pinctrl";
146			reg = <0x11000000 0x1000>;
147			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
148
149			wakup_eint: wakeup-interrupt-controller {
150				compatible = "samsung,exynos4210-wakeup-eint";
151				interrupt-parent = <&gic>;
152				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
153			};
154		};
155
156		pinctrl_2: pinctrl@3860000 {
157			compatible = "samsung,exynos4210-pinctrl";
158			reg = <0x03860000 0x1000>;
159		};
160
161		g2d: g2d@12800000 {
162			compatible = "samsung,s5pv210-g2d";
163			reg = <0x12800000 0x1000>;
164			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
165			clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
166			clock-names = "sclk_fimg2d", "fimg2d";
167			power-domains = <&pd_lcd0>;
168			iommus = <&sysmmu_g2d>;
169		};
170
171		ppmu_acp: ppmu@10ae0000 {
172			compatible = "samsung,exynos-ppmu";
173			reg = <0x10ae0000 0x2000>;
174			status = "disabled";
175		};
176
177		ppmu_lcd1: ppmu@12240000 {
178			compatible = "samsung,exynos-ppmu";
179			reg = <0x12240000 0x2000>;
180			clocks = <&clock CLK_PPMULCD1>;
181			clock-names = "ppmu";
182			status = "disabled";
183		};
184
185		sysmmu_g2d: sysmmu@12a20000 {
186			compatible = "samsung,exynos-sysmmu";
187			reg = <0x12A20000 0x1000>;
188			interrupt-parent = <&combiner>;
189			interrupts = <4 7>;
190			clock-names = "sysmmu", "master";
191			clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
192			power-domains = <&pd_lcd0>;
193			#iommu-cells = <0>;
194		};
195
196		sysmmu_fimd1: sysmmu@12220000 {
197			compatible = "samsung,exynos-sysmmu";
198			interrupt-parent = <&combiner>;
199			reg = <0x12220000 0x1000>;
200			interrupts = <5 3>;
201			clock-names = "sysmmu", "master";
202			clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
203			power-domains = <&pd_lcd1>;
204			#iommu-cells = <0>;
205		};
206
207		bus_dmc: bus-dmc {
208			compatible = "samsung,exynos-bus";
209			clocks = <&clock CLK_DIV_DMC>;
210			clock-names = "bus";
211			operating-points-v2 = <&bus_dmc_opp_table>;
212			status = "disabled";
213		};
214
215		bus_acp: bus-acp {
216			compatible = "samsung,exynos-bus";
217			clocks = <&clock CLK_DIV_ACP>;
218			clock-names = "bus";
219			operating-points-v2 = <&bus_acp_opp_table>;
220			status = "disabled";
221		};
222
223		bus_peri: bus-peri {
224			compatible = "samsung,exynos-bus";
225			clocks = <&clock CLK_ACLK100>;
226			clock-names = "bus";
227			operating-points-v2 = <&bus_peri_opp_table>;
228			status = "disabled";
229		};
230
231		bus_fsys: bus-fsys {
232			compatible = "samsung,exynos-bus";
233			clocks = <&clock CLK_ACLK133>;
234			clock-names = "bus";
235			operating-points-v2 = <&bus_fsys_opp_table>;
236			status = "disabled";
237		};
238
239		bus_display: bus-display {
240			compatible = "samsung,exynos-bus";
241			clocks = <&clock CLK_ACLK160>;
242			clock-names = "bus";
243			operating-points-v2 = <&bus_display_opp_table>;
244			status = "disabled";
245		};
246
247		bus_lcd0: bus-lcd0 {
248			compatible = "samsung,exynos-bus";
249			clocks = <&clock CLK_ACLK200>;
250			clock-names = "bus";
251			operating-points-v2 = <&bus_leftbus_opp_table>;
252			status = "disabled";
253		};
254
255		bus_leftbus: bus-leftbus {
256			compatible = "samsung,exynos-bus";
257			clocks = <&clock CLK_DIV_GDL>;
258			clock-names = "bus";
259			operating-points-v2 = <&bus_leftbus_opp_table>;
260			status = "disabled";
261		};
262
263		bus_rightbus: bus-rightbus {
264			compatible = "samsung,exynos-bus";
265			clocks = <&clock CLK_DIV_GDR>;
266			clock-names = "bus";
267			operating-points-v2 = <&bus_leftbus_opp_table>;
268			status = "disabled";
269		};
270
271		bus_mfc: bus-mfc {
272			compatible = "samsung,exynos-bus";
273			clocks = <&clock CLK_SCLK_MFC>;
274			clock-names = "bus";
275			operating-points-v2 = <&bus_leftbus_opp_table>;
276			status = "disabled";
277		};
278
279		bus_dmc_opp_table: opp-table1 {
280			compatible = "operating-points-v2";
281			opp-shared;
282
283			opp-134000000 {
284				opp-hz = /bits/ 64 <134000000>;
285				opp-microvolt = <1025000>;
286			};
287			opp-267000000 {
288				opp-hz = /bits/ 64 <267000000>;
289				opp-microvolt = <1050000>;
290			};
291			opp-400000000 {
292				opp-hz = /bits/ 64 <400000000>;
293				opp-microvolt = <1150000>;
294				opp-suspend;
295			};
296		};
297
298		bus_acp_opp_table: opp-table2 {
299			compatible = "operating-points-v2";
300			opp-shared;
301
302			opp-134000000 {
303				opp-hz = /bits/ 64 <134000000>;
304			};
305			opp-160000000 {
306				opp-hz = /bits/ 64 <160000000>;
307			};
308			opp-200000000 {
309				opp-hz = /bits/ 64 <200000000>;
310			};
311		};
312
313		bus_peri_opp_table: opp-table3 {
314			compatible = "operating-points-v2";
315			opp-shared;
316
317			opp-5000000 {
318				opp-hz = /bits/ 64 <5000000>;
319			};
320			opp-100000000 {
321				opp-hz = /bits/ 64 <100000000>;
322			};
323		};
324
325		bus_fsys_opp_table: opp-table4 {
326			compatible = "operating-points-v2";
327			opp-shared;
328
329			opp-10000000 {
330				opp-hz = /bits/ 64 <10000000>;
331			};
332			opp-134000000 {
333				opp-hz = /bits/ 64 <134000000>;
334			};
335		};
336
337		bus_display_opp_table: opp-table5 {
338			compatible = "operating-points-v2";
339			opp-shared;
340
341			opp-100000000 {
342				opp-hz = /bits/ 64 <100000000>;
343			};
344			opp-134000000 {
345				opp-hz = /bits/ 64 <134000000>;
346			};
347			opp-160000000 {
348				opp-hz = /bits/ 64 <160000000>;
349			};
350		};
351
352		bus_leftbus_opp_table: opp-table6 {
353			compatible = "operating-points-v2";
354			opp-shared;
355
356			opp-100000000 {
357				opp-hz = /bits/ 64 <100000000>;
358			};
359			opp-160000000 {
360				opp-hz = /bits/ 64 <160000000>;
361			};
362			opp-200000000 {
363				opp-hz = /bits/ 64 <200000000>;
364				opp-suspend;
365			};
366		};
367	};
368};
369
370&cpu_alert0 {
371	temperature = <85000>; /* millicelsius */
372};
373
374&cpu_alert1 {
375	temperature = <100000>; /* millicelsius */
376};
377
378&cpu_alert2 {
379	temperature = <110000>; /* millicelsius */
380};
381
382&cpu_thermal {
383	polling-delay-passive = <0>;
384	polling-delay = <0>;
385	thermal-sensors = <&tmu 0>;
386};
387
388&gic {
389	cpu-offset = <0x8000>;
390};
391
392&camera {
393	clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
394		 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
395	clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
396};
397
398&combiner {
399	samsung,combiner-nr = <16>;
400	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
401		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
402		     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
403		     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
404		     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
405		     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
406		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
407		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
408		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
409		     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
410		     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
411		     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
412		     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
413		     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
414		     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
415		     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
416};
417
418&fimc_0 {
419	samsung,pix-limits = <4224 8192 1920 4224>;
420	samsung,mainscaler-ext;
421	samsung,cam-if;
422};
423
424&fimc_1 {
425	samsung,pix-limits = <4224 8192 1920 4224>;
426	samsung,mainscaler-ext;
427	samsung,cam-if;
428};
429
430&fimc_2 {
431	samsung,pix-limits = <4224 8192 1920 4224>;
432	samsung,mainscaler-ext;
433	samsung,lcd-wb;
434};
435
436&fimc_3 {
437	samsung,pix-limits = <1920 8192 1366 1920>;
438	samsung,rotators = <0>;
439	samsung,mainscaler-ext;
440	samsung,lcd-wb;
441};
442
443&gpu {
444	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
445		     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
446		     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
447		     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
448		     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
449		     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
450		     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
451		     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
452		     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
453		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
454	interrupt-names = "gp",
455			  "gpmmu",
456			  "pp0",
457			  "ppmmu0",
458			  "pp1",
459			  "ppmmu1",
460			  "pp2",
461			  "ppmmu2",
462			  "pp3",
463			  "ppmmu3";
464	operating-points-v2 = <&gpu_opp_table>;
465
466	gpu_opp_table: opp-table {
467		compatible = "operating-points-v2";
468
469		opp-160000000 {
470			opp-hz = /bits/ 64 <160000000>;
471			opp-microvolt = <950000>;
472		};
473		opp-267000000 {
474			opp-hz = /bits/ 64 <267000000>;
475			opp-microvolt = <1050000>;
476		};
477	};
478};
479
480&mdma1 {
481	power-domains = <&pd_lcd0>;
482};
483
484&mixer {
485	clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
486		      "sclk_mixer";
487	clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
488		 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
489		 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
490};
491
492&pmu {
493	interrupts = <2 2>, <3 2>;
494	interrupt-affinity = <&cpu0>, <&cpu1>;
495	status = "okay";
496};
497
498&pmu_system_controller {
499	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
500			"clkout4", "clkout8", "clkout9";
501	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
502		<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
503		<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
504	#clock-cells = <1>;
505};
506
507&rotator {
508	power-domains = <&pd_lcd0>;
509};
510
511&sysmmu_rotator {
512	power-domains = <&pd_lcd0>;
513};
514
515&tmu {
516	compatible = "samsung,exynos4210-tmu";
517	clocks = <&clock CLK_TMU_APBIF>;
518	clock-names = "tmu_apbif";
519	samsung,tmu_gain = <15>;
520	samsung,tmu_reference_voltage = <7>;
521};
522
523#include "exynos4210-pinctrl.dtsi"
524